Semiconductor quantum dot device and preparation method thereof

Abstract

The invention discloses a semiconductor quantum device and a preparation method thereof, and relates to the field of quantum devices, and the semiconductor quantum device comprises a semiconductor-on-insulator substrate which comprises a semiconductor substrate, an insulating layer and an epitaxial base layer which are stacked in sequence; the insulating layer comprises a central region and an edge region surrounding the central region; etching the edge region to remove the insulating layer so as to form a suspension gap on the lower surface of the epitaxial base layer for releasing the stress of an interface between the epitaxial base layer and the insulating layer; the insulating layer in the central area is reserved as a supporting body for bearing the epitaxial base layer; the silicon-germanium heterojunction is arranged on the upper surface of the epitaxial base layer based on the suspension gap; and the gate structure is arranged on the upper surface of the silicon-germanium heterojunction, and quantum dots are formed in the silicon-germanium heterojunction based on the gate structure. According to the invention, dislocation caused by interface stress can be reduced based on the suspension gap, the epitaxial quality of the silicon-germanium heterojunction can be further improved, the growth time of the relaxation epitaxial layer can be shortened, and the performance of the device can be further improved.

Description

Technical Field

[0001] The present application relates to the field of quantum devices, and particularly to a semiconductor quantum device and a preparation method thereof. Background Art

[0002] Semiconductor quantum dots formed based on silicon-germanium heterojunctions have the characteristic of long correlation time, enabling the semiconductor quantum dots to maintain quantum states for a relatively long time. This property is crucial for reducing the error rate in quantum computing. Semiconductor quantum dots also have high manipulation fidelity. Research shows that a spin flip rate exceeding 1.2 GHz can be achieved through the mechanism of electric dipole spin resonance. This high-speed spin qubit manipulation characteristic helps to improve the fidelity of quantum gate operations. The manufacturing process of semiconductor quantum dots is compatible with existing semiconductor processes, which provides the possibility for large-scale production and is conducive to realizing the two-dimensional expansion of quantum bit units. Semiconductor quantum dots also have high tunability and can be regulated through quantum dot arrays, providing the possibility for realizing complex quantum computing and simulation.

[0003] Due to the above-mentioned many advantages of semiconductor quantum dots, semiconductor quantum dots have become an important research direction in the field of quantum computing. With the continuous development of science and technology, semiconductor quantum dots are expected to play a key role in future quantum computers.

[0004] In the prior art, when preparing a silicon-germanium heterojunction on a semiconductor substrate, the silicon-germanium heterojunction is subjected to relatively large stress, which will in turn affect the performance of the device. Summary of the Invention

[0005] In view of the above problems, the present application provides a semiconductor quantum device and a preparation method thereof to achieve the purpose of reducing the dislocations of the silicon-germanium heterojunction and improving the device performance. The specific solutions are as follows:

[0006] The first aspect of the present application provides a semiconductor quantum dot device, including:

[0007] A semiconductor-on-insulator substrate, which includes a semiconductor substrate, an insulating layer, and an epitaxial layer stacked in sequence. The insulating layer includes a central region and an edge region surrounding the central region. The edge region is etched to remove the insulating layer to form a suspended gap on the lower surface of the epitaxial layer for releasing the stress at the interface between the epitaxial layer and the insulating layer. The insulating layer in the central region is retained as a support for carrying the epitaxial layer;

[0008] Based on the suspended gap, a silicon-germanium heterojunction is provided on the upper surface of the epitaxial layer;

[0009] A gate structure is provided on the upper surface of the silicon-germanium heterojunction, and quantum dots are formed in the silicon-germanium heterojunction based on the gate structure.

[0010] Optionally, in the above semiconductor quantum dot device, the silicon-germanium heterojunction includes:

[0011] A silicon-germanium buffer layer disposed on the upper surface of the epitaxial base layer;

[0012] A silicon-germanium relaxation layer disposed on the upper surface of the silicon-germanium buffer layer;

[0013] A well layer disposed on the upper surface of the silicon-germanium relaxation layer, and quantum dots are located in the well layer;

[0014] A silicon-germanium spacer layer disposed on the upper surface of the well layer; both the silicon-germanium relaxation layer and the silicon-germanium spacer layer are Si 1-x Ge x film layer; where x is a constant related to the material of the epitaxial base layer;

[0015] A cap layer disposed on the upper surface of the silicon-germanium spacer layer.

[0016] Optionally, in the above semiconductor quantum dot device, the semiconductor-on-insulator substrate is a silicon-on-insulator substrate, and the epitaxial base layer is a single-crystalline silicon layer;

[0017] The well layer is a single-crystalline silicon layer for forming silicon quantum dots.

[0018] Optionally, in the above semiconductor quantum dot device, the semiconductor-on-insulator substrate is a germanium-on-insulator substrate, and the epitaxial base layer is a single-crystalline germanium layer;

[0019] The well layer is a single-crystalline germanium layer for forming germanium quantum dots.

[0020] Optionally, in the above semiconductor quantum dot device, if the epitaxial base layer is a single-crystalline silicon layer, then 0 < x < 0.4;

[0021] If the epitaxial base layer is a single-crystalline germanium layer, then 0.6 < x < 0.85.

[0022] Optionally, in the above semiconductor quantum dot device, in the direction of the epitaxial base layer pointing to the silicon-germanium heterojunction, if 0 < x < 0.4, the component of germanium element in the silicon-germanium buffer layer gradually increases, and if 0.6 < x < 0.85, the component of germanium element in the silicon-germanium buffer layer gradually decreases.

[0023] Optionally, in the above semiconductor quantum dot device, the upper surface of the silicon-germanium heterojunction is covered with a gate dielectric layer;

[0024] The gate structure includes: a plurality of barrier gates spaced apart and disposed on the upper surface of the gate dielectric layer; energy level gates are respectively disposed between adjacent barrier gates; there are a plurality of quantum dots in the silicon-germanium heterojunction that are arranged in one-to-one correspondence with the energy level gates;

[0025] Wherein, the surface of the energy level gate is covered with an insulating isolation layer to isolate the barrier gate from the energy level gate.

[0026] Optionally, in the above semiconductor quantum dot device, the insulating isolation layer and the gate dielectric layer are made of the same insulating material.

[0027] Optionally, in the above semiconductor quantum dot device, within the suspension gap, the sidewalls of the support body, the upper surface of the semiconductor substrate, and the lower surface of the epitaxial base layer are all covered with an inner gap layer;

[0028] Wherein, there is a spacing between the inner gap layers on the upper surface of the semiconductor substrate and the lower surface of the epitaxial base layer.

[0029] Optionally, in the above semiconductor quantum dot device, the inner gap layer is formed synchronously with at least one layer of the silicon-germanium heterojunction.

[0030] The second aspect of this application also provides a method for manufacturing the above semiconductor quantum dot device, including:

[0031] Providing a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate includes a semiconductor substrate, an insulating layer, and an epitaxial base layer stacked in sequence; the insulating layer includes a central region and an edge region surrounding the central region;

[0032] Etching away the insulating layer in the edge region to form a suspension gap on the lower surface of the epitaxial base layer for releasing the stress at the interface between the epitaxial base layer and the insulating layer; wherein, the insulating layer in the central region serves as a support body for carrying the epitaxial base layer;

[0033] Based on the suspension gap, forming a silicon-germanium heterojunction on the upper surface of the epitaxial base layer;

[0034] Forming a gate structure on the upper surface of the silicon-germanium heterojunction, and forming quantum dots in the silicon-germanium heterojunction based on the gate structure.

[0035] By means of the above technical solution, in the semiconductor quantum device and its manufacturing method provided by this application, a suspension gap is formed between the semiconductor substrate and the epitaxial base layer. Through the suspension gap, the stress between the epitaxial base layer and the insulating layer can be eliminated, and the stress applied by the insulating layer to the epitaxial base layer can be prevented from affecting the epitaxial quality of the silicon-germanium heterojunction, thereby improving the device performance. In particular, the epitaxial base layer around the support body can increase the flexible bending ability based on the suspension gap, making the epitaxial base layer equivalent to a flexible substrate. Therefore, when forming a silicon-germanium heterojunction on the upper surface of the epitaxial base layer with a suspension gap, the stress generated due to lattice mismatch at the interface between the epitaxial base layer and the insulating layer can be released, reducing the stress, reducing the dislocations generated due to the interface stress, further improving the epitaxial quality of the silicon-germanium heterojunction, and further improving the device performance. Description of the Drawings

[0036] To more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0037] The structures, proportions, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those familiar with this technology to understand and read, and are not used to limit the limiting conditions under which the present application can be implemented. Therefore, they do not have a substantial technical meaning. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the present application can produce and the purposes that can be achieved, should still fall within the scope covered by the technical content disclosed in the present application.

[0038] Figure 1 It is a schematic structural diagram of a semiconductor quantum dot device provided by an embodiment of the present application;

[0039] Figure 2 It is a schematic structural diagram of another semiconductor quantum dot device provided by an embodiment of the present application;

[0040] Figure 3 It is a schematic structural diagram of yet another semiconductor quantum dot device provided by an embodiment of the present application;

[0041] Figure 4 It is a schematic structural diagram of yet another semiconductor quantum dot device provided by an embodiment of the present application;

[0042] Figures 5 - 12 It is a product structure diagram of a method for preparing a semiconductor quantum dot device provided by an embodiment of the present application in different process steps;

[0043] Figure 13 It is a curve of the thickness and relaxation degree of an epitaxial base layer and a silicon-germanium buffer layer provided by an embodiment of the present application.

[0044] Reference numerals:

[0045] 11 - Semiconductor-on-insulator substrate; 111 - Semiconductor substrate; 112 - Insulating layer; 112a - Central region; 112b - Edge region; 113 - Epitaxial base layer; 113a - Base layer unit; 13 - Suspended space; 14 - Silicon-germanium heterojunction; 141 - Silicon-germanium buffer layer; 142 - Silicon-germanium relaxation layer; 143 - Well layer; 144 - Silicon-germanium spacer layer; 145 - Cap layer; 15 - Gate structure; 16 - Gate dielectric layer; 17 - Energy level gate; 18 - Barrier gate; 19 - Insulating isolation layer; 20 - Inner gap film layer. Detailed implementation manners

[0046] The embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. As known to those of ordinary skill in the art, with the development of technology and the emergence of new scenarios, the technical solutions provided by the embodiments of the present application are equally applicable to similar technical problems.

[0047] Silicon-based semiconductor quantum dot spin qubits have become one of the potential candidate systems for fault-tolerant quantum computing due to their long coherence time, good controllability, and compatibility with modern advanced integrated circuit manufacturing processes, and have received extensive attention in the scientific community. Among them, silicon / silicon germanium (Si / SiGe) heterojunctions, germanium / silicon germanium (Ge / SiGe) heterojunctions, and silicon metal oxide semiconductor / silicon dioxide (SiMOS or Si / SiO2) are the most studied silicon-based substrate materials at present.

[0048] For Si / SiGe heterojunctions and Si / SiO2 heterojunctions, two-dimensional electron gas (2DEG) exists in the strained Si well and at the interface between Si and SiO2, respectively. For Ge / SiGe heterojunctions, 2DEG exists in the strained Ge well. By using micro-nano processing technology to prepare a metal gate structure on the surface of these substrates and applying a certain voltage to the gate structure, a potential well can be formed in the substrate to confine free electrons (or holes) in the substrate to form an island, that is, a semiconductor quantum dot.

[0049] In high-quality quantum computing, material preparation is a key factor. For silicon-based semiconductor quantum dots, their core structure is an epitaxial layer with silicon germanium heterojunction. To prepare a high-quality epitaxial layer, generally, a compositionally graded SiGe buffer layer needs to be formed on the surface of the semiconductor substrate first, and then a relaxed SiGe epitaxial layer with a stable composition is grown on the surface of the SiGe buffer layer. As the SiGe buffer layer grows, the Ge composition in the SiGe buffer layer gradually changes with the increase of the film thickness, and the stress accumulated during the film growth process can be gradually released through the generation of misfit dislocations, and the dislocations are distributed throughout the SiGe buffer layer.

[0050] The advantage of the compositionally graded SiGe buffer layer technology is that the dislocation density of the thin film is very low, and the disadvantage is that the surface of the thin film shows a cross-hatch morphology, resulting in a large surface roughness of the SiGe buffer layer. In addition, in order to achieve a better stress release effect, a SiGe buffer layer with a larger thickness (generally 1μm - 2μm) is required, which leads to a long growth time of the epitaxial layer and is not conducive to integration with other optoelectronic devices.

[0051] To solve the above problems, the embodiments of the present application provide a semiconductor quantum dot device, including:

[0052] A semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate includes a semiconductor substrate, an insulating layer, and an epitaxial base layer stacked in sequence; the insulating layer includes a central region and an edge region surrounding the central region; the edge region is etched to remove the insulating layer to form a suspended gap on the lower surface of the epitaxial base layer for releasing the stress at the interface between the epitaxial base layer and the insulating layer; the insulating layer in the central region is retained as a support for carrying the epitaxial base layer;

[0053] A silicon-germanium heterojunction disposed on the upper surface of the epitaxial base layer based on the suspended gap;

[0054] A gate structure disposed on the upper surface of the silicon-germanium heterojunction, and quantum dots are formed in the silicon-germanium heterojunction based on the gate structure.

[0055] In the embodiment of the present application, a suspended gap is formed between the semiconductor substrate and the epitaxial base layer. Through the suspended gap, the stress between the film layers in the semiconductor-on-insulator substrate can be released, and the stress applied by the epitaxial base layer on the silicon-germanium heterojunction during the formation of the silicon-germanium heterojunction can also be released, which can reduce the influence of stress on the device performance.

[0056] In addition, since the suspended gap can reduce the internal stress of the device, the thickness of the buffer layer can be reduced, or the buffer layer can be omitted, thereby reducing the device thickness, reducing the growth time of the epitaxial layer, reducing the thickness of the silicon-germanium buffer layer, and facilitating the integration of the device with other optoelectronic components.

[0057] To make the above objects, features, and advantages of the present application more obvious and understandable, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0058] Refer to Figure 1 , Figure 1 which is a schematic structural diagram of a semiconductor quantum dot device provided by an embodiment of the present application. The semiconductor quantum dot device shown includes:

[0059] A semiconductor-on-insulator substrate 11, the semiconductor-on-insulator substrate 11 includes a semiconductor substrate 111, an insulating layer 112, and an epitaxial base layer 113 stacked in sequence; the insulating layer 112 includes a central region 112a and an edge region 112b surrounding the central region 112a; the edge region 112b is etched to remove the insulating layer 112 to form a suspended gap 13 on the lower surface of the epitaxial base layer 113, and the suspended gap 13 is used for releasing the stress at the interface between the epitaxial base layer 113 and the insulating layer 112; the insulating layer 112 in the central region 112a is retained as a support for carrying the epitaxial base layer 113;

[0060] A silicon-germanium heterojunction 14 disposed on the upper surface of the epitaxial base layer 113 based on the suspended gap 13;

[0061] The gate structure 15 disposed on the upper surface of the silicon-germanium heterojunction 14 forms quantum dots within the silicon-germanium heterojunction based on the gate structure.

[0062] In the semiconductor quantum dot device provided by the embodiment of the present application, through the suspension gap 13, the stress between the epitaxial base layer 113 and the insulating layer 112 can be eliminated, and the stress applied by the insulating layer 112 to the epitaxial base layer 113 can be prevented from affecting the epitaxial quality of the silicon-germanium heterojunction 14, thereby improving the device performance.

[0063] In addition, the epitaxial base layer 113 around the support body can increase the flexible bending ability based on the suspension gap 13, making the epitaxial base layer 113 equivalent to a flexible substrate. Therefore, when forming the silicon-germanium heterojunction 14 on the upper surface of the epitaxial base layer 113 with the suspension gap 13, the stress generated due to lattice mismatch at the interface between the epitaxial base layer 113 and the insulating layer 112 can be released, reducing the stress, reducing the dislocations generated due to the interface stress, further improving the epitaxial quality of the silicon-germanium heterojunction, and further improving the device performance.

[0064] Young's modulus is a measure of the stiffness of a solid under load or its resistance to elastic deformation, which relates stress (force per unit area) to strain (proportional deformation) along an axis or line. The basic principle is that materials undergo elastic deformation when compressed or stretched and return to their original shape after the load is removed. More deformation occurs in flexible materials compared to rigid materials. A low Young's modulus value indicates that the solid is elastic, while a high Young's modulus value indicates that the solid is inelastic or hard.

[0065] The Young's modulus of single-crystalline silicon is 104 GPa, the Young's modulus of silicon dioxide is 71 GPa, the Young's modulus of porous silicon is 11 GPa - 17 GPa, and the Young's modulus of air (at room temperature of 20 °C) is 0.0001 GPa. Among them, 1 GPa = 10 9 N / m 2 In the embodiment of the present application, by forming the suspension gap 13 in the epitaxial base layer 113, it is equivalent to forming an elastic air cushion at the suspension gap 13, which can make the epitaxial base layer 113 equivalent to a flexible substrate and release stress through its own deformation during the growth of the silicon-germanium heterojunction 14.

[0066] In the semiconductor quantum dot device provided by the embodiment of the present application:

[0067] On the one hand, the suspension gap 13 can release the stress between the epitaxial base layer 113 and the insulating layer 112 in the semiconductor-on-insulator substrate 11, and can release the stress between the film layers during the preparation of the semiconductor-on-insulator substrate 11.

[0068] On the other hand, based on the suspension space gap 13, the epitaxial base layer 113 can be equivalent to a flexible substrate, and the flexible characteristics of the flexible substrate can release the stress exerted by the epitaxial base layer 113 on the silicon-germanium heterojunction during the formation of the silicon-germanium heterojunction 14.

[0069] In the embodiment of the present application, the silicon-germanium heterojunction 14 may include Si 1-x Ge x / Ge / Si 1-x Ge x heterojunction, or Si 1-x Ge x / Si / Si 1-x Ge x heterojunction.

[0070] Refer to Figure 2 , Figure 2 which is a schematic structural diagram of another semiconductor quantum dot device provided by the embodiment of the present application. Based on any of the above embodiments, the silicon-germanium heterojunction 14 includes:

[0071] A silicon-germanium buffer layer 141 disposed on the upper surface of the epitaxial base layer 113;

[0072] A silicon-germanium relaxation layer 142 disposed on the upper surface of the silicon-germanium buffer layer 141;

[0073] A well layer 143 disposed on the upper surface of the silicon-germanium relaxation layer 142, and quantum dots are located in the well layer 143;

[0074] A silicon-germanium spacer layer 144 disposed on the upper surface of the well layer 143; both the silicon-germanium relaxation layer 142 and the silicon-germanium spacer layer 144 are Si 1-x Ge x film layers; where x is a constant related to the material of the epitaxial base layer 113;

[0075] A cap layer 145 disposed on the upper surface of the silicon-germanium spacer layer 144.

[0076] In Figure 2 the shown manner, a silicon-germanium buffer layer 141 is disposed between the epitaxial base layer 113 and the silicon-germanium relaxation layer 142. Through the synergistic action of the suspension space gap 13 and the silicon-germanium buffer layer 141, the stress between the film layers inside the device can be better released, and a high-quality silicon-germanium relaxation layer 142 with a high relaxation degree can be epitaxially grown. Based on this, a strained single-crystal layer (single-crystalline silicon layer or single-crystalline silicon-germanium layer) of this quality can be further epitaxially grown as the well layer 143, which can be used to form a high-quality semiconductor quantum dot device.

[0077] In addition, due to the existence of the suspension gap 13 that can release stress, the thickness of the silicon-germanium buffer layer 141 can be reduced, thereby reducing the device thickness. The growth time of the relaxed epitaxial layer (silicon-germanium relaxed layer 142) can be decreased, and the thickness of the silicon-germanium buffer layer can be minimized, facilitating the integration of the device with other optoelectronic components.

[0078] Based on the above description, it can be seen that in the embodiments of the present application, by setting the suspension gap 13, the thickness of the silicon-germanium buffer layer 141 can be reduced. Therefore, the problem of relatively large surface roughness caused by the excessive thickness of the silicon-germanium buffer layer 141 can be prevented, the surface roughness of the silicon-germanium buffer layer 141 can be decreased, the growth thickness and growth time of the silicon-germanium buffer layer 141 can be reduced, and the device cost can be lowered. The smaller surface roughness also facilitates the subsequent integration of the device.

[0079] Among them, by setting the suspension gap 13, the silicon-germanium buffer layer 141 can be reduced to less than 1 μm, and the thickness of the silicon-germanium buffer layer 141 can be made less than 1 μm. Compared with the conventional buffer layer with a thickness of 1 μm to 2 μm, the thickness of the buffer layer can be significantly reduced. In the embodiments of the present application, when the thickness of the silicon-germanium buffer layer 141 is equal to 300 nm, a silicon-germanium relaxed layer 142 with a relaxation degree of 89% can be obtained, and the dislocation density of the silicon-germanium relaxed layer 142 is small.

[0080] As described above, since the stress between the film layers in the device is released through the suspension gap 13, in one implementation of the embodiments of the present application, a silicon-germanium relaxed layer 142 with a fixed Ge component can be directly prepared on the epitaxial base layer 113, and at this time, there is no need to set the silicon-germanium buffer layer 141.

[0081] In one implementation of the embodiments of the present application, the semiconductor-on-insulator substrate 11 can be a silicon-on-insulator (SOI) substrate, and the epitaxial base layer 113 is a single-crystalline silicon layer; the well layer 143 is a single-crystalline silicon layer and is used to form silicon quantum dots. In this way, the semiconductor quantum dot device is a silicon-based device with silicon quantum dots. The bandgap width of silicon element is relatively wide, about 1.12 electron volts, which is suitable for high-temperature and strong-radiation environments. Silicon quantum dots have good compatibility with modern semiconductor manufacturing processes.

[0082] If the epitaxial base layer 113 is a single-crystalline silicon layer, then 0 < x < 0.4. When the epitaxial base layer 113 is a single-crystalline silicon layer, silicon quantum dots are formed in the silicon-germanium heterojunction 14. By setting 0 < x < 0.4, the silicon quantum dots in the silicon-germanium heterojunction 14 can form high-performance spin qubits with longer correlation times and good controllability.

[0083] Optionally, in the direction of the epitaxial base layer 113 pointing to the SiGe heterojunction 14, if 0 < x < 0.4, the composition of germanium in the SiGe buffer layer 141 gradually increases, and the germanium composition in the SiGe buffer layer 141 can finally increase to x. At this time, the strain accumulated during the film growth process can be gradually released through the generation of misfit dislocations, so that the dislocations are distributed throughout the SiGe buffer layer 141.

[0084] If 0 < x < 0.4, further, x can be set to 0.1, or 0.15, or 0.2, or 0.3, or 0.35, etc. Taking x = 0.2 as an example, the SiGe heterojunction 14 can have Si 0.8 Ge 0.2 / Si / Si 0.8 Ge 0.2 heterojunction stacked in sequence. This method can release the stress during the film growth process by growing the SiGe buffer layer 141 with gradually increasing germanium composition, so as to improve the quality of the film grown subsequently on the surface of the SiGe buffer layer 141. A SiGe relaxed layer 142 with a relaxation degree of 93% can be formed, and the dislocation density in the SiGe relaxed layer 142 can be effectively reduced.

[0085] In this application, x can also be set to 0.32. At this time, the SiGe heterojunction 14 can have Si 0.68 Ge 0.32 / Si / Si 0.68 Ge 0.32 heterojunction stacked in sequence.

[0086] In this application, x can also be set to 0.3. At this time, the SiGe heterojunction 14 can have Si 0.7 Ge 0.3 / Si / Si 0.7 Ge 0.3 heterojunction stacked in sequence. Si 0.7 Ge 0.3 / Si / Si 0.7 Ge 0.3 For the heterojunction, the thicknesses of the three layers of film from bottom to top can be 300 nm, 10 nm, and 30 nm in sequence.

[0087] When 0 < x < 0.4, the value of x and the thicknesses of each film layer in the SiGe heterojunction 14 can be adjusted according to requirements to optimize the relaxation degree of the film layer and the stress between the film layers. Among them, the thicknesses of each film layer in the SiGe heterojunction 14 and the value of x include but are not limited to the implementation manners provided in the embodiments of this application.

[0088] If 0 < x < 0.4, that is, Si 1-x Ge xThe germanium component in the film layer is less than the silicon component. Using a single-crystalline silicon layer as the epitaxial base layer 113 and the well layer 143, silicon quantum dots with good performance can be formed based on the silicon-germanium heterojunction 14, which can be used for the preparation of high-quality silicon quantum dot devices.

[0089] In an implementation manner of the embodiments of the present application, the semiconductor-on-insulator substrate 11 can also be a germanium-on-insulator (GOI) substrate, the epitaxial base layer 113 is a single-crystalline germanium layer; the well layer 143 is a single-crystalline germanium layer, which is used to form germanium quantum dots. In this way, the semiconductor quantum dot device is a silicon-based device with germanium quantum dots. The germanium element has a relatively narrow bandgap width, about 0.66 electron volts, and can have advantages in applications such as quantum computing that require long-term maintenance of quantum states. Germanium quantum dots are suitable for the fields of quantum computing and quantum information storage due to their long spin relaxation time and quantum decoherence time.

[0090] If the epitaxial base layer is a single-crystalline germanium layer, then 0.6 < x < 0.85. When the epitaxial base layer 113 is a single-crystalline germanium layer, germanium quantum dots are formed in the silicon-germanium heterojunction 14. Setting 0.6 < x < 0.85 can enable the germanium quantum dots in the silicon-germanium heterojunction 14 to form high-performance spin qubits with longer correlation times and good controllability.

[0091] Optionally, in the direction of the epitaxial base layer 113 pointing to the silicon-germanium heterojunction 14, if 0.6 < x < 0.85, the germanium component in the silicon-germanium buffer layer 141 gradually decreases, and the germanium component in the silicon-germanium buffer layer 141 can finally decrease to x. At this time, the strain accumulated during the film growth process can be gradually released through the generation of misfit dislocations, so that the dislocations are distributed throughout the silicon-germanium buffer layer 141.

[0092] If 0.6 < x < 0.85, further, x can be set to 0.65, or 0.7, or 0.75, or 0.77, or 0.8, etc.

[0093] Taking x = 0.8 as an example, the silicon-germanium heterojunction 14 can have Si 0.2 Ge 0.8 / Ge / Si 0.2 Ge 0.8 heterojunction Si 0.2 Ge 0.8 / Ge / Si 0.2 Ge 0.8 The thicknesses of the three film layers in the heterojunction can be 160 nm, 16 nm, and 22 nm in sequence from bottom to top.

[0094] When 0.6 < x < 0.85, the composition of germanium in the silicon-germanium buffer layer 141 gradually decreases. By growing the silicon-germanium buffer layer 141 with a gradually decreasing germanium composition, the stress during the film growth can be released to improve the quality of the film grown subsequently on the surface of the silicon-germanium buffer layer 141.

[0095] In the embodiments of the present application, if both the silicon-germanium relaxation layer 142 and the silicon-germanium spacer layer 144 are Si 1-x Ge x films, when 0.6 < x < 0.85, that is, in the Si 1-x Ge x film, the germanium composition is greater than the silicon composition. Taking the single-crystalline germanium layer as the epitaxial base layer 113 and the well layer 143, good-performance germanium quantum dots can be formed based on the silicon-germanium heterojunction 14, which can be used for the preparation of high-quality germanium quantum dot devices.

[0096] Reference Figure 3 , Figure 3 FIG. Figure 3 shows a schematic structural diagram of another semiconductor quantum dot device provided by the embodiments of the present application. On the basis of any of the above embodiments, Figure 3 in the semiconductor quantum dot device shown, a gate dielectric layer 16 covers the upper surface of the silicon-germanium heterojunction 14. The gate structure 15 includes: a plurality of barrier gates 18 distributed at intervals on the upper surface of the gate dielectric layer 16; energy level gates 17 are respectively arranged between adjacent barrier gates 18; there are a plurality of quantum dots (such as

[0097] shown by the dashed ellipse in Figure 3 FIG.

[0098] In the Figure 3 shown manner, taking the device having 4 energy level gates 17 and correspondingly having 4 quantum dots as an example for illustration. It should be noted that the number of energy level gates 17 and the number of quantum dots can be set according to requirements, and the embodiments of the present application do not limit the number of energy level gates 17 and quantum dots.

[0099] The gate structure 15 includes two types of gates, namely, the energy-level gate 17 and the barrier gate 18. The energy-level gate 17 can control the chemical potential of the quantum dots, and the barrier gate 18 can control the barrier between the quantum dots and the tunneling rate between the quantum dots and the electron reservoir. The semiconductor quantum dot device can adjust the gates so that when only electrons are occupied in the quantum dots, under the action of a set external magnetic field, the spin states of the electrons are split into the spin-up state and the spin-down state. These two spin states can form a good two-level system, which can be used for encoding to form electron spin qubits.

[0100] In an implementation manner of the embodiment of the present application, the insulating isolation layer 19 and the gate dielectric layer 16 can be the same insulating material, such as both being Al2O3 thin films. Using the same material to prepare the insulating isolation layer 19 and the gate dielectric layer 16 is convenient for the preparation of the semiconductor quantum dot device. Moreover, using the same insulating material for the insulating isolation layer 19 and the gate dielectric layer 16 can make the insulating isolation layer 19 and the gate dielectric layer 16 have better consistency and can improve the device performance.

[0101] Reference Figure 4 , Figure 4 is a schematic structural diagram of another semiconductor quantum dot device provided by the embodiment of the present application. Based on any of the above implementation manners, Figure 4 In the semiconductor quantum dot device shown, within the suspension gap 13, the side walls of the support body, the upper surface of the semiconductor substrate 111, and the lower surface of the epitaxial base layer 113 are all covered with an inner gap layer 20; among them, there is a distance H between the inner gap layer 20 on the upper surface of the semiconductor substrate 111 and the inner gap layer 20 on the lower surface of the epitaxial base layer 113.

[0102] As Figure 4 shown, on the left and right sides of the remaining insulating layer 112 serving as the support body, the inner gap layer 20 covering the surface of the suspension gap 13 can form two symmetric elastic support members on the left and right. The support member includes: a first part that covers the upper surface of the semiconductor substrate 111; a second part that covers the lower surface of the epitaxial base layer 113; and a third part that covers the side wall of the support body. The three parts of the support member can form a C-shaped elastic support structure. Based on the distance H, the opposite first part and second part can release stress in the vertical direction. This method can form an elastic support structure through the inner gap layer 20. On the basis of ensuring the flexible characteristics of the epitaxial base layer 113, it can also provide a support force for the area above the suspension gap 13. During the growth process of the silicon-germanium heterojunction 14, as the thickness and weight of the film layer above the epitaxial base layer 113 increase, it can prevent the device from collapsing in this area.

[0103] In an implementation manner of the embodiment of the present application, the inner spacer layer 20 can be formed synchronously with at least one of the film layers in the silicon-germanium heterojunction 14. In this way, the inner spacer layer 20 can be formed synchronously during the preparation of the silicon-germanium heterojunction 14, and there is no need to separately prepare the inner spacer layer 20, which can simplify the preparation process and reduce the manufacturing cost.

[0104] In other implementation manners, the inner spacer layer 20 can also be prepared first before forming the silicon-germanium heterojunction 14. After forming the inner spacer layer 20, the silicon-germanium heterojunction 14 is started to be prepared on the epitaxial substrate 113.

[0105] In the embodiment of the present application, the silicon-germanium heterojunction 14 can be formed through the suspended gap 13, which can effectively release the stress in the device. Through the relatively thin silicon-germanium buffer layer 141, a silicon-germanium relaxed layer 142 with a relaxation degree reaching 93% or even higher can be obtained, which can effectively reduce the dislocation density in the silicon-germanium relaxed layer 142. Based on the high lattice quality silicon-germanium relaxed layer 142, high-quality quantum dot-in-well layers 143, silicon-germanium spacer layers 144, and cap layers 145 can be sequentially formed on its surface.

[0106] Therefore, the technical solution of the embodiment of the present application can form a silicon-germanium relaxed layer 142 with a high relaxation degree. Further, based on the surface of the high-relaxation-degree silicon-germanium relaxed layer 142, quantum dot-in-well layers 143, silicon-germanium spacer layers 144, and cap layers 145 with relatively high epitaxial quality can be sequentially formed, and a high-quality silicon-germanium heterojunction 14 can be formed. The preparation method of the device is simple, the overall thickness is small, the film growth time is short, and the production cost is low.

[0107] In the embodiment of the present application, the quantum dot-in-well layer 143 can form two-dimensional carrier gases with the silicon-germanium relaxed layers 142 and the silicon-germanium spacer layers 144 on its upper and lower sides respectively. If the quantum dot-in-well layer 143 is a single-crystalline silicon layer, the two-dimensional carrier is a silicon electron gas. If the quantum dot-in-well layer 143 is a single-crystalline germanium layer, the two-dimensional carrier gas is a germanium hole gas.

[0108] Experimentally, the quality of the two-dimensional carrier gas is generally judged by measuring the low-temperature Hall mobility. Factors such as the material interface quality, uniformity, internal background impurities, and defects that affect the mobility will have an impact on the performance of the quantum dot device. Generally speaking, under the same device structure, a higher mobility indicates less scattering of carriers, a more "pure" two-dimensional carrier gas system, less background noise for quantum dots, and higher uniformity, which is helpful for the subsequent integration of quantum dot devices.

[0109] Since the semiconductor quantum dot device provided by the embodiment of the present application can eliminate the stress between the epitaxial base layer 113 and the insulating layer 112 through the suspended space gap 13, a high-quality silicon-germanium heterojunction 14 can be obtained, and the two-dimensional carrier gas performance in the silicon-germanium heterojunction 14 can be optimized and improved. Therefore, the formed quantum dots are less affected by background noise and have higher uniformity, which is helpful for the subsequent integration of quantum dot devices.

[0110] In the semiconductor quantum dot device, the epitaxial base layer 113, the well layer 143, and the cap layer 145 are all single-crystalline semiconductor layers. In the embodiment of the present application, it is set that the epitaxial base layer 113, the well layer 143, and the cap layer 145 are all single-crystalline semiconductor layers in decreasing order, that is, the thickness of the epitaxial base layer 113 is greater than the thickness of the well layer 143, and the thickness of the well layer 143 is greater than the thickness of the cap layer 145. This can further improve the film crystal quality in the silicon-germanium heterojunction 14 and optimize the quantum dot performance in the device.

[0111] Based on the semiconductor quantum dot device provided in the above embodiment, another embodiment of the present application further provides a preparation method, which can be used to prepare the semiconductor quantum dot device provided in any one of the above embodiments. The preparation method can be as Figures 5 - 12 shown.

[0112] Refer to Figures 5 - 12 , Figures 5 - 12 which is the product structure diagram of a semiconductor quantum dot device preparation method provided by the embodiment of the present application in different process steps. The shown preparation method includes:

[0113] Step S11: As Figure 5 and Figure 6 shown, provide a semiconductor-on-insulator substrate 11, and the semiconductor-on-insulator substrate 11 includes a semiconductor substrate 111, an insulating layer 112, and an epitaxial base layer 113 that are stacked in sequence.

[0114] Optionally, in the semiconductor-on-insulator substrate 11, the thickness of the insulating layer 112 can be 1 μm to 2 μm; the thickness of the epitaxial base layer 113 can be 10 nm to 30 nm. As described above, if a silicon-on-insulator substrate is used, the epitaxial base layer 113 is a single-crystalline silicon layer, and if a germanium-on-insulator substrate is used, the epitaxial base layer 113 is a single-crystalline germanium layer.

[0115] Among them, Figure 5 is the cross-sectional view of the semiconductor-on-insulator substrate 11 along the thickness direction, Figure 6 is the top view of the insulating layer 112 in the semiconductor-on-insulator substrate 11. The insulating layer 112 includes a central region 112a and an edge region 112b surrounding the central region 112a.

[0116] In the embodiments of the present application, the semiconductor-on-insulator substrate 11 may be provided to include a plurality of device regions arranged in an array. In each device region, the insulating layer 112 includes a central region 112a and an edge region 112b surrounding the central region 112a.

[0117] Step S12: As Figure 7 and Figure 8 shown, etch away the insulating layer 112 in the edge region 112b to form a suspended gap 13 on the lower surface of the epitaxial base layer 113 for releasing the stress at the interface between the epitaxial base layer 113 and the insulating layer 112; wherein, the insulating layer 112 in the central region 112a serves as a support for carrying the epitaxial base layer 113.

[0118] Wherein, Figure 7 is a top view of etching the semiconductor-on-insulator substrate 11 to form the suspended gap 13, Figure 8 is Figure 7 a cross-sectional view along the A-A' direction. As Figure 7 shown, a plurality of independent suspended device structures can be formed on the semiconductor-on-insulator substrate 11, and a plurality of semiconductor quantum dot devices can be simultaneously fabricated based on the same semiconductor-on-insulator substrate 11.

[0119] In step S12, the epitaxial base layer 113 may be etched first to etch it into a plurality of separated base units 113a. The base unit 113a may be a rectangle as Figure 7 shown, with a length of 15 μm to 20 μm and a width of 5 μm.

[0120] In the same semiconductor quantum dot device, the larger the aspect ratio of the length to the width of the epitaxial base layer 113, the more dislocations can be restricted, and a higher-quality silicon-germanium heterojunction 14 can be formed. Optionally, in the embodiments of the present application, it is set that in the same semiconductor quantum dot device, the aspect ratio of the length to the width of the epitaxial base layer 113 is not less than 3, that is, the aspect ratio of the length to the width of the base unit 113a is not less than 3.

[0121] After the etching of the epitaxial base layer 113 is completed, the insulating layer 112 is etched, and only the insulating layer 112 in the central region 112a is retained, and the insulating layer 112 in other regions is removed, and a suspended structure as Figure 8 shown can be formed. This suspended structure can release the stress generated due to lattice mismatch at the interface between the epitaxial base layer 113 and the insulating layer 112, and can avoid the generation of dislocations during the subsequent thin film growth process.

[0122] Step S13: As Figures 9 - 12 shown, based on the suspended gap 13, a silicon-germanium heterojunction 14 is formed on the upper surface of the epitaxial base layer 113.

[0123] In step S13, first as Figure 9As shown, a silicon-germanium buffer layer 141 is formed on the upper surface of the epitaxial substrate 113; then, as Figure 10 shown, a silicon-germanium relaxed layer 142 is formed on the upper surface of the silicon-germanium buffer layer 141; then, as Figure 11 shown, a well layer 143 is formed on the upper surface of the silicon-germanium relaxed layer 142; finally, as Figure 12 shown, a silicon-germanium spacer layer 144 and a cap layer 145 are sequentially formed on the upper surface of the well layer 143.

[0124] As described above, both the silicon-germanium relaxed layer 142 and the silicon-germanium spacer layer 144 are Si 1-x Ge x . If the epitaxial substrate 113 is a single-crystalline silicon layer, then 0 < x < 0.4, and further, 0.2 < x < 0.4. As described below, according to the thickness of the epitaxial substrate 113, a silicon-germanium buffer layer 141 with an appropriate thickness and Ge composition can be grown to obtain a silicon-germanium relaxed layer 142 with a relaxation degree close to 100%.

[0125] Step S14: A gate structure 15 is formed on the upper surface of the silicon-germanium heterojunction 14, and quantum dots are formed in the silicon-germanium heterojunction 14 based on the gate structure 15, and a semiconductor quantum dot device with the structure shown in FIG. 4 can be formed.

[0126] Optionally, the thickness ratio of the silicon-germanium buffer layer 141 to the epitaxial substrate 113 is not less than 10. Let the thickness of the silicon-germanium buffer layer 141 be t(SiGe), and the thickness of the epitaxial substrate 113 be t(Si), and t(SiGe) / t(Si) is not less than 10, so that a silicon-germanium relaxed layer 142 with a high relaxation degree can be obtained.

[0127] Refer to Figure 13 , Figure 13 which is a curve of the thickness and relaxation degree of an epitaxial substrate and a silicon-germanium buffer layer provided by an embodiment of the present application. The horizontal axis is t(SiGe) / t(Si), and the vertical axis is the relaxation degree of the silicon-germanium relaxed layer 142. Figure 13 In

[0128] a single-crystalline silicon layer is used as the epitaxial substrate 113.

[0129] If t(SiGe) = 94 nm, t(Si) = 116 nm, t(SiGe) / t(Si) = 0.81, the relaxation degree is 45%.

[0130] If t(SiGe) = 290 nm, t(Si) = 33 nm, t(SiGe) / t(Si) = 8.79, the relaxation degree is 88%.

[0131] If t(SiGe) = 324 nm, t(Si) = 27 nm, t(SiGe) / t(Si) = 12, the relaxation degree is 92%.

[0132] Based on Figure 13 it can be known that the larger t(SiGe) / t(Si) is, the larger the relaxation degree of the silicon-germanium relaxation layer 142 is. When t(SiGe) / t(Si) is not less than 10, the relaxation degree can reach more than 90%. Optionally, in the embodiments of the present application, t(SiGe) / t(Si) can be set to be not less than 12 so that the relaxation degree reaches more than 92%.

[0133] In the embodiments of the present application, the relaxation degree can be further optimized and improved to reach a relaxation degree close to 100% by adjusting the Ge component while the thickness ratio of the silicon-germanium buffer layer 141 to the epitaxial base layer 113 is small.

[0134] For example, when a single-crystalline silicon layer with a thickness of 27 nm is used as the epitaxial base layer 113 and x = 0.32, gradually increasing the Ge component in the silicon-germanium buffer layer 141 to 0.32, a silicon-germanium buffer layer 141 with a thickness greater than 160 nm can be used to finally form a Si 0.68 Ge 0.32 film layer. Based on this, further grow a Si 0.68 Ge 0.32 film layer as the silicon-germanium relaxation layer 142, and a silicon-germanium relaxation layer 142 with a relaxation degree close to 100% can be obtained.

[0135] As the thickness of the silicon-germanium buffer layer 141 increases, when a fully relaxed Si 0.68 Ge 0.32 film layer is formed in the silicon-germanium buffer layer 141, and then continue to epitaxially grow a Si 0.68 Ge 0.32 film layer as the silicon-germanium relaxation layer 142, the thickness of the silicon-germanium relaxation layer 142 can be 300 nm, and a high-quality and high-relaxation-degree silicon-germanium relaxation layer 142 can be formed.

[0136] After forming a certain thickness of Si 0.68 Ge 0.32 film layer as the silicon-germanium relaxation layer 142, epitaxially grow a single-crystalline silicon layer on the upper surface of the silicon-germanium relaxation layer 142 as the well layer 143. Based on the fully relaxed Si 0.68 Ge 0.32 film layer to form a single-crystalline silicon layer, a high-strain single-crystalline silicon layer can be obtained. The greater the strain of the single-crystalline silicon layer, the higher the mobility, and the silicon electron gas can be localized in the single-crystalline silicon layer.

[0137] After forming the well layer 143, continue to epitaxially grow a certain thickness of Si 0.68 Ge 0.32The film layer serves as the silicon-germanium spacer layer 144, and then a single-crystalline silicon layer with a thickness of 2 nm is epitaxially grown on the surface of the silicon-germanium spacer layer 144 as the cap layer 145. The cap layer 145 can prevent the film layer below it from being oxidized. Finally, a gate structure is fabricated on the cap layer 145 to form Figures 1 - 4 the semiconductor quantum dot device shown.

[0138] If a germanium-on-insulator substrate is used, the epitaxial base layer 113 is a single-crystalline germanium layer, 0.6 < x < 0.85. In the silicon-germanium film layer above the epitaxial base layer 113, the Ge component is relatively large. The value range of x can be set to 7 - 8. For example, when x = 8, the fully relaxed silicon-germanium film layer finally formed by the silicon-germanium buffer layer 141 is Si 0.2 Ge 0.8 , and both the silicon-germanium relaxation layer 142 and the silicon-germanium spacer layer 144 are Si 0.2 Ge 0.8 film layers. In this method, the epitaxial base layer 113 can be a single-crystalline germanium layer with a thickness of 30 nm. Due to the relatively large Ge component, when the thickness of the silicon-germanium buffer layer 141 is 160 nm, a fully relaxed Si 0.2 Ge 0.8 film layer can be obtained. Based on this, further epitaxy can form a high-relaxation Si 0.2 Ge 0.8 film layer as the silicon-germanium relaxation layer 142.

[0139] After the silicon-germanium buffer layer 141 forms a fully relaxed Si 0.2 Ge 0.8 film layer, the epitaxy can continue with the same concentration to form a Si 0.2 Ge 0.8 film layer with a thickness of 160 nm as the silicon-germanium relaxation layer 142. Then, a fully strained single-crystalline silicon germanium with a thickness of 16 nm after epitaxy is formed on the surface of the silicon-germanium relaxation layer 142 as the well layer 143. Further, a Si 0.2 Ge 0.8 film layer with a thickness of 22 nm is epitaxially grown on the surface of the well layer 143 as the silicon-germanium spacer layer 144. Finally, a 1-nm single-crystalline silicon layer is formed on the surface of the silicon-germanium spacer layer 144 as the cap layer 145. A gate structure is fabricated on the surface of the cap layer 145 to form Figures 1 - 4 the semiconductor quantum dot device shown.

[0140] As can be seen from the above description, based on the preparation method provided in the embodiments of the present application, the semiconductor quantum dot device provided in the above embodiments can be prepared. By forming a suspended space gap 13 under the surface of the epitaxial base layer 113, the thickness of the silicon-germanium buffer layer 141 can be reduced. A fully relaxed silicon-germanium film layer can be formed with a relatively thin silicon-germanium buffer layer 141. Further, a silicon-germanium relaxation layer 142 with a high relaxation degree can be formed on the silicon-germanium buffer layer 141 to form a high-quality silicon-germanium heterojunction 14. This preparation method can reduce the growth time of the epitaxial layer and facilitate the integration of the device with other optoelectronic components.

[0141] The embodiments in the specification of the present application are described in a progressive, or parallel, or a combination of progressive and parallel manners. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. The embodiments provided in the embodiments of the present application can be combined with each other without conflict.

[0142] It should be noted that in the description of the present application, it should be understood that the descriptions of the drawings and embodiments are illustrative rather than restrictive. The same reference numerals throughout the embodiments of the specification identify the same structures. Additionally, for the sake of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. At the same time, it can be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element can be directly on the other element or there may be intervening elements. Further, "on" means positioning the element on or under another element, but does not inherently mean positioning on the upper side of another element according to the direction of gravity.

[0143] The orientation or positional relationship indicated by the terms "upper", "lower", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be intervening components present.

[0144] It should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that an article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or elements inherent to such article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the article or device comprising the above elements.

[0145] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor quantum dot device, characterized in that, Comprising: A semiconductor-on-insulator substrate, which includes a semiconductor substrate, an insulating layer, and an epitaxial base layer stacked in sequence; The insulating layer includes a central region and an edge region surrounding the central region; the edge region is etched to remove the insulating layer, so as to form a suspended gap on the lower surface of the epitaxial base layer for releasing the stress at the interface between the epitaxial base layer and the insulating layer; the insulating layer in the central region is retained as a support for carrying the epitaxial base layer; Based on the suspended gap, a silicon-germanium heterojunction is provided on the upper surface of the epitaxial base layer; A gate structure is provided on the upper surface of the silicon-germanium heterojunction, and quantum dots are formed in the silicon-germanium heterojunction based on the gate structure.

2. The semiconductor quantum dot device according to claim 1, wherein The silicon-germanium heterojunction includes: A silicon-germanium buffer layer provided on the upper surface of the epitaxial base layer; A silicon-germanium relaxed layer provided on the upper surface of the silicon-germanium buffer layer; A well layer provided on the upper surface of the silicon-germanium relaxed layer, and the quantum dots are located in the well layer; A silicon-germanium spacer layer disposed on the upper surface of the well layer; both the silicon-germanium relaxation layer and the silicon-germanium spacer layer are Si 1-x Ge x film layers; where x is a constant related to the material of the epitaxial base layer; A cap layer provided on the upper surface of the silicon-germanium spacer layer.

3. The semiconductor quantum dot device according to claim 2, wherein The semiconductor-on-insulator substrate is a silicon-on-insulator substrate, and the epitaxial base layer is a single-crystalline silicon layer; The well layer is a single-crystalline silicon layer for forming silicon quantum dots.

4. The semiconductor quantum dot device according to claim 2, wherein The semiconductor-on-insulator substrate is a germanium-on-insulator substrate, and the epitaxial base layer is a single-crystalline germanium layer; The well layer is a single-crystalline germanium layer for forming germanium quantum dots.

5. The semiconductor quantum dot device according to claim 2, characterized in that, If the epitaxial base layer is a single-crystalline silicon layer, then 0 < x < 0.4; If the epitaxial base layer is a single-crystalline germanium layer, then 0.6 < x < 0.

85.

6. The semiconductor quantum dot device according to claim 5, characterized in that, In the direction from the epitaxial base layer to the silicon-germanium heterojunction, if 0 < x < 0.4, the component of germanium element in the silicon-germanium buffer layer gradually increases, and if 0.6 < x < 0.85, the component of germanium element in the silicon-germanium buffer layer gradually decreases.

7. The semiconductor quantum dot device according to claim 1, wherein, The upper surface of the silicon-germanium heterojunction is covered with a gate dielectric layer; The gate structure includes: a plurality of barrier gates spaced apart from each other provided on the upper surface of the gate dielectric layer; energy level gates are respectively provided between adjacent barrier gates; there are a plurality of the quantum dots in the silicon-germanium heterojunction arranged in one-to-one correspondence with the energy level gates; Wherein, the surface of the energy level gate is covered with an insulating isolation layer to isolate the barrier gate from the energy level gate.

8. The semiconductor quantum dot device according to claim 7, characterized in that, The insulating isolation layer and the gate dielectric layer are made of the same insulating material.

9. The semiconductor quantum dot device according to any one of claims 1-8, characterized in that, In the suspended gap, the side wall of the support, the upper surface of the semiconductor substrate, and the lower surface of the epitaxial base layer are all covered with an inner gap layer; Wherein, there is a spacing between the inner gap layers on the upper surface of the semiconductor substrate and the lower surface of the epitaxial base layer.

10. The semiconductor quantum dot device according to claim 9, characterized in that, The inner gap layer is formed synchronously with at least one layer of the film layer in the silicon-germanium heterojunction.

11. A method for preparing a semiconductor quantum dot device according to any one of claims 1-10, characterized in that, Comprising: Providing a semiconductor-on-insulator substrate, which includes a semiconductor substrate, an insulating layer, and an epitaxial base layer stacked in sequence; The insulating layer includes a central region and an edge region surrounding the central region; Etching to remove the insulating layer in the edge region to form a suspended gap on the lower surface of the epitaxial base layer for releasing the stress at the interface between the epitaxial base layer and the insulating layer; wherein, the insulating layer in the central region serves as a support for carrying the epitaxial base layer; Based on the suspension gap, a silicon-germanium heterojunction is formed on the upper surface of the epitaxial base layer; A gate structure is formed on the upper surface of the silicon-germanium heterojunction, and quantum dots are formed in the silicon-germanium heterojunction based on the gate structure.

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