Reinforcement learning-based combinatorial logic clustering optimization method and system

Abstract

The application discloses a kind of based on reinforcement learning's combination logic clustering optimization method and system, method includes: S1, the fan-out information of register and combination logic unit in circuit netlist is counted;S2, according to fan-out information, the register and combination logic unit that the fan-out quantity is greater than first preset threshold and the worst timing path timing violation value of output signal is less than second preset threshold are screened out, and target unit list is generated;S3, the fan-out combination logic information of each unit in target unit list is acquired;S4, based on fan-out combination logic information, based on reinforcement learning algorithm respectively to fan-out logic unit is clustered operation;S5, after completing logic clustering, the netlist of circuit is revised;After revision is completed, equivalence check is carried out;S6, according to the netlist of modification circuit is re-layouted and routed.The application can effectively reduce critical path delay, optimize circuit performance, especially suitable for large-scale integrated circuit design.

Description

Technical Field

[0001] The present invention mainly relates to the field of integrated circuit design, and specifically to a combinational logic clustering optimization method and system based on reinforcement learning. Background Art

[0002] In digital circuit design, in-depth optimization of critical paths is crucial for improving design frequency and performance. As integrated circuit process nodes continue to shrink, circuit size and complexity are rapidly increasing. High fan-out (HFO) registers or combinational logic on critical paths often pose challenges for timing optimization. Currently, commercial electronic design automation (EDA) tools widely use inverter or buffer insertion techniques to optimize the timing paths of high fan-out registers. However, this traditional approach has significant drawbacks in practical applications, specifically the following two aspects:

[0003] (1) The position and number of inverter / buffer insertion are unreasonable

[0004] Commercial EDA tools typically insert inverters / buffers based on fixed rules or heuristic algorithms. For example, during global optimization, the tool may blindly insert inverters / buffers into non-critical paths, resulting in wasted area and power. On critical paths, due to a lack of in-depth analysis of logic structure dependencies and physical layout, the number of inserted inverters / buffers may be insufficient or unevenly distributed, failing to effectively reduce signal transmission delay. Furthermore, traditional methods lack the ability to dynamically adjust the number of inverters / buffers inserted, making them difficult to meet the demands of high-performance designs. Excessive insertion can easily lead to routing congestion and increased latency.

[0005] (2) Existing technologies lack intelligent optimization capabilities

[0006] Traditional methods rely on static rules or empirical formulas and are unable to adaptively adjust optimization strategies based on information such as the functional relevance of circuit logic units, physical layout density, and signal timing delays. This results in multi-objective optimization imbalances such as routing conflicts and increased timing delays due to factors such as grouping and position of inserted inverters / buffers.

[0007] In recent years, reinforcement learning (RL) technology has demonstrated significant advantages in solving complex decision-making problems. By interacting with the environment and dynamically adjusting strategies based on feedback rewards, RL can effectively solve high-dimensional, multi-constrained optimization problems. In the field of timing optimization, some research has attempted to apply RL to the place-and-route stage, but its application remains limited to local adjustments and has yet to fully integrate the coordinated optimization of logic structure clustering and inverter / buffer insertion. Therefore, there is an urgent need for an intelligent optimization method based on RL to address the inherent shortcomings of traditional inverter / buffer insertion techniques and achieve precise optimization of critical path timing. Summary of the Invention

[0008] In response to the technical problems existing in the prior art, the present invention provides a combinational logic clustering optimization method and system based on reinforcement learning for achieving efficient optimization of critical path timing.

[0009] In order to solve the above technical problems, the technical solution proposed by the present invention is:

[0010] A combination logic clustering optimization method based on reinforcement learning, comprising the steps of:

[0011] S1. Count the fan-out information of registers and combinational logic units in the circuit netlist;

[0012] S2. Based on the fan-out information in step S1, screen out registers and combinational logic units whose fan-out quantity is greater than a first preset threshold and whose worst timing path timing violation value of the output signal is less than a second preset threshold, and generate a target unit list;

[0013] S3. Obtain fan-out combinational logic information of each unit in the target unit list;

[0014] S4. Based on the fan-out combinational logic information, the fan-out logic units are clustered using a reinforcement learning algorithm.

[0015] S5. After completing the logic clustering, revise the circuit netlist; after the revision is completed, perform an equivalence check;

[0016] S6. Re-layout and re-route the circuit according to the modified netlist.

[0017] Preferably, the specific steps of S1 are:

[0018] S101, traverse all registers and combinational logic units in the circuit netlist and record the output signal of each unit;

[0019] S102, analyzing the fan-out of the output signal of each unit, including the buffer, inverter, and combinational logic unit, adding the combinational logic unit to list1, and adding the buffer and inverter to list2;

[0020] S103, recursively analyzing the fan-out of the output signals of the buffers and inverters. For each buffer or inverter in list2, traverse to find all the combinational logic units that are directly fanned out, and add them to list1. Then, traverse to find all the buffers and inverters that are directly fanned out; recursively find all the combinational logic units that are finally fanned out, and add them to list1.

[0021] S104: Count the fan-out quantity of each register and combinational logic unit, and generate a fan-out information table.

[0022] Preferably, the specific steps of S3 are:

[0023] For each cell in the target cell list, obtain all logic cells son_cells whose output signals fan out; traverse son_cells, and if the cell type is not a buffer or inverter, add the cell name, corresponding input pin, and cell location information to the list f0_list; if the cell type is a buffer or inverter, recursively search for all non-buffer and non-inverter logic cells that appear for the first time, and then add the cell name, corresponding input pin, and cell location information to the list f0_list and list f1_list respectively according to the phase.

[0024] Preferably, the specific steps of S4 include:

[0025] S401, specify the size of the cluster according to the logic effect and fan-out constraint, denoted as Knum;

[0026] S402, define state space and action space: the state space is the mathematical representation of clusters, and the action space includes three types of actions: changing the cluster affiliation of elements, adding clusters, and deleting clusters;

[0027] S403, defining a reward function based on the time series element and the distance element;

[0028] S404, initializing the number of clusters and the corresponding center coordinates;

[0029] S405, initializing clusters;

[0030] S406, reinforcement learning optimization clustering: using the initial clustering as the initial state space, optimization is performed through reinforcement learning. The optimization stops when the optimization result meets the expectation, and the final state is used as the final clustering result;

[0031] S407. Record cluster information: record the final number of clusters final_cl_num corresponding to each unit in the target unit list targetr_list, and the element list in each cluster.

[0032] Preferably, the specific steps of S404 are:

[0033] For each unit in the target unit list target_list, calculate the relationship between the number of elements in the corresponding list f0_list and the list f1_list and the multiple of the cluster size Knum, and the multiple value rounddown(size(f0_list) / Knum) is used as the initial cluster number i0_cl_num corresponding to the list f0_list, where rounddown represents the rounding down function and size represents the function for finding the number of sets;

[0034] Randomly select Knum units from the list f0_list, calculate the mean of their physical positions, and use it as the initial value of the center coordinates of the current cluster. Repeat this process i0_cl_num times to obtain the initial values ​​of the center coordinates of all clusters.

[0035] Preferably, the specific steps of S405 are:

[0036] Traverse each unit in the list f0_list and the list f1_list, calculate the Manhattan distance between its physical position and the initial value of the center coordinate of each cluster cluster in turn, classify the unit into the cluster with the shortest Manhattan distance, then recalculate the mean of the physical position of the logical unit in each cluster cluster, and use this mean to update the center coordinate of the cluster cluster.

[0037] Preferably, the specific steps of S5 are:

[0038] S501, for each cell cell0 in the target cell list target_list and its corresponding cluster, first disconnect the original connection of each cell input pin in the cluster;

[0039] S502. For each cluster, determine the phase relationship between its phase and the output of cell0: if the cluster is in phase with the output of cell0, insert a buffer between the output of cell0 and the cluster, and connect the output of the buffer to the input pin of each unit in the cluster; if the cluster is in anti-phase with the register output, insert an inverter, and connect the output of the inverter to the input pin of each unit in the cluster;

[0040] S503, connecting the input of the inserted buffer or inverter to the output of cell0, and removing other inverter or buffer loads on the register output;

[0041] S504, saving the modified netlist;

[0042] S505: Perform an equivalence check; if the check passes, the process ends; otherwise, return to S502 to modify the connection relationship.

[0043] The present invention also discloses a combination logic clustering optimization system based on reinforcement learning, comprising a memory and a processor connected to each other, wherein a computer program is stored on the memory, and when the computer program is run by the processor, the steps of the above method are executed.

[0044] Compared with the prior art, the advantages of the present invention are:

[0045] This method optimizes critical path timing and improves circuit performance by collecting register and combinational logic fan-out information, generating a target unit list, obtaining target unit fan-out combinational logic information, implementing reinforcement learning-driven combinational logic clustering, revising the netlist and performing equivalence checks, and using the new netlist for layout and routing. This method effectively reduces critical path delays and optimizes circuit performance, making it particularly suitable for large-scale integrated circuit design.

[0046] The present invention's reinforcement learning-based combinatorial logic clustering optimization method automatically identifies critical timing paths by statistically analyzing fan-out information for all units encompassing registers and combinatorial logic and generating a list of target units. It then clusters these units using a reinforcement learning approach and then inserts inverters or buffers based on the clustering information, effectively avoiding irrational inverter or buffer insertion and improving delays in critical paths with large fan-out. The present invention implements logic clustering based on reinforcement learning, allowing inverters or buffers to be driven nearby in the physical layout, effectively reducing the length of the timing paths in critical paths with large fan-out, thereby improving circuit performance. The method is particularly suitable for large-scale integrated circuit design.

[0047] The present invention introduces reinforcement learning technology to propose a new solution to the two major defects of existing commercial EDA tools in processing large fan-out units, namely, unreasonable insertion positions of inverters / buffers and lack of consideration of physical factors. The present invention can accurately locate the list of large fan-out units on the critical path, and adopts a combination of reinforcement learning and clustering to effectively consider the influence of physical factors, shorten the critical path distance, and reduce the risk of signal propagation delay and wiring congestion. The present invention has high reliability and ensures the consistency of optimized circuit functions through equivalence checks. The combinational logic clustering optimization method and system based on reinforcement learning support integration with mainstream EDA tools and are suitable for large-scale circuit design. Under a sub-20 nanometer process, the method was implemented on a certain core module, and the maximum setup timing violation was reduced by 13ps, and the number of timing violations was reduced by 12.3%, which greatly improved the design performance. The advantage of this method is that it can be extended to other optimization scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 A flowchart of a combinational logic clustering optimization method based on reinforcement learning is provided for an embodiment of the present invention.

[0049] Figure 2 This is a flowchart of the reinforcement learning-driven combinational logic clustering provided by an embodiment of the present invention.

[0050] Figure 3 This is a flowchart of the first-level combinational logic clustering provided by an embodiment of the present invention.

[0051] Figure 4 This is a flow chart of modifying a netlist after clustering provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0053] like Figure 1 As shown, the combination logic clustering optimization method based on reinforcement learning provided by the embodiment of the present invention includes the following steps:

[0054] S1. Count the fan-out information of registers and combinational logic units in the circuit netlist. In the circuit netlist, registers and combinational logic units account for more than 90% of the number of units.

[0055] S2. Generate a target unit list: Based on the fan-out information generated in S1, and according to the timing analysis results, screen out registers and combinational logic units that have a greater impact on the timing path, and generate a target unit list. Specifically, for each register or combinational logic unit whose fan-out number exceeds a first preset threshold, check the worst timing path timing violation value of the output signal through the register or combinational logic unit to see if it is lower than a second preset threshold. If so, add it to the target unit list target_list.

[0056] S3. Get the target unit fan-out combinational logic information: For each unit in the target unit list target_list, get all the logic units son_cells whose output signals fan out; traverse son_cells, and if the unit type is not a buffer or inverter, add the unit name, corresponding input pin, and unit position information to f0_list; if the unit type is a buffer or inverter, recursively search for all the first-appearing non-buffer and non-inverter logic units (i.e., combinational logic units and sequential logic units other than buffers and inverters), and then add the unit name, corresponding input pin, and unit position information to the list f0_list and list f1_list respectively according to the phase;

[0057] S4. Implement reinforcement learning-driven combinatorial logic clustering: Based on the fan-out combinatorial logic information obtained in S3, the fan-out logic units are clustered using a reinforcement learning algorithm. The clustering algorithm groups physically adjacent logic units that have no negative impact on timing into the same cluster based on their physical location and timing relationships. The clustered logic units can be treated as a whole, facilitating subsequent optimization operations.

[0058] S5. Revise the netlist and perform an equivalence check: After completing the logic clustering, revise the circuit netlist by associating the clustered logic units and adjusting their connections. Netlist revisions can reduce the physical distance of timing paths, thereby optimizing the circuit's timing performance. After the revisions are complete, perform an equivalence check to ensure that the modified circuit functions identically to the original circuit.

[0059] S6. Place and route using the new netlist: Re-place and route the module based on the revised netlist. This re-placement and routing process includes placement, clock tree synthesis, global routing, and detailed routing. During placement, the buffers and inverters inserted in S5 must be configured to not be optimized. The rest of the process remains the same as before.

[0060] In this embodiment, the specific steps of S1 include:

[0061] S101, traverse all registers and combinational logic units in the circuit and record the output signal of each unit;

[0062] S102, analyzing the output signal fan-out of each unit, including buffers, inverters, and combinational logic units, and adding the combinational logic units to list1, and adding the buffers and inverters to list2;

[0063] like Figure 2As shown, in this embodiment, for the combinational logic unit C0, the combinational logic units C1 to C19 whose output signal Z is fanned out are added to list1, and then the buffer Buf1 and the inverter Inv1 are added to list2;

[0064] S103, recursively analyzing the fan-out of the output signals of the buffers and inverters. For each buffer or inverter in list2, traverse to find all the combinational logic units that are directly fanned out, and add them to list1. Then, traverse to find all the buffers and inverters that are directly fanned out, recursively find all the combinational logic units that are ultimately fanned out, and add them to list1.

[0065] like Figure 2 As shown, in this embodiment, for the inverter Inv1, all the combinational logic units D1 to D27 that are fanned out are found and added to list1; for the buffer Buf1, its direct fan-out is an inverter Inv2 and combinational logic units E1 to E33, E1 to E33 are added to list1, and then all the combinational logic units F1 to F25 and G1 to G23 that are finally fanned out are recursively found and also added to list1;

[0066] S104: Count the fan-out quantity of each register and combinational logic unit, and generate a fan-out information table.

[0067] In this embodiment, if Figure 3 As shown, the specific steps of S4 include:

[0068] S401, according to the logic effect and fan-out constraint, specify the size of the cluster, denoted as Knum ;

[0069] S402, define state space and action space: the state space is the mathematical representation of clusters, and the action space includes three types of actions: changing the cluster affiliation of elements, adding clusters, and deleting clusters;

[0070] S403, defining a reward function based on time series factors, distance factors, etc.;

[0071] S404. Initialize the number of clusters and the corresponding center coordinates: For each unit in the target unit list target_list, calculate the relationship between the number of elements in the corresponding f0_list and f1_list and the multiple of the cluster size Knum, and use the multiple value rounddown(size(f0_list) / Knum) as the initial number of clusters i0_cl_num corresponding to f0_list, where rounddown represents the rounding down function and size represents the function for finding the number of sets; randomly select Knum units from f0_list, calculate the mean of their physical positions, and use it as the initial value of the center coordinates of the current cluster. Repeat this process i0_cl_num times to obtain the initial values ​​of the center coordinates of all clusters.

[0072] S405. Initialize clusters: traverse each unit in f0_list and f1_list, calculate the Manhattan distance between its physical location and the center of each cluster in turn, and classify the unit into the cluster with the shortest Manhattan distance. Then recalculate the mean of the physical location of the logical unit in each cluster, and use this mean to update the center coordinates of the cluster.

[0073] S406, reinforcement learning optimization clustering: using the initial clustering as the initial state space, optimization is performed through reinforcement learning. The optimization stops when the optimization result meets the expectation, and the final state is used as the final clustering result;

[0074] S407. Record cluster information: record the final number of clusters final_cl_num corresponding to each unit in the target unit list targetr_list, and the element list in each cluster.

[0075] In this embodiment, the specific steps of S5 include:

[0076] S501, for each cell cell0 in the target_list and its corresponding cluster, first disconnect the original connection of each cell input pin in the cluster;

[0077] S502. For each cluster, determine the phase relationship between its phase and the output of cell0: if the cluster is in phase with the output of cell0, insert a buffer between the output of cell0 and the cluster, and connect the output of the buffer to the input pin of each unit in the cluster; if the cluster is in anti-phase with the register output, insert an inverter, and connect the output of the inverter to the input pin of each unit in the cluster;

[0078] like Figure 4As shown, units D24, D25, D26, and D27 belong to the same cluster as units G20, G21, G22, and G23, and their phases are opposite to that of unit C0. Therefore, an inverter INV_cl1 is inserted, and the output of the inverter is connected to the corresponding input pins of D24 to D27 and G20 to G23.

[0079] S503, connecting the input of the inserted buffer or inverter to the output of cell0, and removing other inverter or buffer loads on the register output;

[0080] S504, saving the modified netlist;

[0081] S505 , use a formal verification tool or a simulation tool to perform an equivalence check; if the check passes, the process ends; otherwise, the process returns to S502 or S503 to correct the connection relationship.

[0082] This method optimizes critical path timing and improves circuit performance by collecting register and combinational logic fan-out information, generating a target unit list, obtaining target unit fan-out combinational logic information, implementing reinforcement learning-driven combinational logic clustering, revising the netlist and performing equivalence checks, and using the new netlist for layout and routing. This method effectively reduces critical path delays and optimizes circuit performance, making it particularly suitable for large-scale integrated circuit design.

[0083] The present invention's reinforcement learning-based combinatorial logic clustering optimization method automatically identifies critical timing paths by statistically analyzing fan-out information for all units encompassing registers and combinatorial logic and generating a list of target units. It then clusters these units using a reinforcement learning approach and then inserts inverters or buffers based on the clustering information, effectively avoiding irrational inverter or buffer insertion and improving delays in critical paths with large fan-out. The present invention implements logic clustering based on reinforcement learning, allowing inverters or buffers to be driven nearby in the physical layout, effectively reducing the length of the timing paths in critical paths with large fan-out, thereby improving circuit performance. The method is particularly suitable for large-scale integrated circuit design.

[0084] The present invention introduces reinforcement learning technology to propose a new solution to the two major defects of existing commercial EDA tools in processing large fan-out units, namely, unreasonable insertion positions of inverters / buffers and lack of consideration of physical factors. The present invention can accurately locate the list of large fan-out units on the critical path, and adopts a combination of reinforcement learning and clustering to effectively consider the influence of physical factors, shorten the critical path distance, and reduce the risk of signal propagation delay and wiring congestion. The present invention has high reliability and ensures the consistency of optimized circuit functions through equivalence checks. The combinational logic clustering optimization method and system based on reinforcement learning support integration with mainstream EDA tools and are suitable for large-scale circuit design. Under a sub-20 nanometer process, the method was implemented on a certain core module, and the maximum setup timing violation was reduced by 13ps, and the number of timing violations was reduced by 12.3%, which greatly improved the design performance. The advantage of this method is that it can be extended to other optimization scenarios.

[0085] The present invention also discloses a reinforcement learning-based combinatorial logic clustering optimization system, comprising an interconnected memory and a processor, wherein the memory stores a computer program that, when executed by the processor, performs the steps of the above-described method. The optimization system of the present invention corresponds to the above-described optimization method and similarly possesses the advantages of the above-described optimization method.

[0086] The present invention can implement all or part of the process steps in the above-described method embodiments through hardware associated with computer program instructions. The computer program can be stored in a computer-readable storage medium. When executed by a processor, the computer program can implement the steps of the above-described method embodiments. The computer program includes computer program code, which can be in source code form, object code form, executable file, or some intermediate form. Computer-readable storage media include any entity or device capable of carrying computer program code, recording media, USB flash drives, removable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media. Memory is used to store computer programs and / or modules. The processor implements various functions by running or executing the computer programs and / or modules stored in the memory and accessing data stored in the memory. The memory may include a high-speed random access memory and may also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, at least one disk storage device, a flash memory device, or other volatile solid-state storage device.

[0087] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions based on the principles of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A combination logic clustering optimization method based on reinforcement learning, characterized in that: Including steps: S1. Count the fan-out information of registers and combinational logic units in the circuit netlist; S2. Based on the fan-out information in step S1, screen out registers and combinational logic units whose fan-out quantity is greater than a first preset threshold and whose worst timing path timing violation value of the output signal is less than a second preset threshold, and generate a target unit list; S3. Obtain fan-out combinational logic information of each unit in the target unit list; S4. Based on the fan-out combinational logic information, the fan-out logic units are clustered using a reinforcement learning algorithm. S5. After completing the logic clustering, revise the circuit netlist; after the revision is completed, perform an equivalence check; S6. Re-layout and re-routing the circuit according to the modified netlist; The specific steps of S3 are: For each cell in the target cell list, obtain all logic cells son_cells whose output signals fan out; traverse son_cells, and if the cell type is not a buffer or an inverter, add the cell name, the corresponding input pin, and the cell location information to the list f0_list; if the cell type is a buffer or an inverter, recursively search for all non-buffer and non-inverter logic cells that appear for the first time, and then add the cell name, the corresponding input pin, and the cell location information of the non-buffer and non-inverter logic cells that appear for the first time to the list f0_list and the list f1_list respectively according to the phase; The specific steps of S4 include: S401, specify the size of the cluster according to the logic effect and fan-out constraint, denoted as Knum; S402, define state space and action space: the state space is the mathematical representation of clusters, and the action space includes three types of actions: changing the cluster affiliation of elements, adding clusters, and deleting clusters; S403, defining a reward function based on the time series element and the distance element; S404, initializing the number of clusters and the corresponding center coordinates; S405, initializing clusters; S406, reinforcement learning optimization clustering: using the initial clustering as the initial state space, optimization is performed through reinforcement learning. The optimization stops when the optimization result meets the expectation, and the final state is used as the final clustering result; S407 , record cluster information: record the final number of clusters final_cl_num corresponding to each unit in the target unit list target_list, and the element list in each cluster.

2. The combinational logic clustering optimization method based on reinforcement learning according to claim 1, characterized in that: The specific steps of S1 are: S101, traverse all registers and combinational logic units in the circuit netlist and record the output signal of each unit; S102, analyzing the fan-out of the output signal of each unit, including the buffer, inverter, and combinational logic unit, adding the combinational logic unit to list1, and adding the buffer and inverter to list2; S103, recursively analyzing the fan-out of the output signals of the buffers and inverters. For each buffer or inverter in list2, traverse to find all the combinational logic units that are directly fanned out by each buffer or inverter in list2, add them to list1, and then traverse to find all the buffers and inverters that are directly fanned out by each buffer or inverter in list2. Recursively find all the combinational logic units that are finally fanned out and add them to list1; S104: Count the fan-out quantity of each register and combinational logic unit, and generate a fan-out information table.

3. The combinational logic clustering optimization method based on reinforcement learning according to claim 1, characterized in that: The specific steps of S404 are: For each unit in the target unit list target_list, calculate the relationship between the number of elements in the corresponding list f0_list and the list f1_list and the multiple of the cluster size Knum, and the multiple value rounddown(size(f0_list) / Knum) is used as the initial cluster number i0_cl_num corresponding to the list f0_list, where rounddown represents the rounding down function and size represents the function for finding the number of sets; Randomly select Knum units from the list f0_list, calculate the mean of their physical positions, and use it as the initial value of the center coordinates of the current cluster. Repeat this process i0_cl_num times to obtain the initial values ​​of the center coordinates of all clusters.

4. The combinational logic clustering optimization method based on reinforcement learning according to claim 3, characterized in that: The specific steps of S405 are: Traverse each unit in the list f0_list and the list f1_list, calculate the Manhattan distance between its physical position and the initial value of the center coordinate of each cluster in turn, classify the unit into the cluster with the shortest Manhattan distance, then recalculate the mean of the physical position of the logical unit in each cluster, and use this mean to update the center coordinate of the cluster.

5. The combinational logic clustering optimization method based on reinforcement learning according to claim 1 or 2, characterized in that: The specific steps of S5 are: S501, for each cell cell0 in the target cell list target_list and its corresponding cluster, first disconnect the original connection of each cell input pin in the cluster; S502. For each cluster, determine the phase relationship between its phase and the output of cell0: if the cluster is in phase with the output of cell0, insert a buffer between the output of cell0 and the cluster, and connect the output of the buffer to the input pin of each unit in the cluster; if the cluster is in anti-phase with the register output, insert an inverter, and connect the output of the inverter to the input pin of each unit in the cluster; S503, connecting the input of the inserted buffer or inverter to the output of cell0, and removing other inverter or buffer loads on the register output; S504, saving the modified netlist; S505: Perform an equivalence check; if the check passes, the process ends; otherwise, return to S502 to modify the connection relationship.

6. A combinational logic clustering optimization system based on reinforcement learning, comprising a memory and a processor connected to each other, wherein a computer program is stored on the memory, characterized in that: When the computer program is executed by a processor, the computer program performs the steps of the method according to any one of claims 1 to 5.

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