Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises a semiconductor substrate, the semiconductor substrate comprises a first region and a second region, a silicon layer is formed on the surface of the semiconductor substrate in the first region, a silicon germanium layer is formed on the surface of the semiconductor substrate in the second region, and the silicon germanium layer is formed on the surface of the semiconductor substrate in the second region. The surface of the silicon layer is flush with the surface of the silicon germanium layer; and the fins are respectively located in the first region and the second region, the heights of the fins in the first region and the second region are the same, the fin in the first region is composed of a part of the semiconductor substrate and the silicon layer, and the fin in the second region is composed of a part of the semiconductor substrate and the silicon germanium layer. According to the semiconductor structure and the forming method thereof, the depths of the silicon fins and the silicon germanium fins can be consistent, and the defects of fin merging, fin bending and the like caused by the fact that the silicon germanium fins are too deep are avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] In the process of a FinFET device with a silicon / silicon germanium double fin structure, the etching depth of the silicon germanium fin is deeper than that of the silicon fin because silicon germanium has a higher etching rate under the commonly used halogen etching gas. This makes the silicon germanium fin prone to defects such as fin merging / fin bending due to the high aspect ratio, especially when forming fin strips in the active area vertical removal (ARV) process.

[0003] Therefore, it is necessary to provide a more reliable and effective technical solution to make the depths of the silicon fin and the silicon germanium fin consistent and avoid defects such as fin merging and fin bending caused by the excessive depth of the silicon germanium fin. Summary of the Invention

[0004] This application provides a semiconductor structure and a method for forming the same, which can make the depths of the silicon fin and the silicon germanium fin consistent and avoid defects such as fin merging and fin bending caused by the excessive depth of the silicon germanium fin.

[0005] One aspect of this application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, the semiconductor substrate including a first region and a second region, a silicon layer being formed on the surface of the semiconductor substrate in the first region, and a silicon germanium layer being formed on the surface of the semiconductor substrate in the second region, the surfaces of the silicon layer and the silicon germanium layer being flush; forming a patterned mask layer on the surfaces of the silicon layer and the silicon germanium layer, the patterned mask layer defining the positions of the fins; performing a first etching process to make the surface of the silicon layer exposed by the patterned mask layer lower than the surface of the silicon germanium layer; using the patterned mask layer as a mask to perform a second etching process to etch the silicon layer and the silicon germanium layer into the semiconductor substrate to form fins in the first region and the second region respectively, and the fins in the first region and the second region having the same height.

[0006] In some embodiments of this application, the first etching process includes: forming a hard mask layer covering the second region on the semiconductor substrate; etching the silicon layer in the first region to make the surface of the silicon layer exposed by the patterned mask layer lower than the surface of the silicon germanium layer.

[0007] In some embodiments of this application, the etching selectivity of the first etching process for the silicon layer and the silicon germanium layer is greater than 10.

[0008] In some embodiments of this application, the first etching process is a hydrogen plasma etching process.

[0009] In some embodiments of the present application, the process parameters of the hydrogen plasma etching process include: the etching agent includes any one or more of H2 / N2 / He / Ar; the etching time is less than or equal to 600 seconds; the etching temperature is 50 - 300 degrees Celsius; the etching pressure is less than or equal to 5000 mTorr.

[0010] In some embodiments of the present application, the process parameters of the second etching process include: the etching agent includes any one or more of Cl2 / CH x F y / HBr / O2 / Ar / He, where x and y are any positive integers; the etching time is less than or equal to 600 seconds; the etching temperature is 50 - 200 degrees Celsius; the etching pressure is less than or equal to 200 mTorr.

[0011] In some embodiments of the present application, the height difference between the surface of the silicon layer exposed by the patterned mask layer after the first etching process and the surface of the silicon germanium layer is 50 - 300 angstroms.

[0012] In some embodiments of the present application, the aspect ratios of the fins in the first region and the fins in the second region are the same.

[0013] In some embodiments of the present application, the aspect ratios of the fins in the first region and the fins in the second region are 5 - 15.

[0014] Another aspect of the present application further provides a semiconductor structure, including: a semiconductor substrate, the semiconductor substrate includes a first region and a second region, a silicon layer is formed on the surface of the semiconductor substrate in the first region, a silicon germanium layer is formed on the surface of the semiconductor substrate in the second region, and the surfaces of the silicon layer and the silicon germanium layer are flush; fins are respectively located in the first region and the second region, the fins in the first region and the second region have the same height, the fins in the first region are composed of a part of the semiconductor substrate and the silicon layer, and the fins in the second region are composed of a part of the semiconductor substrate and the silicon germanium layer.

[0015] In some embodiments of the present application, the aspect ratios of the fins in the first region and the fins in the second region are the same.

[0016] In some embodiments of the present application, the aspect ratios of the fins in the first region and the fins in the second region are 5 - 15.

[0017] The present application provides a semiconductor structure and a method for forming the same, which can make the depths of the silicon fins and the silicon germanium fins consistent, and avoid defects such as fin merging and fin bending caused by the excessive depth of the silicon germanium fins. Description of the Drawings

[0018] The following drawings detail the exemplary embodiments disclosed in the present application. Wherein the same reference numerals represent similar structures in several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for illustrative and descriptive purposes and are not intended to limit the scope of the present application. Embodiments in other ways may also achieve the inventive concept in the present application. It should be understood that the drawings are not drawn to scale.

[0019] Wherein:

[0020] Figures 1 to 2 are schematic structural diagrams of each step in a method for forming some semiconductor structures;

[0021] Figures 3 to 6 are schematic structural diagrams of each step in the method for forming the semiconductor structure according to the embodiment of the present application. Detailed Description of Specific Embodiments

[0022] The following description provides specific application scenarios and requirements of the present application, aiming to enable those skilled in the art to manufacture and use the content in the present application. For those skilled in the art, various partial modifications to the disclosed embodiments are obvious, and the general principles defined here can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the illustrated embodiments, but to the broadest scope consistent with the claims.

[0023] The technical solution of the present invention will be described in detail below in conjunction with the embodiments and the drawings.

[0024] Figures 1 to 2 are schematic structural diagrams of each step in a method for forming some semiconductor structures.

[0025] Referring to Figure 1 as shown, a semiconductor substrate 100 is provided. The semiconductor substrate 100 includes a first region 101 and a second region 102. A silicon layer 110 is formed on the surface of the semiconductor substrate 100 in the first region 101, and a silicon-germanium layer 120 is formed on the surface of the semiconductor substrate 100 in the second region 102. The surfaces of the silicon layer 110 and the silicon-germanium layer 120 are flush, and a patterned mask layer 130 is further formed on the surfaces of the silicon layer 110 and the silicon-germanium layer 120. The patterned mask layer 130 defines the positions of the fins.

[0026] Referring to Figure 2 as shown, using the patterned mask layer 130 as a mask, the silicon layer 110 and the silicon-germanium layer 120 are etched into the semiconductor substrate 100 to form fins 140 in the first region 101 and the second region 102 respectively. The silicon layer 110 and the silicon-germanium layer 120 are etched to become part of the fins 140.

[0027] However, in the current process of etching fins, the etching rate of the silicon germanium layer 120 is greater than that of the silicon layer 110, which results in a deeper depth of the fins 140 in the second region 102 and a greater aspect ratio of the fins 140 in the second region 102. This makes the fins 140 in the second region 102 prone to defects such as fin merging / fin bending due to the high aspect ratio. If the etching depth of the fins 140 in the second region 102 is directly reduced, it will result in too small a depth of the fins 110 in the first region 101, not meeting the requirements.

[0028] Based on this, the present application provides a semiconductor structure and a method for forming the same, which can make the depths of the silicon fins and the silicon germanium fins consistent, and avoid defects such as fin merging and fin bending caused by the excessive depth of the silicon germanium fins.

[0029] Figures 3 to 6 FIG. is a schematic structural diagram of each step in the method for forming the semiconductor structure according to the embodiment of the present application. The method for forming the semiconductor structure according to the embodiment of the present application will be described in detail below with reference to the accompanying drawings.

[0030] Refer to Figure 3 As shown, a semiconductor substrate 200 is provided. The semiconductor substrate 200 includes a first region 201 and a second region 202. A silicon layer 210 is formed on the surface of the semiconductor substrate 200 in the first region 201, and a silicon germanium layer 220 is formed on the surface of the semiconductor substrate 200 in the second region 202. The surfaces of the silicon layer 210 and the silicon germanium layer 220 are flush.

[0031] In some embodiments of the present application, the semiconductor structure described in the present application is, for example, a FinFET device having a silicon / silicon germanium double fin structure. As the name implies, the FinFET device having a silicon / silicon germanium double fin structure simultaneously includes a fin structure etched from silicon material and a fin structure etched from silicon germanium material.

[0032] In some embodiments of the present application, the material of the semiconductor substrate 200 includes (i) elemental semiconductors, such as silicon or germanium, etc.; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide, etc.; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide, or gallium indium phosphide, etc.; or (iv) a combination of the above.

[0033] In some embodiments of the present application, the first region 201 is a region for forming silicon fins, and the second region 202 is a region for forming silicon germanium fins.

[0034] In some embodiments of the present application, the material of the silicon layer 210 is silicon, and the material of the silicon germanium layer 220 is silicon germanium.

[0035] Reference Figure 4 As shown, a patterned mask layer 230 is formed on the surfaces of the silicon layer 210 and the silicon-germanium layer 220, and the patterned mask layer 230 defines the positions of the fins.

[0036] In some embodiments of the present application, the material of the patterned mask layer 230 includes silicon nitride.

[0037] Reference Figure 5 As shown, a first etching process is performed to make the surface of the silicon layer 210 exposed by the patterned mask layer 230 lower than the surface of the silicon-germanium layer 220.

[0038] In some embodiments of the present application, the etching selectivity of the first etching process for the silicon layer 210 and the silicon-germanium layer 220 is greater than 10. At this etching selectivity, it is possible to achieve substantially no loss of the silicon-germanium layer 220 when etching the silicon layer 210, and thus realize the selective etching of the silicon layer 210 without a mask.

[0039] In some embodiments of the present application, the first etching process is a hydrogen plasma etching process (H2 plasma etch). The hydrogen plasma etching process is a process that uses hydrogen as the main etching gas, ionizes hydrogen molecules through an alternating electric field, or excites hydrogen molecules with the help of other precursors, and mainly uses the generated hydrogen ions and hydrogen radicals to remove specific materials from the substrate surface isotropically or anisotropically through physical and chemical reactions with specific materials.

[0040] In some embodiments of the present application, the process parameters of the hydrogen plasma etching process include: the etchant includes any one or more of H2 / N2 / He / Ar; the etching time is less than or equal to 600 seconds; the etching temperature is 50 - 300 degrees Celsius; the etching pressure is less than or equal to 5000 millitorr.

[0041] In some other embodiments of the present application, the first etching process includes: forming a hard mask layer covering the second region 202 on the semiconductor substrate 200; etching the silicon layer 210 in the first region 201 to make the surface of the silicon layer 210 exposed by the patterned mask layer 230 lower than the surface of the silicon-germanium layer 220. In some other embodiments, it is also possible to use a hard mask layer to block the second region 202 to achieve the selective etching of the silicon layer 210 in the first region 201.

[0042] In some embodiments of the present application, after the first etching process, the height difference between the surface of the silicon layer 210 exposed by the patterned mask layer 230 and the surface of the silicon germanium layer 220 is 50-300 angstroms. The setting of this height difference needs to be combined with the set depth value of the fin in the process design, so that when the fin depths of the first region 201 and the second region 202 are consistent in the subsequent second etching process, the set depth value of the fin in the process design is exactly reached.

[0043] refer to Figure 6 As shown, a second etching process is performed using the patterned mask layer 230 as a mask to etch the silicon layer 210 and the silicon germanium layer 220 into the semiconductor substrate 200 to form fins 240 in the first region 201 and the second region 202, respectively. The fins 240 in the first region 201 and the second region 202 have the same height. Both the silicon layer 210 and the silicon germanium layer 220 are etched to form part of the fin 240.

[0044] In the second etching process, the etching rate of the silicon germanium layer is greater than the etching rate of the silicon layer. Since a portion of the silicon layer in the first region 201 has been pre-etched, as long as the process parameters are controlled well, consistent etching depths can be achieved in the first region 201 and the second region 202.

[0045] In some embodiments of the present application, the process parameters of the second etching process include: the etchant includes Cl2 / CH x F y / HBr / O2 / Ar / He, wherein x and y are any positive integers; the etching time is less than or equal to 600 seconds; the etching temperature is 50-200 degrees Celsius; and the etching pressure is less than or equal to 200 mTorr.

[0046] In some embodiments of the present application, the fins 240 in the first region 201 and the fins 240 in the second region 202 have the same aspect ratio. The aspect ratio refers to the ratio of the depth to the width of the fin. The depth of the fin refers to the longitudinal dimension of the fin in the accompanying drawings, and the width of the fin refers to the transverse dimension of the fin in the accompanying drawings.

[0047] In some embodiments of the present application, the aspect ratio of the fins 240 in the first region 201 and the fins 240 in the second region 202 is 5-15.

[0048] In the technical solution of the present application, the depths of the fins 240 in the first region 201 and the second region 202 are consistent and meet the device requirements, and the aspect ratio of the fins 240 in the second region 202 is controlled to avoid defects such as fin merging and fin bending caused by the fins 240 in the second region 202 having a large aspect ratio, thereby improving device reliability.

[0049] In some embodiments of the present application, the technical solution of the present application can be applied to various logic devices and SRAM circuits, including STC, IO, HC, HD, etc. The technical solution of the present application can be applied to technology nodes of 5 nanometers and below.

[0050] The present application provides a method for forming a semiconductor structure, which can make the depth of silicon fins and silicon germanium fins consistent, avoiding defects such as fin merging and fin bending caused by the silicon germanium fins being too deep.

[0051] The embodiment of the present application further provides a semiconductor structure, referring to Figure 6 As shown, it includes: a semiconductor substrate 200, the semiconductor substrate 200 includes a first region 201 and a second region 202, a silicon layer 210 is formed on the surface of the semiconductor substrate 200 in the first region 201, and a silicon germanium layer 220 is formed on the surface of the semiconductor substrate 200 in the second region 202, and the surfaces of the silicon layer 210 and the silicon germanium layer 220 are flush; fins 240 are respectively located in the first region 201 and the second region 202, the fins 240 in the first region 201 and the second region 202 have the same height, the fins 240 in the first region 201 are composed of part of the semiconductor substrate 200 and the silicon layer 210, and the fins 240 in the second region 202 are composed of part of the semiconductor substrate 200 and the silicon germanium layer 220.

[0052] In some embodiments of the present application, the semiconductor structure described herein is, for example, a FinFET device having a silicon / silicon-germanium dual-fin structure. As the name implies, the FinFET device having a silicon / silicon-germanium dual-fin structure includes both a fin structure etched from a silicon material and a fin structure etched from a silicon-germanium material.

[0053] In some embodiments of the present application, the material of the semiconductor substrate 200 includes (i) an elemental semiconductor, such as silicon or germanium; (ii) a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) an alloy semiconductor, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) a combination of the above.

[0054] In some embodiments of the present application, the first region 201 is a region for forming silicon fins, and the second region 202 is a region for forming silicon germanium fins.

[0055] In some embodiments of the present application, the material of the silicon layer 210 is silicon, and the material of the silicon germanium layer 220 is silicon germanium.

[0056] Continue to refer Figure 6 As shown, a patterned mask layer 230 is formed on the surface of the fin 240 .

[0057] In some embodiments of the present application, the material of the patterned mask layer 230 includes silicon nitride.

[0058] In some embodiments of the present application, the aspect ratios of the fins 240 in the first region 201 and the fins 240 in the second region 202 are the same. Herein, the aspect ratio refers to the ratio of the depth to the width of the fin. Herein, the depth of the fin refers to the longitudinal dimension of the fin in the drawing, and the width of the fin refers to the transverse dimension of the fin in the drawing.

[0059] In some embodiments of the present application, the aspect ratios of the fins 240 in the first region 201 and the fins 240 in the second region 202 are 5 - 15.

[0060] In the technical solution of the present application, the depths of the fins 240 in the first region 201 and the second region 202 are the same and meet the device requirements. The aspect ratio of the fins 240 in the second region 202 is controlled to avoid defects such as fin merging and fin bending caused by too large an aspect ratio of the fins 240 in the second region 202, thereby improving device reliability.

[0061] The present application provides a semiconductor structure and a method for forming the same, which can make the depths of silicon fins and silicon germanium fins the same, and avoid defects such as fin merging and fin bending caused by too deep silicon germanium fins.

[0062] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing application content may be presented only by way of example and may not be restrictive. Although not explicitly stated herein, those skilled in the art can understand that the present application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of the present application.

[0063] It should be understood that the term “and / or” used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or there may also be an intermediate element.

[0064] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It should also be understood that the terms "comprises," "comprising," "includes," or "including," when used in this application, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0065] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be referred to as a second element in other embodiments without departing from the teachings of this application. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0066] In addition, the present application specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Accordingly, differences from the shapes shown due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but should include deviations in shapes resulting from, for example, manufacturing. For example, an etched region shown as rectangular will typically have rounded or curved features. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a semiconductor substrate, the semiconductor substrate including a first region and a second region, a silicon layer being formed on the surface of the semiconductor substrate in the first region, a silicon germanium layer being formed on the surface of the semiconductor substrate in the second region, and the surfaces of the silicon layer and the silicon germanium layer being flush; Forming a patterned mask layer on the surfaces of the silicon layer and the silicon germanium layer, the patterned mask layer defining the positions of fins; Performing a first etching process to make the surface of the silicon layer exposed by the patterned mask layer lower than the surface of the silicon germanium layer; Using the patterned mask layer as a mask to perform a second etching process to etch the silicon layer and the silicon germanium layer into the semiconductor substrate to form fins in the first region and the second region respectively, and the fins in the first region and the second region having the same height.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first etching process includes: Forming a hard mask layer covering the second region on the semiconductor substrate; Etching the silicon layer in the first region to make the surface of the silicon layer exposed by the patterned mask layer lower than the surface of the silicon germanium layer.

3. The method for forming a semiconductor structure according to claim 1, wherein, The etching selectivity of the first etching process for the silicon layer and the silicon germanium layer is greater than 10.

4. The method for forming a semiconductor structure according to claim 3, wherein, The first etching process is a hydrogen plasma etching process.

5. The method for forming a semiconductor structure according to claim 4, wherein The process parameters of the hydrogen plasma etching process include: the etchant includes any one or more of H2 / N2 / He / Ar; the etching time is less than or equal to 600 seconds; the etching temperature is 50 - 300 degrees Celsius; the etching pressure is less than or equal to 5000 mTorr.

6. The method for forming a semiconductor structure according to claim 1, wherein, The process parameters of the second etching process include: the etchant includes any one or more of Cl2 / CH x F y / HBr / O2 / Ar / He, where x and y are any positive integers; the etching time is less than or equal to 600 seconds; the etching temperature is 50 - 200 degrees Celsius; the etching pressure is less than or equal to 200 millitorr.

7. The method for forming a semiconductor structure according to claim 1, wherein, After the first etching process, the height difference between the surface of the silicon layer exposed by the patterned mask layer and the surface of the silicon germanium layer is 50 - 300 angstroms.

8. The method for forming a semiconductor structure according to claim 1, wherein, The aspect ratios of the fins in the first region and the fins in the second region are the same.

9. The method for forming a semiconductor structure according to claim 7, wherein The aspect ratios of the fins in the first region and the fins in the second region are 5 - 15.

10. A semiconductor structure, characterized in that, Comprising: A semiconductor substrate, the semiconductor substrate including a first region and a second region, a silicon layer being formed on the surface of the semiconductor substrate in the first region, a silicon germanium layer being formed on the surface of the semiconductor substrate in the second region, and the surfaces of the silicon layer and the silicon germanium layer being flush; Fins, respectively located in the first region and the second region, the fins in the first region and the second region having the same height, the fins in the first region being composed of a part of the semiconductor substrate and the silicon layer, and the fins in the second region being composed of a part of the semiconductor substrate and the silicon germanium layer.

11. The semiconductor structure according to claim 10, wherein The aspect ratios of the fins in the first region and the fins in the second region are the same.

12. The semiconductor structure according to claim 11, wherein The aspect ratios of the fins in the first region and the fins in the second region are 5 - 15.

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