High-voltage direct-current transmission converter thyristor fault identification method based on reliability evaluation

Abstract

The invention discloses a high-voltage direct current transmission converter thyristor fault identification method based on reliability evaluation. The method comprises the following steps: constructing a stress-degradation-life mapping relation model through a stepped temperature-voltage cooperative stress test; establishing a three-stage Wiener degradation model, and predicting a critical failure point in combination with a dynamic threshold jump mechanism; an FPGA + CPU heterogeneous computing platform is adopted to execute an EM-MCMC joint estimation algorithm in parallel, and parameter updating is accelerated through assembly line MCMC sampling; designing a dynamic correction factor optimization reliability index based on the buffer layer parameters; constructing a dual-channel LSTM network to extract degradation features and generate a dynamic failure threshold value; a converter topology is reconstructed through a graph neural network, and fault positioning and damage grading are realized in combination with a three-level early warning mechanism. According to the method, fault identification is carried out through combination of multi-stress coupling modeling and a dynamic threshold value, the real-time performance is improved through a heterogeneous computing architecture, the false alarm rate is reduced through combination of a dynamic correction and topology reconstruction technology, and accurate identification and operation and maintenance decision support of the thyristor fault are realized.

Description

Technical Field

[0001] The present invention relates to the technical field of high - voltage direct - current (HVDC) transmission systems, and particularly to a method for identifying faults in HVDC converters based on reliability assessment. Background Art

[0002] As a core technology for long - distance and large - capacity electric energy transmission, the reliability of the thyristors in the converter of the HVDC transmission system directly affects the system stability. As a key component of the converter valve, thyristors are long - term subjected to the combined action of multiple stresses such as high voltage, large current, and temperature fluctuations, and are prone to performance degradation or even failure, which directly affects the reliability of the converter valve and the power grid stability. Existing technologies still have significant deficiencies in aspects such as high - precision degradation modeling, real - time monitoring, and fault location, specifically manifested as follows:

[0003] Most existing technologies are based on degradation models driven by a single stress (such as temperature or voltage). For example, Patent CN114184927A constructs a lifetime distribution function through an accelerated aging test, but only relies on the failure time data under temperature stress and does not consider the accelerating effect of voltage fluctuations on material damage.

[0004] Traditional methods mostly adopt fixed failure thresholds and cannot capture the mutation characteristics when thyristors are approaching failure. For example, Patent CN117669227A predicts the remaining life through a binary degradation trajectory model, relying on offline parameter estimation and a centralized computing architecture, resulting in insufficient real - time performance. And it does not dynamically correct the reliability index in combination with the physical structure of thyristors, which is prone to false alarms.

[0005] Existing technologies lack real - time identification and visualization of the fault location and damage level. For example, although Patent CN117669227A optimizes parameter estimation through Bayesian methods, it does not integrate the function of converter topology reconstruction, cannot locate faulty devices before thyristor failure, and the maintenance strategy still relies on regular inspections. Summary of the Invention

[0006] The purpose of the present invention is to provide a method for identifying thyristor faults based on multi - stress collaborative loading, dynamic threshold jumping, and heterogeneous collaborative computing. A non - linear damage model is constructed through temperature - voltage stepped collaborative stress tests, a heterogeneous computing platform at the edge is constructed to accelerate parameter update, and a graph neural network topology reconstruction and a three - level early warning mechanism are integrated to improve the accuracy and real - time performance of fault identification.

[0007] The technical solution adopted by the present invention is that the method for identifying faults in thyristors of HVDC converters based on reliability assessment includes the following steps:

[0008] S1. Real-time collect the voltage, current and junction temperature parameters of the thyristor under working conditions through a distributed sensor array, synchronously control the stepped stress loading device to perform a stepped temperature-voltage collaborative stress test, record the degradation data and failure time at each stress level, and construct a stress-degradation-life mapping relationship model;

[0009] S2. Perform wavelet denoising and normalization preprocessing on the collected data at the edge computing node. Based on the stress-degradation-life mapping relationship model, construct a stage degradation model of the thyristor through the Wiener process. The stage degradation model includes three stages: the first stage describes the stable period through linear drift, the second stage introduces a non-linear temperature-voltage coupling damage factor to describe accelerated failure, and the third stage combines a threshold jump model to predict the critical failure point;

[0010] S3. Deploy the EM-MCMC joint estimation algorithm on the heterogeneous computing platform to estimate the latent variable parameters of the Wiener process. The latent variables include drift coefficients μ1, μ2 and diffusion coefficients σ1, σ2. The drift coefficients characterize the degradation trend of the thyristor, and the diffusion coefficients characterize the random fluctuations during the degradation process. The heterogeneous computing platform includes an FPGA coprocessor and a CPU main processor. The FPGA coprocessor uses a pipelined MCMC sampler to perform parallel sampling on the latent variables to generate a latent variable sample chain. The CPU main processor executes EM algorithm iteration based on the sampling results to update the posterior distribution of the latent variables and the Bayesian network conditional probability table. The posterior distribution is used to quantify the uncertainty of the latent variable parameter estimation, and the Bayesian network conditional probability table is used to encode the dynamic coupling relationship between the temperature-voltage stress and the degradation trend;

[0011] S4. Calculate the remaining service life and instantaneous failure rate of the thyristor according to the updated latent variable parameters, and design a dynamic correction factor based on the buffer layer structure parameters to generate a corrected reliability index;

[0012] S5. Construct a dual-channel LSTM neural network to extract the degradation time series features and stress-life correlation features respectively, output a dynamic failure threshold, and compensate for the environmental temperature fluctuation through the generalized Eyring model;

[0013] S6. Use a high-speed data acquisition card to obtain the thyristor status data in real time. When it is detected that the reliability index continuously crosses the dynamic threshold, trigger a three-level alarm signal, and reconstruct the converter topology based on the graph neural network, and mark the position and damage level of the faulty thyristor on the visualization interface.

[0014] Further, in step S1, the stress-degradation-life mapping relationship model quantifies the influence of multi-stress coupling on the life of the thyristor. The expression of the stress-degradation-life mapping relationship model is:

[0015]

[0016] In formula (1), C1 and C2 are material damage weight coefficients, and V ref , T ref are the reference voltage and reference junction temperature respectively, α is the temperature acceleration aging index, γ and β are voltage acceleration aging indices, E a is the activation energy for thyristor failure, and k is the Boltzmann constant.

[0017] Furthermore, in the step S2, the Wiener process with linear drift is used to describe the early stable degradation stage of the thyristor in the first stage, and the model expression of the first stage is:

[0018] X1(t) = μ1t + σ1B1(t) (2)

[0019] In formula (1), X1(t) is the degradation amount in the first stage, μ1 is the linear drift coefficient, σ1 is the diffusion coefficient, and B1(t) is the standard Brownian motion;

[0020] In the second stage, a non - linear temperature - voltage coupling damage factor is introduced to describe the accelerated failure, and the model expression of the second stage is:

[0021]

[0022] In formula (2), X2(t) is the degradation amount in the second stage, μ2 is the non - linear drift coefficient, is the temperature - voltage coupling damage factor, T is the junction temperature, V is the voltage stress, m is the correction coefficient, σ2 is the diffusion coefficient, and B2(t) is the standard Brownian motion;

[0023] In the third stage, the threshold jump model is combined. When the degradation amount approaches the failure threshold, a Poisson jump term is introduced to predict the critical failure point, and the model expression of the third stage is:

[0024]

[0025] In formula (3), X3(t) is the degradation amount in the third stage, is the degradation amount before the i - th jump occurs, λ i is the amplitude coefficient of the i - th jump, n(t) is the number of jumps up to time t, which follows a Poisson jump process with intensity λ t , I(·) is the indicator function, N is the failure threshold, and δ(t) is the dynamic threshold buffer interval.

[0026] Furthermore, the mathematical expression of the correction coefficient is:

[0027]

[0028] In formula (5), θ is the sensitivity adjustment factor, which is updated by the gradient descent method:

[0029]

[0030] In formula (6), ψ ∈ (0, 1) is the learning rate, and L is the mean square error loss function of the degraded data and the model output.

[0031] Furthermore, in step S3, data interaction is implemented between the FPGA coprocessor and the CPU main processor of the heterogeneous computing platform, specifically including:

[0032] The dual-port RAM is divided into a parameter update area and a latent variable sampling area. The parameter update area stores the drift coefficients μ1, μ2 and the diffusion coefficients σ1, σ2, and the latent variable sampling area stores the latent variable sequence output by the MCMC sampler;

[0033] The timing of the EM algorithm and the MCMC sampling is synchronized through the hardware handshake signal READY;

[0034] The FPGA coprocessor batch-transmits the latent variable sampling results to the memory of the CPU main processor through DMA transmission, and the transmission bandwidth matches the update frequency of the Bayesian network conditional probability table.

[0035] Furthermore, the specific method steps of the EM-MCMC joint estimation algorithm are as follows:

[0036] L1. Load the multi-stress level degradation data set and initialize the prior distribution of the latent variables of the Wiener process;

[0037] L2. The FPGA coprocessor generates candidate samples, calculates the posterior probability ratio in parallel through the MCMC sampler, and receives the samples according to the Metropolis-Hastings criterion;

[0038] L3. The CPU main processor updates the latent variables and the Bayesian network conditional probability table through the EM algorithm;

[0039] L4. Repeat steps L2 - L3 until the parameters converge or reach the maximum number of iterations, and output the optimal latent variable parameters.

[0040] Furthermore, the MCMC sampler with a pipeline structure includes the following units:

[0041] Normal candidate generation unit: Configure 4 groups of parallel random number generators to generate Gaussian perturbation terms through the Box-Muller algorithm, and 4 candidate latent variable parameters can be generated per cycle;

[0042] Parallel likelihood calculation array: Configure 8 floating-point arithmetic units to calculate the likelihood values of degradation data at each stress level in parallel;

[0043] Hierarchical acceptance decision unit: The first-level multiplier calculates the numerator and denominator components of the likelihood probability ratio p, the second-level comparator array calculates the acceptance probability A = min(1, p), and the third-level arbiter generates a uniform random number u ∈ [0, 1] through a linear feedback shift register, executes the judgment of u ≤ A, and processes one sample per clock cycle through a three-stage pipeline structure;

[0044] Dual-buffer storage unit: Adopt the ping-pong transfer mechanism to trigger DMA transfer.

[0045] Further, in the step S4, the mathematical expression of the dynamic correction factor is:

[0046]

[0047] In formula (7), η(t) is the dynamic correction factor, k1 and k2 are the characteristic coefficients of the buffer layer material, d 缓冲 is the actual thickness of the buffer layer, d 标称 is the designed nominal thickness, T ref 、V ref are the reference junction temperature and reference voltage respectively, T(t) and V(t) are the junction temperature and voltage stress values collected in real time; the corrected reliability index is:

[0048]

[0049] In formula (8), R 修正 (t) is the corrected reliability index, R(t) is the original reliability index, and ∈ is the gradient compensation factor.

[0050] Further, in the step S6, the hierarchical warning includes:

[0051] First-level warning: When the reliability index first crosses 80% of the dynamic failure threshold, trigger a yellow warning signal and mark the thyristor position as a potential risk area on the visualization interface;

[0052] Second-level alarm: When the reliability index continuously crosses 90% of the dynamic failure threshold in 3 sampling periods, trigger an orange alarm signal, start the redundant capacity allocation strategy of the converter, and generate a degradation trend prediction curve;

[0053] Third-level emergency shutdown: When the instantaneous value of the reliability index is lower than the dynamic failure threshold and the graph neural network reconstruction shows that the local topological impedance change rate ≥ 15%, trigger a red shutdown signal, cut off the bridge arm where the faulty thyristor is located, and mark the damage level with a flashing polygon in the three-dimensional interface. The damage level is divided according to the following formula:

[0054]

[0055] In formula (9), U is the damage level, N is the failure threshold, [·] represents the floor operation, the damage level ranges from 1 to 10 levels, and emergency shutdown is initiated when U≥7.

[0056] The beneficial effects of the present invention are as follows:

[0057] Construct a non-linear coupling damage factor through a stepped temperature-voltage collaborative stress test, quantify the influence of multi-stress interaction on the degradation of thyristors, introduce a Poisson jump term to predict the critical failure point, and solve the problem of early warning lag caused by a fixed threshold;

[0058] Adopt an FPGA+CPU heterogeneous computing architecture, jointly iterate through a pipelined MCMC sampler and an EM algorithm, and use a dual-port RAM and a DMA transmission mechanism to realize real-time update of the conditional probability table of the Bayesian network. Compared with cloud centralized computing, hardware acceleration is used to improve the fault response efficiency;

[0059] Dynamically correct the reliability index in combination with the buffer layer thickness and material properties, reduce false alarms of thyristor faults, reconstruct the converter topology based on a graph neural network, and through a three-level alarm mechanism, and map the damage level through a multi-spectral heat map to achieve precise operation and maintenance decisions.

[0060] The present invention improves the accuracy and real-time performance of thyristor fault identification in high-voltage DC transmission converters through multi-stress collaborative modeling, heterogeneous computing acceleration, and intelligent diagnosis technology, and realizes precise positioning of thyristor faults. Description of the Drawings

[0061] Figure 1 is a schematic flow chart of the method for identifying thyristor faults in a high-voltage DC transmission converter based on reliability assessment of the present invention;

[0062] Figure 2 is a schematic diagram of data interaction between the FPGA coprocessor and the CPU main processor;

[0063] Figure 3 is a schematic flow chart of the EM-MCMC joint estimation algorithm;

[0064] Figure 4 is a schematic diagram of the dual-channel LSTM neural network structure. Detailed Embodiments

[0065] The technical method of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative work belong to the scope of protection of the present invention.

[0066] Please refer to Figure 1 , the thyristor fault identification method for high-voltage direct current transmission converters based on reliability assessment includes the following steps:

[0067] S1. Real-time collect the voltage, current and junction temperature parameters of the thyristor under working conditions through a distributed sensor array, synchronously control the stepped stress loading device to perform a stepped temperature-voltage collaborative stress test, record the degradation data and failure time at each stress level, and construct a stress-degradation-life mapping relationship model;

[0068] S2. Perform wavelet denoising and normalization preprocessing on the collected data at the edge computing node. Based on the stress-degradation-life mapping relationship model, construct a thyristor stage degradation model through the Wiener process. The stage degradation model includes three stages: the first stage describes the stable period through linear drift, the second stage introduces a non-linear temperature-voltage coupling damage factor to describe accelerated failure, and the third stage combines a threshold jump model to predict the critical failure point;

[0069] S3. Deploy the EM-MCMC joint estimation algorithm on the heterogeneous computing platform to estimate the latent variable parameters of the Wiener process. The latent variables include drift coefficients μ1, μ2 and diffusion coefficients σ1, σ2. The drift coefficients characterize the degradation trend of the thyristor, and the diffusion coefficients characterize the random fluctuations during the degradation process. The heterogeneous computing platform includes an FPGA coprocessor and a CPU main processor. The FPGA coprocessor uses a pipelined MCMC sampler to perform parallel sampling on the latent variables to generate a latent variable sample chain. The CPU main processor performs EM algorithm iteration based on the sampling results to update the posterior distribution of the latent variables and the Bayesian network conditional probability table. The posterior distribution is used to quantify the uncertainty of the latent variable parameter estimation, and the Bayesian network conditional probability table is used to encode the dynamic coupling relationship between the temperature-voltage stress and the degradation trend;

[0070] S4. Calculate the remaining useful life and instantaneous failure rate of the thyristor according to the updated latent variable parameters, and design a dynamic correction factor based on the buffer layer structure parameters to generate a corrected reliability index;

[0071] S5. Construct a dual-channel LSTM neural network to extract the degradation time series features and stress-life correlation features respectively, output a dynamic failure threshold, and compensate for the environmental temperature fluctuation through the generalized Arrhenius model;

[0072] S6. Use a high-speed data acquisition card to obtain the thyristor status data in real time. When it is detected that the reliability index continuously crosses the dynamic threshold, trigger a three-level alarm signal, and reconstruct the converter topology based on the graph neural network, and mark the position and damage level of the faulty thyristor on the visualization interface.

[0073] Embodiment 1

[0074] Specifically, please refer to Figures 2 - 3 , the specific implementation process of thyristor degradation modeling and parameter estimation for the thyristor fault identification method of a high-voltage DC transmission converter based on reliability assessment is as follows:

[0075] Randomly select several thyristors of a certain model from the thyristors of the same batch production, ensure that the electrical performance and physical characteristics of these thyristors are basically the same to ensure the accuracy and comparability of the test results. Connect the step stress loading device to the thyristor to ensure that the temperature and voltage can be accurately applied to the thyristor. Set the initial junction temperature to 85 °C, the voltage stress to 5 kV, and set the temperature gradient and voltage gradient in the step stress loading device, where:

[0076] Temperature gradient: ΔT = 10 °C (increase by 10 °C per stage, up to 135 °C);

[0077] Voltage gradient: ΔV = 0.5 kV (increase by 0.5 kV per stage, up to 8 kV).

[0078] The operating time of each stress level is set as shown in Table 1:

[0079] Table 1 Stress level and operating time setting table

[0080] Level Temperature (°C) Voltage (kV) Operating time (hours) Test purpose Level 1 105℃ 5.5 kV 400 hours Medium - voltage long - term operation simulation Level 2 115℃ 6.0 kV 300 hours Short - term overload simulation Level 3 125℃ 6.5 kV 200 hours Extreme load fluctuation simulation Level 4 135℃ 7.0 kV 100 hours Accelerate to device failure

[0081] According to the stress level and operating time settings in Table 1, conduct tests for each stress level in sequence. At the beginning of each stress level, record the start time and collect the on-state voltage drop, reverse recovery charge, and junction temperature data in real time.

[0082] Collect the on-state voltage drop, reverse recovery charge, and junction temperature data in real time through a distributed sensor array. The sensors include a voltage sensor, a current sensor, and an infrared temperature measurement module.

[0083] The voltage sensor uses a LEM LV 25-P type voltage transformer, with an accuracy of ±0.1%, a bandwidth of DC-100 kHz, and is installed in the thyristor anode and cathode circuit.

[0084] The current sensor uses a LEM LA 55-P type Hall current sensor, with an accuracy of ±0.1%, a response time <1 μs, and is connected in series on the cathode side of the thyristor.

[0085] The infrared temperature measurement module uses a FLIR A655sc infrared thermal imaging module with a resolution of 0.1 °C. It is calibrated through blackbody radiation and focuses on the surface of the thyristor chip.

[0086] When reaching level 4 and the thyristor fails, the test is stopped. All the data collected during the test process are sorted out, including the on-state voltage drop, reverse recovery charge, junction temperature data at each stage, and the failure time.

[0087] Quantify the influence of the multi-stress coupling effect on the thyristor life through the stress-degradation-life mapping relationship model. The expression of the stress-degradation-life mapping relationship model is:

[0088]

[0089] In formula (1), C1 and C2 are material damage weight coefficients, V ref , T ref are the reference voltage and reference junction temperature respectively, α is the temperature acceleration aging index, γ and β are the voltage acceleration aging indices, E a is the thyristor failure activation energy, and k is the Boltzmann constant.

[0090] Specifically, the stress-degradation-life mapping relationship model t f consists of the superposition of two terms. characterizes the Arrhenius-type failure mechanism dominated by voltage. characterizes the power-law failure mechanism of the temperature-voltage synergistic effect. Use the Levenberg-Marquardt algorithm to minimize the mean square error, fit and predict the failure time, and determine the parameters C1, C2, α, γ, β, and E a in the model.

[0091] Deploy edge computing nodes inside the converter control cabinet. The edge computing nodes use NVIDIA Jetson AGX Xavier, perform 5-layer decomposition through the db4 wavelet basis, separate the noise frequency band and the degradation signal, and normalize the original data to improve the data quality and the accuracy of the model.

[0092] Based on the stress-degradation-life mapping relationship model, construct a thyristor stage degradation model through the Wiener process, which is divided into three stages:

[0093] The first stage uses a Wiener process with linear drift to describe the early stable degradation stage of the thyristor. The model expression of the first stage is:

[0094] X1(t) = μ1t + σ1B1(t) (2)

[0095] In formula (1), X1(t) is the degradation amount in the first stage, μ1 is the linear drift coefficient, σ1 is the diffusion coefficient, and B1(t) is the standard Brownian motion;

[0096] In the second stage, a non-linear temperature-voltage coupling damage factor is introduced to describe the accelerated failure. The model expression in the second stage is:

[0097]

[0098] In formula (2), X2(t) is the degradation amount in the second stage, μ2 is the non-linear drift coefficient, is the temperature-voltage coupling damage factor, T is the junction temperature, V is the voltage stress, m is the correction coefficient, σ2 is the diffusion coefficient, and B2(t) is the standard Brownian motion;

[0099] In the third stage, the threshold jump model is combined. When the degradation amount approaches the failure threshold, a Poisson jump term is introduced to predict the critical failure point. The model expression in the third stage is:

[0100]

[0101] In formula (3), X3(t) is the degradation amount in the third stage, is the degradation amount before the i-th jump occurs, λ i is the amplitude coefficient of the i-th jump, n(t) is the number of jumps up to time t, which follows a Poisson jump process with intensity λ t , I(·) is the indicator function, N is the failure threshold, and δ(t) is the dynamic threshold buffer interval.

[0102] The mathematical expression of the correction coefficient is:

[0103]

[0104] In formula (5), θ is the sensitivity adjustment factor, which is updated by the gradient descent method:

[0105]

[0106] In formula (6), ψ ∈ (0, 1) is the learning rate, and L is the mean square error loss function between the degradation data and the model output.

[0107] Deploy a heterogeneous computing platform in the converter control system, and the parameter estimation of the thyristor stage degradation model is jointly completed by the FPGA coprocessor and the CPU main processor.

[0108] Specifically, the FPGA coprocessor uses Xilinx UltraScale+ XCVU9P, integrating a hard processor system (PS) and programmable logic (PL). The CPU main processor uses Intel Xeon Gold 6230, supporting dual-channel parallel computing. The dual-port RAM uses Cypress CY7C029C with a capacity of 32KB×16bit, supporting independent dual-port access. The DMA controller uses the Xilinx AXI DMA IP core, supporting the ping-pong transfer mode with a theoretical bandwidth of 1GB / s.

[0109] Data interaction between the FPGA coprocessor and the CPU main processor of the heterogeneous computing platform is achieved using a dual-port RAM, specifically including:

[0110] The dual-port RAM is divided into a parameter update area and a latent variable sampling area. The parameter update area stores the drift coefficients μ1, μ2, and the diffusion coefficients σ1, σ2. The latent variable sampling area stores the sequence of latent variables output by the MCMC sampler.

[0111] The timing of the EM algorithm and MCMC sampling is synchronized through the hardware handshake signal READY.

[0112] The FPGA coprocessor batch-transfers the latent variable sampling results to the memory of the CPU main processor through DMA transfer, and the transfer bandwidth matches the update frequency of the conditional probability table of the Bayesian network.

[0113] Specifically, the parameter update area is 32KB in size, storing the drift coefficients μ1, μ2, and the diffusion coefficients σ1, σ2, with each parameter occupying 4 bytes. The latent variable sampling area is 128KB in size, storing the sequence of latent variables generated by the MCMC sampler. Each sample contains 4 parameters (μ1, μ2, σ1, σ2), totaling 16 bytes / sample, and can store 8192 samples.

[0114] Specifically, the data interaction process between the FPGA coprocessor and the CPU main processor is as follows:

[0115] The MCMC sampler of the FPGA coprocessor generates a 128KB sequence of latent variables and writes it into the latent variable sampling area of the dual-port RAM through the AXI interface.

[0116] The FPGA coprocessor sets the READY signal to notify the CPU main processor that the data is available.

[0117] After reading the data, the CPU main processor runs the EM algorithm to update the parameters, writes the new parameters into the parameter update area of the dual-port RAM, and sets the ACK signal.

[0118] After detecting the ACK signal, the FPGA coprocessor reads the new parameters and starts the next cycle of MCMC sampling.

[0119] The specific method steps of the EM-MCMC joint estimation algorithm are as follows:

[0120] L1. Load the multi-stress-level degradation data set and initialize the prior distribution of the latent variables of the Wiener process;

[0121] Specifically, read the multi-stress-level degradation data set from the database. These data contain the degradation information of thyristors under different stress conditions such as temperature and voltage. Set appropriate prior distributions for the drift coefficients μ1, μ2 and the diffusion coefficients σ1, σ2 according to historical data. For example, μ1, μ2, σ1, σ2 can be initialized to follow a normal distribution.

[0122] L2. The FPGA coprocessor generates candidate samples, calculates the posterior probability ratio in parallel through the MCMC sampler, and accepts the samples according to the Metropolis-Hastings criterion;

[0123] L3. The CPU main processor updates the parameters and the conditional probability table of the Bayesian network through the EM algorithm;

[0124] Specifically, the CPU main processor executes the E-step and M-step of the EM algorithm according to the latent variable samples transmitted by the FPGA coprocessor. In the E-step, calculate the posterior expectation based on the latent variable samples transmitted by the FPGA coprocessor; in the M-step, update the parameters and at the same time update the conditional probability table of the Bayesian network, specifically including:

[0125] The drift coefficients μ1, μ2 are updated by weighted least squares;

[0126] The diffusion coefficients σ1, σ2 are updated by maximum likelihood estimation of the residual variance;

[0127] The conditional probability table (CPT) of the Bayesian network is updated based on the sample frequency.

[0128] L4. Repeat steps L2-L3 until the parameters converge or reach the maximum number of iterations, and output the optimal parameters.

[0129] Specifically, the parameter convergence judgment is as follows: calculate the change rate of the parameters. If the change rates of the parameters in several consecutive rounds (such as 5 rounds) are all less than the preset threshold (such as 0.1%), it is considered that the parameters have converged;

[0130] Setting of the maximum number of iterations: If the number of iterations reaches the preset maximum number of iterations (such as 1000 times), stop the iteration.

[0131] The MCMC sampler with a pipeline structure includes the following units:

[0132] Normal candidate generation unit: Configure 4 groups of parallel random number generators to generate Gaussian perturbation terms through the Box-Muller algorithm, and 4 candidate parameters can be generated per cycle;

[0133] Parallel likelihood calculation array: Configure 8 floating-point operation units to calculate the likelihood values of degradation data at each stress level in parallel;

[0134] Hierarchical acceptance decision unit: The first-level multiplier calculates the numerator and denominator components of the likelihood probability ratio p, the second-level comparator array calculates the acceptance probability A = min(1, p), and the third-level arbiter generates a uniform random number u ∈ [0, 1] through a linear feedback shift register, executes the judgment of u ≤ A, and processes one sample per clock cycle through a three-stage pipeline structure;

[0135] Dual-buffer storage unit: Adopt the ping-pong transmission mechanism to trigger DMA transmission.

[0136] Specifically, the working mechanism of the MCMC sampler with a pipeline structure is as follows:

[0137] Normal candidate generation unit: Every clock cycle, 4 groups of parallel random number generators each generate two independent uniformly distributed random numbers U1 and U2, with a range between [0, 1]. Then use the Box-Muller algorithm to convert the random numbers into standard normal distribution random numbers Z0 and Z1, and add these random numbers as Gaussian perturbation terms to the current parameters to generate 4 candidate parameters;

[0138] Parallel likelihood calculation array: 8 floating-point operation units work in parallel, and each unit is responsible for calculating the likelihood value of degradation data at one stress level. According to the probability distribution of the degradation data (such as normal distribution), combined with the current candidate parameters and observed data, calculate the likelihood value.

[0139] Hierarchical acceptance decision unit:

[0140] First-level multiplier: Receive the candidate parameters output by the parallel likelihood calculation array and the likelihood values under the current parameters, and calculate the numerator and denominator components of the likelihood probability ratio p.

[0141] Second-level comparator array: Calculate the acceptance probability A = min(1, p) according to the numerator and denominator components obtained in the first level.

[0142] Third-level arbiter: The linear feedback shift register generates a uniform random number u ∈ [0, 1], compares u with A, and outputs an acceptance or rejection signal according to the comparison result.

[0143] Dual-buffer storage unit: Adopting the ping-pong transmission mechanism, it contains two buffers. When the MCMC sampler generates a new set of latent variable samples, the latent variable samples are stored in the currently available buffer. Meanwhile, the other buffer transfers the previously stored samples to the memory of the CPU main processor through DMA transfer. After the DMA transfer is completed, the roles of the two buffers are swapped to achieve continuous data acquisition and transfer.

[0144] Calculate the remaining useful life and instantaneous failure rate according to the updated thyristor stage degradation model, and design a dynamic correction factor based on the buffer layer structure parameters. The mathematical expression of the dynamic correction factor is:

[0145]

[0146] In formula (7), η(t) is the dynamic correction factor, k1 and k2 are the buffer layer material characteristic coefficients, d 缓冲 is the actual thickness of the buffer layer, d 标称 is the designed nominal thickness, T ref 、V ref are the reference junction temperature and reference voltage respectively, and T(t), V(t) are the junction temperature and voltage stress values collected in real time; the corrected reliability index is:

[0147]

[0148] In formula (8), R 修正 (t) is the corrected reliability index, R(t) is the original reliability index, and ∈ is the gradient compensation factor.

[0149] Embodiment 2

[0150] Specifically, please refer to Figure 4 , the specific implementation process of dynamic threshold generation and fault identification for a thyristor fault identification method based on reliability assessment in a high-voltage DC transmission converter is as follows:

[0151] Through the National Instruments PXIe-6363 high-speed data acquisition card installed in the dedicated card slot of the converter control cabinet, various signal changes during the operation of the thyristor are quickly and accurately captured, and high-speed data communication is carried out with the edge computing node through the PXIe bus.

[0152] The high-speed data acquisition card acquires the thyristor status data in real time, specifically including:

[0153] Obtain the on-state voltage drop. Measure the voltage drop when the thyristor conducts using a voltage sensor. After the collected voltage signal is processed by the conditioning circuit, it is connected to the analog input channel of the high-speed data acquisition card.

[0154] Obtaining the reverse recovery charge: The reverse recovery charge is calculated by integrating the current signal within the reverse recovery time using a current sensor. After the current signal is processed by the conditioning circuit, it is transmitted to the high-speed data acquisition card.

[0155] Obtaining the junction temperature data: The infrared thermal imaging module measures the junction temperature with a resolution of 0.1 °C through blackbody radiation calibration and is connected to the high-speed data acquisition card via the RS485 communication interface. The data acquisition card reads the junction temperature data at the set sampling frequency.

[0156] Obtaining the arm impedance: An AC signal with a specific frequency (such as 1 kHz) and amplitude (such as 5 V) is injected into the converter arm circuit. By measuring the voltage and current responses of the injected signal, the arm impedance is calculated using the cross-correlation algorithm, and the calculated arm impedance value is converted into a digital signal and input into the digital input channel of the high-speed data acquisition card.

[0157] Outputting the dynamic failure threshold by constructing a dual-channel LSTM neural network. The dual-channel LSTM neural network specifically includes:

[0158] Input layer: Receiving the thyristor state parameters obtained in real time by the high-speed data acquisition card, including the on-state voltage drop, reverse recovery charge, junction temperature, and voltage. The input data is normalized to map parameters in different ranges to the [0, 1] interval, and the continuous time series data is framed according to a fixed time window to form input samples.

[0159] Degradation time series channel: Used to extract the degradation characteristics of the on-state voltage drop and reverse recovery charge changing with time, including:

[0160] 3 layers of LSTM units: Each layer is set with 128 neurons. The LSTM units capture the time series characteristics of the on-state voltage drop and reverse recovery charge through the gating mechanism.

[0161] 2 layers of Dropout units: Dropout units are added between every two layers of LSTM units, and the Dropout rate is set to 0.2 to randomly ignore some neurons to prevent overfitting.

[0162] Activation function: The hyperbolic tangent function is used to map the input value to the [-1, 1] interval and introduce non-linearity.

[0163] Output: After processing, a 256-dimensional degradation trend feature vector is output. The degradation trend feature vector contains the comprehensive feature information of the on-state voltage drop and reverse recovery charge changing with time.

[0164] Stress-life channel: Used to analyze the influence of stress factors such as junction temperature and voltage on the thyristor life and establish a correlation model between stress and life, including:

[0165] 2-layer LSTM unit: Each layer has 64 neurons. The LSTM unit is used to extract features from the time series data of junction temperature and voltage, and to explore the temporal variation patterns of stress factors and their potential relationship with thyristor life.

[0166] Two-layer regularization unit: A regularization unit is added between every two layers of LSTM units. The L2 regularization method is used, and the regularization coefficient is set to 0.001. The weight of the model is constrained by adding the square sum of weights to the loss function.

[0167] Activation function: Using the rectified linear unit (ReLU) as the activation function can alleviate the gradient disappearance problem;

[0168] Output: After processing, a 128-dimensional stress-life feature vector is output. The stress-life feature vector contains characteristic information about the effects of junction temperature and voltage on the life of the thyristor.

[0169] Fusion output layer: used to fuse the features extracted from the degradation timing channel and the stress-life channel and output the dynamic failure threshold, including:

[0170] The 256-dimensional degradation trend feature vector output by the degradation time series channel and the 128-dimensional stress-life feature vector output by the stress-life channel are spliced in the feature dimension to obtain a 384-dimensional fusion feature vector;

[0171] A fully connected layer is used to map the 384-dimensional fused feature vector to a scalar value, the dynamic failure threshold N. Each neuron in the fully connected layer is connected to all neurons in the previous layer, and the fused feature vector is converted into a prediction of the dynamic failure threshold by learning weight parameters.

[0172] Temperature compensation layer: used to perform temperature compensation on the output dynamic failure threshold. It receives the dynamic failure threshold output by the fusion output layer and the junction temperature data collected in real time, performs temperature compensation based on the generalized Eyring model, and outputs the dynamic failure threshold after temperature compensation.

[0173] When the reliability index is detected to have continuously crossed the dynamic threshold, a three-level alarm signal is triggered. The graded warning includes:

[0174] Level 1 warning: When the reliability index crosses 80% of the dynamic failure threshold for the first time, a yellow warning signal is triggered and the thyristor position is marked as a potential risk area on the visual interface;

[0175] Level 2 alarm: When the reliability index exceeds 90% of the dynamic failure threshold for three consecutive sampling periods, an orange alarm signal is triggered, the converter redundant capacity allocation strategy is activated, and a degradation trend prediction curve is generated;

[0176] Level 3 emergency shutdown: When the instantaneous value of the reliability index is lower than the dynamic failure threshold and the graph neural network reconstruction shows that the local topological impedance change rate ≥ 15%, a red shutdown signal is triggered, the arm where the faulty thyristor is located is cut off, and the damage level is marked with a flashing polygon in the 3D interface. The damage level is divided according to the following formula:

[0177]

[0178] In formula (9), U is the damage level, N is the failure threshold, [·] represents the floor operation, the damage level value range is 1 - 10 levels, and emergency shutdown is initiated when U ≥ 7.

[0179] Specifically, a GCN graph convolutional network is constructed to identify the fault probability vector and the arm impedance change rate of the output arm. The converter node voltage / current matrix collected in real time is input into the trained GCN graph convolutional network to output the fault probability of each arm, and the obtained arm impedance change rate is used to assist in judging the severity of the fault and triggering the level 3 shutdown condition.

[0180] Specifically, the Three.js library is used to build a 3D visualization scene. A 3D canvas is created in the HTML5 page. By loading the pre-made 3D model of the converter (including models of components such as thyristors, arms, and radiators) and scaling and positioning the model according to the actual size and position information, the physical structure of the converter can be accurately displayed;

[0181] The 3D visualization interface updates the temperature field distribution of the thyristor in real time according to the junction temperature data collected by the infrared thermal imaging module, maps the temperature data to a color gradient interval (such as from blue representing low temperature to red representing high temperature), and intuitively displays its temperature distribution by color rendering the surface of the thyristor model.

[0182] When a faulty thyristor is detected and the damage level is calculated, the position and damage level of the faulty thyristor are marked in the 3D scene in the form of a flashing red polygon (such as a regular hexagon). By setting CSS3 animation (keyframe animation), the polygon flashes at a refresh rate of 30Hz, which can highlight the faulty thyristor among many thyristors and facilitate the maintenance personnel to quickly locate and understand the severity of the fault.

[0183] When a fault triggers an alarm or shutdown signal, the system automatically generates a PDF report. The fault-related information in the HTML page (such as fault waveform diagrams, parameter comparison tables, 3D scene screenshots, etc.) is converted into PDF format through the wkhtmltopdf engine, and the generated PDF report is stored in a specified folder for the convenience of maintenance personnel to view and archive.

[0184] The basic principles of the present application have been described in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are only examples and not limitations. It cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present application. Additionally, the specific details disclosed above are only for illustrative and easy-to-understand purposes, not limitations. These details do not limit the present application to necessarily implementing with the above specific details.

[0185] The block diagrams of the devices, apparatuses, equipment, and systems involved in the present application are only illustrative examples and do not intend to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open-ended terms, meaning "including but not limited to", and can be used interchangeably with each other. The word "or" and "and" used herein refer to the word "and / or", and can be used interchangeably with it, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to", and can be used interchangeably with it.

[0186] It should also be noted that in the devices, equipment, and methods of the present application, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of the present application.

[0187] The above description of the disclosed aspects enables any person skilled in the art to make or use the present application. Various modifications to these aspects are very obvious to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the present application. Therefore, the present application is not intended to be limited to the aspects shown herein, but rather to the broadest scope consistent with the principles and novel features invented herein.

[0188] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, etc. made within the spirit and principles of the present application shall be included within the protection scope of the present application.

Claims

1. A method for identifying thyristor faults in a high-voltage DC transmission converter based on reliability assessment, characterized in that The method includes the following steps: S1. Real-time collect the voltage, current and junction temperature parameters of the thyristor under operating conditions through a distributed sensor array, synchronously control the stepped stress loading device to perform a stepped temperature-voltage collaborative stress test, record the degradation data and failure time at each stress level, and construct a stress-degradation-life mapping relationship model; S2. Perform wavelet denoising and normalization preprocessing on the collected data at the edge computing node. Based on the stress-degradation-life mapping relationship model, construct a stage degradation model of the thyristor through a Wiener process. The stage degradation model includes three stages: the first stage describes the stable period through linear drift, the second stage introduces a non-linear temperature-voltage coupling damage factor to describe accelerated failure, and the third stage combines a threshold jump model to predict the critical failure point; S3. Deploy an EM-MCMC joint estimation algorithm on a heterogeneous computing platform to estimate the latent variable parameters of the Wiener process. The latent variables include drift coefficients μ1, μ2 and diffusion coefficients σ1, σ2. The drift coefficients characterize the degradation trend of the thyristor, and the diffusion coefficients characterize the random fluctuations during the degradation process. The heterogeneous computing platform includes an FPGA coprocessor and a CPU main processor. The FPGA coprocessor uses a pipeline-structured MCMC sampler to perform parallel sampling on the latent variables to generate a latent variable sample chain. The CPU main processor performs EM algorithm iteration based on the sampling results to update the posterior distribution of the latent variables and the conditional probability table of the Bayesian network. The posterior distribution is used to quantify the uncertainty of the latent variable parameter estimation, and the conditional probability table of the Bayesian network is used to encode the dynamic coupling relationship between the temperature-voltage stress and the degradation trend; S4. Calculate the remaining service life and instantaneous failure rate of the thyristor according to the updated latent variable parameters, and design a dynamic correction factor based on the buffer layer structure parameters to generate a corrected reliability index; S5. Construct a dual-channel LSTM neural network to extract the degradation time series features and stress-life correlation features respectively, output a dynamic failure threshold, and compensate for the environmental temperature fluctuation through a generalized Arrhenius model; S6. Use a high-speed data acquisition card to obtain the thyristor status data in real time. When it is detected that the reliability index continuously crosses the dynamic threshold, trigger a three-level alarm signal, and reconstruct the converter topology based on a graph neural network, and mark the position and damage level of the faulty thyristor on the visualization interface.

2. The method for identifying faults of a high-voltage DC transmission converter based on reliability assessment according to claim 1, wherein: In step S1, the stress-degradation-life mapping relationship model quantifies the influence of multi-stress coupling on the life of the thyristor. The expression of the stress-degradation-life mapping relationship model is: In formula (1), C1 and C2 are material damage weight coefficients, V ref , T ref are the reference voltage and the reference junction temperature respectively, α is the temperature acceleration aging index, γ and β are the voltage acceleration aging indices, E a is the activation energy for thyristor failure, and k is the Boltzmann constant.

3. A fault identification method for a high-voltage DC transmission converter based on reliability assessment according to claim 1, characterized in that: In step S2, the first stage uses a Wiener process with linear drift to describe the early stable degradation stage of the thyristor. The expression of the first stage model is: X1(t) = μ1t + σ1B1(t) (2) In formula (1), X1(t) is the degradation amount in the first stage, μ1 is the linear drift coefficient, σ1 is the diffusion coefficient, and B1(t) is the standard Brownian motion; The second stage introduces a non-linear temperature-voltage coupling damage factor to describe accelerated failure. The expression of the second stage model is: In Equation (2), X2(t) is the degradation amount in the second stage, μ2 is the non-linear drift coefficient, is the temperature-voltage coupling damage factor, T is the junction temperature, V is the voltage stress, m is the correction coefficient, σ2 is the diffusion coefficient, and B2(t) is the standard Brownian motion; In the third stage, combined with the threshold jump model, a Poisson jump term is introduced when the degradation amount approaches the failure threshold to predict the critical failure point. The expression of the third-stage model is as follows: In formula (3), X3(t) is the degradation amount in the third stage, is the degradation amount before the i-th jump occurs, λ i is the amplitude coefficient of the i-th jump, n(t) is the number of jumps up to time t, and it follows a Poisson jump process with intensity λ t I(·) is the indicator function, N is the failure threshold, and δ(t) is the dynamic threshold buffer interval.

4. The method for identifying faults in a HVDC converter based on reliability assessment according to claim 3, wherein: The mathematical expression of the correction coefficient is as follows: In formula (5), θ is the sensitivity adjustment factor, which is updated by the gradient descent method: In formula (6), ψ ∈ (0,1) is the learning rate, and L is the mean square error loss function between the degradation data and the model output.

5. The method for identifying faults of a high-voltage DC transmission converter based on reliability assessment according to claim 1, wherein: In step S3, data interaction is realized between the FPGA coprocessor and the CPU main processor of the heterogeneous computing platform, specifically including: The dual-port RAM is divided into a parameter update area and a latent variable sampling area. The parameter update area stores the drift coefficients μ1, μ2 and the diffusion coefficients σ1, σ2, and the latent variable sampling area stores the latent variable sequence output by the MCMC sampler; The timing of the EM algorithm and the MCMC sampling is synchronized through the hardware handshake signal READY; The FPGA coprocessor batches and transfers the latent variable sampling results to the memory of the CPU main processor through DMA transfer, and the transfer bandwidth matches the update frequency of the Bayesian network conditional probability table.

6. The method for identifying faults of a high-voltage direct current transmission converter based on reliability assessment according to claim 5, wherein: The specific method steps of the EM-MCMC joint estimation algorithm are as follows: L1. Load the multi-stress level degradation data set and initialize the prior distribution of the latent variables of the Wiener process; L2. The FPGA coprocessor generates candidate samples, calculates the posterior probability ratio in parallel through the MCMC sampler, and receives the samples according to the Metropolis-Hastings criterion; L3. The CPU main processor updates the latent variables and the Bayesian network conditional probability table through the EM algorithm; L4. Repeat steps L2-L3 until the parameters converge or reach the maximum number of iterations, and output the optimal latent variable parameters.

7. The method for identifying a high-voltage direct current transmission converter fault based on reliability assessment according to claim 6, wherein: The MCMC sampler with a pipeline structure includes the following units: Normal candidate generation unit: Configure 4 groups of parallel random number generators to generate Gaussian perturbation terms through the Box-Muller algorithm, and 4 candidate latent variable parameters can be generated per cycle; Parallel likelihood calculation array: Configure 8 floating-point operation units to calculate the likelihood values of the degradation data under each stress level in parallel; Hierarchical acceptance decision unit: The first-level multiplier calculates the numerator and denominator components of the likelihood probability ratio p, the second-level comparator array calculates the acceptance probability A = min(1, p), and the third-level arbiter generates a uniform random number u ∈ [0,1] through a linear feedback shift register, executes the u ≤ A judgment, and processes one sample per clock cycle through a three-stage pipeline structure; Dual-buffer storage unit: Trigger the DMA transfer by using the ping-pong transfer mechanism.

8. The method for identifying a high-voltage direct current transmission converter fault based on reliability assessment according to claim 1, wherein: In step S4, the mathematical expression of the dynamic correction factor is as follows: In formula (7), η(t) is the dynamic correction factor, k1 and k2 are the characteristic coefficients of the buffer layer material, d 缓冲 is the actual thickness of the buffer layer, d 标称 is the designed nominal thickness, T ref , V ref are the reference junction temperature and reference voltage respectively, and T(t), V(t) are the junction temperature and voltage stress values collected in real time; the corrected reliability index is as follows: In Equation (8), R 修正 (t) is the corrected reliability index, R(t) is the original reliability index, and ∈ is the gradient compensation factor.

9. The method for identifying faults of a high-voltage DC transmission converter based on reliability assessment according to claim 1, characterized in that: In step S6, the hierarchical early warning includes: First-level early warning: When the reliability index first crosses 80% of the dynamic failure threshold, trigger a yellow early warning signal and mark the thyristor position as a potential risk area on the visualization interface; Second-level alarm: When the reliability index crosses 90% of the dynamic failure threshold for 3 consecutive sampling periods, trigger an orange alarm signal, start the redundant capacity allocation strategy of the converter, and generate a degradation trend prediction curve; Level 3 emergency shutdown: When the instantaneous value of the reliability index is lower than the dynamic failure threshold and the graph neural network reconstruction shows that the local topological impedance change rate ≥ 15%, a red shutdown signal is triggered, the arm of the faulty thyristor is cut off, and the damage level is marked by a flashing polygon in the 3D interface. The damage level is divided according to the following formula: In formula (9), U is the damage level, N is the failure threshold, [·] represents the floor operation, the damage level ranges from 1 to 10 levels, and emergency shutdown is initiated when U ≥ 7.

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