A neuronal circuit and brain-like computing system based on multi-neuromorphic behavior

Abstract

The present invention discloses a neuron circuit and a brain-like computing system based on multi-neuronal morphological behavior. The neuron circuit maps the Hindmarsh-Ross model to the physical circuit field through a capacitor dynamic response mechanism and the cross-interval nonlinear characteristics of metal-oxide semiconductor field-effect transistors, and then implements the extended Hindmarsh-Ross model through a metal-oxide semiconductor field-effect transistor design. The neuron circuit includes a membrane voltage circuit, a slow variable circuit, and a recovery variable circuit. The membrane voltage circuit is used to receive an input signal and accumulate membrane voltage. The slow variable circuit is used to accumulate a slow variable according to the membrane voltage, and to cause the neuron circuit to enter a hyperpolarization stage after the slow variable is greater than a preset threshold. The recovery variable circuit is used to delay the output of a recovery variable according to the membrane voltage, and to reset the membrane voltage to a resting potential through the recovery variable.

Description

Technical Field

[0001] The present invention belongs to the field of brain-like computing and bionic circuit technology, and specifically relates to a neuron circuit based on multi-neural morphological behavior and a brain-like computing system. Background Art

[0002] Currently, artificial intelligence (AI) is showing broad application prospects in areas such as pattern recognition, intelligent perception, and automatic control, placing higher demands on efficient, low-power, and integrable computing hardware. Traditional von Neumann-based computing systems face memory and energy bottlenecks when processing brain-inspired tasks, making it difficult to meet the requirements for real-time performance and energy efficiency. Therefore, brain-inspired computing systems based on neuronal circuits, as an effective way to implement brain-like information processing, have become an important research direction supporting neuromorphic intelligent computing systems.

[0003] Currently, there are many implementation options for neuronal circuits, but all have significant technical limitations. Traditional neuronal circuits have significant deficiencies in their behavioral patterns and can typically only simulate a single discharge pattern. This makes it impossible to dynamically adapt to diverse information processing needs when handling complex neuromorphic computing tasks, severely restricting their application in scenarios such as intelligent perception and edge computing. In addition, neuronal circuits capable of generating a variety of neuromorphic behaviors have complex circuit structures and require a large number of transistors to achieve basic functions, significantly increasing chip area and power consumption costs, further limiting the overall performance improvement of brain-inspired chips.

[0004] Traditional integrate-and-fire (IF) neuron circuits have a simple structure and are easy to integrate, but they can only simulate the accumulation and discharge of membrane voltage, resulting in a single output behavior that cannot meet the diverse discharge patterns required in cognitive computing. While the improved leaky integrate-and-fire (LIF) circuit introduces a leakage mechanism, improving biological plausibility, it is still based on a simplified first-order model and cannot express key dynamic behaviors such as adaptive firing, burst discharge, and hyperpolarization. It also cannot reflect physiological mechanisms such as sodium and potassium channels, limiting its functionality. Although complex models such as the Hodgkin-Huxley (HH) and Hindmarsh-Rose (HR) models can reproduce a variety of neural activities, their mathematical expressions are complex and lack a direct correspondence with hardware circuit components, making efficient and low-power integrated designs difficult. Summary of the Invention

[0005] In view of the shortcomings of existing neuronal circuits in behavioral diversity and hardware efficiency, the purpose of the present invention is to provide a neuronal circuit and brain-like computing system based on multi-neuromorphic behavior, providing a solution with richer dynamic characteristics and higher energy efficiency for the development of brain-like computing systems, so as to meet the urgent needs of artificial intelligence applications for complex neuromorphic computing.

[0006] In a first aspect, the present invention provides a neuron circuit based on multi-neuronal morphological behavior, comprising a membrane voltage circuit, a slow variable circuit, and a restoration variable circuit; the membrane voltage circuit is configured to receive an input signal and accumulate a membrane voltage; the slow variable circuit is configured to accumulate a slow variable according to the membrane voltage and cause the neuron circuit to enter a hyperpolarization phase after the slow variable exceeds a preset threshold; the restoration variable circuit is configured to output a restoration variable with a delay according to the membrane voltage and reset the membrane voltage to a resting potential via the restoration variable;

[0007] The membrane voltage circuit includes a membrane capacitor Cm and a positive feedback circuit; the positive feedback circuit includes three field effect transistors M1, M2 and M3; the gate of the field effect transistor M1 is connected to the gate of the field effect transistor M2, the drain of the field effect transistor M1 and the drain of the field effect transistor M3; one end of the membrane capacitor Cm is connected to the drain of the field effect transistor M2, the gate of the field effect transistor M3 and the input signal; the other end of the membrane capacitor Cm is grounded; the sources of the field effect transistors M1 and M2 are connected to the power supply voltage; and the source of the field effect transistor M3 is grounded.

[0008] Preferably, the slow variable circuit includes an integrating capacitor Cu, a leakage resistor R and two field effect transistors M4 and M5; the gate of the field effect transistor M5 is connected to the gate of the field effect transistor M1; the drain of the field effect transistor M5 is connected to the gate of the field effect transistor M4, one end of the integrating capacitor Cu, and one end of the leakage resistor R; the source of the field effect transistor M4, the other end of the integrating capacitor Cu, and the other end of the leakage resistor R are all grounded; the drain of the field effect transistor M4 is connected to the input signal; and the source of the field effect transistor M5 is connected to the power supply voltage.

[0009] Preferably, the recovery variable circuit includes a capacitor Ck and a cascade push-pull feedback circuit; the cascade push-pull feedback circuit includes five field effect transistors M6, M7, M8, M9 and M10; the drain of the field effect transistor M6 is connected to the gates of the field effect transistors M3, M7 and M8; the gate of the field effect transistor M6 is connected to the drain of the field effect transistor M9, the drain of the field effect transistor M10 and one end of the capacitor Ck; the other end of the capacitor Ck is grounded; the drains of the field effect transistors M7 and M8 are both connected to the gates of the field effect transistors M9 and M10; the sources of the field effect transistors M6, M8 and M10 are all grounded; and the sources of the field effect transistors M7 and M9 are both connected to the power supply voltage.

[0010] Preferably, the working process of the neuron circuit is as follows:

[0011] Membrane voltage circuit at input current Input activates the positive feedback circuit, accumulating membrane voltage ;Recovery variable circuit in membrane voltage When the membrane voltage increases Delayed output recovery variable and restore the variable by Control the drain current of field effect transistor M6 , so that the membrane voltage is reset to the resting potential; the slow variable circuit accumulates the action potential pulse into a slow variable through the current mirror when the membrane voltage is released , until the neuron circuit enters the hyperpolarization stage, the membrane voltage is at the resting potential, and the slow variable is released through the leakage resistor R to the initial accumulation value, and the next cycle begins.

[0012] Preferably, the condition for determining that the neuron circuit enters the hyperpolarization stage is that the gate voltage of the field effect transistor M4 is greater than the threshold voltage of the field effect transistor M4.

[0013] Preferably, the aspect ratio of the field effect transistor M5 matches that of the field effect transistor M1 to form a current mirror.

[0014] As a preference, by adjusting the current mirror ratio The parameters of the integrating capacitor Cu and the leakage resistor R control the resting state duration and the hyperpolarization period.

[0015] Preferably, the field effect transistors M1, M2, M5, M7 and M9 are P-type metal-oxide semiconductor field effect transistors; and the field effect transistors M3, M4, M6, M8 and M10 are N-type metal-oxide semiconductor field effect transistors.

[0016] Preferably, the neuron model formed by the neuron circuit is as follows:

[0017]

[0018] in, is the membrane capacitance in the membrane voltage circuit; is the membrane voltage of the neuron; is the input current; is the drain current of field effect transistor M2; is the drain current of field effect transistor M6; is the drain current of field effect transistor M4; and are the drain currents of field effect transistor M9 and field effect transistor M10 respectively; To restore the variables; is a slow variable; and They are the energy storage capacitors for recovery variables and slow variables respectively; is the current mirror ratio value; is the derivative of the resistance R.

[0019] In a second aspect, the present invention provides a brain-like computing system comprising a plurality of the aforementioned neuronal circuits; the brain-like computing system realizes the output of pulse sequences of various neuromorphic behaviors by adjusting the input current and leakage resistance R of each neuronal circuit.

[0020] The present invention has the following beneficial effects:

[0021] 1. The present invention can achieve multiple neuromorphic behaviors by adjusting the input current and leakage resistance of the neuron circuit, breaking through the limitation of existing circuits that only support a single behavior and improving the expressive power and functional flexibility of the neuromorphic computing system. At the same time, the present invention effectively simulates the emission process of neuron membrane voltage by switching MOS tubes between multiple working intervals, meeting the computational requirements of nonlinear high-order terms in neurons.

[0022] 2. The present invention can realize complex neural behaviors by using only a small number of capacitors, resistors and MOS tubes. Compared with the existing circuits with complex implementation and a large number of devices, it greatly reduces the complexity of hardware implementation and reduces the complexity of the neuron circuit structure.

[0023] 3. The present invention effectively regulates the working state of MOS tubes through capacitors and resistors, realizing the hyperpolarization process in biological neurons and improving the circuit's ability to simulate biological characteristics. At the same time, by adjusting the resistance parameters, the duration of hyperpolarization can be flexibly controlled, thereby adjusting the output mode of neuromorphic behavior, giving the neuronal circuit stronger input adaptability and improving the flexibility of behavior regulation. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is a circuit structure diagram of the present invention.

[0025] Figure 2 Schematic diagram of the changes in membrane voltage, recovery variable and slow variable at different times in the present invention; among them, (a) is a schematic diagram of the change in membrane voltage; (b) is a schematic diagram of the change in recovery variable; (c) is a schematic diagram of the change in slow variable.

[0026] Figure 3 Schematic diagram of the slow variable changing with input current in the present invention.

[0027] Figure 4 Schematic diagram of the change of membrane voltage with input current in the present invention.

[0028] Figure 5 Schematic diagram of the fast emission mode in the present invention.

[0029] Figure 6 Schematic diagram of the slow emission mode in the present invention.

[0030] In the attached figure: 1. membrane voltage circuit; 2. slow variable circuit; 3. input signal; 4. recovery variable circuit. DETAILED DESCRIPTION

[0031] The present invention will be further described below with reference to the accompanying drawings.

[0032] like Figure 1 As shown, a neuron circuit based on multi-neuromorphic behavior includes a membrane voltage circuit 1, a slow variable circuit 2, and a recovery variable circuit 4. The membrane voltage circuit 1 is used to receive an input signal 3 and accumulate membrane voltage, and accelerate the rise of the membrane voltage to form a pulse spike through a positive feedback mechanism. The membrane voltage circuit 1 includes a membrane capacitor Cm and a positive feedback circuit. The positive feedback circuit includes a field effect transistor M1, a field effect transistor M2, and a field effect transistor M3. The gate of the field effect transistor M1 is connected to the gate of the field effect transistor M2, the drain of the field effect transistor M1, and the drain of the field effect transistor M3. One end of the membrane capacitor Cm is connected to the drain of the field effect transistor M2, the gate of the field effect transistor M3, and the input signal, and the other end of the membrane capacitor Cm is grounded. The sources of the field effect transistors M1 and M2 are connected to the power supply voltage VDD. The source of the field effect transistor M3 is grounded.

[0033] In this embodiment, the field effect transistors M1 and M2 are PMOS transistors (P-type metal-oxide semiconductor field effect transistors); the field effect transistor M3 is an NMOS transistor (N-type metal-oxide semiconductor field effect transistor).

[0034] Slow variable circuit 2 is used to convert action potential pulses (the drain current of field-effect transistor M5) into a charging current for integrating capacitor Cu, achieving step-by-step accumulation of the slow variable, and setting the decay time constant via a leakage resistor. Slow variable circuit 2 includes integrating capacitor Cu, leakage resistor R, field-effect transistors M4 and M5. Field-effect transistors M5 and M1 form a current mirror, with their gates interconnected and width-to-length ratios matched. Both operate in the saturation region, achieving accurate replication of the reference current. The drain of field-effect transistor M5 is connected to the gate of field-effect transistor M4, one end of integrating capacitor Cu, and one end of leakage resistor R. The drain of field-effect transistor M4 is connected to the input signal. The source of field-effect transistor M4, the other end of integrating capacitor Cu, and the other end of leakage resistor R are all grounded. The source of field-effect transistor M5 is connected to power supply voltage VDD.

[0035] In this embodiment, the field effect transistor M4 is an NMOS transistor; the field effect transistor M5 is a PMOS transistor.

[0036] The recovery variable circuit 4 is used to receive the output signal of the membrane voltage circuit 1 and delay the output of the recovery variable, and reset the membrane voltage to the resting potential by controlling the drain current of the field effect transistor M6; the recovery variable circuit 4 includes a capacitor Ck and a cascade push-pull feedback circuit; the cascade push-pull feedback circuit includes field effect transistors M6, M7, M8, M9 and M10; the drain of the field effect transistor M6 is connected to the gates of the field effect transistors M3, M7 and M8; the gate of the field effect transistor M6 is connected to the drain of the field effect transistor M9, the drain of the field effect transistor M10 and one end of the capacitor Ck; the other end of the capacitor Ck is grounded; the drains of the field effect transistors M7 and M8 are both connected to the gates of the field effect transistors M9 and M10; the sources of the field effect transistors M6, M8 and M10 are all grounded; the sources of the field effect transistors M7 and M9 are both connected to the power supply voltage VDD.

[0037] In this embodiment, the field effect transistors M6 , M8 and M10 are NMOS transistors; the field effect transistors M7 and M9 are PMOS transistors.

[0038] The mathematical model of HR neurons is as follows:

[0039] (1)

[0040] (2)

[0041] (3)

[0042] in, is the membrane potential; is fast current; It is a slow current; It is an external stimulation current; is a constant used to adjust the discharge mode.

[0043] Formula (1) is the dynamic change of membrane voltage, formula (2) is the recovery variable used to reset the pulse, and formula (3) is the slow variable of rhythmic modulation and pulse burst. 、 and The equation is divided into dynamic variables on the left side, representing the changes in the neuron state over time, and functional variables on the right side, describing the mechanism driving these changes. This separation corresponds directly to basic electronic behavior. The time derivative operation in the dynamic variables is inherently consistent with the dynamic characteristics of the capacitor voltage, while the nonlinear behavior in the functional variables can be realized through the nonlinear current characteristics of the transistor. Therefore, the dynamic variables can be mapped to capacitors, and the functional variables can be mapped to transistors, realizing the correspondence between the mathematical model of the HR neuron and the physical extended model. The specific mapping method is as follows:

[0044] In formula (1) The membrane voltage Control the drain current generated by field effect transistor M2 The working state of the field effect tube M2 (subthreshold, saturation, linear) will cause the drain current The exponential, quadratic and linear changes enable the membrane voltage to respond quickly and drive the formation of spikes. In the extended HR model, due to the amplitude limitation of the hardware voltage supply, the nonlinear term No longer needed. The nonlinear current (drain current) generated by the field effect transistor M6 ) replaces the In the HR mathematical model, due to It is a negative value, so the drain current Add a minus sign before At the same time, the drain current of FET M4 Instead of the formula (1) According to the above replacement, the first-order dynamic response equation composed of the drain current of the field effect tube and the membrane capacitor Cm in the membrane voltage circuit 1 realizes the mapping from formula (1) to formula (4), which is as follows:

[0045] (4)

[0046] The constant of the recovery variable in formula (2) Replaced by GND, indicating a baseline of 0. The drain current of FET M9 At the same time, the drain current through the field effect transistor M10 Replacement fast current Based on the above substitution, the first-order dynamic response equation composed of the drain current and capacitor Ck in the recovery variable circuit 4 realizes the mapping from (2) to (5), and the formula is as follows:

[0047] (5)

[0048] The constant in formula (3) Replace it with a capacitor value to adjust the response speed of slow variables. Using GND instead means the resting potential is 0. use Replacement; among them, Represents the current mirror ratio value. Constant This is achieved through a linear resistor structure. This structure combines the recovery variable and resistors To achieve the function of slow-changing dynamic attenuation. Based on the above substitution, the first-order dynamic response equation composed of the drain current of the field effect transistor in the slow-variable circuit 2 and the capacitor Cu realizes the mapping from (3) to (6), and the formula is as follows:

[0049] (6)

[0050] Therefore, the HR neuron model is extended as follows:

[0051] (7)

[0052] in, is the membrane capacitance in the membrane voltage circuit; is the membrane voltage of the neuron; is the input current; is the drain current of field effect transistor M2; is the drain current of field effect transistor M6; is the drain current of field effect transistor M4; and are the drain currents of field effect transistor M9 and field effect transistor M10 respectively; To restore the variables; is a slow variable; and They are the energy storage capacitors for recovery variables and slow variables respectively; is the current mirror ratio value; is the derivative of resistance and is used to implement the leakage function.

[0053] The neuron circuit works as follows:

[0054] Membrane voltage circuit 1 at input current The positive feedback circuit is activated when input is applied, causing the membrane voltage to Rapid accumulation and accelerated membrane voltage through a positive feedback mechanism The membrane voltage circuit 1 achieves a rapid response to the input signal and an efficient generation of pulse spikes through the synergistic effect of membrane capacitance integration and positive feedback.

[0055] Recovery variable circuit 4 in membrane voltage When the voltage increases rapidly, the output signal of the membrane voltage circuit is received through the cascade push-pull feedback circuit, and the received signal is delayed and output to restore the variable through the cascade push-pull feedback circuit. ; Restore variables By controlling the drain current of FET M6 The membrane voltage is reset to the resting potential, and the membrane voltage circuit 1 restarts the accumulation of the membrane voltage.

[0056] The slow variable circuit 2 converts the action potential pulse into a charging current for the capacitor Cu through the current mirror each time the membrane voltage is released, thus realizing the slow variable (the gate voltage of the field effect transistor M4). At the same time, by forming a leakage circuit by connecting the integral capacitor Cu and the leakage resistor R in parallel, the decay time constant is set to achieve the slow variable leakage and energy storage; when the slow variable When the voltage reaches the threshold voltage of the field effect tube M4, the hyperpolarization mechanism of the neuron is triggered, and the current mirror ratio is adjusted. The parameters of the integrating capacitor Cu and the leakage resistor R can control the resting state duration and hyperpolarization period, thereby realizing dynamic regulation of the periodic accumulation-discharge process of the neuronal membrane voltage.

[0057] A brain-like computing system is constructed using multiple neuron circuits, and the pulse sequence output of various neuromorphic behaviors is achieved by adjusting the input current and leakage resistance R of each neuron circuit.

[0058] like Figure 2 As shown, when the input signal is When the membrane capacitor Cm accumulates charge, the membrane voltage It rises and acts as a control signal to drive the field effect tube M3, triggering a positive feedback loop and accelerating the membrane voltage The rising process of membrane voltage A hysteresis recovery variable signal is generated by the cascade push-pull circuit and the capacitor Ck. , restore the variable signal The rapidly rising membrane voltage is reset to the resting potential by controlling the gate of the field effect tube M6; the slow variable circuit 2 accumulates the integral capacitor Cu through the current mirror during each membrane voltage release process. After three accumulations, the slow variable When the voltage accumulates to the threshold voltage of the field effect transistor M4, the neuron circuit enters the hyperpolarization stage, and the membrane voltage is in a long-term resting potential until the slow variable is slowly released to the initial accumulation value through the leakage resistor R, and a new round of cycle begins.

[0059] like Figure 3 As shown, the slow variable With input current The slow variable increases steadily, and this increase has a clear mapping relationship. Specifically, under different input current conditions, the slow variable The membrane voltage gradually increases during the accumulation period. Each time the slow variable is released, the membrane voltage rises one step, and when the threshold voltage is reached, the hyperpolarization mechanism is triggered to make the neuron enter a long-term resting state potential.

[0060] like Figure 4 As shown, when the input signals are 、 、 、 、 、 、 、 When the neuron circuit receives input current, the positive feedback circuit is rapidly activated as the membrane voltage accumulates, accelerating the increase in membrane voltage. The increased membrane voltage is reset to rest by the hysteresis signal generated by the recovery variable. During each membrane voltage release, the slow variable circuit 2 accumulates the voltage on capacitor Cu through a current mirror. Once the accumulated voltage reaches the threshold voltage of field-effect transistor M4, the neuron circuit immediately enters the hyperpolarization phase, causing the membrane voltage to maintain a long-term resting potential until the slow variable is slowly released through the leakage resistor R to the initial value of accumulation. This cycle repeats. As the input signal increases, the long-term resting state caused by the slow variable hyperpolarization process becomes shorter and the energy dissipated becomes lower, resulting in the membrane voltage's clustered pulse emission behavior that changes with the stimulus intensity and exhibits eight different neuromorphic behaviors.

[0061] like Figure 5 As shown in Figure 2, when the resistance of the resistor in the slow variable circuit 2 is 0.5MΩ and the input current is 30μA, the neuron circuit is in the fast firing mode. The accumulated membrane voltage begins to accumulate As a control signal to control the field effect tube M3, it activates the positive feedback circuit to accelerate the increase of the membrane voltage; restore the variable signal By controlling the field effect transistor M6, the rapidly rising membrane voltage is reset to the resting potential; the slowly increasing variable accumulates to the threshold voltage of the field effect transistor M4, causing the neuron circuit to enter the hyperpolarization stage.

[0062] like Figure 6 As shown, when the resistance value of the resistor in the slow variable circuit 2 is 2MΩ and the input current is 30μA, the neuron circuit is in the slow firing mode; the resistance value increases the time constant of the slow variable circuit 2, making the slow variable By reducing the speed of dissipation of the resistor, the duration of the hyperpolarization phase of the neuron circuit is increased. By adjusting the resistance value of the resistor, the emission frequency can be continuously adjusted, forming the frequency modulation characteristic of the neuron circuit.

[0063] The above-described embodiments merely represent several implementation methods of the present application. The detailed descriptions are intended to clearly illustrate the inventor's invention verification process, but are not to be construed as limiting the scope of patent protection for the present invention. It should be noted that a person skilled in the art may make various improvements and optimizations without departing from the principles of the present invention, and these improvements and optimizations fall within the scope of protection of the present application.

Claims

1. A neuron circuit based on multi-neuronal morphological behavior, comprising a membrane voltage circuit (1), a slow variable circuit (2) and a recovery variable circuit (4); the membrane voltage circuit (1) is used to receive an input signal (3) and accumulate membrane voltage; the slow variable circuit (2) is used to accumulate the slow variable according to the membrane voltage, and to cause the neuron circuit to enter a hyperpolarization stage after the slow variable is greater than a preset threshold; The recovery variable circuit (4) is used for outputting a recovery variable according to the membrane voltage delay, and resetting the membrane voltage to the resting potential through the recovery variable; Its characteristics are: The membrane voltage circuit includes a membrane capacitor Cm and a positive feedback circuit; the positive feedback circuit includes three field effect transistors M1, M2, and M3; the gate of the field effect transistor M1 is connected to the gate of the field effect transistor M2, the drain of the field effect transistor M1, and the drain of the field effect transistor M3; one end of the membrane capacitor Cm is connected to the drain of the field effect transistor M2, the gate of the field effect transistor M3, and the input signal; the other end of the membrane capacitor Cm is grounded; the sources of the field effect transistors M1 and M2 are connected to the power supply voltage; and the source of the field effect transistor M3 is grounded; The slow variable circuit includes an integrating capacitor Cu, a leakage resistor R, and two field effect transistors M4 and M5; the gate of the field effect transistor M5 is connected to the gate of the field effect transistor M1; the drain of the field effect transistor M5 is connected to the gate of the field effect transistor M4, one end of the integrating capacitor Cu, and one end of the leakage resistor R; the source of the field effect transistor M4, the other end of the integrating capacitor Cu, and the other end of the leakage resistor R are all grounded; the drain of the field effect transistor M4 is connected to the input signal; the source of the field effect transistor M5 is connected to the power supply voltage; The recovery variable circuit includes a capacitor Ck and a cascade push-pull feedback circuit; the cascade push-pull feedback circuit includes five field effect transistors M6, M7, M8, M9 and M10; the drain of the field effect transistor M6 is connected to the gates of the field effect transistors M3, M7 and M8; the gate of the field effect transistor M6 is connected to the drain of the field effect transistor M9, the drain of the field effect transistor M10 and one end of the capacitor Ck; the other end of the capacitor Ck is grounded; the drains of the field effect transistors M7 and M8 are both connected to the gates of the field effect transistors M9 and M10; the sources of the field effect transistors M6, M8 and M10 are all grounded; and the sources of the field effect transistors M7 and M9 are both connected to the power supply voltage.

2. The multi-neuromorphic behavior-based neuron circuit according to claim 1, characterized in that: The working process of this neuron circuit is as follows: Membrane voltage circuit at input current Input activates the positive feedback circuit, accumulating membrane voltage ; Recovery variable circuit in membrane voltage When the membrane voltage increases Delayed output recovery variable and restore the variable by Control the drain current of field effect transistor M6 , so that the membrane voltage is reset to the resting potential; The slow variable circuit accumulates the action potential pulse into a slow variable when the membrane voltage is released through the current mirror , until the neuron circuit enters the hyperpolarization stage, the membrane voltage is at the resting potential, and the slow variable is released through the leakage resistor R to the initial accumulation value, and the next cycle begins.

3. The multi-neuromorphic behavior-based neuron circuit according to claim 2, characterized in that: The condition for judging that the neuron circuit enters the hyperpolarization stage is that the gate voltage of the field effect transistor M4 is greater than the threshold voltage of the field effect transistor M4.

4. The multi-neuromorphic behavior-based neuron circuit according to claim 1, characterized in that: The width-to-length ratio of the field effect tube M5 matches that of the field effect tube M1 to form a current mirror.

5. The multi-neuromorphic behavior-based neuron circuit according to claim 4, characterized in that: By adjusting the current mirror ratio The parameters of the integrating capacitor Cu and the leakage resistor R control the resting state duration and the hyperpolarization period.

6. The multi-neuromorphic behavior-based neuron circuit according to claim 1, characterized in that: The field effect transistors M1, M2, M5, M7 and M9 are P-type metal-oxide semiconductor field effect transistors; the field effect transistors M3, M4, M6, M8 and M10 are N-type metal-oxide semiconductor field effect transistors.

7. The multi-neuromorphic behavior-based neuron circuit according to claim 1, characterized in that: The neuron model composed of this neuron circuit is as follows: ； in, is the membrane capacitance in the membrane voltage circuit; is the membrane voltage of the neuron; is the input current; is the drain current of field effect transistor M2; is the drain current of field effect transistor M6; is the drain current of field effect transistor M4; and are the drain currents of field effect transistor M9 and field effect transistor M10 respectively; To restore the variables; is a slow variable; and They are the energy storage capacitors for recovery variables and slow variables respectively; is the current mirror ratio value; is the derivative of the resistance R.

8. A brain-inspired computing system, characterized in that: The invention comprises a plurality of neuron circuits with multiple neuromorphic behaviors as described in any one of claims 1 to 7; the brain-like computing system realizes the pulse sequence output of multiple neuromorphic behaviors by adjusting the input current and leakage resistance R of each neuron circuit.

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