Multifunctional floating gate transistor based on two-dimensional material heterojunction and preparation method thereof

Abstract

The invention provides a multifunctional floating gate transistor based on a two-dimensional material heterojunction and a preparation method thereof, and relates to the technical field of semiconductors, and the multifunctional floating gate transistor comprises a substrate which comprises a back gate and a gate dielectric layer which are stacked from bottom to top; the floating gate layer is located on the surface, away from the back gate, of the gate dielectric layer; the tunneling dielectric layers are located on the surfaces, away from the back gate, of the floating gate layer and the gate dielectric layer respectively, and the floating gate layer is covered with the tunneling dielectric layers; the channel layer is located on the surface, away from the substrate, of the tunneling dielectric layer, and the first orthographic projection of the channel layer on the substrate and the second orthographic projection of the floating gate layer on the substrate are at least partially overlapped; the channel layer is also provided with a source electrode and a drain electrode, and a channel region is formed between the source electrode and the drain electrode. The multifunctional floating gate transistor based on the two-dimensional material heterojunction can be used as a nonvolatile memory and has excellent storage capability.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a multifunctional floating-gate transistor based on a two-dimensional material heterojunction and a preparation method thereof. Background Art

[0002] With the rapid development of the Internet of Things and the popularization of big data, the demand for non-volatile storage technology is rapidly escalating, especially in terms of storage windows and multi-level storage capabilities.

[0003] Currently, two-dimensional materials have become an ideal choice for building high-performance memory and neuromorphic devices due to their excellent performance brought by their atomic-level thickness and arbitrary stacking ability. Therefore, how to provide a suitable multifunctional two-dimensional material device is a technical problem that needs to be solved urgently. Summary of the Invention

[0004] In view of this, the present application proposes a multifunctional floating-gate transistor based on a two-dimensional material heterojunction and a preparation method thereof.

[0005] In a first aspect, the present application provides a multifunctional floating-gate transistor based on a two-dimensional material heterojunction, comprising:

[0006] A substrate comprising a back gate and a gate dielectric layer stacked from bottom to top;

[0007] a floating gate layer, located on a surface of the gate dielectric layer away from the back gate;

[0008] a tunneling dielectric layer, located respectively on surfaces of the floating gate layer and the gate dielectric layer away from the back gate, the tunneling dielectric layer covering the floating gate layer;

[0009] a channel layer located on a surface of the tunnel dielectric layer away from the substrate, wherein a first orthographic projection of the channel layer on the substrate at least partially overlaps with a second orthographic projection of the floating gate layer on the substrate; a source electrode and a drain electrode are further provided on the channel layer, and a channel region is formed between the source electrode and the drain electrode;

[0010] When a voltage pulse is applied to the back gate, the carriers in the channel layer are transferred between the channel layer and the floating gate layer under the driving of the internal electric field of the multifunctional floating gate transistor; after the voltage pulse is removed, the wide bandgap effect of the tunneling dielectric layer prevents the carriers from tunneling back, so that the remaining carriers in the floating gate layer are retained for a long time.

[0011] In one embodiment, the back gate is made of silicon, the gate dielectric layer is made of silicon dioxide, and the thickness of the silicon dioxide is 250-350 nm.

[0012] In one embodiment, the material of the floating gate layer is graphene, and the thickness of the floating gate layer is 15 - 25 nm;

[0013] The material of the tunneling dielectric layer is hexagonal boron nitride, and the thickness of the tunneling dielectric layer is 10 - 20 nm;

[0014] The material of the channel layer is molybdenum ditelluride, and the thickness of the channel layer is 5 - 10 nm.

[0015] In one embodiment, the source electrode and the drain electrode include a chromium layer and a gold layer stacked from bottom to top, the thickness of the chromium layer is 4 - 6 nm, and the thickness of the gold layer is 45 - 55 nm.

[0016] In a second aspect, the present application further provides a preparation method of a multifunctional floating gate transistor based on a two-dimensional material heterojunction. The preparation method includes:

[0017] [[ID=!5]]Providing a substrate, the substrate includes a back gate and a gate dielectric layer stacked from bottom to top;

[0018] Forming a floating gate layer on the surface of the gate dielectric layer away from the back gate;

[0019] Forming a tunneling dielectric layer covering the floating gate layer on the surfaces of the floating gate layer and the gate dielectric layer away from the back gate;

[0020] Forming a channel layer on the surface of the tunneling dielectric layer away from the substrate, and the first orthographic projection of the channel layer on the substrate at least partially overlaps with the second orthographic projection of the floating gate layer on the substrate;

[0021] Respectively forming a source electrode and a drain electrode on the surface of the channel layer away from the substrate.

[0022] In one embodiment, forming the floating gate layer on the surface of the gate dielectric layer away from the back gate includes:

[0023] Using the mechanical exfoliation method to extend a graphene material block into a graphene thin sheet;

[0024] Transferring the graphene thin sheet to the surface of the gate dielectric layer away from the back gate by dry transfer to form the floating gate layer.

[0025] In one embodiment, forming the tunneling dielectric layer covering the floating gate layer on the surfaces of the floating gate layer and the gate dielectric layer away from the back gate includes:

[0026] Using the mechanical exfoliation method to extend a hexagonal boron nitride material block into a hexagonal boron nitride thin sheet;

[0027] Transfer the hexagonal boron nitride sheet to the surface of the floating gate layer and the gate dielectric layer away from the back gate by dry transfer to form the tunneling dielectric layer covering the floating gate layer.

[0028] In one embodiment, forming a channel layer on the surface of the tunneling dielectric layer away from the substrate includes:

[0029] Extend a molybdenum disulfide material block into a molybdenum disulfide sheet by mechanical exfoliation;

[0030] Transfer the molybdenum disulfide sheet to the surface of the tunneling dielectric layer away from the substrate by dry transfer to form the channel layer.

[0031] In a third aspect, the present application also provides an artificial synapse, which uses the multifunctional floating gate transistor as described in the first aspect. The presynaptic stimulus of the artificial synapse is the back gate voltage pulse of the multifunctional floating gate transistor, and the postsynaptic current of the artificial synapse is the channel layer current of the multifunctional floating gate transistor.

[0032] In a fourth aspect, the present application also provides an artificial nociceptor, which uses the multifunctional floating gate transistor as described in the first aspect. The external nociceptive stimulus of the artificial nociceptor is the back gate voltage pulse of the multifunctional floating gate transistor, and the response signal of the artificial nociceptor is the channel layer current of the multifunctional floating gate transistor.

[0033] The multifunctional floating gate transistor based on two-dimensional material heterojunction of the present application has the following beneficial effects compared with the related technology:

[0034] 1. For the multifunctional floating gate transistor based on two-dimensional material heterojunction of the present application, by applying a negative voltage to the back gate, a large number of holes in the channel layer can pass through the tunneling dielectric layer and enter the floating gate layer. After removing the pulse, due to the existence of the tunneling dielectric layer barrier, a large number of holes are trapped in the floating gate layer and cannot return to the channel layer, completing the write operation. When a positive voltage is applied to the back gate, a large number of holes trapped in the floating gate layer pass through the tunneling dielectric layer and return to the channel layer, and at the same time, a small amount of electrons in the channel layer pass through the tunneling dielectric layer and enter the floating gate layer. After removing the pulse, due to the existence of the tunneling dielectric layer barrier, a small amount of electrons are trapped in the floating gate layer, and a large number of holes remain in the channel layer, completing the erase operation. Therefore, the multifunctional floating gate transistor based on two-dimensional material heterojunction of the present application can be used as a non-volatile memory.

[0035] 2. For the multifunctional floating gate transistor provided by the present application, its storage window can increase with the increase of the back gate voltage scanning range. Therefore, the multifunctional floating gate transistor of the present application has excellent storage ability.

[0036] 3. Since the number of holes in the floating gate layer can be effectively controlled by the magnitude of the voltage applied to the back gate and the pulse time, the multifunctional floating gate transistor of the present application can record multiple different storage states during writing and erasing; and during reading, the current passing through the source electrode and the drain electrode is in different intervals under different storage states, enabling the reading of multiple different storage states. Therefore, the multifunctional floating gate transistor of the present application has excellent multi-level storage capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] To more clearly illustrate the technical solutions in the embodiments of the present application or the related art, the following will briefly introduce the drawings required for use in the description of the embodiments or the related art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0038] Figure 1 Schematic cross-sectional structure diagram of a multifunctional floating gate transistor based on a two-dimensional material heterojunction in an embodiment of the present application;

[0039] Figure 2 Schematic flow diagram of a method for manufacturing a multifunctional floating gate transistor based on a two-dimensional material heterojunction in an embodiment of the present application;

[0040] Figure 3 Schematic cross-sectional structure diagram of the substrate provided in step S201 in an embodiment of the present application;

[0041] Figure 4 Schematic cross-sectional structure diagram of the structure formed in step S202 in an embodiment of the present application;

[0042] Figure 5 Schematic cross-sectional structure diagram of the structure formed in step S203 in an embodiment of the present application;

[0043] Figure 6 Schematic cross-sectional structure diagram of the structure formed in step S204 in an embodiment of the present application;

[0044] Figure 7a and Figure 7b Are respectively the transfer curve under different back gate voltage scanning ranges and the multi-level storage schematic diagram triggered by input pulses of different amplitudes;

[0045] Figure 8a and Figure 8b Are respectively the schematic diagrams of the postsynaptic current triggered by positive pulses of different frequencies and negative pulses of different frequencies;

[0046] Figure 9 Schematic diagram of the minimum power consumption of the floating gate transistor in an embodiment of the present application;

[0047] Figure 10a Schematic diagram of postsynaptic current triggered by sequential application of 200 positive pulses and 200 negative pulses in one embodiment of the present application;

[0048] Figure 10b Schematic diagram of the image recognition accuracy using floating-gate transistors as artificial synapses in one embodiment of the present application;

[0049] Figure 11a This is a schematic diagram of response current triggered by pulses of different amplitudes in one embodiment of the present application;

[0050] Figure 11b A schematic diagram of a response current triggered by a pair of pulses with different intervals in one embodiment of the present application;

[0051] Figure 12a This is a schematic diagram of the response current triggered by multiple consecutive 1.5V and 2V pulses in one embodiment of the present application;

[0052] Figure 12b Schematic diagram of response current under undamaged, 4V damaged and 5V damaged conditions in one embodiment of the present application.

[0053] Description of reference numerals:

[0054] 10 - substrate, 11 - back gate, 12 - gate dielectric layer, 13 - floating gate layer, 14 - tunneling dielectric layer, 15 - channel layer, 16 - source electrode, 17 - drain electrode. DETAILED DESCRIPTION

[0055] The following will be combined with the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0056] As described in the background technology, with the rapid development of the Internet of Things and the popularization of big data, the demand for non-volatile storage technology is rapidly escalating, especially in terms of storage windows and multi-level storage capabilities.

[0057] Currently, two-dimensional materials have become an ideal choice for building high-performance memory and neuromorphic devices due to their excellent performance brought by their atomic-level thickness and arbitrary stacking ability. Therefore, how to provide a suitable multifunctional two-dimensional material device is a technical problem that needs to be solved urgently.

[0058] Based on this, Figure 1As shown in the figure, an embodiment of the present application provides a multifunctional floating gate transistor based on a two-dimensional material heterojunction. The multifunctional floating gate transistor includes: a substrate 10, a floating gate layer 13, a tunneling dielectric layer 14, a channel layer 15, a source electrode 16, and a drain electrode 17. It should be noted that Figure 1 the positions of the source electrode 16 and the drain electrode 17 can be interchanged.

[0059] The substrate 10 includes a back gate 11 and a gate dielectric layer 12 stacked from bottom to top. The floating gate layer 13 is located on the surface of the gate dielectric layer 12 away from the back gate 11. The tunneling dielectric layer 14 is respectively located on the surfaces of the floating gate layer 13 and the gate dielectric layer 12 away from the back gate 11, and the tunneling dielectric layer 14 covers the floating gate layer 13. The channel layer 15 is located on the surface of the tunneling dielectric layer 14 away from the substrate 10. The first orthographic projection of the channel layer 15 on the substrate 10 and the second orthographic projection of the floating gate layer 13 on the substrate 10 at least partially overlap. Exemplarily, the second orthographic projection of the floating gate layer 13 on the substrate 10 can cover the first orthographic projection of the channel layer 15 on the substrate 10. The source electrode 16 and the drain electrode 17 are further provided on the channel layer 15, and a channel region is formed between the source electrode 16 and the drain electrode 17.

[0060] Among them, when a voltage pulse is applied to the back gate 11, under the drive of the internal electric field of the multifunctional floating gate transistor, the carriers in the channel layer 15 are transferred between the channel layer 15 and the floating gate layer 13; after the voltage pulse is removed, the wide bandgap effect of the tunneling dielectric layer 14 prevents the carriers from tunneling back, so that the remaining carriers in the floating gate layer 13 are retained for a long time.

[0061] It can be understood that when a negative voltage is applied to the back gate 11, a large number of holes in the channel layer 15 pass through the tunneling dielectric layer 14 and enter the floating gate layer 13. After the pulse is removed, due to the existence of the potential barrier of the tunneling dielectric layer 14, a large number of holes are trapped in the floating gate layer 13 and cannot return to the channel layer 15, completing the write operation. When a positive voltage is applied to the back gate 11, a large number of holes trapped in the floating gate layer 13 pass through the tunneling dielectric layer 14 and return to the channel layer 15. At the same time, a small amount of electrons in the channel layer 15 pass through the tunneling dielectric layer 14 and enter the floating gate layer 13. After the pulse is removed, due to the existence of the potential barrier of the tunneling dielectric layer 14, a small amount of electrons are trapped in the floating gate layer 13, while a large number of holes remain in the channel layer 15, completing the erase operation. Therefore, the multifunctional floating gate transistor based on the two-dimensional material heterojunction of the present application can be used as a non-volatile memory.

[0062] In applications, as Figure 2 shown, Figure 2 a in the figure is the transfer curve within different back gate 11 voltage scanning ranges. During the test, the source-drain voltage V dsIt is fixed at 0.2V (in subsequent tests, unless otherwise stated, the source-drain voltage is fixed at 0.2V). It can be seen that its storage window increases with the increase of the back-gate 11 voltage scanning range. The storage window under the back-gate 11 voltage scanning range of ±40V is 65.82V, and the corresponding storage window ratio is 82.28%, showing excellent storage ability. Figure 2 In b of Figure 2 , after applying 8 pulses with different amplitudes (pulse widths are all 500ms), 8 different current states can be clearly distinguished within the test time of more than 100s, showing excellent multi-level storage ability.

[0063] For the multi-functional floating-gate transistor of the above two-dimensional material heterojunction, by applying a negative voltage to the back-gate 11, a large number of holes in the channel layer 15 can pass through the tunneling dielectric layer 14 and enter the floating-gate layer 13. After removing the pulse, due to the existence of the tunneling dielectric layer 14 barrier, a large number of holes are trapped in the floating-gate layer 13 and cannot return to the channel layer 15, completing the write operation. When a positive voltage is applied to the back-gate 11, a large number of holes trapped in the floating-gate layer 13 pass through the tunneling dielectric layer 14 and return to the channel layer 15. At the same time, a small number of electrons in the channel layer 15 pass through the tunneling dielectric layer 14 and enter the floating-gate layer 13. After removing the pulse, due to the existence of the tunneling dielectric layer 14 barrier, a small number of electrons are trapped in the floating-gate layer 13, and a large number of holes remain in the channel layer 15, completing the erase operation. Therefore, the multi-functional floating-gate transistor based on the two-dimensional material heterojunction of the present application can be used as a non-volatile memory. In addition, the storage window of the multi-functional floating-gate transistor can increase with the increase of the back-gate 11 voltage scanning range. Therefore, the multi-functional floating-gate transistor of the present application has excellent storage ability.

[0064] It can also be understood that since the number of holes in the floating-gate layer 13 can be effectively controlled by the magnitude of the voltage applied to the back-gate 11 and the pulse time, therefore, when writing and erasing, the multi-functional floating-gate transistor of the present application can record multiple different storage states; and when reading, the current passing through the source electrode 16 and the drain electrode 17 is in different intervals in different storage states, and multiple different storage states can be read. Therefore, the multi-functional floating-gate transistor of the present application has excellent multi-level storage ability.

[0065] In some embodiments, the material of the back-gate 11 is silicon, the material of the gate dielectric layer 12 is silicon dioxide, and the thickness of the silicon dioxide is 250 - 350nm.

[0066] It can be understood that the back gate 11 is made of silicon, which is the most commonly used basic material in the semiconductor industry. It has excellent electrical properties, mature manufacturing processes, and good mechanical stability, and can provide a stable substrate support and charge regulation basis for the device. The gate dielectric layer 12 is made of silicon dioxide because it has natural good compatibility with the silicon substrate 10 (a silicon dioxide layer can be naturally formed on the silicon surface), and as an insulating medium, it can effectively isolate the back gate 11 (silicon) from the floating gate, regulate the carrier migration through a stable electric field effect, and at the same time has high insulation strength, low leakage current, and long-term reliability.

[0067] In applications, the material of the back gate 11 can also include other materials, such as III-V compounds like gallium arsenide. When the material of the back gate 11 changes, the material of the gate dielectric layer 12 can be adjusted accordingly. Those skilled in the art can select the constituent material of the substrate 10 according to the type of device structure formed on the substrate 10.

[0068] Exemplarily, the thickness of the silicon dioxide can be 250 nm, 260 nm, 270 nm, 280 nm, 290 nm, 300 nm, 310 nm, 320 nm, 330 nm, 340 nm, 350 nm. Also exemplarily, the thickness of the silicon dioxide can be 300 nm. It should be noted that the thicknesses in the above examples are only some examples of the embodiments of this application, and the thickness of the silicon dioxide can be any value between 250 and 350 nm.

[0069] In one embodiment, the material of the floating gate layer 13 is graphene, and the thickness of the floating gate layer 13 is 15 - 25 nm. The material of the tunneling dielectric layer 14 is hexagonal boron nitride, and the thickness of the tunneling dielectric layer 14 is 10 - 20 nm. The material of the channel layer 15 is molybdenum disulfide, and the thickness of the channel layer 15 is 5 - 10 nm.

[0070] It can be understood that the floating gate layer 13 is made of graphene because it has excellent electrical conductivity, single-atom layer thickness, and high carrier mobility, can efficiently store and regulate charges, and the thickness range of 15 - 25 nm can achieve effective electric field modulation of the channel layer 15 while ensuring structural stability. The tunneling dielectric layer 14 is made of hexagonal boron nitride (h-BN), whose atomically flat insulating properties form a good interface match with two-dimensional materials such as graphene and molybdenum disulfide. The thickness of 10 - 20 nm not only ensures the barrier height required for the quantum tunneling effect but also can control the efficiency of charge injection / release. The channel layer 15 is made of molybdenum disulfide (MoTe2). As a two-dimensional semiconductor material, its thickness of 5 - 10 nm can achieve a strong quantum confinement effect, have a suitable bandgap and electron mobility, and facilitate the floating gate layer 13 to precisely regulate the channel carrier concentration through the electric field applied by the tunneling dielectric layer 14, thereby realizing the storage or logic function of the device.

[0071] Exemplarily, the thickness of the floating gate layer 13 can be 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm. Again exemplarily, the thickness of the floating gate layer 13 can be 20 nm. It should be noted that the thicknesses of the above examples are only partial examples of the embodiments of the present application, and the thickness of the floating gate layer 13 can be any value between 15 and 25 nm.

[0072] Exemplarily, the thickness of the tunneling dielectric layer 14 can be 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm. Again exemplarily, the thickness of the tunneling dielectric layer 14 can be 20 nm. It should be noted that the thicknesses of the above examples are only partial examples of the embodiments of the present application, and the thickness of the floating gate layer 13 can be any value between 10 and 20 nm.

[0073] Exemplarily, the thickness of the channel layer 15 can be 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm. Again exemplarily, the thickness of the channel layer 15 can be 8 nm. It should be noted that the thicknesses of the above examples are only partial examples of the embodiments of the present application, and the thickness of the channel layer 15 can be any value between 5 and 10 nm.

[0074] It should also be noted that the floating gate layer 13, the tunneling dielectric layer 14, and the channel layer 15 can also be made of other types of materials. For example, the floating gate layer 13 can be made of HfS2, the tunneling dielectric layer 14 can be made of Al2O3, and the channel layer 15 can be made of WSe2.

[0075] In one embodiment, the source electrode 16 and the drain electrode 17 include a chromium layer and a gold layer stacked from bottom to top. The thickness of the chromium layer is 4 - 6 nm, and the thickness of the gold layer is 45 - 55 nm.

[0076] It can be understood that the source electrode 16 and the drain electrode 17 adopt a stacked structure of a chromium (Cr) layer and a gold (Au) layer from bottom to top. The chromium layer with a thickness of 4 - 6 nm serves as the bottom layer, and its good adhesion characteristics are used to ensure a stable bond between the electrode and the channel layer 15, avoiding peeling or interface defects that occur when the gold layer is directly deposited. The upper gold layer with a thickness of 45 - 55 nm relies on its extremely low resistivity (about 2.4×10 -8 Ω·m) and excellent chemical stability (corrosion resistance, oxidation resistance) to provide a conductive path with low contact resistance. At the same time, the thick gold layer can reduce the edge effect or fracture risk during the electrode preparation process. This combination takes into account both the electrical performance of the device and the process reliability.

[0077] Exemplarily, the thickness of the chromium layer can be 4 nm, 5 nm, or 6 nm. Again exemplarily, the thickness of the chromium layer can be 5 nm. It should be noted that the thicknesses in the above examples are only partial examples of the embodiments of the present application, and the thickness of the chromium layer can be any value between 5 and 10 nm.

[0078] Exemplarily, the thickness of the gold layer is 45 nm, 46 nm, 47 nm, 48 nm, 49 nm, 50 nm, 51 nm, 52 nm, 53 nm, 54 nm, or 55 nm. Again exemplarily, the thickness of the gold layer is 50 nm. It should be noted that the thicknesses in the above examples are only partial examples of the embodiments of the present application, and the thickness of the gold layer can be any value between 45 and 55 nm.

[0079] It should also be noted that the source electrode 16 and the drain electrode 17 can also be made of other types of materials. For example, in the source electrode 16 and the drain electrode 17, Cr can be replaced with Ti, and Au can be replaced with Pd or Ag.

[0080] The embodiments of the present application also provide a method for manufacturing a multifunctional floating-gate transistor based on a two-dimensional material heterojunction. As Figure 2 shown, the manufacturing method includes the following steps S201 to S205.

[0081] S201: Provide a substrate 10, where the substrate 10 includes a back gate 11 and a gate dielectric layer 12 stacked from bottom to top, as Figure 3 shown.

[0082] Among them, the back gate 11 can be a silicon wafer, and the gate dielectric layer 12 can be silicon dioxide. Exemplarily, a silicon wafer with a 300-nm SiO2 oxide layer can be used as the substrate 10, and the substrate 10 is successively placed in acetone, absolute ethanol, and deionized water for ultrasonic cleaning for a predetermined time (e.g., 15 min), and then dried with nitrogen.

[0083] S202: Form a floating-gate layer 13 on the surface of the gate dielectric layer 12 away from the back gate 11, forming a structure as Figure 4 shown.

[0084] Among them, the floating-gate layer 13 can be formed by methods such as mechanical exfoliation or chemical vapor deposition (CVD).

[0085] The mechanical exfoliation method can obtain an extended thin film by repeatedly peeling a tape from a bulk material of the floating-gate layer 13 and transferring it to the surface of the gate dielectric layer 12 with the assistance of PDMS. The chemical vapor deposition method can first grow a floating-gate material layer on a corresponding substrate 10 (e.g., a copper or nickel substrate 10), and then transfer it to the surface of the gate dielectric layer 12 with PDMS protection.

[0086] S203: A tunneling dielectric layer 14 covering the floating gate layer 13 is formed on the surface of the floating gate layer 13 and the gate dielectric layer 12 away from the back gate 11, forming a structure as Figure 5 shown.

[0087] Among them, the tunneling dielectric layer 14 is prepared by atomic layer deposition (ALD), chemical vapor deposition (CVD) or mechanical transfer method. Using its atomically flat insulating property, a high-barrier interface is formed with the floating gate layer 13, which not only allows the quantum tunneling effect to achieve the charge injection / release of the floating gate layer 13, but also can isolate external interference to keep the charge for a long time.

[0088] S204: A channel layer 15 is formed on the surface of the tunneling dielectric layer 14 away from the substrate 10. The first orthographic projection of the channel layer 15 on the substrate 10 and the second orthographic projection of the floating gate layer 13 on the substrate 10 at least partially overlap, forming a structure as Figure 6 shown.

[0089] Among them, the channel layer 15 can be formed by mechanical exfoliation, chemical vapor deposition (CVD) method and other methods. By driving the carriers to transfer between the channel layer 15 and the floating gate layer 13, "writing" and "erasing" operations can be realized, thus endowing the finally formed floating gate transistor with good non-volatile storage ability.

[0090] S205: A source electrode 16 and a drain electrode 17 are respectively formed on the surface of the channel layer 15 away from the substrate 10, forming a structure as Figure 1 shown.

[0091] It should be noted that the preparation method of the multifunctional floating gate transistor provided in the embodiment of the present application and the multifunctional floating gate transistor provided in the embodiment of the present application are based on the same inventive concept. Therefore, the multifunctional floating gate transistor prepared in this embodiment can refer to the description of the foregoing multifunctional floating gate transistor, and the repeated parts will not be described again.

[0092] In some embodiments, in step S202, forming the floating gate layer 13 on the surface of the gate dielectric layer 12 away from the back gate 11 includes: extending a graphene material block into a graphene thin sheet by mechanical exfoliation; transferring the graphene thin sheet to the surface of the gate dielectric layer 12 away from the back gate 11 by dry transfer to form the floating gate layer 13.

[0093] Among them, single-layer or multi-layer graphene can be obtained by repeatedly peeling off from highly oriented pyrolytic graphite with tape and transferred to the surface of the gate dielectric layer 12 with the assistance of PDMS.

[0094] Exemplarily, a fixture (such as tweezers) can be used to place a small block of graphene material on the tape. The tape is repeatedly folded in half and then separated, and this is repeated multiple times (such as 5 to 8 times) until the block material expands into a large area on the tape. A small piece of PDMS is attached to the expanded material and pressed. Subsequently, the PDMS with the adhered material is picked up by the fixture, and using a two-dimensional material transfer platform, the target material on the PDMS is transferred to the substrate 10.

[0095] In some embodiments, in step S203, a tunneling dielectric layer 14 covering the floating gate layer 13 is formed on the surfaces of the floating gate layer 13 and the gate dielectric layer 12 away from the back gate 11, including: using a mechanical exfoliation method to extend a bulk hexagonal boron nitride material into a hexagonal boron nitride thin sheet; transferring the hexagonal boron nitride thin sheet to the surfaces of the floating gate layer 13 and the gate dielectric layer 12 away from the back gate 11 by dry transfer to form the tunneling dielectric layer 14 covering the floating gate layer 13.

[0096] Exemplarily, a fixture can be used to place a bulk hexagonal boron nitride material on the tape. The tape is repeatedly folded in half and then separated, and this is repeated multiple times (such as 5 to 8 times) until the bulk hexagonal boron nitride material expands into a large area on the tape. A small piece of PDMS is attached to the expanded material and pressed. Subsequently, the PDMS with the adhered material is picked up by the fixture, and using a two-dimensional material transfer platform, the target material on the PDMS is transferred to the substrate 10.

[0097] In some embodiments, in step S204, a channel layer 15 is formed on the surface of the tunneling dielectric layer 14 away from the substrate 10, including: using a mechanical exfoliation method to extend a bulk molybdenum disulfide material into a molybdenum disulfide thin sheet; transferring the molybdenum disulfide thin sheet to the surface of the tunneling dielectric layer 14 away from the substrate 10 by dry transfer to form the channel layer 15.

[0098] Exemplarily, similarly, a fixture can be used to place a bulk molybdenum disulfide material on the tape. The tape is repeatedly folded in half and then separated, and this is repeated multiple times (such as 5 to 8 times) until the bulk molybdenum disulfide material expands into a large area on the tape. A small piece of PDMS is attached to the expanded material and pressed. Subsequently, the PDMS with the adhered material is picked up by the fixture, and using a two-dimensional material transfer platform, the target material on the PDMS is transferred to the substrate 10.

[0099] Combined with the above embodiments, in one example, steps S202 to S204 can form a three-layer heterojunction on the substrate 10, successively forming a floating gate layer 13, a tunneling dielectric layer 14, and a channel layer 15. The materials used for the floating gate layer 13, the tunneling dielectric layer 14, and the channel layer 15 are multi-layer graphene, hexagonal boron nitride (h-BN), and molybdenum ditelluride (MoTe2), respectively. The thicknesses of the graphene, h-BN, and MoTe2 nanosheets can be 17.6 nm, 13.3 nm, and 8.2 nm, respectively, and the floating gate layer 13 does not contact the channel layer 15.

[0100] In one embodiment, in step S205, forming the source electrode 16 and the drain electrode 17 on the surface of the channel layer 15 away from the substrate 10 includes: performing ultraviolet mask lithography on the channel layer 15, etching out the patterns of the source electrode 16 and the drain electrode 17 on the surface of the channel layer 15 away from the substrate 10, and then depositing a chromium layer and a gold layer through thermal evaporation to form the source electrode 16 and the drain electrode 17.

[0101] Exemplarily, a 5-nm chromium layer and a 50-nm gold layer can be deposited on the surface of the channel layer 15 away from the substrate 10. After the deposition is completed, the substrate 10 with the material (i.e., the structure formed in S205) can be immersed in acetone. After the excess metal and photoresist are removed, it can be placed in deionized water for cleaning, and then dried with nitrogen to complete the preparation of the multifunctional floating gate transistor.

[0102] The present application also provides an artificial synapse. The artificial synapse uses the multifunctional floating gate transistor of any of the above solutions. The presynaptic stimulus of the artificial synapse is the back gate voltage pulse of the multifunctional floating gate transistor, and the postsynaptic current of the artificial synapse is the channel layer current of the multifunctional floating gate transistor.

[0103] In the related art, in the field of neuromorphic computing, related devices mainly only implement the function of artificial synapses, lacking the exploration of other neuromorphic functions. At the same time, in the process of implementing artificial synapses, the simulation of inhibitory synapse functions is often lacking.

[0104] However, using the floating gate transistor in the above embodiments as an artificial synapse, with the back gate voltage pulse as the presynaptic stimulus and the channel layer current as the postsynaptic current, since the positive back gate voltage pulse is the stimulus for the excitatory postsynaptic current, while the negative back gate voltage pulse is the stimulus for the inhibitory postsynaptic current. Therefore, the artificial synapse of this embodiment can realize the simulation of the inhibitory synapse function. In addition, by changing parameters such as the number and frequency of pulses, the capture and release efficiency of carriers by the floating gate layer is regulated to realize the reversible adjustment of the channel current, simulating biological synapse behaviors such as pulse number and frequency-dependent plasticity. Therefore, this floating gate transistor can simulate various synapse behaviors, providing an effective hardware platform for constructing a neuromorphic computing system.

[0105] As Figure 7a shown Figure 7a in, the postsynaptic current is under the condition of applying positive and negative gate voltage pulses with different frequencies. Under the condition that the pulse width is set to 100 ms and the number of pulses is 10, the amplitude of the excitatory postsynaptic current triggered by a 2V pulse gradually increases as the pulse frequency increases from 0.5 Hz to 5.0 Hz. Similarly, the inhibitory postsynaptic current triggered by a -2V pulse is also closely related to the frequency of the input pulse, and its amplitude gradually decreases as the pulse frequency increases from 0.5 Hz to 2.5 Hz, as Figure 7b shown. The results show that the artificial synaptic device of this embodiment exhibits obvious spike frequency-dependent plasticity.

[0106] As Figure 9 shown Figure 9 shows the power consumption of the floating-gate transistor in the embodiment of the present application. For electrical operations, the following formula is used to calculate the power consumption of the floating-gate transistor: E = V ds × I peak × t, where V ds is the source-drain voltage, I peak is the amplitude of the postsynaptic current, and t is the pulse width of the applied back-gate voltage pulse. The floating-gate transistor as an artificial synapse in this embodiment can operate at an extremely low source-drain voltage (0.0005 V), and thus can complete a single synaptic activity with an extremely low power consumption of 3.96 fJ.

[0107] As Figure 10a shown Figure 10a shows the long-term potentiation and long-term depression characteristics of the floating-gate transistor in the embodiment, which are realized by applying 200 2V pulses (pulse width: 500 ms, interval: 500 ms) and 200 -2V pulses (pulse width: 500 ms, interval: 500 ms). Parameters such as the ratio of the maximum to minimum conductance values, the number of pulses, and the non-linearity are extracted from the long-term plasticity to construct an artificial neural network for recognizing handwritten digit images. The recognition results are as Figure 10b shown. After one hundred training cycles, the recognition accuracy reaches 90.16%.

[0108] The present application also provides an artificial nociceptor. The artificial nociceptor uses the multifunctional floating-gate transistor in any of the above solutions. The external nociceptive stimulus of the artificial nociceptor is the back-gate voltage pulse of the multifunctional floating-gate transistor, and the response signal of the artificial nociceptor is the channel layer current of the multifunctional floating-gate transistor.

[0109] In an application, nociceptors, as an important part of the nervous system, are responsible for perceiving stimuli from the external environment. When the free nerve endings of nociceptors receive external stimuli, the nociceptors generate action potentials and send excitatory signals to the central nervous system. When the amplitude of the excitatory signal exceeds the threshold level, the human body will experience nociception. Nociceptors have four key characteristics: threshold, relaxation, adaptation, and sensitization. In this embodiment, the floating-gate transistor in the above embodiment is used as an artificial nociceptor. By programming the amplitude, interval, and repetition times of the input pulses, the capture, release, and enhanced sensitization process of carriers in the floating-gate layer are induced, so as to reproduce various key characteristics of human nociceptors such as threshold, relaxation, adaptation, and sensitization, providing effective hardware support for constructing the nervous system.

[0110] As Figure 11a shown, Figure 11a Figure shows the threshold characteristics of the floating-gate transistor in this application simulating human nociceptors in the implementation example. A series of pulses with different amplitudes (pulse width: 300 ms) are applied. The results show that the amplitude of the response current triggered by the pulses gradually increases with the increase of the pulse amplitude. When the amplitude increases to 2.0 V, the amplitude of the response current exceeds the threshold current (22 nA), indicating the onset of nociception.

[0111] Figure 11b Figure shows the relaxation characteristics of the floating-gate transistor in the implementation example simulating human nociceptors. First, a 3.0 V pulse (pulse width: 300 ms) is applied, and then a 1.5 V pulse (pulse width: 300 ms) is applied. By changing the interval (1.1, 2.4, 4.1, and 16.9 s) between these two pulses, the change of the response current is observed. The results show that the amplitude of the response current triggered by the 1.5 V pulse gradually decreases with the extension of the interval. It shows that the nociceptor remains active after the removal of the harmful stimulus and requires a certain time to fully relax.

[0112] As Figure 12a shown, Figure 12a Figure shows the response current triggered under the condition of continuously applying 1.5 V and 2.0 V pulses (pulse width: 300 ms, interval: 300 ms). The response current triggered by consecutive multiple pulses does not weaken due to adaptation, but gradually increases and tends to saturate. This phenomenon is similar to the adaptation characteristic.

[0113] As Figure 12b shown, Figure 12bThe simulation of the sensitization characteristics is shown. First, a series of pulses with different amplitudes (0.5, 1.0, 1.5, 2.0, 2.5, and 3.0 V, pulse width: 300 ms) were applied to simulate the response of nociceptors in the undamaged state. Subsequently, the same pulse sequence was applied again, but a 4 V or 5 V (pulse width: 300 ms) pulse was pre-applied before each pulse to simulate the response of nociceptors in the damaged state. The results show that after pre-applying a 4 V or 5 V pulse, the amplitude of the response current triggered by 0.5 V to 1.5 V pulses exceeds the threshold current, that is, a harmless stimulus also elicits nociception, showing the characteristics of allodynia. For 2 V to 3 V pulses, the response current triggered by them is significantly enhanced compared with that without pre-applying a high-amplitude pulse, indicating that the nociception caused by a harmful stimulus is more significant, presenting the characteristics of hyperalgesia.

[0114] Those skilled in the art can understand that the features recited in the various embodiments and / or claims of the present application can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly recited in the present application. In particular, without departing from the spirit and teachings of the present application, the features recited in the various embodiments and / or claims of the present application can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present application. Therefore, the scope of the present application should not be limited to the above embodiments, but should be determined not only by the appended claims but also by the equivalents of the appended claims. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A multifunctional floating-gate transistor based on a two-dimensional material heterojunction, characterized in that, Comprising: A substrate including a back gate and a gate dielectric layer stacked from bottom to top; A floating gate layer located on the surface of the gate dielectric layer away from the back gate; A tunneling dielectric layer respectively located on the surfaces of the floating gate layer and the gate dielectric layer away from the back gate, the tunneling dielectric layer covering the floating gate layer; A channel layer located on the surface of the tunneling dielectric layer away from the substrate, and a first orthographic projection of the channel layer on the substrate at least partially overlaps with a second orthographic projection of the floating gate layer on the substrate; A source electrode and a drain electrode are further provided on the channel layer, and a channel region is formed between the source electrode and the drain electrode; Wherein, when a voltage pulse is applied to the back gate, under the drive of the internal electric field of the multifunctional floating gate transistor, carriers in the channel layer are transferred between the channel layer and the floating gate layer; After removing the voltage pulse, the wide bandgap effect of the tunneling dielectric layer prevents the carriers from back tunneling, so that the remaining carriers in the floating gate layer are retained for a long time.

2. The multifunctional floating-gate transistor based on a two-dimensional material heterojunction according to claim 1, wherein The material of the back gate is silicon, the material of the gate dielectric layer is silicon dioxide, and the thickness of the silicon dioxide is 250 - 350 nm.

3. The multifunctional floating gate transistor based on a two-dimensional material heterojunction according to claim 1, wherein The material of the floating gate layer is graphene, and the thickness of the floating gate layer is 15 - 25 nm; The material of the tunneling dielectric layer is hexagonal boron nitride, and the thickness of the tunneling dielectric layer is 10 - 20 nm; The material of the channel layer is molybdenum disulfide, and the thickness of the channel layer is 5 - 10 nm.

4. The multifunctional floating-gate transistor based on a two-dimensional material heterojunction according to claim 1, wherein The source electrode and the drain electrode include a chromium layer and a gold layer stacked from bottom to top, the thickness of the chromium layer is 4 - 6 nm, and the thickness of the gold layer is 45 - 55 nm.

5. A preparation method of a multifunctional floating-gate transistor based on a two-dimensional material heterojunction, characterized in that, The preparation method includes: Providing a substrate, the substrate including a back gate and a gate dielectric layer stacked from bottom to top; Forming a floating gate layer on the surface of the gate dielectric layer away from the back gate; Forming a tunneling dielectric layer covering the floating gate layer on the surfaces of the floating gate layer and the gate dielectric layer away from the back gate; Forming a channel layer on the surface of the tunneling dielectric layer away from the substrate, and a first orthographic projection of the channel layer on the substrate at least partially overlaps with a second orthographic projection of the floating gate layer on the substrate; Forming a source electrode and a drain electrode on the surface of the channel layer away from the substrate respectively.

6. The preparation method according to claim 5, characterized in that, The forming a floating gate layer on the surface of the gate dielectric layer away from the back gate includes: Using a mechanical exfoliation method to extend a graphene material block into a graphene thin sheet; Transferring the graphene thin sheet to the surface of the gate dielectric layer away from the back gate by dry transfer to form the floating gate layer.

7. The preparation method according to claim 5, characterized in that The forming a tunneling dielectric layer covering the floating gate layer on the surfaces of the floating gate layer and the gate dielectric layer away from the back gate includes: Using a mechanical exfoliation method to extend a hexagonal boron nitride material block into a hexagonal boron nitride thin sheet; Transferring the hexagonal boron nitride thin sheet to the surfaces of the floating gate layer and the gate dielectric layer away from the back gate by dry transfer to form the tunneling dielectric layer covering the floating gate layer.

8. The preparation method according to claim 5, characterized in that, The forming a channel layer on the surface of the tunneling dielectric layer away from the substrate includes: Using a mechanical exfoliation method to extend a molybdenum disulfide material block into a molybdenum disulfide thin sheet; Transfer the molybdenum disulfide flakes to the surface of the tunneling dielectric layer away from the substrate by dry transfer to form the channel layer.

9. An artificial synapse, characterized in that, The artificial synapse uses the multifunctional floating-gate transistor according to any one of claims 1 to 4. The presynaptic stimulus of the artificial synapse is the back-gate voltage pulse of the multifunctional floating-gate transistor, and the postsynaptic current of the artificial synapse is the channel layer current of the multifunctional floating-gate transistor.

10. An artificial nociceptor, characterized in that, The artificial nociceptor uses the multifunctional floating-gate transistor according to any one of claims 1 to 4. The external nociceptive stimulus of the artificial nociceptor is the back-gate voltage pulse of the multifunctional floating-gate transistor, and the response signal of the artificial nociceptor is the channel layer current of the multifunctional floating-gate transistor.

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