Method for manufacturing semiconductor device structure and semiconductor device structure

Abstract

The present invention relates to a method for manufacturing a semiconductor device structure and a semiconductor device structure, belonging to the field of semiconductor manufacturing technology. The method comprises: providing a semiconductor substrate, sequentially depositing a gate oxide layer and a high-k dielectric material layer on the substrate; generating a PMOS work function layer on the high-k dielectric material layer, the work function layer comprising a capping layer implanted with gallium ions and a gallium oxide film of a preset thickness; preparing a dummy gate structure, sequentially depositing a contact etch stop layer and a zeroth interlayer dielectric layer and planarizing them, the dielectric layer comprising two layers of boron phosphosilicate glass films with different boron contents; sequentially performing dummy gate removal, metal filling, and planarization processes to form a semiconductor device structure with an integrated metal gate and source-drain contacts. The present invention effectively improves the performance and stability of semiconductor devices by introducing gallium ions and a gallium oxide film in the PMOS region and using a double layer of boron phosphosilicate glass with different boron contents as the zeroth interlayer dielectric layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device structure and a semiconductor device structure. Background Art

[0002] In semiconductor manufacturing, as device feature sizes continue to shrink, traditional silicon dioxide / polysilicon gate structures are no longer able to meet the demands of advanced processes. This has led to the emergence of high-k metal gate (HKMG) technology, with the replacement metal gate (RMG) process becoming the mainstream implementation. This process requires precise deposition of metal gate material in the trench after the dummy gate has been removed, placing extremely high demands on the step coverage of the thin-film deposition process.

[0003] Currently, the industry primarily uses atomic layer deposition (ALD) to deposit metal gate materials. However, in actual production, ALD is prone to metal gate loss at locations with smaller critical dimensions in polysilicon, resulting in a decrease in chip yield.

[0004] At the same time, the silicon nitride sidewalls exert tensile stress on the silicon substrate. Due to the lattice constant mismatch between the silicon sidewalls and pseudo-polysilicon, dislocation defects are easily formed at the interface. These dislocation defects can cause slight deformation of the metal gate sidewalls, reducing the width of the gate in the middle. This deformation makes trench filling difficult during the subsequent deposition of multiple layers of metals such as tantalum nitride, titanium-aluminum alloy, titanium nitride, and aluminum, exacerbating metal gate loss.

[0005] This series of process defects seriously restricts the yield and reliability of HKMG devices under advanced processes. Summary of the Invention

[0006] In order to solve the problem of metal gate loss caused by multiple factors such as insufficient step coverage of the atomic layer deposition process and stress mismatch between the silicon nitride sidewall and the pseudo polysilicon at locations with smaller gate critical dimensions in semiconductor manufacturing processes, especially in the RMG process of HKMG technology, the present invention provides a manufacturing method and a semiconductor device structure.

[0007] To this end, the present invention provides the following technical solutions:

[0008] In one aspect, the present invention provides a method for manufacturing a semiconductor device structure, comprising:

[0009] S1: Providing a semiconductor substrate, wherein at least one NMOS region, at least one PMOS region, and an isolation structure between the regions are formed on the surface of the semiconductor substrate; depositing a gate oxide layer and a high-k dielectric layer in sequence on the semiconductor substrate;

[0010] S2. Generating a PMOS work function layer on the high-k dielectric layer, wherein the PMOS work function layer includes a capping layer implanted with gallium ions and a gallium oxide film of a preset thickness;

[0011] S3, forming a dummy gate on the basis of the PMOS work function layer, and forming sidewalls and corresponding source and drain regions on both sides of the dummy gate;

[0012] S4. Depositing a contact etch stop layer and a zeroth interlayer dielectric layer in sequence on the exposed surface of the dummy gate, and performing a planarization operation on the zeroth interlayer dielectric layer; the zeroth interlayer dielectric layer comprises: a first borophosphosilicate glass film and a second borophosphosilicate glass film, wherein the boron content of the first borophosphosilicate glass film is lower than that of the second borophosphosilicate glass film;

[0013] S5. Performing dummy gate removal, metal filling and planarization processing on the planarized zeroth interlayer dielectric layer in sequence.

[0014] Furthermore, forming a PMOS work function layer on the high-k dielectric layer comprises:

[0015] depositing a capping layer on the high-k dielectric layer;

[0016] providing a mask on the cover layer;

[0017] Disposing a photoresist at a position corresponding to the NMOS region on the mask to cover the NMOS region and expose the PMOS region; performing gallium ion implantation on the exposed PMOS region;

[0018] depositing a gallium oxide thin film of a preset thickness on the mask and the photoresist;

[0019] The photoresist and the gallium oxide film covering the photoresist are removed, and high dielectric constant material annealing is performed.

[0020] Furthermore, the high dielectric constant material is annealed at a temperature of 800° C. to 1000° C. in an oxygen atmosphere.

[0021] Furthermore, the thickness of the gallium oxide film is preset according to the height of the PMOS gate.

[0022] Furthermore, the implantation energy and implantation dose of the gallium ions are set according to the target effective work function of the PMOS.

[0023] Furthermore, the boron content in the first borophosphosilicate glass film is 4%, and the boron content in the second borophosphosilicate glass film is 10%.

[0024] Furthermore, after depositing the zeroth interlayer dielectric layer and before performing a planarization operation on the zeroth interlayer dielectric layer, it also includes: reflowing the borophosphosilicate glass and performing acid tank cleaning after reflow to remove boron ions and phosphorus ions precipitated during the reflow process of the borophosphosilicate glass.

[0025] Furthermore, on the planarized zero-th interlayer dielectric layer, dummy gate removal, metal filling and planarization are sequentially performed, including:

[0026] On the planarized zeroth interlayer dielectric layer, removing the exposed dummy gate by dry etching and wet etching to form a gate opening;

[0027] Tantalum nitride and titanium aluminum alloy are filled in the gate opening in sequence, and then metal filling is achieved by aluminum deposition, and finally a metal gate planarization operation is performed.

[0028] Furthermore, the contact etching stop layer is made of silicon nitride material.

[0029] In another aspect, the present invention further provides a semiconductor device structure formed by using the above-mentioned method for manufacturing a semiconductor device structure, comprising:

[0030] A metal gate stack structure and a zeroth interlayer dielectric layer covering the metal gate stack structure;

[0031] The metal gate stack structure includes: a semiconductor substrate; the semiconductor substrate includes at least one NMOS region, at least one PMOS region and an isolation structure between the regions;

[0032] The NMOS region includes, from bottom to top, a gate oxide layer, a high-k dielectric layer, a capping layer, a tantalum nitride, an NMOS work function layer, a barrier layer, and an aluminum-copper alloy;

[0033] The PMOS region includes, from bottom to top, a gate oxide layer, a high-k dielectric layer, a PMOS work function layer, a tantalum nitride layer, an NMOS work function layer, a barrier layer, and an aluminum-copper alloy; the PMOS work function layer includes a capping layer implanted with gallium ions and a gallium oxide film of a preset thickness; the NMOS work function layer includes a titanium-aluminum alloy;

[0034] The zeroth interlayer dielectric layer includes: a first borophosphosilicate glass film and a second borophosphosilicate glass film, wherein the boron content in the first borophosphosilicate glass film is lower than that in the second borophosphosilicate glass film.

[0035] Advantages and positive effects of the present invention:

[0036] In the present invention, gallium ion implantation and gallium oxide film growth are added to the process flow after the deposition of the cap layer to adjust the effective work function of the PMOS, instead of subsequently filling the gate opening with PMOS work function metal and removing the PMOS work function metal in the NMOS area. This can avoid the metal gate defect phenomenon caused by atomic layer deposition at the position where the critical dimension of the polysilicon gate is small, thereby improving the wafer test yield.

[0037] At the same time, the zeroth interlayer dielectric layer of the present invention uses borophosphosilicate glass. The compressive stress of the borophosphosilicate glass film is greater than that of the silicon dioxide film, which can effectively offset the stress of the side wall on the pseudo-gate polysilicon, thereby avoiding the problem of metal gate sidewall deformation and effectively solving the metal gate loss problem.

[0038] The present invention has the following unexpected technical effects: On the one hand, by adjusting the thickness of the gallium oxide film, it can compensate for the loss of PMOS gate height caused by Sigma trench etching, thus resolving the threshold voltage drift, drive current drop, and device mismatch problems caused by height deviation. On the other hand, by placing a first boron-phosphosilicate glass film with a lower boron content in the lower layer, boron diffusion into the substrate is reduced. Placing a second boron-phosphosilicate glass film with a higher boron content in the upper layer of the first boron-phosphosilicate glass film can reduce the reflow temperature and improve fluidity, thereby achieving the goal of both suppressing boron diffusion and improving reflow planarization. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0040] Figure 1 is a process flow chart of a method for manufacturing a semiconductor device structure according to an embodiment of the present invention;

[0041] Figures 2A to 2M is a cross-sectional view of a semiconductor device structure formed by relevant steps of a method for manufacturing a semiconductor device structure according to an embodiment of the present invention;

[0042] Figure 3 A schematic diagram of ion reaction during annealing of a high dielectric constant material according to an embodiment of the present invention;

[0043] Figure 4 is a schematic diagram of a metal gate stack structure according to an embodiment of the present invention;

[0044] In the figure, 1. semiconductor substrate; 2. high-k dielectric layer; 3. capping layer; 4. photoresist; 5. gallium oxide film; 6. amorphous silicon; 7. silicon nitride hard mask; 8. oxide hard mask; 9. organic carbon layer; 10. glass layer; 11. contact etch stop layer; 12. first borophosphosilicate glass film; 13. second borophosphosilicate glass film; 14. zeroth interlayer dielectric layer; 15. tantalum nitride; 16. titanium aluminum alloy; 17. aluminum. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0047] The advanced manufacturing process is divided into the following stages: front-end-of-line (FOL), used to fabricate transistors (such as gate stacks and ion implantation); mid-stage (MOL), used to complete local interconnects (contact holes and vias); and back-end-of-line (BOL), used to construct multi-layer metal wiring (copper interconnects and dielectric layers), ultimately resulting in highly integrated chips. Each stage relies on precision lithography, etching, and deposition techniques to ensure nanoscale structural accuracy.

[0048] Replacement Metal Gate (RMG) is a key process in the front-end (FOL) of the manufacturing process, primarily used in the fabrication of novel transistor structures such as Fin Field-Effect Transistors (FinFETs) and Gate-All-Around (GAA) transistors. The core of this process lies in forming a dummy gate structure through a gate-last process. After processing the source and drain regions, the dummy gate is removed and a high-k dielectric layer and metal gate material are deposited. This process, combining a high-k dielectric with a metal gate, effectively reduces gate leakage current and improves device performance, making it an indispensable key technology in modern advanced manufacturing processes. Furthermore, the RMG process enables precise control of transistor electrical characteristics. In particular, by selecting metal materials with different work functions, the threshold voltage of both NMOS and PMOS can be optimized. In a specific implementation, PMOS usually uses a metal material with a higher work function, while NMOS uses a material with a lower work function.

[0049] The present invention optimizes the performance of semiconductor device structure by improving the replacement metal gate process in the front-end process. Figure 1 As shown, a method for manufacturing a semiconductor device structure includes the following steps:

[0050] S1: Providing a semiconductor substrate 1, wherein at least one NMOS region, at least one PMOS region, and an isolation structure between the regions are formed on the surface of the semiconductor substrate 1; depositing a gate oxide layer and a high-k dielectric layer 2 in sequence on the semiconductor substrate 1;

[0051] Specifically, semiconductor substrate 1 can be made of common semiconductor materials such as a silicon substrate, a germanium substrate, or a silicon-germanium substrate. In this embodiment, a silicon substrate is used as semiconductor substrate 1. An NMOS region and a PMOS region are formed on semiconductor substrate 1 through processes such as photolithography and ion implantation, and an isolation structure is formed between the NMOS region and the PMOS region. The isolation structure can be a shallow trench isolation (STI) structure or a local oxide of silicon isolation (LOCOS) structure. In this embodiment, a shallow trench isolation structure is used as the isolation structure.

[0052] like Figure 2A As shown, after forming the NMOS region, the PMOS region and the isolation structure, a gate oxide layer ( Figure 2AThe gate oxide layer (GOX) is formed on the surface of the semiconductor substrate 1 using a thermal oxidation process (not shown). The high-k dielectric layer 2 is formed on the surface of the semiconductor substrate 1 using a gate oxide layer (not shown). The gate oxide layer (GOX) can be made of silicon dioxide (SiO2) and grown on the surface of the semiconductor substrate 1 using a thermal oxidation process. The high-k dielectric layer 2 can be made of materials such as hafnium oxide (HfO2), zirconium oxide (ZrO2), or aluminum oxide (Al2O3) and deposited on the gate oxide layer using an atomic layer deposition (ALD) process. In this embodiment, the gate oxide layer is made of SiO2, and the high-k dielectric layer 2 is made of HfO2.

[0053] S2: Generating a PMOS work function layer on the high-k dielectric layer 2, the PMOS work function layer comprising a capping layer 3 implanted with gallium ions and a gallium oxide film 5 of a preset thickness;

[0054] The specific steps of forming a PMOS work function layer on the high-k dielectric layer 2 include:

[0055] S21, depositing a capping layer 3 on the high-k dielectric layer 2; Figure 2A As shown;

[0056] The cover layer 3 can be made of materials such as titanium nitride (TiN), tantalum nitride (TaN) or tungsten nitride (WN), and is deposited on the high-k dielectric layer 2 by physical vapor deposition (PVD) or chemical vapor deposition (CVD) processes. In this embodiment, the cover layer 3 is made of TiN material.

[0057] S22, setting a mask on the cover layer 3;

[0058] S23, disposing a photoresist 4 at a position corresponding to the NMOS region on the mask to cover the NMOS region and expose the PMOS region; performing gallium ion implantation on the exposed PMOS region;

[0059] S24, depositing a gallium oxide film 5 of a preset thickness on the mask and the photoresist 4;

[0060] S25 , removing the photoresist 4 and the gallium oxide film 5 covering the photoresist 4 , and performing high dielectric constant material annealing.

[0061] Specifically, if Figure 2BAs shown, a mask is first set on the cover layer 3. Then, a photoresist is coated on the mask at the corresponding position of the NMOS area, and after exposure and development, a photoresist 4 is formed, which covers the NMOS area and exposes the PMOS area. Next, gallium ion implantation is performed on the exposed PMOS area. The implantation energy and implantation dose can be set according to the target effective work function of the PMOS. The effective work function of the PMOS is adjusted by implanting gallium ions. In a specific implementation, the mask can directly call the four-layer global interconnect dual metal gate mask (MEOL 4G Dual Metal Gate Mask) in the middle process. The gallium ion implantation step is a new step in the front-end process after the present invention improves the process flow. The mask in the middle process is used in advance and does not need to be used in the middle process later, and no additional cost is added due to the new step.

[0062] like Figure 2C As shown, after the gallium ion implantation is completed, a gallium oxide film 5 of a preset thickness is deposited on the mask and photoresist 4. The gallium oxide film 5 can be deposited using processes such as ALD or PVD. The thickness of the gallium oxide film 5 is preset based on the PMOS gate height. The effective work function of the gallium oxide film 5 can reach approximately 5.0 eV, which can increase the effective work function of the PMOS and achieve the technical effect of regulating the PMOS effective work function. Furthermore, the thickness of the gallium oxide film 5 can compensate for the low PMOS gate height caused by trench etching, achieving unexpected technical benefits.

[0063] like Figure 2D As shown, after the gallium oxide film 5 is deposited, the photoresist 4 and the gallium oxide film 5 covering the photoresist 4 are removed, and the photoresist 4 and the gallium oxide film 5 on the photoresist 4 can be removed by a lift-off process (Lift Off). Then, the high dielectric constant material is annealed in an oxygen atmosphere at a temperature of 800°C to 1000°C, and the annealing time can be 30-120 seconds. In this embodiment, the annealing temperature is controlled at about 800°C. During the annealing of the high dielectric constant material, the gallium ions doped into the covering layer 3 are activated and diffused in a high temperature environment, and a gallium-oxygen dipole layer is formed in the gate oxide layer and the high dielectric constant dielectric layer 2 through an interface reaction, pointing from the high dielectric constant dielectric layer 2 to the interface layer, so that the effective work function of the PMOS moves from the silicon valence band direction, thereby achieving the technical effect of improving the effective work function of the PMOS. In more detail, as Figure 3 As shown, the high temperature process of annealing the high dielectric constant material can activate the gallium ions doped into the cover layer 3 (TiN metal), diffuse and gather in the Figure 3At positions A and C shown in the figure, gallium ions doped into position A can change the material properties of TiN, thereby causing the effective work function of PMOS to change; and at the interface between HfO2 and SiO2, gallium ions accumulated at position C will form a gallium-oxygen dipole through interfacial reaction at high temperature, and the direction of the dipole moment will point from HfO2 to SiO2, thereby changing the effective work function of PMOS to the top of the valence band close to the substrate energy band.

[0064] S3: manufacturing a dummy gate on the basis of the PMOS work function layer, and forming sidewalls and corresponding source and drain regions on both sides of the dummy gate;

[0065] Specifically, when preparing a dummy gate structure on an existing structure, as Figure 2E and Figure 2F As shown, a dummy gate material, such as amorphous silicon 6, is first deposited. This is then etched to form the gate structure, which is then removed during the gate replacement process. A silicon nitride hard mask 7 is then deposited on the amorphous silicon 6 layer to improve etch selectivity, protect the amorphous silicon 6 layer, and ensure the accuracy of subsequent pattern transfer. An oxide hard mask 8, such as SiO2, is then deposited on the silicon nitride hard mask 7 as a second hard mask layer to enhance etch protection and optimize the accuracy of photolithographic pattern transfer. An organic carbon layer 9 and a spin-on glass layer 10 are then spin-coated. The organic carbon layer is applied to planarize the surface and improve the uniformity of the photoresist. A glass-like material, such as a silicon-containing polymer, is then applied as an antireflective layer to enhance photolithographic exposure accuracy. The organic carbon layer 9 and glass layer 10 are thermally cured to improve film stability and prevent deformation or peeling during subsequent processes. After photolithographic exposure, a bake is performed to stabilize the photoresist pattern for subsequent etching or stripping. Finally, a portion of the hard mask and the amorphous silicon 6 is removed by dry etching (such as reactive ion etching (RIE)) to form a dummy gate structure.

[0066] like Figure 2G As shown, spacers are formed on the sidewalls of the dummy gate structure. The spacers can be made of silicon nitride or silicon oxide. Next, based on the dummy gate structure and the spacers, source and drain regions are formed by ion implantation.

[0067] S4: depositing a contact etching stop layer 11 and a zeroth interlayer dielectric layer 14 in sequence on the exposed surface of the dummy gate, and performing a planarization operation on the zeroth interlayer dielectric layer 14;

[0068] The zeroth interlayer dielectric layer 14 includes: a first borophosphosilicate glass film 12 and a second borophosphosilicate glass film 13, wherein the boron content in the first borophosphosilicate glass film 12 is lower than that in the second borophosphosilicate glass film 13;

[0069] Specifically, a contact etch stop layer 11 is grown on the exposed surface of the dummy gate. The contact etch stop layer 11 is a key thin film mainly used to control etching selectivity and adjust device stress. In this embodiment, the contact etch stop layer 11 is made of silicon nitride.

[0070] A zero-level inter-layer dielectric (ILD0) layer 14 is deposited on the contact etch stop layer 11. ILD0 is a critical insulating layer in semiconductor manufacturing, located between the transistor active area (gate, source / drain) and the first metal interconnect (Metal 1). Its core functions are electrical isolation (preventing short circuits between the active area and the metal layer), planarization (providing a uniform surface for subsequent metal layers), and mechanical support (protecting front-end device structures). It serves as a crucial transition layer between the front-end and back-end processes. In semiconductor manufacturing, ILD0 is typically composed of plasma-enhanced tetraethyl orthosilicate (PETEOS) film. However, PETEOS film lacks high-temperature reflow capability, resulting in poor fill and planarization performance for high-aspect-ratio structures. It also has limited stress regulation flexibility. Furthermore, PETEOS requires high-temperature annealing for densification, requiring higher thermal stability. Furthermore, pure SiO2 structures are more susceptible to moisture absorption, potentially impacting device reliability. To this end, the PETEOS film can be replaced by high-boron-doped borophosphosilicate glass (BPSG, which refers to silicon dioxide glass doped with boron and phosphorus) or low-phosphorus-doped BPSG. Boron can significantly reduce the glass transition temperature of SiO2 and the temperature required for reflow, thereby reducing thermal damage to underlying devices (such as shallow junctions and metal silicides); at the same time, high boron content can improve the fluidity of the glass during reflow, improve trench filling ability, reduce voids, and improve the density of the dielectric layer. However, when ILD0 uses BPSG with a high boron content, boron easily diffuses into the substrate, pseudo-gate structure or shallow trench isolation, which may cause device performance degradation (such as threshold voltage drift, work function change, drive current drop, isolation area leakage, crosstalk between devices, etc.). In order to solve this problem, in this embodiment, if Figure 2HAs shown, ILD0 utilizes multiple BPSG films with varying boron contents, including a first borophosphosilicate glass (BPSG) film 12 and a second borophosphosilicate glass (BPSG) film 13. The first borophosphosilicate glass (BPSG) film 12 has a lower boron content than the second borophosphosilicate glass (BPSG) film 13. The first and second BPG films 12, 13 can be deposited via a chemical vapor deposition (CVD) process. In this embodiment, the boron content of the first BPG film 12 is 4%, while the boron content of the second BPG film 13 is 10%. The first BPG film 12, located as the lower layer, has a lower boron content, which reduces boron diffusion into the semiconductor substrate 1. The second BPG film 13, located above the first BPG film 12, has a higher boron content, which reduces the reflow temperature and improves fluidity. This achieves both boron diffusion suppression and improved reflow planarization, resolving existing process challenges and achieving unexpected technical benefits.

[0071] like Figure 2I As shown, after ILD0 deposition, BPSG reflow is performed. In this embodiment, the reflow temperature is controlled at approximately 400°C to reduce the thermal budget and facilitate the formation of ultra-shallow junctions. BPSG flows at high temperatures, achieving local planarization and reducing voids. After reflow, an acid bath clean is performed to remove boron and phosphorus ions precipitated during the borophosphosilicate glass reflow process. A dilute hydrofluoric acid solution with a concentration of 1-5% can be used for the acid bath clean, and the cleaning time can be 1-5 minutes.

[0072] like Figure 2J As shown, after cleaning, ILD0 is planarized, and a chemical mechanical polishing (CMP) process may be used for planarization.

[0073] S5: on the planarized ILD0, performing dummy gate removal, metal filling and planarization processing in sequence.

[0074] Specifically, if Figure 2K As shown, the exposed dummy gate is removed on the planarized ILD0 by dry etching and wet etching to form a gate opening; the gate opening refers to a trench formed after removing the dummy gate, which is used to fill the metal gate.

[0075] like Figure 2L As shown, after removing the dummy gate, the gate opening is filled with tantalum nitride 15 (TaN) and titanium aluminum alloy 16 (TiAL). TaN can be deposited via physical vapor deposition (PVD) or chemical vapor deposition (CVD). TiAL can be deposited via physical vapor deposition. TaN acts as a barrier layer to prevent penetration of the overlying aluminum metal layer. TiAL, as the NMOS work function metal layer, provides a low work function to reduce the threshold voltage, ensuring high on-current and low power consumption for the NMOS.

[0076] In the existing process, after filling TaN, it is necessary to first deposit a PMOS work function metal layer film, usually titanium nitride (TiN), which is deposited at the gate opening through an atomic layer deposition process. The PMOS work function metal layer film in the NMOS region is then removed. At locations where the critical dimension (Poly CD) of the polysilicon gate is small, the width of the gate opening is also correspondingly reduced. Performing atomic layer deposition and film removal at small gate openings is a very difficult process. In the present invention, PMOS work function regulation is achieved through S2, eliminating the need for atomic layer deposition and film removal at small gate openings, reducing process difficulty, avoiding metal gate defects caused by atomic layer deposition at locations with small Poly CD, and improving wafer test yield.

[0077] like Figure 2M As shown, after filling with tantalum nitride 15 and titanium aluminum alloy 16, metal filling is achieved by depositing aluminum 17, which can be deposited by physical vapor deposition. Finally, a metal gate planarization operation is performed, which can be performed using a CMP process. After that, subsequent middle and back-end processes can be completed according to existing processes to manufacture the final semiconductor device.

[0078] Through the above manufacturing method, a semiconductor device structure is formed, including:

[0079] A metal gate stack structure and an ILD0 covering the metal gate stack structure;

[0080] The metal gate stack structure includes: a semiconductor substrate 1; the semiconductor substrate 1 includes at least one NMOS region, at least one PMOS region, and isolation structures between the regions;

[0081] The NMOS region includes, from bottom to top, a gate oxide layer, a high-k dielectric layer 2, a cap layer 3, a tantalum nitride 15, a titanium-aluminum alloy 16 (NMOS work function layer), a barrier layer, and an aluminum-copper alloy.

[0082] The PMOS region includes, from bottom to top, a gate oxide layer, a high-k dielectric layer 2, a PMOS work function layer, a tantalum nitride 15, a titanium-aluminum alloy 16 (NMOS work function layer), a barrier layer, and an aluminum-copper alloy. The PMOS work function layer includes a capping layer 3 implanted with gallium ions and a gallium oxide film 5 of a predetermined thickness.

[0083] ILD0 includes: a first borophosphosilicate glass film 12 and a second borophosphosilicate glass film 13 . The boron content in the first borophosphosilicate glass film 12 is lower than that in the second borophosphosilicate glass film 13 .

[0084] like Figure 4 As shown, Figure 4The figure shows a metal gate stack structure obtained according to the manufacturing method of the present invention. Atop the high-k dielectric layer (HfO2) are, in this order, a capping layer (Cap TiN) implanted with gallium ions, GaO, TaN, and TiAl (the NMOS work function metal layer). In this invention, the process flow of adding gallium ion implantation and GaO film growth after the deposition of the capping layer 3 is used to adjust the effective work function of the PMOS. This replaces the subsequent filling of the PMOS work function metal TiN in the gate opening and the removal of TiN from the NMOS region. This avoids metal gate defects that can occur when using atomic layer deposition in locations with low Poly CD, thereby improving wafer testing yield.

[0085] At the same time, the ILD0 of the present invention adopts BPSG film, which has greater compressive stress than SiO2 film (which can be achieved by adjusting the growth process parameters), and can effectively offset the stress of the side wall on the pseudo-gate polysilicon, thereby avoiding the problem of metal gate sidewall deformation and effectively solving the problem of metal gate loss.

[0086] The present invention has the following unexpected technical effects: On the one hand, by adjusting the thickness of the GaO film, the loss of PMOS gate height caused by Sigma trench etching can be compensated, thus solving the threshold voltage drift, drive current drop, and device mismatch problems caused by height deviation. On the other hand, by placing a first boron-phosphosilicate glass film with a lower boron content in the lower layer, boron diffusion into the substrate is reduced. Placing a second boron-phosphosilicate glass film with a higher boron content on top of the first boron-phosphosilicate glass film reduces the reflow temperature and improves fluidity, thereby achieving the goal of both suppressing boron diffusion and improving reflow planarization.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a semiconductor device structure, characterized in that: include: S1: providing a semiconductor substrate, wherein at least one NMOS region, at least one PMOS region, and isolation structures between the regions are formed on a surface of the semiconductor substrate; Depositing a gate oxide layer and a high-k dielectric layer in sequence on the semiconductor substrate; S2. Generating a PMOS work function layer on the high-k dielectric layer, the PMOS work function layer comprising a capping layer implanted with gallium ions and a gallium oxide film of a preset thickness; wherein the step of generating the PMOS work function layer on the high-k dielectric layer comprises: depositing a capping layer on the high-k dielectric layer; providing a mask on the capping layer; providing a photoresist at a position corresponding to an NMOS region on the mask to cover the NMOS region and expose the PMOS region; performing gallium ion implantation on the exposed PMOS region; depositing a gallium oxide film of a preset thickness on the mask and the photoresist; removing the photoresist and the gallium oxide film covering the photoresist, and performing annealing on the high-k dielectric material; S3, manufacturing a dummy gate on the basis of the PMOS work function layer, and forming sidewalls and corresponding source and drain regions on both sides of the dummy gate; S4. Depositing a contact etch stop layer and a zeroth interlayer dielectric layer in sequence on the exposed surface of the dummy gate, and performing a planarization operation on the zeroth interlayer dielectric layer; the zeroth interlayer dielectric layer comprises: a first borophosphosilicate glass film and a second borophosphosilicate glass film, wherein the boron content of the first borophosphosilicate glass film is lower than that of the second borophosphosilicate glass film; S5. Performing dummy gate removal, metal filling and planarization processing on the planarized zeroth interlayer dielectric layer in sequence.

2. The method for manufacturing a semiconductor device structure according to claim 1, wherein: Annealing of high-k dielectric materials is performed at a temperature of 800°C to 1000°C in an oxygen atmosphere.

3. The method for manufacturing a semiconductor device structure according to claim 1, wherein: The thickness of the gallium oxide film is preset according to the height of the PMOS gate.

4. The method for manufacturing a semiconductor device structure according to claim 1, wherein: The implantation energy and implantation dose of gallium ions are set according to the target effective work function of the PMOS.

5. The method for manufacturing a semiconductor device structure according to claim 1, wherein: The boron content in the first borophosphosilicate glass film is 4%, and the boron content in the second borophosphosilicate glass film is 10%.

6. The method for manufacturing a semiconductor device structure according to claim 1, wherein: After depositing the zeroth interlayer dielectric layer and before performing a planarization operation on the zeroth interlayer dielectric layer, the method further includes: reflowing the borophosphosilicate glass and performing acid bath cleaning after reflow to remove boron ions and phosphorus ions precipitated during the reflow process of the borophosphosilicate glass.

7. The method for manufacturing a semiconductor device structure according to claim 1, wherein: On the planarized zero-th interlayer dielectric layer, dummy gate removal, metal filling and planarization are sequentially performed, including: On the planarized zeroth interlayer dielectric layer, removing the exposed dummy gate by dry etching and wet etching to form a gate opening; Tantalum nitride and titanium aluminum alloy are filled in the gate opening in sequence, and then metal filling is achieved by aluminum deposition, and finally a metal gate planarization operation is performed.

8. The method for manufacturing a semiconductor device structure according to claim 1, wherein: The contact etching stop layer is made of silicon nitride material.

9. A semiconductor device structure, characterized in that: The semiconductor device structure is formed by the method for manufacturing the semiconductor device structure according to any one of claims 1 to 8, wherein the semiconductor device structure comprises: A metal gate stack structure and a zeroth interlayer dielectric layer covering the metal gate stack structure; The metal gate stack structure includes: a semiconductor substrate; the semiconductor substrate includes at least one NMOS region, at least one PMOS region and an isolation structure between the regions; The NMOS region includes, from bottom to top, a gate oxide layer, a high-k dielectric layer, a capping layer, a tantalum nitride, an NMOS work function layer, a barrier layer, and an aluminum-copper alloy; The PMOS region includes, from bottom to top, a gate oxide layer, a high-k dielectric layer, a PMOS work function layer, a tantalum nitride layer, an NMOS work function layer, a barrier layer, and an aluminum-copper alloy; the PMOS work function layer includes a capping layer implanted with gallium ions and a gallium oxide film of a preset thickness; the NMOS work function layer includes a titanium-aluminum alloy; The zeroth interlayer dielectric layer includes: a first borophosphosilicate glass film and a second borophosphosilicate glass film, wherein the boron content in the first borophosphosilicate glass film is lower than that in the second borophosphosilicate glass film.

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