Super-dimensional vector similarity query-oriented high-energy-efficiency coarse-grained in-memory query method and circuit

Abstract

The invention discloses a super-dimensional vector similarity query-oriented high-energy-efficiency coarse-grained in-memory query method, which comprises the following steps of: segmenting a super-dimensional vector, performing query operation on each segment of input super-dimensional vector, and calculating a Hamming distance between the input super-dimensional vector and the corresponding segment of stored super-dimensional vector; comparing each section of input super-dimensional vector with a storage section step by step, and compressing the Hamming distance between each section of super-dimensional vector into a binary code with a fixed length; and summarizing the compressed codes of the Hamming distance of each segment, and calculating the matching degree between the super-long-dimension input feature vector data and the storage category data by fusing the compressed Hamming distance information of the input super-dimension vector of each segment and the stored super-dimension vector of the corresponding segment. According to the method, the matching degree between the super-long-dimension input feature vector data and the storage category data can be efficiently calculated, so that low-complexity coarse-grained super-dimension vector similarity query is realized.

Description

Technical Field

[0001] The present invention relates to the field of digital integrated circuit design, and specifically designs a high-energy-efficiency coarse-grained in-memory query method and circuit for hyperdimensional vector similarity query. Background Art

[0002] The rapid development of big data-driven applications and the exponential growth of unstructured data are placing higher demands on the data processing and computing performance of edge devices. Existing high-performance edge devices based on neural networks have difficulty achieving further breakthroughs in energy efficiency due to the arithmetic operations involved in high-precision data. Hyperdimensional computing, as an emerging computing framework, achieves a holographic distributed representation of information by encoding various forms of data into hyperdimensional vectors. It is hardware-friendly and highly robust, and is an effective alternative to the deployment of neural networks on edge devices. However, hyperdimensional computing involves similarity query operations on hyperdimensional vectors, which require calculations on ultra-high-dimensional data, placing higher demands on the operating bandwidth of traditional computing circuits. To address this demand, in-memory computing technology has emerged.

[0003] In-memory computing integrates computational operations into storage units, eliminating data transmission bottlenecks and improving computational efficiency and system performance. A circuit specifically designed for hyperdimensional vector similarity queries, called hyperdimensional associative memory, significantly reduces query latency through fully parallel in-memory computing. However, existing hyperdimensional associative memory is limited by the high-precision query requirements inherent in hyperdimensional computing, making it difficult to reduce its hardware resource consumption. Therefore, reducing hardware overhead while maintaining query accuracy is a pressing technical challenge in the field of hyperdimensional computing. Summary of the Invention

[0004] The purpose of the present invention is to provide a high-energy-efficiency coarse-grained in-memory query method and circuit for hyperdimensional vector similarity query, which can efficiently calculate the matching degree between ultra-long dimensional input feature vector data and stored category data, thereby realizing low-complexity coarse-grained hyperdimensional vector similarity query.

[0005] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0006] In a first aspect, the present invention discloses a high-energy-efficiency coarse-grained in-memory query method for hyperdimensional vector similarity query, the method comprising the following steps:

[0007] S1, segment the hyperdimensional vector, perform query operation on each segment of the input hyperdimensional vector, and calculate the Hamming distance with the corresponding segment stored hyperdimensional vector;

[0008] S2, compares each input hyperdimensional vector with the storage segment step by step, compresses the Hamming distance between each hyperdimensional vector segment, and compresses it into a fixed-length binary code;

[0009] S3, summarizes the compressed coding of each segment of Hamming distance, and calculates the matching degree between the ultra-long dimensional input feature vector data and the stored category data by fusing the compressed Hamming distance information of each segment of input hyperdimensional vector and the corresponding segment of stored hyperdimensional vector.

[0010] Step S1 further comprises:

[0011] Store N super-dimensional vectors into a storage array, where the storage array consists of N rows × D columns, and each row stores a D-dimensional super-dimensional vector;

[0012] Each row is divided into S-bit storage segments, and each segment unit is connected in series to form a time domain path. The Hamming distance is calculated by matching the time domain difference generated by the input hyperdimensional vector of each S-bit length with the corresponding segment storage hyperdimensional vector.

[0013] Step S2 further comprises:

[0014] Connecting a plurality of D latches and a plurality of reference branches having the same length as the segment at the end of the segment, wherein the reference branches are set to a fixed matching number;

[0015] The time domain difference between the segment and the reference branch is compared by using a D latch, and the Hamming distance between each segment of the hyperdimensional vector is compressed.

[0016] Step S3 further comprises:

[0017] N aggregation branches are constructed, each consisting of a transmission gate, a long inverter chain, and a short inverter chain. A binary Hamming distance compression code is used as input, and the transmission gate is selected based on the compression code value: when the code is 1, the short inverter branch is activated, and vice versa, the long inverter branch is enabled. This generates different delay differences, so that the similarity between each query hyperdimensional vector and the input hyperdimensional vector is expressed as the delay difference of the aggregation branch.

[0018] The output signals of all summary branches are connected to the write control signal of a dual inverter respectively. The latch structure of the dual inverter is written to 0 in advance. The latch structure of the branch with the shortest delay is written to 1 the fastest, and the write path of the remaining summary branches is turned off to obtain the output result in the form of one-hot encoding.

[0019] In a second aspect, the present invention discloses a high-energy-efficiency coarse-grained in-memory query circuit for super-dimensional vector similarity query, the circuit comprising a D-dimensional register group, an ND-dimensional storage array for storing super-dimensional vectors, a Hamming distance compression module corresponding to each segment, N compression coding aggregation modules, and an N-bit input time-domain winner-takes-all circuit;

[0020] The D-dimensional register group is used to store external input super-dimensional vectors and control the query signal within the storage array;

[0021] The ND-dimensional storage array storing the super-dimensional vector performs segment processing on the super-dimensional vector, then performs a query operation on each segment of the input super-dimensional vector, and calculates the Hamming distance with the corresponding segment of the stored super-dimensional vector;

[0022] The Hamming distance compression module corresponding to the segment is used to compare each segment of input super-dimensional vector with the storage segment step by step, compress the Hamming distance between each segment of super-dimensional vector, and compress it into a binary code of fixed length;

[0023] The compression coding summary module is used to summarize the compression coding of each segment of Hamming distance;

[0024] The time-domain winner-takes-all circuit calculates the matching degree between the ultra-long dimensional input feature vector data and the stored category data by fusing the compressed Hamming distance information of each segment input hyperdimensional vector and the corresponding segment stored hyperdimensional vector.

[0025] Furthermore, the memory array comprises a plurality of memory cells connected in series, each memory cell comprising a differential signal input circuit, two NMOSs connected in parallel, and two MRAMs connected correspondingly to the NMOSs;

[0026] The differential signal input circuit is used to input a differential signal controlled by the corresponding bit of the super-dimensional vector, respectively controlling two NMOSs. The two MRAMs connected to the NMOSs are used to store the bits corresponding to the super-dimensional vector to be queried. The two MRAMs are in a differential state, one high-resistance and the other low-resistance. Under the action of the differential signal, if the input super-dimensional vector matches the corresponding bit of the super-dimensional vector to be queried, the low-resistance path is turned on; if there is no match, the high-resistance path is turned on, and then a rising edge signal is provided to the input end of the segment.

[0027] Furthermore, an inverter is added to each of the two sides of the storage unit.

[0028] Furthermore, the Hamming distance compression module includes a plurality of compression units, each compression end unit includes a reference branch and a D latch; the CLK end of the D latch is connected to the output end of the reference branch, and the D end is connected to the output end of each storage unit;

[0029] The reference branch generates a signal Ref<1-n> that is identical to the segment in the storage array, and the SL&SLB signals of the reference branch are pre-set before querying to represent different Hamming distances. The D latch determines the corresponding Hamming distance by the delay difference between the reference branch and the segment output.

[0030] Furthermore, the compression coding aggregation module includes 2*N / S transmission gates and N / S inverter chains of two different lengths, and each two transmission gates are connected to inverter chains of different lengths, and together they constitute a aggregation unit;

[0031] The compression coding aggregation module connects the compression codes of the single stored super-dimensional vectors to the aggregation units respectively, and opens different transmission gate branches according to the different codes. If the code is 1, the branch corresponding to the short inverter chain is opened; otherwise, the branch corresponding to the long inverter chain is opened.

[0032] Furthermore, the one-hot encoding generation circuit includes multiple groups of dual-inverter latch structures and corresponding write branches, and a feedback branch composed of several parallel NMOS transistors, wherein the dual-inverter latch structure and the write branch correspond to the output signals of all the summary branches; when the output end of the summary branch becomes 1, the corresponding write branch is turned on, and the latch structure of the corresponding dual inverter is written to 1, and at the same time, the feedback branch composed of several parallel NMOS transistors turns off all write paths to obtain an output result in the form of one-hot encoding.

[0033] Compared with the prior art, the present invention has the following beneficial effects:

[0034] The present invention's energy-efficient, coarse-grained, in-memory query method and circuit for hyperdimensional vector similarity queries implements energy-efficient, coarse-grained hyperdimensional vector similarity queries through segmented processing, Hamming distance calculation compression, and the design of a summary circuit module. Compared to traditional methods, this method offers advantages such as fast computational speed, low energy consumption, and strong scalability, and has broad application prospects in fields such as big data processing and machine learning. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of a coarse-grained hyperdimensional vector similarity query method provided by an embodiment of the present invention;

[0036] Figure 2 A circuit diagram of a hyperdimensional associative storage hardware provided by an embodiment of the present invention;

[0037] Figure 3 A schematic diagram of a basic storage unit and its corresponding intra-segment connection method provided in an embodiment of the present invention; wherein (a) is a schematic diagram of the intra-segment connection method of the storage unit, and (b) is a diagram of the storage unit structure;

[0038] Figure 4 A schematic diagram of a Hamming distance compression module provided by an embodiment of the present invention; wherein (a) is a diagram of the segment aggregation circuit structure, and (b) is a schematic diagram of the principle of a D latch;

[0039] Figure 5A schematic diagram of a compressed coding summary output module provided for an embodiment of the present invention; wherein (a) is a class summary circuit structure diagram, (b) is a one-hot encoding generation circuit structure diagram connected to all class summary branches, and (c) is a single circuit unit structure diagram in the class summary circuit. DETAILED DESCRIPTION

[0040] The embodiments of the present invention are described in further detail below with reference to the accompanying drawings.

[0041] The present invention discloses a high-energy-efficiency coarse-grained in-memory query method for super-dimensional vector similarity query, the method comprising the following steps:

[0042] S1, segment the hyperdimensional vector, perform query operation on each segment of the input hyperdimensional vector, and calculate the Hamming distance with the corresponding segment stored hyperdimensional vector;

[0043] S2, compares each input hyperdimensional vector with the storage segment step by step, compresses the Hamming distance between each hyperdimensional vector segment, and compresses it into a fixed-length binary code;

[0044] S3, summarizes the compressed coding of each segment of Hamming distance, and calculates the matching degree between the ultra-long dimensional input feature vector data and the stored category data by fusing the compressed Hamming distance information of each segment of input hyperdimensional vector and the corresponding segment of stored hyperdimensional vector.

[0045] The first step is segmentation. When performing a similarity query on N D-dimensional hyperdimensional vectors in memory, the hyperdimensional vectors are first segmented into segments of length S bits. This requires a total of N*D / S segments of Hamming distance calculation and compression operations, as well as N aggregation operations.

[0046] Next, Hamming distance calculation and compression are performed. When calculating the Hamming distance between each S-bit input hyperdimensional vector and the corresponding stored hyperdimensional vector, the Hamming distance between the two is prioritized. The Hamming distance reflects the number of bits that differ between two vectors at corresponding positions and is an important metric for measuring vector similarity. The calculated Hamming distance is then compressed into a fixed-length binary code, less than S. The larger the Hamming distance, the smaller the proportion of 1s in the binary code. This compression method reduces data transmission while preserving key information about vector similarity.

[0047] To achieve the aforementioned Hamming distance calculation compression operation, the present invention designs a hyperdimensional vector storage array with Hamming distance calculation compression functionality. This array comprises N rows and D columns of storage cells, with each row storing a D-dimensional hyperdimensional vector. For segmented processing, each row of the storage array is further subdivided into multiple S-bit segments. The Hamming distance calculation is performed based on the time domain differences generated by the matching of input data with stored data. Furthermore, multiple D latches and multiple reference branches of the same length as the segment are connected at the end of each segment, where the reference branches are set to a fixed number of matches. By comparing the time domain differences between the segments and the reference branches, the Hamming distance compression function is achieved.

[0048] The present invention also designs a summarization circuit module that incorporates multiple Hamming distance compression structures. This module takes multiple binary Hamming distance compression codes as input and outputs an N-bit one-hot code of the final similarity query operation. Specifically, the circuit that performs the summarization operation on the compressed code of a stored hyperdimensional vector comprises 2*N / S transmission gates and N / S inverter chains of two different lengths. Each pair of transmission gates is connected to an inverter chain of different lengths, forming a summarization unit. By connecting the compressed code of a single stored hyperdimensional vector to the summarization unit, different transmission gate branches are enabled depending on the code. If the code is 1, the branch corresponding to the short inverter chain is enabled; otherwise, the branch corresponding to the long inverter chain is enabled. For example, if the Hamming distance between the input hyperdimensional vector and the stored hyperdimensional vector is 0, in this case, the compression code is all 1, and the branch with the corresponding conductive transmission gates has the fewest number of inverters, resulting in the shortest transmission delay.

[0049] The output module in this module is a time-domain winner-take-all circuit. When a rising edge signal is applied to N summing branches, different transmission delays are generated due to the different conduction paths of different branches. The summing branch with the shortest delay has its output terminal's rising edge arrive first, setting the corresponding winner-take-all module to 1 while simultaneously blocking the other branch paths, ultimately generating a one-hot encoded output result.

[0050] Based on the above scheme and circuit structure, the present invention implements an in-memory query circuit for energy-efficient, coarse-grained hyperdimensional vector similarity query. The circuit includes a D-dimensional register group (for storing external input hyperdimensional vectors and controlling in-memory query signals for the storage array), an N-dimensional storage array for storing hyperdimensional vectors (and a Hamming distance compression module corresponding to the segment), N compression coding aggregation modules (and an N-bit input time-domain winner-takes-all circuit). The N D-dimensional hyperdimensional vectors are stored row by row in an N-row * D-column storage array, and the similarity query operation between the input hyperdimensional vector and the N stored hyperdimensional vectors is completed through in-memory fully parallel Hamming distance calculation compression and the final compression result aggregation.

[0051] The query circuit of the present invention is described below from two aspects of query method and hardware implementation through an example.

[0052] (1) Query method

[0053] In step S101 , a 10,000-dimensional hyperdimensional vector is taken as an example, and is evenly divided into 100 segments of 100 bits in length, with the Hamming distance between each segment of the input hyperdimensional vector and the query hyperdimensional vector being in the range of 0-100.

[0054] In step S102, the Hamming distance between the input hyperdimensional vector and the hyperdimensional vector to be queried is calculated on a segment basis. The calculated Hamming distance is then compressed into a 10-bit binary code using a 10-bit step size. The smaller the Hamming distance, the more 1s there are in the binary code. For example, if the Hamming distance is 5, in the range of 0-10, the binary code is 1111111111; if the Hamming distance is 12, in the range of 11-20, the binary code is 11111111110.

[0055] In step S103, the binary codes obtained in step S102 are summarized, and the number of 1s in the binary codes of all segments of the same type of super-dimensional vectors is counted. If the number of 1s is greater, the Hamming distance between the corresponding input super-dimensional vector and the super-dimensional vector to be queried is smaller, that is, the similarity between the two is the highest.

[0056] (2) Hardware implementation

[0057] Based on the coarse-grained query method mentioned above, the present invention proposes Figure 2 The hyperdimensional associative storage shown in the figure. A segment (Seg) is a segmented structure obtained by connecting storage units in series. Through a unit structure based on time domain differences, the Hamming distance of each segment is ultimately presented as the delay difference between the input signal and the output signal. The Hamming distance of each segment is then compressed and aggregated by a segment aggregation circuit (Merge Seg, MS) based on the delay difference between the reference branch and the Seg. Finally, the output of the MS is connected to a one-hot encoding generation circuit (OG) based on the time domain to obtain the final classification result. The following will specifically implement the above steps S101-S103 from the perspective of hardware implementation.

[0058] Step S201 corresponds to step S101. First, STT-MRAM with high read and write times, low static power consumption, and low read latency is selected as the storage unit on the device. At the same time, in order to achieve Hamming distance compression within the segment, the present invention proposes a cell structure that relies on time domain differences to determine the matching situation. Since the delay difference between the matched and mismatched cell structures is constant, even if more cell structures are connected in series, the delay difference between different matching numbers will not change. The specific cell structure and the segment composed of the cell structure are as follows: Figure 3 shown.

[0059] Since STT-MRAM essentially stores information through resistance value, a delay difference can be generated at the output by charging and discharging the first-order RC network formed by STT-MRAM and the transistor gate. Figure 3 The SL&SLB signals in the scheme are differential signals controlled by the corresponding bits of the input hyperdimensional vector. They each control an NMOS transistor. The two MRAMs connected to the NMOS transistors are used to store the bits corresponding to the hyperdimensional vector to be queried, also in a differential state of one high-resistance and one low-resistance. Due to the differential nature of the SL&SLB signals, only one of the two controlled branches is conductive during the query process. If the input hyperdimensional vector matches the corresponding bit of the hyperdimensional vector to be queried, the low-resistance path is controlled to conduct; if not, the high-resistance path is controlled to conduct. A rising edge signal is then provided to the segment input. The Hamming distance can be calculated based on the rising edge delay between the segment output and input. The difference between a match and a mismatch is approximately 10 ps, and lower delays correspond to smaller Hamming distances.

[0060] In addition to the core storage unit, the present invention adds an inverter on both sides. On the one hand, this serves to isolate the various unit structures. On the other hand, since STT-MRAM itself exhibits different resistance values under high and low voltage working environments, which in turn affects the delay difference between matching and mismatching, adding two inverters can ensure that the delay difference of each unit is relatively constant.

[0061] Step S202 corresponds to step S102. The signal delay of each input and output terminal of the storage array is obtained from step S201. In order to convert it into a digital signal, the present invention sets the following Figure 4 The MS shown in FIG1 , where Ref<1-n> is the signal generated by the reference branch, is exactly the same as the segment in the storage array. The only difference is that the SL&SLB signals of the reference branch are pre-set before the query to represent different Hamming distances.

[0062] from Figure 4The main component of the Hamming distance compression module is the D latch. The corresponding Hamming distance is determined by the delay difference between the reference branch and the segment output. To maintain the stability of the D latch output signal, the signals at both ends of transmission gate T2 must be identical. The longest branch of the signal from D to T2 passes through I1, T1, I3, and I2 in sequence. The total delay generated by these devices is the D latch setup time, which is approximately 30 ps. Therefore, the delay between the reference signals of each D latch needs to be maintained at more than 30 ps. The delay difference between the matched and mismatched storage cells in step S201 is approximately 10 ps, so the MS resolution is greater than 3 bits, which is sufficient to meet the 10-bit step size compression requirement mentioned in step S102.

[0063] Step S203 corresponds to step S103. In order to save hardware overhead to the greatest extent, the summary operation of binary code also adopts OG based on time domain difference, and its specific structure is as follows: Figure 5 As shown. The one-hot encoding generation circuit consists of multiple sets of dual-inverter latch structures and corresponding write branches, as well as several parallel NMOS transistors, where the dual-inverter latch structures and write branches correspond to the OUT signals of all the summary branches. Figure 5 It can be seen that the binary code output by the intra-segment search controls the delay branch of the summary circuit. The more 1s in the binary code, the fewer inverters will pass through the path of the final summary circuit, and the smaller the total delay. In OG, the latch structure of the dual inverter is preferably written as 1. When the output end of a summary branch becomes 1, the corresponding write branch is turned on, and the latch structure of the corresponding dual inverter is written as 1. At the same time, since the Dis signal is connected to several parallel NMOS transistors, these transistors are controlled by the output signal of the summary branch. When any output signal (corresponding to Figure 5 The OUT signal in (a) and Figure 5 When the IN<1:n> signal in (b) (and all input signals In<1:n> form a dynamic NOR gate through parallel NMOS) goes high, Dis will be discharged to 0, thereby controlling the discharge path of all OG cells and shutting off the write path of the remaining aggregation branches. Since all dual-inverter latch structures are written to 0 before the query, only the dual inverter corresponding to the branch with the shortest delay is written to 1. Therefore, the final output result in one-hot encoding is obtained, that is, the query hyperdimensional vector with the highest similarity to the input hyperdimensional vector is found.

[0064] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0065] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A high-energy-efficiency coarse-grained in-memory query method for hyperdimensional vector similarity query, characterized by: The method comprises the following steps: S1, segment the hyperdimensional vector, perform query operation on each segment of the input hyperdimensional vector, and calculate the Hamming distance with the corresponding segment stored hyperdimensional vector; S2, compares each input hyperdimensional vector with the storage segment step by step, compresses the Hamming distance between each hyperdimensional vector segment, and compresses it into a fixed-length binary code; S3, summarizes the compressed coding of each segment of Hamming distance, and calculates the matching degree between the ultra-long dimensional input feature vector data and the stored category data by fusing the compressed Hamming distance information of each segment of input hyperdimensional vector and the corresponding segment of stored hyperdimensional vector.

2. The energy-efficient coarse-grained in-memory query method for hyperdimensional vector similarity query according to claim 1, characterized in that: Step S1 further comprises: Store N super-dimensional vectors into a storage array, where the storage array consists of N rows × D columns, and each row stores a D-dimensional super-dimensional vector; Each row is divided into S-bit storage segments, and each segment unit is connected in series to form a time domain path. The Hamming distance is calculated by matching the time domain difference generated by the input hyperdimensional vector of each S-bit length with the corresponding segment storage hyperdimensional vector.

3. The energy-efficient coarse-grained in-memory query method for hyperdimensional vector similarity query according to claim 1, characterized in that: Step S2 further comprises: Connecting a plurality of D latches and a plurality of reference branches having the same length as the segment at the end of the segment, wherein the reference branches are set to a fixed matching number; The time domain difference between the segment and the reference branch is compared by using a D latch, and the Hamming distance between each segment of the hyperdimensional vector is compressed.

4. The energy-efficient coarse-grained in-memory query method for hyperdimensional vector similarity query according to claim 1, characterized in that: Step S3 further comprises: N aggregation branches are constructed, each consisting of a transmission gate, a long inverter chain, and a short inverter chain. A binary Hamming distance compression code is used as input, and the transmission gate is selected based on the compression code value: when the code is 1, the short inverter branch is activated, and vice versa, the long inverter branch is enabled. This generates different delay differences, so that the similarity between each query hyperdimensional vector and the input hyperdimensional vector is expressed as the delay difference of the aggregation branch. The output signals of all summary branches are connected to the write control signal of a dual inverter respectively. The latch structure of the dual inverter is written to 0 in advance. The latch structure of the branch with the shortest delay is written to 1 the fastest, and the write path of the remaining summary branches is turned off to obtain the output result in the form of one-hot encoding.

5. A high-energy-efficiency coarse-grained in-memory query circuit for hyperdimensional vector similarity query, characterized in that: The circuit includes a D-dimensional register group, an ND-dimensional storage array for storing super-dimensional vectors, a Hamming distance compression module corresponding to the segment, N compression coding summary modules, and an N-bit input time-domain winner-takes-all circuit; The D-dimensional register group is used to store external input super-dimensional vectors and control the query signal within the storage array; The ND-dimensional storage array storing the super-dimensional vector performs segment processing on the super-dimensional vector, then performs a query operation on each segment of the input super-dimensional vector, and calculates the Hamming distance with the corresponding segment of the stored super-dimensional vector; The Hamming distance compression module corresponding to the segment is used to compare each segment of input super-dimensional vector with the storage segment step by step, compress the Hamming distance between each segment of super-dimensional vector, and compress it into a binary code of fixed length; The compression coding summary module is used to summarize the compression coding of each segment of Hamming distance; The time-domain winner-takes-all circuit calculates the matching degree between the ultra-long dimensional input feature vector data and the stored category data by fusing the compressed Hamming distance information of each segment input hyperdimensional vector and the corresponding segment stored hyperdimensional vector.

6. The high-energy-efficiency coarse-grained in-memory query circuit for hyperdimensional vector similarity query according to claim 5, characterized in that: The memory array comprises a plurality of memory cells connected in series, each memory cell comprising a differential signal input circuit, two NMOSs connected in parallel, and two MRAMs connected correspondingly to the NMOSs; The differential signal input circuit is used to input a differential signal controlled by the corresponding bit of the super-dimensional vector, respectively controlling two NMOSs. The two MRAMs connected to the NMOSs are used to store the bits corresponding to the super-dimensional vector to be queried. The two MRAMs are in a differential state, one high-resistance and the other low-resistance. Under the action of the differential signal, if the input super-dimensional vector matches the corresponding bit of the super-dimensional vector to be queried, the low-resistance path is turned on; if there is no match, the high-resistance path is turned on, and then a rising edge signal is provided to the input end of the segment.

7. The high-energy-efficiency coarse-grained in-memory query circuit for hyperdimensional vector similarity query according to claim 6, characterized in that: An inverter is added to each of the two sides of the storage unit.

8. The high-energy-efficiency coarse-grained in-memory query circuit for hyperdimensional vector similarity query according to claim 6, characterized in that: The Hamming distance compression module includes a plurality of compression units, each of which includes a reference branch and a D latch; the CLK terminal of the D latch is connected to the output terminal of the reference branch, and the D terminal is connected to the output terminal of each storage unit; The reference branch generates a signal Ref<1-n> that is identical to the segment in the storage array, and the SL&SLB signals of the reference branch are pre-set before querying to represent different Hamming distances. The D latch determines the corresponding Hamming distance by the delay difference between the reference branch and the segment output.

9. The high-energy-efficiency coarse-grained in-memory query circuit for hyperdimensional vector similarity query according to claim 5, characterized in that: The compression coding aggregation module includes 2*N / S transmission gates and N / S inverter chains of two different lengths. Each two transmission gates are connected to an inverter chain of different lengths, and together they constitute a aggregation unit. The compression coding aggregation module connects the compression codes of the single stored super-dimensional vectors to the aggregation units respectively, and opens different transmission gate branches according to the different codes. If the code is 1, the branch corresponding to the short inverter chain is opened; otherwise, the branch corresponding to the long inverter chain is opened.

10. The high-energy-efficiency coarse-grained in-memory query circuit for super-dimensional vector similarity query according to claim 9, characterized in that: The one-hot encoding generation circuit includes multiple groups of dual-inverter latch structures and corresponding write branches, as well as a feedback branch composed of several parallel NMOS transistors, wherein the dual-inverter latch structures and the write branches correspond to the output signals of all the summary branches; when the output end of the summary branch becomes 1, the corresponding write branch is turned on and the latch structure of the corresponding dual-inverter is written to 1. At the same time, the feedback branch composed of several parallel NMOS transistors turns off all write paths to obtain an output result in the form of one-hot encoding.

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