Modular addressing ultrasonic sensor array receiving circuit system

Abstract

The invention discloses a modular addressing ultrasonic sensor array receiving circuit system, belongs to the field of ultrasonic nondestructive testing instruments, and can be used for receiving echo signals detected by array elements with different apertures in a 64 array element addressing receiving ultrasonic sensor array. Each channel of the circuit system takes a row array element of an addressing ultrasonic sensor array as a receiving unit, and is matched with a column gating switch circuit to realize integral or selective receiving of different array elements in the row, so that the row number is taken as the channel number, and receiving, preprocessing, A / D conversion and decoding of 64 array element signals are realized; and the data can be stored in an FPGA (field programmable gate array) or transmitted to an upper computer so as to facilitate secondary development and utilization of echo signals. The circuit system provided by the invention adopts a modular structure, takes 8 channels as independent modules, and can provide a solution for a 64-array-element addressing ultrasonic sensor array receiving circuit.

Description

Technical Field

[0001] The invention belongs to the technical field of ultrasonic non-destructive testing and relates to an addressing ultrasonic sensor array receiving circuit system. Background Art

[0002] Ultrasonic waves are widely used in industrial nondestructive testing, enabling non-invasive detection of internal defects in materials. Ultrasonic waves are typically generated by sensitive materials with piezoelectric effects under the influence of electrical pulses. After passing through the object being tested, ultrasonic reflection echoes carrying the defect signal are transmitted via the piezoelectric effect, generating an electrical signal on the sensor. After reception and processing, these signals can be used for material defect detection and assessment. Ultrasonic sensor arrays, composed of multiple array elements, enable multi-angle scanning, thereby improving detection efficiency and accuracy. These are currently the most commonly used ultrasonic sensors in industrial ultrasonic testing. In recent years, a new type of ultrasonic sensor array, known as an addressable ultrasonic sensor array, has emerged, offering more convenient and flexible array element control. Compared to traditional ultrasonic sensor arrays, addressable ultrasonic sensor arrays can selectively excite and receive elements of any aperture according to detection requirements. The collinear edge-jointing of rows and columns makes large-scale arrays possible. Furthermore, by varying the transmit and receive apertures and focusing laws, the excitation wavefront can be optimized. However, a receiver circuit system suitable for such sensor arrays is currently lacking. The present invention aims to provide a design and solution for addressable ultrasonic sensor array receiver circuit systems.

[0003] The present invention adopts a modular design scheme, connecting a 64-element addressable ultrasonic sensor array in a collinear manner. Eight signal electrodes (collinear row electrodes on the upper surface) and eight ground electrodes (collinear column electrodes on the lower surface) are formed on the sensor array. The electronic switches on the corresponding elements are turned on and off by high and low voltage levels according to the addressing control rules, thereby selecting and cutting off the corresponding elements. At the element receiving end, an 8-channel integrated chip is used as the echo signal receiving unit to preprocess the element received signals in the sensor array. The signals are then passed through a received data decoding circuit, a host computer communication circuit, and a parameter configuration communication circuit to achieve selective reception of ultrasonic echo signals. The received detection echo signals are then transmitted and stored through a secondary buffer memory circuit. The circuit system of the invention is characterized by a small circuit size and low noise interference. A unique clock signal reconstruction method can reduce the data transmission bit error rate, ensuring data integrity and high-speed transmission. Summary of the Invention

[0004] The present invention aims to provide a design and implementation method for a modular addressable ultrasonic sensor array receiving circuit system for controllable reception of ultrasonic echo signals from array elements with different apertures in an addressable ultrasonic sensor array. The circuit system utilizes an integrated analog front-end integrated chip, resulting in a compact circuit and minimal noise interference. The modular design approach facilitates adaptation to addressable ultrasonic sensor arrays of varying sizes, allowing for expansion of the number of receiving channels. Furthermore, the present invention proposes a data clock signal reconstruction circuit for LVD signals that synchronizes the frame clock with the bit clock, reducing the bit error rate of decoding. A secondary buffer memory architecture is also designed to enable high-capacity, real-time transmission and storage of data collected from multi-channel received echo signals.

[0005] The present invention provides a modular addressable ultrasonic sensor array receiving circuit system. The invention is described as follows:

[0006] The functions of each unit circuit of a modular addressable ultrasonic sensor array receiving circuit system are as follows:

[0007] An addressable ultrasonic sensor array (101) is used to transmit and receive ultrasonic signals and perform ultrasonic detection on a target object; an addressing rule signal generation and control circuit (102) is used to control the conduction of row and column signal lines of a 64-element addressable ultrasonic sensor array so that the elements in the addressable array can be selected according to the addressing rule; a sensor output end integrated receiving circuit (103) is used to receive signals from the addressable ultrasonic sensor array and perform amplification, filtering, and A / D conversion on the signals to a certain extent; and a multi-channel receiving data decoding circuit (104) is used to convert the LVD signals simultaneously output by the 8 channels of the sensor output end integrated receiving circuit into a digital signal. decoding; a host computer communication circuit (105) for storing the 8-channel data promptly and quickly in the FPGA local ROM (read-only memory) or sending it to the addressable ultrasonic sensor array detection system host computer via Ethernet, so as to facilitate further analysis of the echo signal; a parameter configuration communication circuit (106) composed of a serial port transceiver circuit, connected using an SPI bus, for sending addressing rules to the addressing rule signal generating circuit (102), and controlling the channel parameters of the sensor output end integrated receiving circuit (103), which include: input impedance, gain coefficient, DC bias correction, cutoff frequency and encoding format.

[0008] In addition to the above main functional modules, the modular addressable ultrasonic sensor array receiving circuit system of the present invention further includes:

[0009] (1) A limiting circuit uses two anti-parallel diodes, one end of which is grounded and the other end is connected to the signal line of the addressing ultrasonic sensor array. It is used to limit the voltage amplitude of the echo signal to prevent large-value voltage from entering the subsequent circuit and causing damage to components;

[0010] (2) The power module uses multiple voltage conversion chips and voltage regulator chips to convert the input voltage into voltages of various amplitudes, providing a stable, low-ripple power supply for the entire circuit system;

[0011] (3) Clock module, used to provide a stable clock signal to the integrated receiving circuit at the sensor output end and the multi-channel receiving data decoding circuit.

[0012] Furthermore, the addressable ultrasonic sensor array utilizes collinear connections in rows and columns. The top surface electrodes in the same row of the array are connected together and have an output electrode lead connected to an external circuit; the bottom surface electrodes in the same column of the array are connected together and have an output electrode lead connected to an external circuit. A 64-element array consists of eight row electrode leads and eight column electrode leads, which can be used to control the selection and cutoff of the elements in the array. The elements are numbered (i, j), where i is the array row number, i = 1, 2, ..., M, where M is the total number of rows in the array, and j is the array row number, j = 1, 2, ..., N, where N is the total number of columns in the array. When a single element signal needs to be excited and received, the control rule selects row i and column j, i.e., row signal line i and column signal line j are turned on, while the others are turned off. When multiple elements need to be selected, the rows and columns corresponding to the multiple elements are selected separately.

[0013] Furthermore, the addressing rule signal generation and control circuit includes a row gating circuit, a column gating circuit, and an addressing rule signal generation circuit. The addressing rule encodes the rows and columns to be gated, forming an addressing rule. The row and column gating circuits control the gating and blocking of the gating array elements. When the control circuit outputs a logic high, the corresponding switch is turned on; when the control circuit outputs a logic low, the corresponding switch is turned off. The addressing rule is a control level sequence signal composed of these high and low levels, supplemented by timing changes (phase changes), to achieve selective excitation and reception of the array elements. The control signal generated by the control circuit is used to convert the addressing rule transmitted by the parameter configuration communication circuit into a high and low level switching sequence signal that controls the row and column gating circuits. The outputs of the row and column gating control circuits are connected to the collinear electrodes of the addressing ultrasonic sensor array, and a MOS electronic switch is connected in series between the collinear electrodes and the control gating circuit. When the electronic switch is on, the row or column where the array element is located is gated; when the electronic switch is off, the corresponding row or column array element is turned off.

[0014] Furthermore, the sensor output integrated receiving circuit comprises a highly integrated 8-channel analog front-end chip and peripheral circuitry. The peripheral circuitry comprises eight active inputs connected via capacitors to the row signal lines of the addressed ultrasonic sensor array, which pass through a limiting circuit. The eight positive signal inputs of the analog front-end chip IC1 are connected via capacitors to the row signal lines, which pass through the limiting circuit. The eight negative signal inputs of the analog front-end chip IC1 are connected via capacitors to the column signal lines. The sensor output integrated receiving circuit requires four standard voltage levels of varying amplitudes for power supply, a pair of differential voltage levels for controlling the gain coefficient of the voltage-controlled attenuator, and one standard voltage level as an onboard reference voltage for A / D conversion.

[0015] The echo signals on the row signal lines of the addressable ultrasonic sensor array are connected to the corresponding analog front-end channels after passing through the limiting circuit. Each analog front-end channel of the integrated receiving circuit at the sensor output end consists of an LNA, VCAT, PGA, LPF and ADC. The analog signals on the row signal lines of the addressable ultrasonic sensor array are converted into a pair of LVD signals after amplification, filtering, A / D conversion and encoding by the analog front-end channels. The frame clock signal and bit clock signal are also output simultaneously. When the eight channels are working simultaneously, eight pairs of LVD signals are generated: a pair of differential frame clock signals and a pair of differential bit clock signals.

[0016] The configuration parameters of each functional unit of the analog front-end channel are independent, and the parameters of each channel can be configured using SPI communication. The adjustable parameters of LNA are input impedance Z i , gain coefficient G 1i And DC bias correction, VCAT adjustable parameter is attenuation coefficient G2, support the use of digital adjustment and external analog voltage signal adjustment, PGA adjustable parameter is gain coefficient G3, 3 order LPF adjustable parameter is cutoff frequency F L The adjustable parameters of ADC include encoding format, data sequence and reference voltage source. The encoding format can be selected as offset code or complement code, the data sequence can be selected as MSB (most significant bit) first or LSB (least significant bit) first, and the reference voltage source can be selected as the internal reference voltage of the analog front-end chip or the onboard reference voltage of the integrated receiving circuit board at the sensor output end. Each analog front-end channel can set the digital gain coefficient G after the echo signal is converted into a digital signal. 4i , the final signal gain after passing through the analog front-end channel is G i =G 1i +G2+G3+G 4i .

[0017] Furthermore, the multi-channel received data decoding circuit is composed of multiple decoding circuits and a clock reconstruction circuit. The decoding circuit is composed of a data input buffer and a decoder. The data input buffer receives the LVD signal of the corresponding analog front-end channel at the input end and outputs a single-ended signal to the corresponding decoder at the output end. The clock reconstruction circuit is composed of a decoder, a data input buffer, a delay device, and a clock alignment state machine. The input signals of the clock reconstruction circuit are the frame clock signal and bit clock signal of the integrated receiving circuit at the sensor output end. The output reconstructs the bit clock signal and frame clock signal and connects to the decoders in all decoding circuits. After passing through the decoding circuit, the LVD signals of multiple channels are decoded into parallel data and merged into a longer multi-channel data.

[0018] Furthermore, the host computer communication circuit is composed of a secondary buffer memory and an Ethernet communication circuit, wherein the secondary buffer memory is composed of three FIFOs, FIFO1 and FIFO2 constitute the first-level data buffer structure, FIFO3 constitutes the second-level data buffer structure, the data signal port and enable signal port of FIFO3 constitute the GMII interface connected to the Ethernet physical layer chip, and the data is sent to the addressable ultrasonic sensor array detection system host computer using the UDP (User Datagram) protocol.

[0019] Furthermore, the parameter configuration communication circuit comprises a serial transceiver circuit, which is comprised of a USB FIFO (Universal Serial Bus interface conversion chip using memory) and peripheral circuits. The addressing rule signal generation and control circuit and the sensor output integrated receiving circuit are equipped with the following SPI communication ports: SEN is the enable input of the function configuration register; SCLK is the clock signal input of the function configuration register; SDATA is the signal input of the function configuration register; and SSID is the device selector of the function configuration register. The parameter configuration communication circuit is connected to the host computer of the addressing ultrasonic sensor array detection system via USB and to the SEN, SCLK, SDATA, and SSID ports of the addressing rule signal generation and control circuit and the sensor output integrated receiving circuit via an SPI bus. Configuration parameters sent by the addressing ultrasonic sensor array detection system are converted into SPI logic signals with a certain timing sequence by the USB FIFO and sent to the addressing rule signal generation and control circuit and the sensor output integrated receiving circuit to implement parameter adjustment.

[0020] Furthermore, the clock reconstruction circuit is composed of a decoder, a data input buffer and a delay device in the IP core of the FPGA. The differential frame clock and bit clock signals are converted into single-ended signals after passing through the data input buffer, and then decoded into digital signals S by the decoder. F and S B , the clock alignment state machine compares the digital signals of the two, and according to SF and S B The phase difference output phase alignment signal S c , the delay device is based on the phase alignment signal S c Modify the phase of the bit clock signal and output the reconstructed bit clock signal, which is decoded into a digital signal S by the decoder. r , the clock alignment state machine again adjusts S r and S F Phase difference detection is performed to output a phase alignment signal, and the clock reconstruction circuit repeats this process until the phase of the reconstructed bit clock signal is completely aligned with the single-ended frame clock signal.

[0021] Furthermore, the calculation method of the secondary buffer memory related parameters is as follows: the sampling frequency is F s According to the data sheet and circuit structure of the analog front-end chip used, the following clock frequency relationship can be obtained: the frequency of the frame clock f F With sampling frequency F s The same, that is, f F =F s ; The number of ADC bits is a and it is a double-edge signal, then the data bit clock frequency is f D is the sampling frequency F s of times, that is, f D =aF s ; The write clock 1 frequency f1 of FIFO1 and FIFO2 is the same as the frame clock frequency of the data, that is, f2 = F s ; FIFO3 read clock 2 frequency f4 and Ethernet transmission frequency f t Phase, that is, f4=f t ; The write clock 2 frequency f3 of FIFO3 is in phase with the read clock 1 frequency f2 of FIFO1 and FIFO2, that is, f3 = f2; the data collected by the integrated receiving circuit at the output end of the 8-channel sensor is decoded and merged into a single data length of l1 = 8 × 16 = 128, and the data length after conversion by the first-level buffer memory is l2 = 16. The input data length of FIFO3 is l2 = 16, and the output data length is l3 = 8. The ratio of the read clock 2 frequency f4 to the write clock 2 frequency f3 of FIFO3 is The multiple relationship with the second data bit conversion determines whether FIFO3 needs a certain depth. When the data read speed is greater than the write speed, there is no requirement for the depth D of FIFO3; when , FIFO3 needs to have a sufficient depth D to ensure that data is not lost. Further calculation of the depth D of FIFO3, the depth D of FIFO3 needs to satisfy the requirement that all data collected within the sampling window time T can enter FIFO3. The depth D of FIFO3 is The minimum storage unit in FIFO3 is 8 bits. The time t required to complete one ultrasonic signal data transmission is at least t≤2T. When the host computer communication circuit can send all the data within a sampling window time to the addressable ultrasonic sensor array detection system host computer.

[0022] It can be seen from the above method that the present invention has the following beneficial effects: the circuit system uses an integrated chip, which reduces the circuit volume and reduces noise interference; a clock reconstruction circuit is designed to perform phase synchronization reconstruction on the bit clock, and the reconstructed clock signal is used for data decoding, which can reduce the bit error rate of LVD signal decoding; in order to solve the problem that a large amount of data is obtained in a short time under high sampling rate and multiple receiving channels and the data is difficult to store in time, a secondary buffer memory is designed to be used in conjunction with the Ethernet communication circuit to ensure data integrity and transmission speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is a diagram showing the structure of the addressable ultrasonic sensor array detection system;

[0024] Figure 2 Schematic diagram of the integrated receiving circuit at the sensor output end;

[0025] Figure 3 Analog front-end channel circuit diagram;

[0026] Figure 4 Multi-channel receiving data decoding circuit diagram;

[0027] Figure 5 Parameter configuration communication circuit schematic diagram;

[0028] Figure 6 Clock reconstruction circuit diagram;

[0029] Figure 7 Secondary buffer memory circuit diagram;

[0030] Figure 8 (a), (b), (c), and (d) are respectively time domain waveform diagrams of the ultrasonic echo signals measured under four different addressing rules of the present invention. DETAILED DESCRIPTION

[0031] The following will fully describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. It should be noted that the present invention can also be applied through other equivalent implementation methods. The implementation methods and illustrations provided in the embodiments only illustrate the basic technical concept of the present invention in an illustrative manner. The models, numbers, sizes, materials and other parameters of the relevant elements in the embodiments can be changed in the specific implementation environment. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0032] The present invention adopts an addressable ultrasonic sensor array with 8 rows and 8 columns, totaling 64 elements, and a modular addressable ultrasonic sensor array receiving circuit system mainly because it can complete the above functions and can be expanded to different scales by the addressing selection method and modular circuit.

[0033] 1. To facilitate understanding of the modular addressable ultrasonic sensor array receiving circuit system, the exemplary addressable ultrasonic sensor array detection system of the present invention is first described. The addressable ultrasonic sensor array detection system is composed of the following components: Figure 1As shown, 101 is an addressable ultrasonic sensor array, 102 is an addressing rule signal generation and control circuit, 103 is an integrated receiving circuit at the sensor output end, 104 is a multi-channel receiving data decoding circuit, 105 is a host computer communication circuit, and 106 is a parameter configuration communication circuit. The addressable ultrasonic sensor array (101) adopts a collinear connection method for rows and columns. The upper surface electrodes in the same row of the array are connected together, and an output electrode lead is connected to the external circuit; the lower surface electrodes in the same column of the array are connected together, and an output electrode lead is connected to the external circuit. The array of 64 elements consists of 8 row electrodes and 8 column electrodes, which can be used for the selection and cutoff control of the elements in the array. The elements are numbered as (i, j), where i is the array row number, i=1,2,...,8, and j is the array column number, j=1,2,...,8. When it is necessary to excite and receive a single element signal, the control rule selects the i row and j column, and cuts off the others. When multiple array elements need to be selected, the rows and columns corresponding to the multiple array elements are selected respectively. The eight row signal lines are connected to the eight analog front-end channels in the integrated receiving circuit (103) at the sensor output end. When the addressing ultrasonic sensor array (101) receives a signal, the signal line connected to the target array element (i, j) is connected to form a signal loop to realize the selection of the target array element (i, j). The echo signal enters the i-th analog front-end channel. After passing through the analog front-end channel, the echo signal is quantized and encoded into an LVD signal and enters the multi-channel receiving data decoding circuit (104). The LVD signal completes phase synchronization through the clock reconstruction circuit and is converted into multi-channel parallel data through the decoding circuit. The multi-channel parallel data is then transmitted to the host computer of the addressing ultrasonic sensor array detection system through the host computer communication circuit (105). By analyzing the echo signal, the parameters of the detection system are adjusted. The adjusted parameters are sent to the addressing rule signal generation and control circuit (102) and the sensor output end integrated receiving circuit (103) through the parameter configuration communication circuit.

[0034] Combine Figure 1 As shown, this embodiment further includes a power module for providing a stable voltage to the sensor output end integrated receiving circuit module (103), the multi-channel receiving data decoding circuit (104) and the host computer communication circuit (105); and a clock module for providing a stable clock signal to the sensor output end integrated receiving circuit (103) and the multi-channel receiving data decoding circuit (104). In this embodiment, the system adopts an external 5V power supply, the power module provides voltages of +5V, +3.3V, +1.8V, +1.4V, and -5V, and the clock module generates a stable 20MHz clock signal with a duty cycle of 50%, a high level of 3.3V, a low level of 0V, and a maximum rise time and fall time of 5ns.

[0035] The working process of the circuit in this embodiment is as follows:

[0036] Through the host computer input, the multi-channel receiving data decoding circuit (104) and the host computer communication circuit (105) complete the program burning before the detection, and form a decoding circuit, a clock reconstruction circuit and a secondary buffer memory in the FPGA; when receiving the ultrasonic signal, the addressing ultrasonic sensor array detection system host computer sends the configuration parameters to the parameter configuration communication circuit (106), and the parameter configuration communication circuit (106) sends the configuration parameters to the addressing rule signal generation and control circuit (102) and the sensor output end integrated receiving circuit (103) according to a certain time sequence, and the addressing ultrasonic sensor Under the control of the addressing rule signal generation and control circuit (102), the target array element (i, j) is selected, and the echo signal enters the i-th analog front-end channel of the integrated receiving circuit (103) at the sensor output end. The echo signal is amplified, filtered and A / D converted in the i-th analog front-end channel to become an LVD signal. The LVD signal is decoded into a parallel digital signal through a clock reconstruction circuit and a decoding circuit, and the data length is reduced to 8. Then, the LVD signal enters the Ethernet communication circuit, and the data is packaged and sent to the host computer of the addressing ultrasonic sensor array detection system for further processing.

[0037] 2. Figure 2This is a schematic diagram of the integrated receiving circuit for the sensor output of the present invention, which includes a highly integrated 8-channel analog front-end chip IC1 (model AFE5808ZCF) and a peripheral circuit consisting of resistors R1, R2, and capacitors C1 to C35. The peripheral circuit has eight active input terminals connected to the row signal lines of the addressable ultrasonic sensor array through a limiter circuit via capacitors C1, C4, C7, C10, C13, C16, C19, and C22. The eight positive signal input terminals of the analog front-end chip IC1 are connected to the row signal lines through the limiter circuit via capacitors C2, C5, C8, C11, C14, C17, C20, and C23. The eight negative signal input terminals of the analog front-end chip are connected to the column signal lines via capacitors C3, C6, C9, C12, C15, C18, C21, and C24. U1, U2, U3, and U4 are standard voltage levels provided by the power module, with voltages of +5V, -5V, +3.3V, and +1.8V, respectively. They are connected to the corresponding power input pins of the analog front-end chip through two bypass capacitors. U5 and U6 are a pair of differential voltages controlled by variable resistors, which are connected to the positive input and negative input terminals of the voltage-controlled attenuator through resistors R1, R2, and capacitors C33 and C34, respectively. U7 is the reference voltage provided by the power module, with a voltage of +1.4V. It is used as the on-board reference voltage in the ADC configuration parameters and is connected to the A / D converter reference voltage pin of the analog front-end chip through capacitor C35. GND is the reference ground plane shared by analog signals, and DGND is the reference ground plane shared by digital signals.

[0038] D1P to D8P, D1N to D8N, DCLKP, DCLKN, FCLKP, and FCLKN are the signal output terminals of the analog front-end chip. DiP and DiN are the LVD signals representing the data output by analog front-end channel i. DCLKP and DCLKN are the differential bit clock signals output by IC1. FCLKP and FCLKN are the differential frame clock signals output by IC1.

[0039] 3. Figure 3This is a logic diagram of a single analog front-end channel in the integrated receiving circuit of the sensor output end of the present invention. The eight analog front-end channels in the circuit all have the same structure and can be parameterized. The structure of the analog front-end channel is composed of a limiter circuit, LNA, VCAT, PGA, a third-order LPF and a 14-bit high-speed ADC connected in series. The VCAT and ADC require reference voltage input. The VCAT input voltage can be adjusted using a variable resistor. The ADC supports the internal reference voltage of the analog front-end chip and the external input reference voltage. The limiter circuit can limit the voltage range of the input signal to within ±0.7V based on the conduction voltage of the diode used. The various functional structures of the analog front-end channel support parameter configuration using SPI communication. The adjustable parameter of the LNA is the input impedance Z i , gain coefficient G 1i and DC bias correction, G1 range 12dB to 24dB, step length 6dB, input impedance can select individual values between 25Ω and 4500Ω, VCAT adjustable parameter is attenuation coefficient G2, gain range 0dB to -40dB, step length 8dB, supports digital adjustment and external analog voltage signal adjustment, PGA adjustable parameter is gain coefficient G3, gain range 0dB to 30dB, step length 6dB, 3rd order LPF adjustable parameter is cutoff frequency F L The options are 5MHz, 10MHz, and 15MHz. The adjustable parameters of the ADC include the encoding format, data order, and reference voltage source. The encoding format can be selected as offset code or complement code, the data order can be selected as MSB (most significant bit) first or LSB (least significant bit) first, and the reference voltage source can be selected as the internal reference voltage of the analog front-end chip or the +1.4V reference voltage on the integrated receiving circuit board at the sensor output end. Each analog front-end channel can set the digital gain coefficient G after the echo signal is converted into a digital signal. 4i , the range is 0dB to 10dB, the step size is 0.5dB, and the final signal gain after passing through the analog front-end channel i is G i =G 1i +G2+G3+G 4i .

[0040] The circuit in this embodiment operates as follows: After the parameter configuration communication circuit sends parameters to the integrated receiving circuit at the sensor output, the analog front-end channel parameters are adjusted in the next sampling cycle. After the echo signal passes through the limiter circuit, the voltage range is limited to ±0.7V. The signal is amplified after passing through the LNA, VCAT, and PGA. The third-order LPF suppresses high-order harmonic signals. The ADC converts the analog signal into a digital signal, and then performs final gain adjustment on the digital signal before outputting the LVD signal.

[0041] 4. Figure 4The multi-channel receiving data decoding circuit logic diagram of the present invention uses an FPGA chip with model number xc7a35tfgg484 produced by Xilinx for circuit design and development. The IP cores used are ISERDESE2 (deserializer), IBUF (data input buffer) and IDELAY (delay). The multi-channel receiving data decoding circuit consists of a clock reconstruction circuit and 8 decoding circuits. The frame clock signal and bit clock signal in the LVD signal are connected to the clock reconstruction circuit. The data signal generated by each analog front-end channel is connected to the corresponding decoding circuit. The clock reconstruction circuit outputs the frame clock signal and the phase-synchronized reconstructed bit clock signal to the ISERDESE2 of the decoding circuit. The data signal is converted into a single-ended signal by the IBUF and enters the ISERDESE2. After being decoded by the ISERDESE2, each ISERDESE2 generates parallel data within the next frame clock cycle.

[0042] The working process of the circuit in this embodiment is as follows: the frame clock signal and bit clock signal of the integrated receiving circuit at the sensor output end enter the clock reconstruction circuit, the clock reconstruction circuit outputs the reconstructed bit clock signal, the LVD signals DiP and DiN generated by the analog front-end channel i are connected to the decoding circuit i, the data signal is converted into a single-ended signal by IBUF and then enters ISERDESE2, ISERDESE2 decodes according to the frame clock and the reconstructed bit clock signal, and outputs a 16-bit parallel digital signal in the next frame clock cycle, and the parallel data generated by the 8 deserialization circuits are merged into a multi-channel parallel digital signal of the same frame.

[0043] 5. Figure 5 This is a schematic diagram of the parameter configuration communication circuit of the present invention, which consists of a USB FIFO IC2 and its peripheral circuits. The addressable ultrasonic sensor array detection host computer is connected to IC2 via USB TYPEC. CC1 and CC2 of USB TYPEC each use a pull-down resistor to determine whether the USB FIFO is a slave device in the USB protocol. VBUS supplies power to IC2 via a ferrite bead FB1. IC2 can output a 3.3V voltage from its 3.3V_USB pin to power the slave device. DP1 and DP2 are connected to IC2's serial positive data terminal USBDP, while DN1 and DN2 are connected to IC2's serial negative data terminal USBDM. IC2 converts the serial data into SPI logic signals, which are then connected to the addressing rule signal generation circuit and the SPI communication port of the sensor output integrated receiving circuit via the SCLK, SDATA, SEN, and SSID ports.

[0044] The working process of the circuit in this embodiment is as follows: the addressing ultrasonic sensor array detection host computer sends the configuration parameters to the parameter configuration communication circuit, and the configuration parameters are converted into SPI logic signals by IC2 and sent to the SPI communication port of the addressing rule signal generation circuit and the sensor output integrated receiving circuit. The configuration parameters are adjusted in the next sampling cycle.

[0045] 6. Figure 6 This is the logic diagram of the clock reconstruction circuit of the present invention. The frame clock signal and the bit clock signal are converted into single-ended signals after passing through IBUF, and then decoded into digital signals S through ISERDESE2. F and S B The clock alignment state machine compares the digital signals of the two within a frame clock cycle and outputs a phase alignment signal S according to the phase difference of the signals. c IDELAY readjusts the phase of the single-ended bit clock signal according to the phase alignment signal to output the reconstructed bit clock signal. The reconstructed bit clock signal is decoded into a digital signal S by ISERDESE2. r , the clock alignment state machine again adjusts S F and S r Perform phase difference detection and output phase alignment signal S c The clock reconstruction circuit repeats this process until the phase of the reconstructed bit clock signal is aligned with the single-ended frame clock signal. The clock alignment state machine sets the phase alignment flag to 1. When the phase alignment flag is 0, the data output by the decoding circuit has a high bit error rate because the phase of the frame clock and the bit clock are not synchronized. The data at this stage is unusable. When the phase alignment flag is 1, the decoding circuit uses the phase-synchronized frame clock and bit clock for decoding, and the output data bit error rate is reduced. The data reliability at this stage is high.

[0046] 7. Figure 7 This is a schematic diagram of the secondary buffer memory of the present invention. FIFO1 and FIFO2 are used to form a first-level data buffer structure in this structure, which is used to initially reduce the data length of multi-channel data. During the conversion process, FIFO1 and FIFO2 alternately write and read data, reducing the frequency of the read clock. FIFO3 constitutes a second-level buffer structure, which is used to further reduce the data length and perform data caching. After being converted into 8-bit data, the multi-channel parallel data is continuously transmitted to the Ethernet communication circuit. After being packaged, the data is transmitted to the host computer of the addressable ultrasonic sensor array detection system using the UDP protocol.

[0047] In this embodiment, the secondary buffer memory configuration parameters are as follows:

[0048] The sampling frequency is F s=20MHz, the number of bits of ADC is 14, that is, a=14, the sampling window time T=70μs in each addressing ultrasonic sensor array transmission and reception cycle, the clock frequency of the Ethernet communication circuit is f t =125MHz According to the data sheet and circuit structure of the analog front-end chip used, the following clock frequency relationship can be obtained. The frequency of the frame clock is the same as the sampling frequency, that is, f F =F s =20MHz, the bit clock frequency is the sampling frequency times, that is, f D =7F s =140MHz, the write clock 1 frequency f1 of FIFO1 and FIFO2 is the same as the frame clock frequency of the data, that is, f1 = F s =20MHz, FIFO3 read clock 2 frequency f4 and Ethernet transmission frequency f t The same is f4=f t =125MHz, the write clock 2 frequency f3 of FIFO3 is the same as the read clock 1 frequency f2 of FIFO1 and FIFO2, that is, f3=f2. The data collected by the integrated receiving circuit at the output end of the sensor is decoded and merged into a single data length of l1=8×16=128. The data length after conversion by the first-level buffer memory is l2=16. Using the clock of the Ethernet communication circuit can ensure the transmission speed while reducing the clock frequency and saving clock resources. Therefore, the read clock frequency f4 and write clock frequency f3 of FIFO3 are both equal to the Ethernet transmission frequency f t , that is, f3=f4=f t =125MHz, FIFO3 input data length l2 = 16, output data length l3 = 8, FIFO3 read clock 2 frequency f4 and write clock 2 frequency f3 ratio Less than the ratio of the second data bit conversion That is, the data read speed is lower than the data write speed. The depth D of FIFO3 is further calculated. The depth D of FIFO3 needs to satisfy that all the data collected within the sampling time window T = 70μs can enter FIFO3. The depth D of FIFO3 is The minimum storage unit in FIFO3 is 8 bits, and the time t required to complete one ultrasonic signal data transmission is at least That is, t≤140μs is the repetition frequency of the ultrasonic testing system That is, when f<7142Hz, the host computer communication circuit can send all the data within a sampling window time to the host computer of the addressable ultrasonic sensor array detection system.

[0049] 8. Figure 8This is a time-domain waveform of the echo signal drawn based on data received by the host computer during actual measurement using an addressable ultrasonic sensor array detection system. The bottom surface echo of an aluminum specimen with a thickness of h = 36 mm was detected using an addressable ultrasonic sensor array detection system with a detection repetition frequency of f = 1000 Hz. Four addressing rules were set during the test:

[0050] 1) The array elements in the first column are transmitting and receiving, that is, all row signal lines are turned on and the column signal line in the first column is turned on;

[0051] 2) The elements in the 1st and 2nd columns transmit and receive, that is, all row signal lines are turned on, and the 1st and 2nd column signal lines are turned on;

[0052] 3) The array elements in the 1st, 2nd, 3rd, and 4th columns transmit and receive, that is, all row signal lines are turned on, and the signal lines in the 1st, 2nd, 3rd, and 4th columns are turned on;

[0053] 4) Addressing all elements of the ultrasonic sensor array for transmission and reception, that is, all row signal lines are turned on and all column signal lines are turned on;

[0054] All analog front-end channel parameters are set to input impedance Z = 50Ω, gain coefficient G1 = 12dB, G2 = 0dB, G3 = 30dB, G4 = 0dB, total gain G = 42dB, internal reference voltage is selected for A / D conversion, and the third-order LPF cutoff frequency F is set. L =5MHz, the encoding format is LSB and complement. According to the propagation speed of ultrasound in aluminum v = 6300m / s, the propagation time of the first bottom echo can be calculated as There are two features in each figure, namely the initial wave and the first bottom echo. According to the calculated propagation time t r The first bottom wall echo signal can be observed at the corresponding time in each figure. Figure 8 (a) to Figure 8 (d) The peak-to-peak voltage value of the first bottom wall echo signal shows an increasing trend among the figures, and the duration of the first bottom wall echo signal also shows an increasing trend.

[0055] The modular addressable ultrasonic sensor array receiving circuit system of the present invention has the following characteristics:

[0056] (1) The circuit system is designed with highly integrated front-end analog chips and FPGA to reduce circuit volume and noise interference.

[0057] (2) Using a phase-synchronized clock signal for decoding can reduce the bit error rate when decoding the output signal of the integrated receiving circuit at the sensor output end.

[0058] (3) The host computer communication circuit combines the secondary buffer memory and the high-speed communication interface to ensure the integrity and transmission speed of multi-channel data.

[0059] The description in the examples is only for the specific demonstration of the feasibility of the present invention and is not intended to limit the scope of protection of the present invention. Any equivalent implementation or modification that does not depart from the spirit of the present invention should be included in the scope of protection of the present invention.

Claims

1. A modular addressable ultrasonic sensor array receiving circuit system, characterized in that: The invention comprises an addressing ultrasonic sensor array (101), an addressing rule signal generating and controlling circuit (102), a sensor output end integrated receiving circuit (103), a multi-channel receiving data decoding circuit (104), a host computer communication circuit (105) and a parameter configuration communication circuit (106); the addressing ultrasonic sensor array (101) is respectively connected to the addressing rule signal generating and controlling circuit (102) and the sensor output end integrated receiving circuit (103); the sensor output end integrated receiving circuit (103) is respectively connected to the multi-channel receiving data decoding circuit (104) and the parameter configuration communication circuit (106); the multi-channel receiving data decoding circuit (104) is connected to the host computer communication circuit (105); and the host computer communication circuit (105) is connected to the parameter configuration communication circuit (106) via the host computer of the addressing ultrasonic sensor array detection system; An addressable ultrasonic sensor array (101) is used to transmit and receive ultrasonic signals to achieve ultrasonic detection of a target object; An addressing rule signal generating and controlling circuit (102) is used to control the conduction of row and column signal lines of a 64-element addressed ultrasonic sensor array, so that the elements in the addressed array can be strobed for reception according to the addressing rule; The sensor output end integrated receiving circuit (103) is composed of an integrated 8-channel analog front-end chip and peripheral circuits, and is used to receive the echo signal of the addressing ultrasonic sensor array and perform amplification, filtering and A / D conversion on it to a certain extent; A multi-channel receiving data decoding circuit (104), composed of a clock reconstruction circuit and eight decoding circuits, is used to decode low voltage differential digital (LVD) signals simultaneously output by eight channels of an integrated receiving circuit at the output end of a sensor; The host computer communication circuit (105) is composed of a secondary buffer memory and an Ethernet communication circuit, and is used to quickly store the 8-channel data in the local read-only memory ROM of the FPGA, or send it to the host computer via Ethernet; The parameter configuration communication circuit (106) is used to send the addressing rule to the addressing rule signal generating circuit and control the channel parameters of the integrated receiving circuit (103) at the sensor output end. These parameters include: input impedance, gain coefficient, DC offset correction, cutoff frequency and encoding format.

2. The system according to claim 1, wherein: The addressable ultrasonic sensor array (101) adopts a collinear connection mode of rows and columns. The upper surface electrodes in the same row of the array are connected together and have an output electrode lead connected to an external circuit; the lower surface electrodes in the same column of the array are connected together and have an output electrode lead connected to an external circuit; the array of 64 array elements has a total of 8 row electrode leads and 8 column electrode leads, which can be used for gating and cutoff control of array elements in the array; the array elements are numbered as (i, j), wherein i is the array row number, i=1, 2, ..., M, M is the total number of array rows, j is the array column number, j=1, 2, ..., N, N is the total number of array columns; when it is necessary to excite and receive a single array element signal, the control rule will gating the i row and j column, and cut off the others; when it is necessary to gating multiple array elements, the rows and columns corresponding to the multiple array elements are respectively gating.

3. The system according to claim 1, wherein: The addressing rule signal generation and control circuit (102) comprises a row gating circuit, a column gating circuit and an addressing rule signal generation circuit. The addressing rule is to encode the rows and columns to be gated to form an addressing rule, and the row and column gating circuits are used to control the gating and cutoff of the gating array elements. The control signal generated by the control circuit is used to convert the addressing rule sent by the parameter configuration communication circuit into a high and low level switch sequence signal for controlling the row gating circuit and the column gating circuit. The output of the row and column gating control circuit is connected to the common line electrode of the addressing ultrasonic sensor array, and a MOS (metal-oxide semiconductor field effect transistor) type electronic switch is connected in series between the common line electrode and the control gating circuit. When the electronic switch is turned on, the row or column where the array element is located is gated, and when the electronic switch is turned off, the corresponding row or column array element is turned off.

4. The system according to claim 1, wherein: The sensor output end integrated receiving circuit (103) is composed of an integrated 8-channel analog front-end chip and peripheral circuits. The array elements in the addressable ultrasonic sensor array have the functions of transmitting and receiving positive and negative piezoelectric effects. There is an excitation and receiving circuit connection channel. A limiting circuit composed of two reverse parallel diodes prevents the high voltage of the excitation electric pulse from breaking down the subsequent circuit. The front-end analog channel of the sensor output end integrated receiving circuit (103) is composed of a low-noise preamplifier LNA, a voltage-controlled attenuator VCAT, a programmable amplifier PGA, an anti-aliasing filter LPF and a high-speed analog-to-digital converter ADC. The analog signal received by the addressable ultrasonic sensor array is converted into an LVD signal after passing through the analog front-end channel. The sensor output end integrated receiving circuit (103) simultaneously outputs a frame clock signal and a bit clock signal for subsequent decoding of the LVD signal.

5. The system according to claim 1, wherein: The multi-channel receiving data decoding circuit (104) is composed of a decoding circuit and a clock reconstruction circuit, wherein the decoding circuit and the clock reconstruction circuit are composed of an IP core circuit and a logic operation circuit inside an FPGA; the multi-channel receiving data decoding circuit realizes bit clock phase synchronous reconstruction and accurate decoding of LVD signals, and can reduce the bit error rate of multi-channel parallel data.

6. The system according to claim 1, wherein: The host computer communication circuit (105) is composed of a secondary buffer memory and an Ethernet communication circuit. The secondary buffer memory can buffer all data within a sampling window time and reduce the data length, which facilitates the Ethernet communication circuit to transmit data. The Ethernet communication circuit can transmit data to the system host computer at high speed.

7. The system according to claim 1, wherein: The parameter configuration communication circuit (106) uses a serial peripheral interface SPI bus to configure parameters of an addressing rule signal generating circuit and a sensor output end integrated receiving circuit, controls the generation of addressing rule signals, controls the circuit to execute addressing rules, and controls input impedance, gain coefficient, and encoding format parameters of each channel of the sensor output end integrated receiving circuit.

8. The system according to claim 5, wherein: The multi-channel receiving data decoding circuit (104) uses a decoder, a data input buffer and a delay device in an IP core of an FPGA to establish a clock reconstruction circuit. The differential frame clock signal and the bit clock signal are converted into single-ended signals after passing through the data input buffer and then decoded into digital signals by the decoder. The clock alignment state machine compares the digital signals of the two and outputs a phase alignment signal according to the phase difference of the signals. The delay device readjusts the phase of the single-ended bit clock signal according to the phase alignment signal and outputs a reconstructed bit clock signal. The reconstructed bit clock signal is decoded into a digital signal by the decoder. The clock alignment state machine performs phase difference detection again and outputs a phase alignment signal. The clock reconstruction circuit repeats this process until the phase of the reconstructed bit clock signal is completely aligned with the phase of the single-ended frame clock signal. The decoding circuit uses the phase-synchronized frame clock and bit clock for decoding, so that the bit error rate of the output data is reduced.

9. The system according to claim 6, wherein: The host computer communication circuit (105) realizes buffer storage of multi-channel data through a designed secondary buffer memory; the Ethernet communication circuit is used to realize high-speed data transmission; three first-in-first-out memories (FIFOs) are used to construct a secondary buffer memory suitable for multi-channel large data volumes, wherein FIFO1 and FIFO2 are used to form a first-level data buffer structure for initially reducing the data length of the multi-channel data; during the conversion process, FIFO1 and FIFO2 alternately write and read data, which can reduce the clock frequency; FIFO3 constitutes a second-level buffer structure for further reducing the data length and performing data caching.

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