Multi-layer flexible board FA impedance board measurement method

Abstract

The invention relates to the technical field of circuit board impedance measurement, and provides a multilayer soft board FA impedance board measurement method, which comprises the following steps: S1, cutting and drilling a base material; s3, target drilling and laser windowing: 1) drilling positioning target holes in four corners of a laminated plate by using an X-ray target drilling machine, and windowing; and S4, impedance testing: carrying out impedance measurement on the exposed FA impedance line by using a time domain reflectometer. According to the technical scheme, the problems that in the existing FPC industry, due to the fact that a dielectric layer of a multi-layer soft board is complex, glue layers and PI layers are stacked repeatedly, and an impedance analog value is often greatly different from an actual value, in general, an impedance FA batch needs to be tried to be made before a formal batch of products is made, and whether the impedance is qualified or not needs to be verified are solved; the problem that the delivery cycle of a formal product is seriously influenced due to the fact that impedance measurement can only be carried out after an outer layer etching circuit is manufactured due to the fact that an impedance product is contained in the inner layer of the multi-layer soft board is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit board impedance measurement, and in particular to a method for measuring the impedance of a multi-layer flexible circuit board (FA). Background Art

[0002] Multilayer soft board FA impedance board is a high-end circuit board that combines multilayer flexible circuit, impedance control and fault analysis technology. It is mainly used in high-frequency signal transmission or high reliability scenarios.

[0003] A search revealed a circuit board impedance measurement method and a circuit board with authorization announcement number CN105338728B. This solution does not increase production costs and can understand the impedance status of the inner layer of the circuit board during production in advance without the need for final pressing and forming. If production impedance anomalies occur, production parameters can be adjusted and processes improved for subsequent production batches in a timely manner, preventing batch scrapping and reducing production quality risks.

[0004] However, in the current FPC industry, multi-layer flexible boards have complex dielectric layers, and usually have repeated stacking of glue layers and PI layers. The impedance simulation values often differ greatly from the actual values. Therefore, in general, before making formal batches of products, it is necessary to first try out an impedance FA batch to verify whether the impedance is qualified. Because the inner layer of the multi-layer flexible board contains impedance products, the impedance measurement must be carried out after the outer layer etching circuit is completed. The required process and time are long, which will seriously affect the formal product delivery cycle. For this reason, we propose a multi-layer flexible board FA impedance board measurement method. Summary of the Invention

[0005] The present invention proposes a method for measuring the impedance of a multi-layer flexible circuit board (FA), which solves the problem mentioned in the background technology that in the existing FPC industry, due to the complexity of the dielectric layer of the multi-layer flexible circuit board, the glue layer and the PI layer are usually stacked repeatedly, and the impedance simulation value often differs greatly from the actual value. Therefore, under normal circumstances, before making a formal batch of products, it is necessary to first try out an impedance FA batch to verify whether the impedance is qualified; because the inner layer of the multi-layer flexible circuit board contains impedance products, the impedance measurement must be carried out after the outer layer etching circuit is completed. The required process and time are long, which will seriously affect the delivery cycle of the formal product.

[0006] The technical solutions of the present invention are as follows:

[0007] A method for measuring a multi-layer flexible FA impedance board comprises the following steps:

[0008] S1. Cutting and drilling the substrate: Cutting the double-sided FPC substrate into a preset size. The double-sided FPC substrate includes a polyimide layer and rolled copper layers on its upper and lower surfaces, and the upper and lower copper layers are pre-etched with inner layer impedance lines. Then, a mechanical drilling process is used to form through holes on the double-sided FPC substrate.

[0009] S2. Substrate lamination and lamination:

[0010] 1) AD adhesive layer and electrolytic copper foil are stacked on the upper surface of the double-sided FPC substrate in sequence to form a stacked structure from bottom to top. The stacked structure is double-sided FPC substrate, AD adhesive layer, and electrolytic copper foil in sequence from bottom to top;

[0011] 2) Place the composite material in a vacuum pressing machine dedicated to FPC circuit boards and press for 60 to 90 minutes at a temperature of 180 to 200°C and a pressure of 20 to 25 MPa to allow the AD adhesive layer to fully cure and bond to the double-sided FPC substrate and electrolytic copper foil;

[0012] S3, target drilling, laser window opening:

[0013] 1) Use an X-ray drilling target machine to drill positioning target holes at the four corners of the laminated plate, and control the alignment deviation between the target hole and the inner layer impedance line to ≤20μm;

[0014] 2) Adjust the laser parameters according to the total thickness of the dielectric layer. Specifically, remove the copper layer and dielectric layer on the surface of the FPC impedance line test point by laser until the impedance line test point on the double-sided FPC substrate surface is exposed;

[0015] S4. Impedance test:

[0016] Use a time domain reflectometer to measure the impedance of the exposed FA impedance line. If the measured impedance value exceeds the target value by ±5%, adjust the line width compensation amount of the official batch according to the following formula:

[0017]

[0018] Among them, K is the material impedance sensitivity coefficient, and K=2.5Ω / μm, ΔW is the line width compensation amount, and finally the line width control range of the official batch is corrected to the design value ±3%.

[0019] As a further technical solution of the present invention, the total thickness of the dielectric layer = the thickness of the AD adhesive layer + the thickness of the double-sided FPC polyimide layer.

[0020] As a further technical solution of the present invention, the thickness of the substrate is 25±2μm, the thickness of the copper foil is 12±1μm, the thickness of the AD glue is 50±5μm, the width of the inner layer impedance line is 0.08±0.01mm, and the spacing is 0.1±0.02mm.

[0021] As a further technical solution of the present invention, the laser parameters include:

[0022] When the total thickness of the dielectric layer is 75 μm, the laser energy density is set to 4.0 ± 0.5 J / cm 2 , the pulse frequency is 10kHz, and the number of pulses is 3 times;

[0023] For every 25μm increase in the total thickness of the dielectric layer, the laser energy density increases by 0.5J / cm 2 , the number of pulses increases by 1, and the laser is stopped immediately after the impedance line test point on the surface of the double-sided FPC substrate is exposed.

[0024] As a further technical solution of the present invention, the through hole diameter on the double-sided FPC substrate is 0.2±0.05 mm, the hole wall copper thickness is ≥15 μm, and the hole position accuracy error is ≤30 μm.

[0025] As a further technical solution of the present invention, during laser lithography, the laser-lithography opening is a chamfered structure, and the chamfer angle is between 30° and 45°.

[0026] As a further technical solution of the present invention, the AD glue is acrylic glue.

[0027] The working principle and beneficial effects of the present invention are:

[0028] In the present invention, the AD adhesive layer and the laser parameters are coordinated to achieve precise removal of the dielectric layer with minimal error. The laser window opening process replaces the original "two-drilling → copper plating → outer layer circuit" process, which can reduce the average processing time by more than 35%. On the basis of ensuring the production cycle, the target hole-impedance line direct alignment system eliminates the cumulative error in the traditional process; at the same time, a compensation mechanism is established to improve the reliability of the test point contact, which brings good processing results on the basis of reducing the processing steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] Figure 1 Flowchart of the process of the present invention and the process of the prior art;

[0031] Figure 2 This is a four-step flow chart of the impedance measurement process method of the present invention. DETAILED DESCRIPTION

[0032] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0033] Example 1

[0034] like Figures 1 and 2 As shown, the S1 substrate cutting and drilling parameters are as follows:

[0035] A 25μm thick double-sided FPC substrate was selected, specifically a 23μm polyimide layer and 1μm upper and lower rolled copper layers; the pre-etched inner layer impedance line width was controlled to 0.08mm and the spacing was controlled to 0.1mm; mechanical drilling was used to form a through hole with a diameter of 0.2mm and a hole wall copper thickness of 15μm.

[0036] The following parameters are used in S2 substrate lamination and pressing:

[0037] 50μm thick AD glue and 12μm electrolytic copper foil were laminated; during the pressing process, the temperature was controlled at 190℃, the pressure was 22MPa, and the time was controlled at 75min.

[0038] The following parameters are used in S3 target drilling and laser window opening:

[0039] Total dielectric layer thickness = 50 μm AD glue + 23 μm × 2 double-sided polyimide = 96 μm; Laser parameters: Energy density is 4.5 J / cm 2 The pulse frequency is 10kHz, and the actual pulse number is 4 times to expose the impedance line test point; the window chamfer angle is 35°, and the alignment deviation is controlled to ≤15μm.

[0040] In the S4 impedance test, the following tests are performed directly:

[0041] The time domain reflectometer test showed an impedance value of 48.6Ω, a target value of 50Ω, a compensation line width of +0.56μm, and an impedance deviation rate of -2.8%.

[0042] Example 2

[0043] like Figures 1 and 2 As shown, the S1 substrate cutting and drilling parameters are as follows:

[0044] A 27μm thick double-sided FPC substrate is selected, specifically 25μm polyimide and 1μm upper and lower rolled copper layers; the pre-etched impedance line width is controlled to 0.09mm, the spacing is controlled to 0.12mm; the drilling aperture is 0.18mm.

[0045] The following parameters are used in S2 substrate lamination and pressing:

[0046] A combination of 55 μm thick AD glue and 10 μm electrolytic copper foil was used; the pressing conditions were set at a temperature of 200°C, a pressure of 25 MPa, and a time of 60 min.

[0047] The following parameters are used in S3 target drilling and laser window opening:

[0048] Total dielectric layer thickness = 55 μm AD glue + 25 μm × 2 double-sided polyimide = 105 μm; laser parameters: energy density 5.0 J / cm2 After 5 pulses, the impedance line test point is exposed; the window chamfer angle is 42°, and stepped laser removal is used.

[0049] In the S4 impedance test, the following tests are performed directly:

[0050] The measured impedance value is 51.3Ω (target 50Ω), the compensation line width is 0.52, and the impedance deviation rate is 2.6%.

[0051] Example 3

[0052] like Figures 1 and 2 As shown, the S1 substrate cutting and drilling parameters are as follows:

[0053] A double-sided FPC substrate is selected with an overall thickness of 23μm, specifically 20μm polyimide and 1.5μm double-sided copper layer; the inner layer impedance line width is 0.07mm and the spacing is 0.08mm; the diameter of the drilled micro-through hole is 0.15mm, and the copper thickness of the hole wall is 18μm.

[0054] The following parameters are used in S2 substrate lamination and pressing:

[0055] A combination of 45 μm thick AD glue and 15 μm copper foil was used; the pressing method was controlled as follows: temperature 180°C, pressure 20 MPa, and time 90 min.

[0056] The following parameters are used in S3 target drilling and laser window opening:

[0057] Total dielectric layer thickness = 45 μm AD glue + 20 μm × 2 double-sided polyimide = 85 μm; Laser parameters: Energy density 4.5 J / cm 2 After 4 pulses, the impedance line test point is exposed; the window chamfer angle is 30°, and a circular scanning path is adopted.

[0058] S4 step:

[0059] Example 3 was implemented in 10 groups, and the average value of the test data was taken;

[0060] The impedance fluctuation range of Example 1 is: ±2.1%; the contact resistance of the test points is reduced by an average of 40.5%.

[0061] The average processing time for Examples 1-3 was 4.2 hours.

[0062] Comparative Example 1

[0063] The comparative example adopts the following construction process: substrate cutting → drilling → composite pressing → drilling target → secondary drilling → chemical copper plating (5μm) → pattern transfer → etching → impedance testing;

[0064] The average processing time in the comparative example was 6.5 hours;

[0065] Except for the above contents, the remaining variables are controlled to be the same as in Example 1.

[0066] After comparing the data in the present invention application with the solution in the prior art comparative example 1, the following table can be obtained:

[0067] Comparison Project Example Comparative Example Improved performance Process steps 7 items 9 items Reduce 22.2% of processes Impedance detection method In-situ non-destructive testing Destructive testing Reduce material consumption by 100% Line width control accuracy ±3％ ±8％ The accuracy is effectively improved by about 2.7 times Dielectric layer processing Laser precision processing Chemical etching Accuracy increased by 5 times Impedance compensation response Real-time closed-loop processing Next batch adjustment Shorten the batch cycle Processing time 4.2 hours 6.5 hours Processing time reduced by more than 35%

[0068] In summary, in the present application, the dielectric layer is accurately removed with minimal error through the coordinated control of the AD adhesive layer and the laser parameters, and the laser window opening process replaces the original "two drilling → copper plating → outer layer circuit" process, which can reduce the average processing time by more than 35%. On the basis of ensuring the production cycle, the target hole-impedance line direct alignment system eliminates the cumulative error in the traditional process; at the same time, an implementation compensation mechanism is established to improve the reliability of the test point contact, which brings good processing results on the basis of reducing the processing steps.

[0069] It can effectively reduce the processing time in impedance measurement, avoid the existing processing time being extended due to the subsequent testing after etching, and through the adjustment of process technology, products with unqualified impedance can be detected in advance and can be eliminated in advance, which can bring better usage prospects in the multi-layer flexible board production scenario.

[0070] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for measuring the impedance of a multi-layer soft board FA board, characterized in that: The measurement method includes the following steps: S1. Cutting and drilling the substrate: Cutting the double-sided FPC substrate into a preset size. The double-sided FPC substrate includes a polyimide layer and rolled copper layers on its upper and lower surfaces, and the upper and lower copper layers are pre-etched with inner layer impedance lines. Then, a mechanical drilling process is used to form through holes on the double-sided FPC substrate. S2. Substrate lamination and lamination: 1) AD adhesive layer and electrolytic copper foil are stacked on the upper surface of the double-sided FPC substrate in sequence to form a stacked structure from bottom to top. The stacked structure is double-sided FPC substrate, AD adhesive layer, and electrolytic copper foil in sequence from bottom to top; 2) Place the composite material in a vacuum pressing machine dedicated to FPC circuit boards and press for 60 to 90 minutes at a temperature of 180 to 200°C and a pressure of 20 to 25 MPa to allow the AD adhesive layer to fully cure and bond to the double-sided FPC substrate and electrolytic copper foil; S3, target drilling, laser window opening: 1) Use an X-ray drilling target machine to drill positioning target holes at the four corners of the laminated plate, and control the alignment deviation between the target hole and the inner layer impedance line to ≤20μm; 2) Adjust the laser parameters according to the total thickness of the dielectric layer. Specifically, remove the copper layer and dielectric layer on the surface of the FPC impedance line test point by laser until the impedance line test point on the double-sided FPC substrate surface is exposed; S4. Impedance test: Use a time domain reflectometer to measure the impedance of the exposed FA impedance line. If the measured impedance value exceeds the target value by ±5%, adjust the line width compensation amount of the official batch according to the following formula: Among them, K is the material impedance sensitivity coefficient, and K=2.5Ω / μm, ΔW is the line width compensation amount, and finally the line width control range of the official batch is corrected to the design value ±3%.

2. The multi-layer soft board FA impedance board measurement method according to claim 1, characterized in that: The total thickness of the dielectric layer = AD adhesive layer thickness + double-sided FPC polyimide layer thickness.

3. The multi-layer soft board FA impedance board measurement method according to claim 1, characterized in that: The thickness of the substrate is 25±2 μm, the thickness of the copper foil is 12±1 μm, the thickness of the AD glue is 50±5 μm, the width of the inner layer impedance line is 0.08±0.01 mm, and the spacing is 0.1±0.02 mm.

4. The method for measuring the FA impedance of a multi-layer flexible board according to claim 3, characterized in that: Laser parameters: When the total thickness of the dielectric layer is 75 μm, the laser energy density is set to 4.0 ± 0.5 J / cm 2 , the pulse frequency is 10kHz, and the number of pulses is 3 times; For every 25μm increase in the total thickness of the dielectric layer, the laser energy density increases by 0.5J / cm 2 , the number of pulses increases by 1, and the laser is stopped immediately after the impedance line test point on the surface of the double-sided FPC substrate is exposed.

5. The method for measuring the FA impedance board of a multi-layer flexible board according to claim 1, characterized in that: The through hole diameter on the double-sided FPC substrate is 0.2±0.05mm, the hole wall copper thickness is ≥15μm, and the hole position accuracy error is ≤30μm.

6. The method for measuring the FA impedance board of a multi-layer flexible board according to claim 4, characterized in that: In laser cutting, the opening produced by the laser is a chamfered structure with a chamfer angle between 30° and 45°.

7. The method for measuring the FA impedance board of a multi-layer flexible board according to claim 1, characterized in that: The AD glue is acrylic glue.

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