An IC carrier board testing method and system

Abstract

The application discloses an IC carrier board testing method and system, mainly relates to the technical field of IC carrier board, to solve the problem of single detection dimension, insufficient positioning accuracy and low test efficiency of the existing scheme. Including: screening out test points with contact resistance value exceeding threshold value or not conducting as detection objects; using TDR time domain reflectometer to perform impedance test under 1GHz frequency band, identifying impedance abnormal area; monitoring the temperature distribution of the IC carrier board, obtaining monitoring temperature points exceeding the preset temperature; determining the monitoring temperature points coinciding with the detection objects or the impedance abnormal area as the abnormal heat conduction points between the multilayer circuits, recording the temperature gradient data of the abnormal heat conduction points; using a preset torque to perform a preset micro stress loading on the IC carrier board; comparing the resistance value change rate of the IC carrier board before and after stress application, and determining the defect type of the carrier board according to the specific preset defect interval where the resistance value change rate falls.

Description

Technical Field

[0001] This application relates to the field of IC substrate technology, and in particular to an IC substrate testing method and system. Background Technology

[0002] Current IC substrate electrical performance testing technologies mainly involve: manually or semi-automatically probing the substrate pads point-by-point, using a multimeter to measure the line resistance to identify open or short circuit defects. In the impedance testing stage, a vector network analyzer (VNA) is used to collect S-parameters (such as S11 and S21), and frequency domain analysis is used to evaluate the transmission line characteristic impedance matching and signal attenuation.

[0003] However, existing technologies have the following drawbacks: First, they have a single detection dimension, which can only reflect static electrical performance and cannot identify thermo-mechanical coupling defects under dynamic operating conditions (such as abnormal temperature rise caused by microcracks); second, their positioning accuracy is insufficient, and traditional VNA testing cannot associate impedance anomalies with specific physical defects (such as interlayer micro-short circuits); third, their testing efficiency is low, with manual intervention accounting for more than 60% of the process, and they lack an intelligent mechanism for determining defect types. Summary of the Invention

[0004] This application provides an IC carrier board testing method and system to solve the problems of existing solutions having a single testing dimension, insufficient positioning accuracy, and low testing efficiency.

[0005] Firstly, this application provides a method for testing an IC carrier board, the method comprising:

[0006] Conduct continuity tests on all pads on the IC substrate, record the contact resistance value of each test point, and screen out test points with contact resistance values ​​exceeding the threshold or not conducting as test objects;

[0007] Based on the node coordinates of the object being tested, an impedance test is performed in the 1GHz band using a time-domain reflectometer (TDR) to identify areas of impedance anomaly. These areas of impedance anomaly are line segments with pre-defined micro-short circuits or pre-defined open circuit defects.

[0008] For areas with abnormal impedance, a preset constant current load is applied, and the temperature distribution of the IC substrate is monitored to obtain the monitoring temperature points that exceed the preset temperature.

[0009] Determine whether the monitoring temperature point coincides with the object being tested or the area of ​​impedance abnormality; determine whether the monitoring temperature point that coincides with the object being tested or the area of ​​impedance abnormality is the heat conduction abnormality point between the multi-layer circuit, and record the temperature gradient data of the heat conduction abnormality point;

[0010] When the temperature gradient data falls into the preset abnormal range, a preset micro-stress is applied to the IC carrier board using a preset torque; the rate of change of resistance value of the IC carrier board before and after stress application is compared, and the type of defect existing in the carrier board is determined based on the specific preset defect range into which the rate of change of resistance value falls.

[0011] In one implementation of this application, continuity testing is performed on all pads on the IC substrate, the contact resistance value of each test point is recorded, and test points with contact resistance values ​​exceeding a threshold or not conducting are selected as test targets. Specifically, this includes:

[0012] Connect the IC substrate test points using a four-wire resistance tester;

[0013] Set the test parameters; the test parameters should include at least the test current and the sampling rate.

[0014] All pads were traversed using a grid scanning method, and the contact resistance value of each test point was recorded.

[0015] Test points that exceed the threshold or are not conductive are marked as detection targets.

[0016] In one implementation of this application, impedance testing is performed using a TDR (Time Domain Reflectometer) in the 1GHz band based on the node coordinates of the object being tested to identify regions of impedance anomalies. Specifically, this includes:

[0017] Connect the IC carrier board using a TDR (Time Domain Reflectometer);

[0018] Configured with a 1GHz test frequency band, rise time ≤35ps;

[0019] An automatic calibration procedure is used to eliminate the influence of test cables;

[0020] Identify areas of impedance anomalies using preset waveform analysis software.

[0021] In one implementation of this application, a preset constant current load is applied to the impedance abnormality region, and the temperature distribution of the IC substrate is monitored to obtain a monitoring temperature point exceeding a preset temperature. Specifically, this includes:

[0022] Build the constant current source circuit corresponding to the IC carrier board;

[0023] Determine the specific test current corresponding to the preset constant current load based on the IC carrier board specifications;

[0024] Use an infrared thermal imager to monitor the IC substrate;

[0025] Set the temperature threshold to a preset temperature and obtain the monitoring temperature points on the IC carrier board that exceed the preset temperature.

[0026] In one implementation of this application, before applying a preset micro-stress load to the IC carrier board using a preset torque when the temperature gradient data falls into a preset abnormal range; and before determining the type of defect in the carrier board by comparing the rate of change of resistance value of the IC carrier board before and after stress application and based on the specific preset defect range into which the rate of change of resistance value falls, the method further includes:

[0027] The preset interface allows you to obtain the correspondence between preset abnormal ranges, specific preset defect ranges, and defect types.

[0028] In one implementation of this application, a preset torque is used to apply a preset micro-stress to the IC carrier board; the rate of change of resistance value of the IC carrier board before and after stress application is compared, and the type of defect existing in the carrier board is determined based on the specific preset defect range into which the rate of change of resistance value falls, specifically including:

[0029] A six-axis micro-force loading stage with a torque range of 0-5 N·m is used.

[0030] Apply a torque of 0.8 N·m at the point of abnormal heat conduction and hold for 30 s;

[0031] Use a multimeter to measure the resistance of the IC carrier board three times before and three times after stress loading;

[0032] When the rate of change is less than the first preset percentage, it is determined to be a cold solder joint.

[0033] When the first preset percentage ≤ the rate of change ≤ the second preset percentage, it is determined to be a microcrack;

[0034] When the rate of change is greater than the second preset percentage, it is determined to be a layered defect.

[0035] Secondly, this application provides an IC carrier board testing system, the system comprising:

[0036] The continuity testing module is used to perform continuity testing on all pads of the IC carrier board, record the contact resistance value of each test point, and screen out test points with contact resistance values ​​exceeding the threshold or not conducting as test objects.

[0037] The identification module is used to identify impedance anomaly areas by performing impedance testing in the 1GHz band using a TDR time domain reflectometer based on the node coordinates of the detection object; wherein the impedance anomaly area is a line segment with a preset micro short circuit or preset open circuit defect.

[0038] The module is used to apply a preset constant current load to the impedance abnormal area, monitor the temperature distribution of the IC carrier board, and obtain the monitoring temperature point that exceeds the preset temperature.

[0039] The heat transfer module is used to determine whether the monitoring temperature point coincides with the detection object or the impedance abnormal area; it determines that the monitoring temperature point that coincides with the detection object or the impedance abnormal area is the heat conduction abnormal point between the multi-layer circuits, and records the temperature gradient data of the heat conduction abnormal point.

[0040] The determination module is used to apply a preset micro-stress to the IC carrier board using a preset torque when the temperature gradient data falls into a preset abnormal range; compare the rate of change of the resistance value of the IC carrier board before and after the stress is applied, and determine the type of defect existing in the carrier board based on the specific preset defect range into which the rate of change of the resistance value falls.

[0041] In one implementation of this application, the continuity detection module includes a continuity detection unit.

[0042] Used for connecting IC carrier board test points using a four-wire resistance tester;

[0043] Set the test parameters; the test parameters should include at least the test current and the sampling rate.

[0044] All pads were traversed using a grid scanning method, and the contact resistance value of each test point was recorded.

[0045] Test points that exceed the threshold or are not conductive are marked as detection targets.

[0046] In one implementation of this application, the heat transfer module includes an anomaly detection unit.

[0047] Used for connecting IC carrier boards using a TDR (Time Domain Reflectometer);

[0048] Configured with a 1GHz test frequency band, rise time ≤35ps;

[0049] An automatic calibration procedure is used to eliminate the influence of test cables;

[0050] Identify areas of impedance anomalies using preset waveform analysis software.

[0051] In one implementation of this application, the determining module includes a determining unit.

[0052] For use with a six-axis micro-force loading stage, torque range 0-5 N·m;

[0053] Apply a torque of 0.8 N·m at the point of abnormal heat conduction and hold for 30 s;

[0054] Use a multimeter to measure the resistance of the IC carrier board three times before and three times after stress loading;

[0055] When the rate of change is less than the first preset percentage, it is determined to be a cold solder joint.

[0056] When the first preset percentage ≤ the rate of change ≤ the second preset percentage, it is determined to be a microcrack;

[0057] When the rate of change is greater than the second preset percentage, it is determined to be a layered defect.

[0058] As can be seen from the above technical solutions, this application has the following advantages:

[0059] By introducing temperature distribution monitoring and micro-stress loading testing under constant current load, dynamic capture of thermo-mechanical coupling defects was achieved. This method can simultaneously detect abnormal temperature rises and resistance changes caused by defects such as microcracks and interlayer delamination, breaking through the limitations of traditional static electrical testing and improving the detection rate of hidden defects.

[0060] By combining impedance testing and temperature gradient data location using a time-domain reflectometry (TDR), a three-dimensional correlation model was established between the impedance anomaly region, the detected object, and the heat conduction anomaly point. Through a coordinate coincidence determination mechanism, the specific circuit layer and physical location of the defect can be pinpointed, improving the accuracy of defect location.

[0061] The system employs an automated, sequential inspection process, eliminating manual intervention. Through a pre-defined defect range determination mechanism, the system can autonomously complete the entire process analysis from anomaly detection to type determination, reducing single-board testing time and avoiding the risk of human error. Attached Figure Description

[0062] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0063] Figure 1 This is a flowchart of an IC carrier board testing method provided in an embodiment of this application.

[0064] Figure 2 This is a schematic diagram of the internal structure of an IC carrier board testing system provided in an embodiment of this application. Detailed Implementation

[0065] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0066] Those skilled in the art should understand that the embodiments described below are merely preferred embodiments of this disclosure and do not imply that this disclosure can only be implemented through these preferred embodiments. These preferred embodiments are merely used to explain the technical principles of this disclosure and are not intended to limit the scope of protection of this disclosure. Based on the preferred embodiments provided by this disclosure, all other embodiments obtained by those skilled in the art without creative effort should still fall within the scope of protection of this disclosure.

[0067] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0068] The technical solutions proposed in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0069] The embodiment provides a method for testing IC carrier boards, such as Figure 1 As shown in the embodiments of this application, the method mainly includes the following steps:

[0070] Step 110: Perform continuity testing on all pads on the IC substrate, record the contact resistance value of each test point, and select test points with contact resistance values ​​exceeding the threshold or not conducting as test targets.

[0071] In some embodiments, this step may specifically be as follows:

[0072] Connect the IC substrate test points using a four-wire resistance tester;

[0073] Set the test parameters; the test parameters should include at least the test current and the sampling rate.

[0074] All pads were traversed using a grid scanning method, and the contact resistance value of each test point was recorded.

[0075] Test points that exceed the threshold or are not conductive are marked as detection targets.

[0076] Understandably, this step achieves the assessment of IC substrate pad quality through a systematic continuity testing process. First, by quantifying contact resistance values ​​(rather than simply determining continuity), potential defects such as oxidation and cold solder joints can be detected early. Second, the threshold screening mechanism can automatically locate pads that need rework, improving repair efficiency. Finally, standardized test parameter settings (such as current intensity and sampling rate) ensure the repeatability of test results.

[0077] Step 120: Based on the node coordinates of the object being tested, use a TDR (Time Domain Reflectometer) to perform impedance testing in the 1GHz band to identify areas of impedance anomaly.

[0078] Among them, the impedance abnormality area is the line section with a preset micro short circuit or preset open circuit defect.

[0079] In some embodiments, this step may specifically be as follows:

[0080] Connect the IC carrier board using a TDR (Time Domain Reflectometer);

[0081] Configured with a 1GHz test frequency band, rise time ≤35ps;

[0082] An automatic calibration procedure is used to eliminate the influence of test cables;

[0083] Identify areas of impedance anomalies using preset waveform analysis software.

[0084] Understandably, this step begins with using a Time Domain Reflectometer (TDR) to perform impedance testing in the 1GHz band, effectively identifying micro-short circuits or open circuits in the circuit. The 1GHz test frequency and ≤35ps rise time configuration ensure sensitive capture of minute impedance changes in the high-frequency signal transmission path, thereby improving the accuracy of defect detection. Secondly, the introduction of an automatic calibration program eliminates the influence of test cables on the measurement results, reduces human error, and makes the test data more reliable and consistent. Furthermore, the automatic identification of impedance anomaly areas through preset waveform analysis software simplifies the data analysis process and improves detection efficiency. Overall, this method, combining hardware configuration and software analysis, achieves efficient and accurate detection of IC substrate circuit defects, providing a reliable basis for subsequent fault location and repair.

[0085] Step 130: Apply a preset constant current load to the impedance abnormal area, monitor the temperature distribution of the IC substrate, and obtain the monitoring temperature point that exceeds the preset temperature.

[0086] In some embodiments, this step may specifically be as follows:

[0087] Build the constant current source circuit corresponding to the IC carrier board;

[0088] Determine the specific test current corresponding to the preset constant current load based on the IC carrier board specifications;

[0089] Use an infrared thermal imager to monitor the IC substrate;

[0090] Set the temperature threshold to a preset temperature and obtain the monitoring temperature points on the IC carrier board that exceed the preset temperature.

[0091] Understandably, this step, by applying a preset constant current load, simulates the current load on the IC substrate under actual operating conditions, thus accurately reflecting the thermal characteristics of areas with abnormal impedance. The introduction of the preset constant current load ensures the controllability and repeatability of the test conditions, resulting in high reliability of the monitoring results. Secondly, using an infrared thermal imager to monitor the temperature distribution of the IC substrate allows for non-contact, high-resolution capture of temperature changes across the entire substrate, avoiding interference that may be introduced by traditional temperature measurement methods. The setting of temperature thresholds enables rapid identification of monitoring points exceeding preset temperatures, providing a clear basis for subsequent fault analysis and repair. Furthermore, this solution combines a constant current source circuit and infrared thermal imaging technology to achieve a comprehensive assessment of the IC substrate's thermal performance, helping to detect potential thermal failure risks early, thereby improving product reliability and lifespan.

[0092] Step 140: Determine whether the monitoring temperature point coincides with the object being tested or the area of ​​impedance abnormality; determine that the monitoring temperature point that coincides with the object being tested or the area of ​​impedance abnormality is the heat conduction abnormal point between the multi-layer circuits, and record the temperature gradient data of the heat conduction abnormal point.

[0093] Understandably, this step, by determining whether the monitored temperature point coincides with the object being tested and the area of ​​impedance anomaly, can locate the heat conduction anomaly point between multi-layer circuits, thereby effectively correlating the temperature monitoring results with the impedance test data and improving the accuracy of fault diagnosis. Secondly, recording the temperature gradient data at the heat conduction anomaly point can quantify the thermal distribution characteristics of that area, providing an objective basis for analyzing the severity and spread of the heat conduction anomaly. Furthermore, this method, by combining impedance anomaly identification and temperature monitoring, achieves cross-dimensional analysis from electrical performance to thermal performance, contributing to a deeper understanding of the impact mechanism of defects on the overall performance of the IC substrate. Overall, through multi-parameter correlation analysis, it provides comprehensive data support for the failure analysis and reliability assessment of the IC substrate, helping to optimize design and improve product quality.

[0094] Step 150: When the temperature gradient data falls into the preset abnormal range, a preset micro-stress is applied to the IC carrier board using a preset torque; the rate of change of resistance value of the IC carrier board before and after stress application is compared, and the type of defect existing in the carrier board is determined according to the specific preset defect range into which the rate of change of resistance value falls.

[0095] Specifically, when the temperature gradient data falls into a preset abnormal range, a preset micro-stress is applied to the IC carrier board using a preset torque. Before determining the type of defect on the carrier board by comparing the rate of change of resistance before and after stress application and based on the specific preset defect range into which the rate of change of resistance falls, the method further includes:

[0096] The preset interface allows you to obtain the correspondence between preset abnormal ranges, specific preset defect ranges, and defect types.

[0097] In some embodiments, this step may specifically be as follows:

[0098] A six-axis micro-force loading stage with a torque range of 0-5 N·m is used.

[0099] Apply a torque of 0.8 N·m at the point of abnormal heat conduction and hold for 30 s;

[0100] Use a multimeter to measure the resistance of the IC carrier board three times before and three times after stress loading;

[0101] When the rate of change is less than the first preset percentage, it is determined to be a cold solder joint.

[0102] When the first preset percentage ≤ the rate of change ≤ the second preset percentage, it is determined to be a microcrack;

[0103] When the rate of change is greater than the second preset percentage, it is determined to be a layered defect.

[0104] Understandably, this step obtains the correspondence between abnormal intervals, defect intervals, and defect types through a preset interface, thus standardizing testing criteria, reducing the subjectivity of human judgment, and improving the accuracy of defect classification. Secondly, using a six-axis micro-force loading stage to apply a torque of 0.8 N·m at the thermal conduction anomaly point and holding it for 30 seconds simulates the micro-stress environment in actual use, effectively stimulating potential defects and making them manifest in resistance changes. Measured resistance three times before and after stress loading using a multimeter ensured data reliability and repeatability. Furthermore, based on the specific preset defect intervals (such as cold solder joints, micro-cracks, and delamination defects) where the resistance change rate falls, the defect type of the IC substrate can be accurately identified, providing a clear basis for subsequent repair and quality control. Overall, by combining temperature gradient monitoring, micro-stress loading, and resistance change analysis, multi-dimensional diagnosis of IC substrate defects is achieved, contributing to improved product reliability and lifespan.

[0105] As described above, this embodiment uses a four-wire resistance tester combined with a grid scanning method to systematically test the continuity of IC substrate pads. This quantifies contact resistance values ​​rather than simply determining continuity. By setting standardized test parameters (such as test current and sampling rate), the repeatability of test results is ensured. A threshold screening mechanism automatically marks pads that exceed the threshold or are not conductive, helping to quickly locate potential defects such as oxidation and cold solder joints, thus improving repair efficiency. This provides an accurate initial data foundation for subsequent defect analysis.

[0106] Impedance testing using a time-domain reflectometer (TDR) in the 1GHz band, combined with an automatic calibration program and pre-set waveform analysis software, can effectively detect micro-short circuits or open circuit defects in lines. High-frequency signal testing (rise time ≤35ps) enhances sensitivity to minute impedance changes, while automatic calibration reduces errors introduced by the test cables. This improves the accuracy of defect location and provides reliable impedance anomaly data for subsequent thermal performance analysis.

[0107] By simulating actual working conditions with a constant current source and monitoring temperature distribution with an infrared thermal imager, the thermal effects of areas with impedance anomalies can be accurately identified. Setting temperature thresholds allows for rapid location of hotspots, and overlapping temperature data with impedance anomaly areas further confirms heat conduction anomalies between multi-layer circuits. Recording temperature gradient data helps quantify thermal distribution characteristics, providing a basis for assessing defect severity. This enables correlation analysis between electrical and thermal performance, improving the comprehensiveness of fault diagnosis.

[0108] By applying micro-stress (e.g., 0.8 N·m torque) to regions with abnormal temperature gradients, and comparing the rate of change in resistance before and after stress loading, combined with preset defect ranges (cold welds, micro-cracks, delamination), the type of carrier plate defect can be accurately identified. A six-axis micro-force loading stage simulates the actual stress environment, stimulating potential defects, while multiple resistance measurements (3 times) ensure data reliability. Standardized defect classification logic reduces subjective judgment errors and provides a clear basis for maintenance decisions.

[0109] Through multi-step collaborative analysis (continuity testing, impedance testing, temperature monitoring, and micro-stress loading), cross-dimensional defect diagnosis is achieved, encompassing electrical, thermal, and mechanical performance. Standardized test parameters, automated analysis processes, and multi-parameter correlation verification enhance the accuracy and reliability of the test results. This method not only locates existing defects but also predicts potential failure risks through thermal conductivity analysis and micro-stress testing, helping to optimize the design and manufacturing processes of IC substrates and thus improve the long-term reliability of products.

[0110] In addition, this application Figure 2 An IC carrier board testing system is provided as an embodiment of this application. For example... Figure 2 As shown in the embodiments of this application, the system mainly includes:

[0111] The continuity detection module 210 is used to perform continuity detection on all pads of the IC carrier board, record the contact resistance value of each test point, and screen out the test points whose contact resistance value exceeds the threshold or are not conductive as the test objects.

[0112] The continuity detection module 210 includes a continuity detection unit.

[0113] Used for connecting IC carrier board test points using a four-wire resistance tester;

[0114] Set the test parameters; the test parameters should include at least the test current and the sampling rate.

[0115] All pads were traversed using a grid scanning method, and the contact resistance value of each test point was recorded.

[0116] Test points that exceed the threshold or are not conductive are marked as detection targets.

[0117] The identification module 220 is used to identify impedance abnormality areas by using a TDR time domain reflectometer to perform impedance testing in the 1GHz frequency band based on the node coordinates of the detection object; wherein the impedance abnormality area is a line segment with a preset micro short circuit or preset open circuit defect.

[0118] The module 230 is used to apply a preset constant current load to the impedance abnormal area, monitor the temperature distribution of the IC carrier board, and obtain the monitoring temperature point that exceeds the preset temperature.

[0119] The heat transfer module 240 is used to determine whether the monitoring temperature point coincides with the detection object or the impedance abnormal area; to determine that the monitoring temperature point that coincides with the detection object or the impedance abnormal area is the heat conduction abnormal point between the multi-layer circuits, and to record the temperature gradient data of the heat conduction abnormal point.

[0120] The heat transfer module 240 includes an anomaly detection unit.

[0121] Used for connecting IC carrier boards using a TDR (Time Domain Reflectometer);

[0122] Configured with a 1GHz test frequency band, rise time ≤35ps;

[0123] An automatic calibration procedure is used to eliminate the influence of test cables;

[0124] Identify areas of impedance anomalies using preset waveform analysis software.

[0125] The determination module 250 is used to apply a preset micro-stress to the IC carrier board using a preset torque when the temperature gradient data falls into a preset abnormal range; compare the rate of change of resistance value of the IC carrier board before and after stress application, and determine the type of defect existing in the carrier board based on the specific preset defect range into which the rate of change of resistance value falls.

[0126] The determining module 250 includes a determining unit.

[0127] For use with a six-axis micro-force loading stage, torque range 0-5 N·m;

[0128] Apply a torque of 0.8 N·m at the point of abnormal heat conduction and hold for 30 s;

[0129] Use a multimeter to measure the resistance of the IC carrier board three times before and three times after stress loading;

[0130] When the rate of change is less than the first preset percentage, it is determined to be a cold solder joint.

[0131] When the first preset percentage ≤ the rate of change ≤ the second preset percentage, it is determined to be a microcrack;

[0132] When the rate of change is greater than the second preset percentage, it is determined to be a layered defect.

[0133] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for testing IC carrier boards, characterized in that, The method includes: Conduct continuity tests on all pads on the IC substrate, record the contact resistance value of each test point, and screen out test points with contact resistance values ​​exceeding the threshold or not conducting as test objects; Based on the node coordinates of the object being tested, an impedance test is performed in the 1GHz band using a time-domain reflectometer (TDR) to identify areas of impedance anomaly. These areas of impedance anomaly are line segments with pre-defined micro-short circuits or pre-defined open circuit defects. For areas with abnormal impedance, a preset constant current load is applied, and the temperature distribution of the IC substrate is monitored to obtain the monitoring temperature points that exceed the preset temperature. Determine whether the monitoring temperature point coincides with the object being tested or the area of ​​impedance abnormality; determine whether the monitoring temperature point that coincides with the object being tested or the area of ​​impedance abnormality is the heat conduction abnormality point between the multi-layer circuit, and record the temperature gradient data of the heat conduction abnormality point; When the temperature gradient data falls into the preset abnormal range, a preset micro-stress is applied to the IC carrier board using a preset torque; the rate of change of resistance value of the IC carrier board before and after stress application is compared, and the type of defect existing in the carrier board is determined based on the specific preset defect range into which the rate of change of resistance value falls.

2. The IC carrier board testing method according to claim 1, characterized in that, Conduct continuity tests on all pads on the IC substrate, record the contact resistance value of each test point, and select test points with contact resistance values ​​exceeding the threshold or no continuity as the test targets. Specifically, this includes: Connect the IC substrate test points using a four-wire resistance tester; Set the test parameters; the test parameters should include at least the test current and the sampling rate. All pads were traversed using a grid scanning method, and the contact resistance value of each test point was recorded. Test points that exceed the threshold or are not conductive are marked as detection targets.

3. The IC carrier board testing method according to claim 1, characterized in that, Based on the node coordinates of the object being tested, impedance testing is performed using a time-domain reflectometer (TDR) in the 1GHz band to identify regions of impedance anomalies, specifically including: Connect the IC carrier board using a TDR (Time Domain Reflectometer); Configured with a 1GHz test frequency band, rise time ≤35ps; An automatic calibration procedure is used to eliminate the influence of test cables; Identify areas of impedance anomalies using preset waveform analysis software.

4. The IC carrier board testing method according to claim 1, characterized in that, For regions with abnormal impedance, a preset constant current load is applied, and the temperature distribution of the IC substrate is monitored to obtain monitoring temperatures exceeding the preset temperature. Specifically, this includes: Build the constant current source circuit corresponding to the IC carrier board; Determine the specific test current corresponding to the preset constant current load based on the IC carrier board specifications; Use an infrared thermal imager to monitor the IC substrate; Set the temperature threshold to a preset temperature and obtain the monitoring temperature points on the IC carrier board that exceed the preset temperature.

5. The IC carrier board testing method according to claim 1, characterized in that, When the temperature gradient data falls into the preset abnormal range, a preset torque is used to apply preset micro-stress to the IC carrier board. Before determining the type of defect on the IC carrier board by comparing the rate of change of resistance before and after stress application and based on the specific preset defect range into which the rate of change of resistance falls, the method further includes: The preset interface allows you to obtain the correspondence between preset abnormal ranges, specific preset defect ranges, and defect types.

6. The IC carrier board testing method according to claim 1, characterized in that, A preset micro-stress load is applied to the IC carrier board using a preset torque. By comparing the rate of change of resistance of the IC substrate before and after stress application, and based on the specific preset defect range into which the rate of change of resistance falls, the type of defect existing in the substrate is determined, including: A six-axis micro-force loading stage with a torque range of 0-5 N·m is used. Apply a torque of 0.8 N·m at the point of abnormal heat conduction and hold for 30 s; Use a multimeter to measure the resistance of the IC carrier board three times before and three times after stress loading; When the rate of change is less than the first preset percentage, it is determined to be a cold solder joint. When the first preset percentage ≤ the rate of change ≤ the second preset percentage, it is determined to be a microcrack; When the rate of change is greater than the second preset percentage, it is determined to be a layered defect.

7. An IC carrier board testing system, characterized in that, The system includes: The continuity testing module is used to perform continuity testing on all pads of the IC carrier board, record the contact resistance value of each test point, and screen out test points with contact resistance values ​​exceeding the threshold or not conducting as test objects. The identification module is used to identify impedance anomaly areas by performing impedance testing in the 1GHz band using a TDR time domain reflectometer based on the node coordinates of the detection object; wherein the impedance anomaly area is a line segment with a preset micro short circuit or preset open circuit defect. The module is used to apply a preset constant current load to the impedance abnormal area, monitor the temperature distribution of the IC carrier board, and obtain the monitoring temperature point that exceeds the preset temperature. The heat transfer module is used to determine whether the monitoring temperature point coincides with the object being tested or the area of ​​impedance abnormality; it determines that the monitoring temperature point that coincides with the object being tested or the area of ​​impedance abnormality is the heat conduction abnormal point between the multi-layer circuits, and records the temperature gradient data of the heat conduction abnormal point. The determination module is used to apply a preset micro-stress to the IC carrier board using a preset torque when the temperature gradient data falls into a preset abnormal range; compare the rate of change of resistance value of the IC carrier board before and after stress application, and determine the type of defect existing in the carrier board based on the specific preset defect range into which the rate of change of resistance value falls.

8. The IC carrier board testing system according to claim 7, characterized in that, The continuity detection module includes a continuity detection unit. Used for connecting IC carrier board test points using a four-wire resistance tester; Set the test parameters; the test parameters should include at least the test current and the sampling rate. All pads were traversed using a grid scanning method, and the contact resistance value of each test point was recorded. Test points that exceed the threshold or are not conductive are marked as detection targets.

9. The IC carrier board testing system according to claim 7, characterized in that, The heat transfer module includes an anomaly detection unit. Used for connecting IC carrier boards using a TDR (Time Domain Reflectometer); Configured with a 1GHz test frequency band, rise time ≤35ps; An automatic calibration procedure is used to eliminate the influence of test cables; Identify areas of impedance anomalies using preset waveform analysis software.

10. The IC carrier board testing system according to claim 7, characterized in that, The determination module includes a determination unit. For use with a six-axis micro-force loading stage, torque range 0-5 N·m; Apply a torque of 0.8 N·m at the point of abnormal heat conduction and hold for 30 s; Use a multimeter to measure the resistance of the IC carrier board three times before and three times after stress loading; When the rate of change is less than the first preset percentage, it is determined to be a cold solder joint. When the first preset percentage ≤ the rate of change ≤ the second preset percentage, it is determined to be a microcrack; When the rate of change is greater than the second preset percentage, it is determined to be a layered defect.

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