Passband flatness optimization method and circuit for on-chip active reconfigurable filter

Abstract

The invention discloses an on-chip active reconfigurable filter passband flatness optimization method and circuit, and belongs to the field of integrated circuits and wireless communication. The filter comprises a coupling element, negative resistance compensation units are connected to the two ends of the coupling element and connected with the coupling element in parallel, and the coupling element comprises a coupling inductor or a coupling capacitor. The invention provides a passband flatness method based on active coupling compensation by deeply analyzing the passband flatness distortion reason of the on-chip coupling filter, and designs a detailed controllable negative resistance unit to compensate the coupling (inductive coupling) loss of the base transformer, thereby greatly reducing the in-band insertion loss variation of the filter, and improving the filter performance. And the amplitude consistency of the signal after passing through the filter is improved.

Description

Technical Field

[0001] The present invention belongs to the field of integrated circuits and wireless communications, and in particular relates to a method and circuit for optimizing the passband flatness of an on-chip active reconfigurable filter. Background Art

[0002] Traditional filters are large and difficult to integrate, making it impossible to integrate filters with other modules in the transceiver system, such as low-noise amplifiers and power amplifiers, on a single chip. An effective way to address this problem is to use advanced semiconductor processes to implement highly integrated reconfigurable filters on the chip, significantly reducing the number of filters while also significantly reducing the filter area. However, due to the limited quality factor of on-chip passive components, existing on-chip coupled reconfigurable filters exhibit large insertion loss fluctuations within the passband, i.e., passband flatness distortion. This filter passband flatness distortion can cause amplitude distortion of the in-band signal, degrading signal integrity. Existing literature lacks research on the issue of passband flatness degradation. Summary of the Invention

[0003] The purpose of this invention is to solve the problem of passband flatness deterioration, and proposes a passband flatness improvement method based on active coupling compensation. By deeply analyzing the filter passband flatness distortion mechanism, an on-chip reconfigurable filter with flat passband response is finally designed to verify the proposed method, which greatly improves the filter passband flatness.

[0004] To solve the above technical problems, the specific technical solutions of the on-chip active reconfigurable filter passband flatness optimization method and circuit of the present invention are as follows:

[0005] A method for optimizing the passband flatness of an on-chip active reconfigurable filter is disclosed. The filter comprises a coupling element, a negative resistance compensation unit is connected at both ends of the coupling element and is connected in parallel with the coupling element, and the coupling element comprises a coupling inductor or a coupling capacitor.

[0006] The negative resistance compensation unit specifically includes a first DC blocking capacitor, a second DC blocking capacitor, a first bias resistor, a second bias resistor, a first NMOS transistor, and a second NMOS transistor; one end of the first DC blocking capacitor and the drain end of the first NMOS transistor are connected to one end of a coupling element, the other end of the first DC blocking capacitor is connected to one end of the second bias resistor and the gate end of the second NMOS transistor; the gate end of the first NMOS transistor is connected to one end of the first bias resistor and one end of the second DC blocking capacitor; the other ends of the first bias resistor and the second bias resistor are connected to a digital control signal Q, and the source ends of the first NMOS transistor and the second NMOS transistor are grounded; the other end of the second DC blocking capacitor and the drain end of the second NMOS transistor are connected to the other end of the coupling element.

[0007] The filter includes two converters, two resonant units, and a coupling element. The first converter is connected to one end of the first resonant unit, the other end of the first resonant unit is connected to one end of the coupling element, the other end of the coupling element is connected to one end of the second resonant unit, and the other end of the second resonant unit is connected to the second converter.

[0008] The present invention also provides an on-chip active reconfigurable filter passband flatness optimization circuit for implementing the above method. The circuit includes two converters, two resonant units, and a coupling element. The first converter is connected to one end of the first resonant unit, the other end of the first resonant unit is connected to one end of the coupling element, the other end of the coupling element is connected to one end of the second resonant unit, and the other end of the second resonant unit is connected to the second converter.

[0009] The coupling element is a coupling inductor or a coupling capacitor;

[0010] Two ends of the coupling element are connected to a negative resistance compensation unit, which is connected in parallel with the coupling element; the negative resistance compensation unit specifically includes a first DC blocking capacitor, a second DC blocking capacitor, a first bias resistor, a second bias resistor, a first NMOS transistor, and a second NMOS transistor; one end of the first DC blocking capacitor and the drain terminal of the first NMOS transistor are connected to one end of the coupling element, the other end of the first DC blocking capacitor is connected to one end of the second bias resistor and the gate terminal of the second NMOS transistor; the gate terminal of the first NMOS transistor is connected to one end of the first bias resistor and one end of the second DC blocking capacitor; the other ends of the first bias resistor and the second bias resistor are connected to a digital control signal Q, and the source terminals of the first NMOS transistor and the second NMOS transistor are grounded; the other end of the second DC blocking capacitor and the drain terminal of the second NMOS transistor are connected to the other end of the coupling element.

[0011] The present invention also provides an on-chip active reconfigurable filter passband flatness optimization circuit. The filter is a second-order reconfigurable filter with a flat passband response, comprising a transformer unit consisting of inductors L1 and L2, a first resonant capacitor unit, a second resonant capacitor unit, a first input coupling capacitor, a second input coupling capacitor, a third input coupling capacitor, a fourth input coupling capacitor, a first inter-stage coupling capacitor, a second inter-stage coupling capacitor, a first source-load coupling capacitor, a second source-load coupling capacitor, and a negative resistance compensation unit. The negative resistance compensation unit comprises a first resonator negative resistance compensation unit, a second resonator negative resistance compensation unit, a first coupling negative resistance compensation unit, and a second coupling negative resistance compensation unit. The specific circuit connection method of the filter is as follows:

[0012] The first port of the transformer is connected to the first resonant capacitor unit, the first input coupling capacitor, the first inter-stage coupling capacitor, the first resonator negative resistance compensation unit, and one end of the first coupled negative resistance compensation unit. The second port of the transformer is connected to the first resonant capacitor unit and the other end of the first resonator negative resistance compensation unit, and is also connected to the second input coupling capacitor, the second inter-stage coupling capacitor, and one end of the second coupled negative resistance compensation unit. The third port of the transformer is connected to the first inter-stage coupling capacitor and the other end of the first coupled negative resistance compensation unit, and is also connected to the second resonant capacitor unit, the second resonator negative resistance compensation unit, and one end of the third input coupling capacitor. The fourth port of the transformer is connected to the second resonant capacitor unit, the second resonator negative resistance compensation unit, the second input coupling capacitor, the second inter-stage coupling capacitor, the other end of the second coupled negative resistance compensation unit, and one end of the fourth input coupling capacitor. The other end of the first input coupling capacitor is connected to one end of the first source load coupling capacitor and is connected to the positive differential input port V in+ , the other end of the second input coupling capacitor is connected to one end of the second source load coupling capacitor and connected to the negative differential input port V in+ , the other end of the third input coupling capacitor is connected to the other end of the first source load coupling capacitor and connected to the positive differential output port V out+ , the other end of the fourth input coupling capacitor is connected to the other end of the second source load coupling capacitor and connected to the negative differential output port V out- The two ends of the inductor L1 in the transformer serve as the first port and the second port of the transformer, and the two ends of the inductor L2 serve as the third port and the fourth port of the transformer;

[0013] The negative resistance compensation unit specifically includes a first DC blocking capacitor, a second DC blocking capacitor, a first bias resistor, a second bias resistor, a first NMOS transistor, and a second NMOS transistor; one end of the first DC blocking capacitor and the drain end of the first NMOS transistor are connected to one end of the corresponding resonant capacitor unit, the other end of the first DC blocking capacitor is connected to one end of the second bias resistor and the gate end of the second NMOS transistor; the gate end of the first NMOS transistor is connected to one end of the first bias resistor and one end of the second DC blocking capacitor; the other ends of the first bias resistor and the second bias resistor are connected to the digital control signal Q, and the source ends of the first NMOS transistor and the second NMOS transistor are grounded; the other end of the second DC blocking capacitor and the drain end of the second NMOS transistor are connected to the other end of the corresponding resonant capacitor unit.

[0014] Furthermore, the resonant capacitor unit includes a first variable capacitor, a second variable capacitor, a first fixed capacitor, a second fixed capacitor, a switch tube M SW , the first resistor, the second resistor; the connection method of the circuit is as follows:

[0015] Variable capacitor control voltage V CRConnect one end of the first variable capacitor and the second variable capacitor, the other end of the first variable capacitor is connected to one end of the first fixed capacitor, the other end of the second variable capacitor is connected to one end of the second fixed capacitor, and the other end of the first fixed capacitor is connected to the switch tube M SW The source terminal of the first resistor and the other end of the second fixed capacitor are connected to the switch tube M SW The drain terminal of the second resistor, the switch tube M SW The gate terminal voltage V SW , the other ends of the first resistor and the second resistor are grounded.

[0016] Furthermore, the two inductors L1 and L2 of the transformer are coil inductors, and the inductors are specifically rectangles with a long diameter of D1 and a short diameter of D2. There is a break in the center of one side of the long diameter of the rectangle facing outward as two connection ports of the inductor; the spacing between L1 and L2 is S1, the line width is W1, and the spacing at the inductor openings is S2; the coupling coefficient between inductor L1 and inductor L2 is determined by D1 and S1.

[0017] Furthermore, the inductor L1 and the first resonant unit constitute the first resonator of the filter, and the inductor L2 and the second resonant unit constitute the second resonator of the filter; L1 and L2 are close to each other to enhance mutual coupling, and the magnetic coupling between L1 and L2 serves as the main coupling between the first resonant unit and the second resonant unit of the filter.

[0018] Furthermore, the interstage coupling capacitor includes two back-to-back variable capacitors; the source-load coupling capacitor includes two back-to-back variable capacitors; the input coupling capacitor includes a fixed capacitor and a variable capacitor connected in series, and the other end of the fixed resistor is connected to the differential port.

[0019] Furthermore, the resonator negative resistance compensation unit includes four parallel negative resistance compensation circuits, and the coupled negative resistance compensation unit includes three parallel negative resistance compensation circuits. The resonator negative resistance compensation unit and the coupled negative resistance compensation unit adopt 4-bit and 3-bit binary digital control respectively, and the size of the cross-coupled transistors in the negative resistance compensation circuit increases in binary.

[0020] The beneficial effects of the present invention are as follows:

[0021] By conducting an in-depth analysis of the causes of passband flatness distortion in on-chip coupled filters, the present invention proposes a passband flatness method based on active coupling compensation, and designs a detailed controllable negative resistance unit to compensate for the base transformer coupling (inductive coupling) loss, thereby significantly reducing the in-band insertion loss variation of the filter and improving the amplitude consistency of the signal after passing through the filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1Schematic diagram of a second-order filter considering coupling loss, where (a) capacitive coupling; (b) inductive coupling;

[0023] Figure 2 The figure shows the amplitude of the transmission coefficient and the transmission loss comparison of the capacitive coupling circuit under different loss resistances.

[0024] Figure 3 The figure shows the amplitude of the transmission coefficient and the transmission loss comparison under different loss resistance of the inductive coupling circuit;

[0025] Figure 4 A second-order filter using coupled negative resistance compensation units. (a) Capacitive coupling; (b) Inductive coupling.

[0026] Figure 5 The amplitude of the filter transmission coefficient and the transmission loss comparison chart after using negative resistance to compensate for the coupling element loss, where (a) is the capacitive coupling case; (b) is the inductive coupling case.

[0027] Figure 6 Schematic diagram of the proposed second-order reconfigurable filter circuit with flat passband response.

[0028] Figure 7 The figure is a specific circuit connection diagram that can be implemented for a second-order reconfigurable filter circuit.

[0029] Figure 8 Detailed circuit for the resonant capacitor.

[0030] Figure 9 Microscope photograph of the designed circuit.

[0031] Figure 10 The figure shows the differential transmission response test of the filter with coupling compensation turned on and off. DETAILED DESCRIPTION

[0032] In order to better understand the purpose, structure and function of the present invention, the following further describes in detail the on-chip active reconfigurable filter passband flatness optimization method and circuit of the present invention in conjunction with the accompanying drawings.

[0033] Firstly, the causes of existing passband flatness distortion are analyzed, such as Figure 1 As shown, Figure 1 (a) and (b) in the figure respectively depict the second-order filter based on capacitive coupling and inductive coupling. In order to eliminate the influence of other factors on the analysis, the external coupling is realized by an ideal J transformer, and the resonators on both sides of the capacitive coupling and inductive coupling are realized by ideal capacitors C R and the ideal inductor L R Implementation; C 12 and L 12 Represent the coupling capacitor and coupling inductor respectively, RC and R L They represent the series losses of the coupling capacitor and the coupling inductor respectively.

[0034] Figure 2 Different R C Under the following conditions (i.e., when the coupling type is capacitive and there is series loss), the transmission coefficient S of the filter is 21 The amplitude and transmission loss P Loss size. Figure 3 Different R L Under the following conditions (i.e., when the coupling type is inductive and there is series loss), the filter's S 21 The amplitude and P Loss Size. From Figure 2 and Figure 3 It can be concluded that when the coupling type is capacitive coupling and coupling loss is present, the loss in the filter's left passband is greater than the loss in the right passband; when the coupling type is inductive coupling and coupling loss is present, the loss in the filter's right passband is greater than the loss in the left passband; and the larger the coupling loss resistance, the more severe the passband distortion and the higher the insertion loss within the passband. The above analysis is based on a second-order filter, and the conclusions obtained are also applicable to higher-order filters. It should be noted that in high-order filters, capacitors and inductors may be used as coupling elements between different resonators. When both capacitive and inductive coupling are present, the loss caused by the coupling resistance will peak both to the left and right of the filter's center frequency. In this case, the passband will exhibit different passband distortion depending on the quality factors of the capacitors and inductors. If the coupling capacitor quality factor is low, the filter's left passband loss will be higher than the right passband; if the coupling inductor loss quality factor is low, the filter's right passband loss will be higher than the left passband.

[0035] In view of the above-mentioned causes of passband flatness distortion, the present invention proposes a passband flatness optimization method based on active negative resistance compensation, such as Figure 4 The general structure of the filter shown includes two converters, two resonators, and a coupling element including a coupling inductor or a coupling capacitor. The first converter is connected to one end of the first resonant unit, the other end of the first resonant unit is connected to one end of the coupling element, the other end of the coupling element is connected to one end of the second resonant unit, and the other end of the second resonant unit is connected to the second converter. The present invention compensates for the loss introduced by the series resistance of the coupling element by introducing a negative resistance compensation unit at both ends of the coupling element.

[0036] Adopt negative resistance compensation unit-R NC (-R NL ) Series loss R of the coupling element C (R L) is used for compensation, where the negative value element introduced by the admittance converter is absorbed into the resonator element. The simulation results of the filter after coupling compensation are shown as follows: Figure 5 As shown in the figure, it can be seen from the simulation results that no matter whether the coupling element is a capacitor or an inductor, the passband flatness of the filter after coupling compensation is close to the response of the ideal filter, which verifies the feasibility of the proposed method.

[0037] In order to verify the proposed passband flatness optimization method, this paper designs a second-order reconfigurable filter with flat passband response. The circuit connection is as follows: Figure 6 As shown, it includes a transformer unit composed of inductors L1 and L2, a first resonant capacitor unit, a second resonant capacitor unit, a first input coupling capacitor, a second input coupling capacitor, a third input coupling capacitor, a fourth input coupling capacitor, a first inter-stage coupling capacitor, a second inter-stage coupling capacitor, a first source-load coupling capacitor, a second source-load coupling capacitor, and a negative resistance compensation unit proposed by the present invention, including a first resonator negative resistance compensation unit, a second resonator negative resistance compensation unit, a first coupling negative resistance compensation unit, and a second coupling negative resistance compensation unit. The specific circuit connection method of the filter is as follows:

[0038] The first port of the transformer is connected to the first resonant capacitor unit, the first input coupling capacitor, the first inter-stage coupling capacitor, the first resonator negative resistance compensation unit, and one end of the first coupled negative resistance compensation unit. The second port of the transformer is connected to the first resonant capacitor unit and the other end of the first resonator negative resistance compensation unit, and is also connected to the second input coupling capacitor, the second inter-stage coupling capacitor, and one end of the second coupled negative resistance compensation unit. The third port of the transformer is connected to the first inter-stage coupling capacitor and the other end of the first coupled negative resistance compensation unit, and is also connected to the second resonant capacitor unit, the second resonator negative resistance compensation unit, and one end of the third input coupling capacitor. The fourth port of the transformer is connected to the second resonant capacitor unit, the second resonator negative resistance compensation unit, the second input coupling capacitor, the second inter-stage coupling capacitor, the other end of the second coupled negative resistance compensation unit, and one end of the fourth input coupling capacitor. The other end of the first input coupling capacitor is connected to one end of the first source load coupling capacitor and is connected to the positive differential input port V in+ , the other end of the second input coupling capacitor is connected to one end of the second source load coupling capacitor and connected to the negative differential input port V in+ , the other end of the third input coupling capacitor is connected to the other end of the first source load coupling capacitor and connected to the positive differential output port V out+ , the other end of the fourth input coupling capacitor is connected to the other end of the second source load coupling capacitor and connected to the negative differential output port V out- The two ends of the inductor L1 in the transformer serve as the first port and the second port of the transformer, and the two ends of the inductor L2 serve as the third port and the fourth port of the transformer.

[0039] The filter adopts differential form, V in+ and V in- Indicates the differential input port, V out+ and V out- Represents the differential output port. The circuit mainly includes:

[0040] Among them, the inductor L1 and the first resonant unit constitute the first resonator of the filter, and the inductor L2 and the second resonant unit constitute the second resonator of the filter; L1 and L2 are close to each other to enhance mutual coupling, and the magnetic coupling between L1 and L2 serves as the main coupling between the first resonant unit and the second resonant unit of the filter; at the same time, an interstage coupling capacitor is loaded between the same-name ends of the transformer, which is composed of two back-to-back variable capacitors and is used to change the equivalent transformer coupling coefficient, so that the bandwidth of the filter has tunable characteristics.

[0041] The circuits of the four input coupling capacitors are the same, all consisting of a fixed capacitor and a variable capacitor in series. The other end of the fixed resistor is connected to the differential port. The source-load coupling capacitor consists of two back-to-back variable capacitors, which are used to introduce zero points on both sides of the passband to improve the selectivity and suppression of the filter. Figure 7 C in SL , C SL1 and C SL2 connected in series, and can be controlled by adjusting the voltage V between the two variable capacitors SL Change C SL The size of the filter is changed, thereby changing the zero point position, so that the filter can obtain a greater degree of suppression at the specified frequency. The resonant capacitor is composed of back-to-back variable capacitors and switch capacitor units. The detailed circuit is as follows Figure 8 As shown, C R Using N + Type variable capacitor; C1 and C2 represent fixed capacitors, which are composed of Metal-Oxide-Metal (MOM) capacitors. The switch tube M SW It is composed of NMOS transistors; the circuit connection is as follows: variable capacitor control voltage V CR Connect the first variable capacitor C R1 and the second variable capacitor C R2 One end of the first variable capacitor C R1 The other end is connected to one end of the first fixed capacitor C1, and the second variable capacitor C R2 The other end of the first fixed capacitor C1 is connected to one end of the second fixed capacitor C2, and the other end of the first fixed capacitor C1 is connected to the switch tube M SW The source terminal and the first resistor R b1 One end of the second fixed capacitor C2 is connected to the switch tube M SW The drain terminal and the second resistor R b2 One end of the switch tube M SW The gate terminal voltage VSW , the first resistor R b1 and the second resistor R b2 The other end of the ground. When the switch is turned on (V SW =2.5V), the fixed capacitor is connected to the resonator, and at this time it has a larger resonant capacitance; when the switch is disconnected, it has a smaller resonant capacitance.

[0042] As an implementation method, the second-order reconfigurable filter circuit is specifically connected as follows: Figure 7 As shown, the two inductors L1 and L2 of the transformer are coil inductors. Specifically, the inductor is a rectangle with a long diameter of D1 and a short diameter of D2. There is a break in the center of one side of the long diameter of the rectangle facing outward as the two connection ports of the inductor; the spacing between L1 and L2 is S1, the line width is W1, and the spacing at the inductor opening is S2; the coupling coefficient between the inductor L1 and the inductor L2 is determined by D1 and S1, and the filter bandwidth that meets the index requirements can be obtained by selecting appropriate D1 and S1.

[0043] The resonator negative resistance compensation unit includes four parallel negative resistance compensation circuits, and the coupled negative resistance compensation unit includes three parallel negative resistance compensation circuits. That is, the resonator negative resistance compensation unit and the coupled negative resistance compensation unit are controlled by 4-bit (Q0-Q3) and 3-bit (B0-B2) binary digital control, respectively. The high level of the control bit is 1.5V and the low level is 0V. The size of the cross-coupled transistors in the negative resistance compensation circuit increases in binary increments. One connection method in the negative resistance compensation circuit is as follows: Figure 7 As shown, including the first DC blocking capacitor (such as Figure 7 C in b1 、C b3 、C b5 、C b7 ), the second DC blocking capacitor (such as Figure 7 C in b2 、C b4 、C b6 、C b8 ), the first bias resistor (such as Figure 7 R in b1 、R b3 、R b5 、R b7 ), the second bias resistor (such as Figure 7 R in b2 、R b4 、R b6 、R b8 ), the first NMOS tube (such as Figure 7 M1, M3, M5, M7 in), the second NMOS tube (such as Figure 7M2, M4, M6, and M8 in the circuit); one end of the first DC blocking capacitor and the drain end of the first NMOS tube are connected to one end of the corresponding resonant capacitor unit, and the other end of the first DC blocking capacitor is connected to one end of the second bias resistor and the gate end of the second NMOS tube; the gate end of the first NMOS tube is connected to one end of the first bias resistor and one end of the second DC blocking capacitor; the other ends of the first bias resistor and the second bias resistor are connected to the digital control signal Q, and the source ends of the first NMOS tube and the second NMOS tube are grounded; the other end of the second DC blocking capacitor and the drain end of the second NMOS tube are connected to the other end of the corresponding resonant capacitor unit.

[0044] The negative resistance compensation circuit used in this section eliminates the tail or top current source. Instead, the control signal is applied directly to the gate of the cross-coupled transistor. The drain of the cross-coupled transistor is connected to the inductor and fed via the inductor's center tap (VDD). With the current source removed, the entire VDD voltage is applied between the source and drain of the cross-coupled transistor, effectively raising the input 1dB compression point. A DC blocking capacitor isolates the DC bias between the transistor's gate and drain; the gate bias resistor serves as both AC choke and DC feed.

[0045] The proposed filter with flat response is processed using SMIC 55nm CMOS process. Microscope photos of the chip are shown in the figure. Figure 9 shown. Figure 10 The differential transmission response of the filter test at different frequencies with the coupled negative resistance compensation turned on and off is given. dd21 Comparison. As can be seen from the figure, when coupling compensation is turned off, the filter's passband flatness deteriorates significantly, with the insertion loss varying by as much as 5dB within the passband. However, when coupling compensation is turned on, the filter's in-band ripple is less than 0.2dB, an improvement of 4.8dB, validating the correctness of the proposed method.

[0046] It will be understood that the present invention is described by way of some embodiments, and it will be appreciated by those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are intended to be protected by the present invention.

Claims

1. A method for optimizing the passband flatness of an on-chip active reconfigurable filter, wherein the filter includes a coupling element, characterized in that: A negative resistance compensation unit is connected at both ends of the coupling element and is connected in parallel with the coupling element. The coupling element includes a coupling inductor or a coupling capacitor.

2. The method for optimizing the passband flatness of an on-chip active reconfigurable filter according to claim 1, wherein: The negative resistance compensation unit specifically includes a first DC blocking capacitor, a second DC blocking capacitor, a first bias resistor, a second bias resistor, a first NMOS transistor, and a second NMOS transistor; one end of the first DC blocking capacitor and the drain end of the first NMOS transistor are connected to one end of a coupling element, the other end of the first DC blocking capacitor is connected to one end of the second bias resistor and the gate end of the second NMOS transistor; the gate end of the first NMOS transistor is connected to one end of the first bias resistor and one end of the second DC blocking capacitor; the other ends of the first bias resistor and the second bias resistor are connected to a digital control signal Q, and the source ends of the first NMOS transistor and the second NMOS transistor are grounded; the other end of the second DC blocking capacitor and the drain end of the second NMOS transistor are connected to the other end of the coupling element.

3. The method for optimizing the passband flatness of an on-chip active reconfigurable filter according to claim 2, wherein: The filter includes two converters, two resonant units, and a coupling element. The first converter is connected to one end of the first resonant unit, the other end of the first resonant unit is connected to one end of the coupling element, the other end of the coupling element is connected to one end of the second resonant unit, and the other end of the second resonant unit is connected to the second converter.

4. An on-chip active reconfigurable filter passband flatness optimization circuit, characterized in that: The circuit includes two converters, two resonant units, and a coupling element, wherein the first converter is connected to one end of the first resonant unit, the other end of the first resonant unit is connected to one end of the coupling element, the other end of the coupling element is connected to one end of the second resonant unit, and the other end of the second resonant unit is connected to the second converter; The coupling element is a coupling inductor or a coupling capacitor; Both ends of the coupling element are connected to a negative resistance compensation unit in parallel with the coupling element; The negative resistance compensation unit specifically includes a first DC blocking capacitor, a second DC blocking capacitor, a first bias resistor, a second bias resistor, a first NMOS transistor, and a second NMOS transistor; one end of the first DC blocking capacitor and the drain end of the first NMOS transistor are connected to one end of a coupling element, the other end of the first DC blocking capacitor is connected to one end of the second bias resistor and the gate end of the second NMOS transistor; the gate end of the first NMOS transistor is connected to one end of the first bias resistor and one end of the second DC blocking capacitor; the other ends of the first bias resistor and the second bias resistor are connected to a digital control signal Q, and the source ends of the first NMOS transistor and the second NMOS transistor are grounded; the other end of the second DC blocking capacitor and the drain end of the second NMOS transistor are connected to the other end of the coupling element.

5. An on-chip active reconfigurable filter passband flatness optimization circuit, characterized in that: The filter is a second-order reconfigurable filter with a flat passband response, including a transformer unit consisting of inductors L1 and L2, a first resonant capacitor unit, a second resonant capacitor unit, a first input coupling capacitor, a second input coupling capacitor, a third input coupling capacitor, a fourth input coupling capacitor, a first inter-stage coupling capacitor, a second inter-stage coupling capacitor, a first source-load coupling capacitor, a second source-load coupling capacitor, and a negative resistance compensation unit; the negative resistance compensation unit includes a first resonator negative resistance compensation unit, a second resonator negative resistance compensation unit, a first coupling negative resistance compensation unit, and a second coupling negative resistance compensation unit; the specific circuit connection method of the filter is as follows: The first port of the transformer is connected to the first resonant capacitor unit, the first input coupling capacitor, the first inter-stage coupling capacitor, the first resonator negative resistance compensation unit, and one end of the first coupled negative resistance compensation unit. The second port of the transformer is connected to the first resonant capacitor unit and the other end of the first resonator negative resistance compensation unit, and is also connected to the second input coupling capacitor, the second inter-stage coupling capacitor, and one end of the second coupled negative resistance compensation unit. The third port of the transformer is connected to the first inter-stage coupling capacitor and the other end of the first coupled negative resistance compensation unit, and is also connected to the second resonant capacitor unit, the second resonator negative resistance compensation unit, and one end of the third input coupling capacitor. The fourth port of the transformer is connected to the second resonant capacitor unit, the second resonator negative resistance compensation unit, the second input coupling capacitor, the second inter-stage coupling capacitor, the other end of the second coupled negative resistance compensation unit, and one end of the fourth input coupling capacitor. The other end of the first input coupling capacitor is connected to one end of the first source load coupling capacitor and is connected to the positive differential input port V in+ , the other end of the second input coupling capacitor is connected to one end of the second source load coupling capacitor and connected to the negative differential input port V in+ , the other end of the third input coupling capacitor is connected to the other end of the first source load coupling capacitor and connected to the positive differential output port V out+ , the other end of the fourth input coupling capacitor is connected to the other end of the second source load coupling capacitor and connected to the negative differential output port V out- The two ends of the inductor L1 in the transformer serve as the first port and the second port of the transformer, and the two ends of the inductor L2 serve as the third port and the fourth port of the transformer; The negative resistance compensation unit specifically includes a first DC blocking capacitor, a second DC blocking capacitor, a first bias resistor, a second bias resistor, a first NMOS transistor, and a second NMOS transistor; one end of the first DC blocking capacitor and the drain end of the first NMOS transistor are connected to one end of the corresponding resonant capacitor unit, the other end of the first DC blocking capacitor is connected to one end of the second bias resistor and the gate end of the second NMOS transistor; the gate end of the first NMOS transistor is connected to one end of the first bias resistor and one end of the second DC blocking capacitor; the other ends of the first bias resistor and the second bias resistor are connected to the digital control signal Q, and the source ends of the first NMOS transistor and the second NMOS transistor are grounded; the other end of the second DC blocking capacitor and the drain end of the second NMOS transistor are connected to the other end of the corresponding resonant capacitor unit.

6. The on-chip active reconfigurable filter passband flatness optimization circuit according to claim 5, characterized in that: The resonant capacitor unit includes a first variable capacitor, a second variable capacitor, a first fixed capacitor, a second fixed capacitor, a switch tube M SW , the first resistor, the second resistor; the connection method of the circuit is as follows: Variable capacitor control voltage V CR Connect one end of the first variable capacitor and the second variable capacitor, the other end of the first variable capacitor is connected to one end of the first fixed capacitor, the other end of the second variable capacitor is connected to one end of the second fixed capacitor, and the other end of the first fixed capacitor is connected to the switch tube M SW The source terminal of the first resistor and the other end of the second fixed capacitor are connected to the switch tube M SW The drain terminal of the second resistor, the switch tube M SW The gate terminal voltage V SW , the other ends of the first resistor and the second resistor are grounded.

7. The on-chip active reconfigurable filter passband flatness optimization circuit according to claim 6, characterized in that: The two inductors L1 and L2 of the transformer are coil inductors. The inductors are specifically rectangles with a long diameter of D1 and a short diameter of D2. There is a break in the center of one side of the long diameter of the rectangle facing outward as the two connection ports of the inductor; the spacing between L1 and L2 is S1, the line width is W1, and the spacing at the inductor openings is S2; the coupling coefficient between inductors L1 and L2 is determined by D1 and S1.

8. The on-chip active reconfigurable filter passband flatness optimization circuit according to claim 7, characterized in that: Inductor L1 and the first resonant unit constitute the first resonator of the filter, and inductor L2 and the second resonant unit constitute the second resonator of the filter; L1 and L2 are close to each other to enhance mutual coupling, and the magnetic coupling between L1 and L2 serves as the main coupling between the first resonant unit and the second resonant unit of the filter.

9. The on-chip active reconfigurable filter passband flatness optimization circuit according to claim 8, characterized in that: The interstage coupling capacitor includes two back-to-back variable capacitors; the source-load coupling capacitor includes two back-to-back variable capacitors; the input coupling capacitor includes a fixed capacitor and a variable capacitor connected in series, and the other end of the fixed resistor is connected to the differential port.

10. The on-chip active reconfigurable filter passband flatness optimization circuit according to claim 9, characterized in that: The resonator negative resistance compensation unit includes four parallel negative resistance compensation circuits, and the coupled negative resistance compensation unit includes three parallel negative resistance compensation circuits. The resonator negative resistance compensation unit and the coupled negative resistance compensation unit adopt 4-bit and 3-bit binary digital control respectively, and the size of the cross-coupled transistors in the negative resistance compensation circuit increases in binary.

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