Driving circuit, driving method, scanning circuit, scanning method and display device

Abstract

The invention provides a driving circuit, a driving method, a scanning circuit, a scanning method and a display device, and relates to the technical field of display driving. The driving circuit comprises a shift register sub-circuit and an output sub-circuit, and realizes phase conversion control from an effective level of a first control clock signal output by the shift register sub-circuit to a first level output by the output sub-circuit. The end time control of the first level output by the output sub-circuit is realized based on the control of the interval clock signal, and the purpose that the pulse width of the first level output by the output sub-circuit is adjustable can be realized by optimizing the interval clock signal. And the purpose of adjusting the interval of the first levels output by the output sub-circuits of the adjacent driving circuits in the scanning circuit is achieved. According to the technical scheme provided by the invention, improvement is carried out on the basis of the shift register sub-circuit, and the output sub-circuit connected with the output of the shift register sub-circuit is added, so that related functions of the driving circuit can be realized, and the design difficulty of the driving circuit is reduced.

Description

Technical Field

[0001] The present application relates to the field of display driving technology, and more specifically, to a driving circuit and driving method, a scanning circuit and scanning method, and a display device. Background Art

[0002] With the development of electronic technology, display devices have been widely used in various fields and various electronic products, and have become an indispensable part of people's lives and work, such as televisions, mobile phones, computers, personal digital assistants, etc. In a display device, the display device generally includes a driving circuit, a scanning circuit, a pixel circuit, a fingerprint recognition circuit, etc. The pixel circuit is used to provide the corresponding driving current for the light-emitting element, the fingerprint recognition circuit is used to collect and identify fingerprints, the driving circuit is mainly used to provide the corresponding driving signal for the pixel circuits or fingerprint recognition circuits belonging to the same group, and the scanning circuit is to cascade these driving circuits, thereby providing driving signals to the pixel circuits or fingerprint circuits belonging to different groups according to the set timing. The quality of these circuits directly affects the performance of the display device. As an important component of the display device, it is one of the key research directions of those skilled in the art. Summary of the Invention

[0003] In view of this, the present application provides a driving circuit and driving method, a scanning circuit and scanning method and a display device, which effectively solve the technical problems existing in the prior art. The driving circuit realizes the phase conversion control from the effective level of the first control clock signal output by the shift register subcircuit to the first level output by the output subcircuit, and realizes the end time control of the first level output by the output subcircuit based on the control of the interval clock signal. Therefore, by optimizing the interval clock signal, the purpose of adjusting the pulse width of the first level output by the output subcircuit and the purpose of adjusting the interval of the first level output by the output subcircuit of adjacent driving circuits in the scanning circuit can be achieved.

[0004] To achieve the above objectives, the technical solutions provided by this application are as follows:

[0005] A driving circuit, comprising a shift register subcircuit and an output subcircuit;

[0006] The first control terminal of the shift register subcircuit is connected to a first control clock signal, the second control terminal of the shift register subcircuit is connected to a second control clock signal, the third control terminal of the shift register subcircuit is connected to a third control clock signal, and the start control terminal of the shift register subcircuit is connected to a start control signal. The first input terminal of the shift register subcircuit is electrically connected to the first level terminal, and the second input terminal of the shift register subcircuit is electrically connected to the second level terminal. The shift register subcircuit outputs a first level at the first level terminal based on an effective level of the second control clock signal, outputs an inactive level of the first control clock signal based on effective levels of the third control clock signal and the start control signal, and then outputs an effective level of the first control clock signal. The first level and the second level of the second level terminal have opposite phases, and the effective level of the first control clock signal and the second level have the same phase.

[0007] The first control terminal of the output subcircuit is electrically connected to the output terminal of the shift register subcircuit, the second control terminal of the output subcircuit receives the interval clock signal, the first input terminal of the output subcircuit is electrically connected to the first level terminal, and the second input terminal of the output subcircuit is electrically connected to the second level terminal; the output subcircuit outputs the first level based on the valid level of the first control clock signal output by the shift register subcircuit, and outputs the second level based on the valid level of the interval clock signal;

[0008] In one driving cycle of the driving circuit, effective levels of the second control clock signal, the third control clock signal, the first control clock signal and the interval clock signal are arranged in time sequence.

[0009] Based on the same inventive concept, the present application also provides a driving method for driving the above-mentioned driving circuit, wherein a driving cycle of the driving method includes a reset phase, a start phase, an output phase, and an end phase performed sequentially in time.

[0010] In the reset phase, the shift register subcircuit outputs the first level of the first level end based on the valid level of the second control clock signal, and the output subcircuit outputs the second level of the second level end;

[0011] In the start-up phase, the shift register sub-circuit outputs an inactive level of the first control clock signal based on the active levels of the third control clock signal and the start-up control signal, and the output sub-circuit outputs the second level;

[0012] In the output stage, the shift register sub-circuit outputs the valid level of the first control clock signal, and the output sub-circuit outputs the first level based on the valid level of the first control clock signal output by the shift register sub-circuit;

[0013] In the end phase, the shift register sub-circuit outputs an inactive level of the first control clock signal, and the output sub-circuit outputs the second level based on the active level of the interval clock signal.

[0014] Based on the same inventive concept, the present application also provides a scanning circuit, which includes: a plurality of cascaded driving circuits, wherein the driving circuit is the driving circuit mentioned above.

[0015] Based on the same inventive concept, the present application further provides a scanning method, which is used in the above-mentioned scanning circuit, wherein the scanning method includes:

[0016] The multiple cascaded driving circuits are controlled to output the first level step by step, wherein the time interval between two adjacent cascaded driving circuits outputting the first level includes: the effective level duration of the interval clock signal connected to the previous stage driving circuit.

[0017] Based on the same inventive concept, the present application also provides a display device, which includes the above-mentioned scanning circuit.

[0018] Compared with the existing technology, the technical solution provided by this application has at least the following advantages:

[0019] The present application provides a driving circuit and driving method, a scanning circuit and scanning method, and a display device. The driving circuit includes a shift register subcircuit and an output subcircuit, wherein a first control terminal of the output subcircuit is electrically connected to an output terminal of the shift register subcircuit, a second control terminal of the output subcircuit receives an interval clock signal, a first input terminal of the output subcircuit is electrically connected to a first level terminal, and a second input terminal of the output subcircuit is electrically connected to a second level terminal; the output subcircuit outputs a first level based on an effective level of the first control clock signal output by the shift register subcircuit, and outputs a second level at the second level terminal based on an effective level of the interval clock signal. The driving circuit provided in the present application implements phase conversion control from the effective level of the first control clock signal output by the shift register subcircuit to a first level output by the output subcircuit, and implements end time control of the first level output by the output subcircuit based on control of the interval clock signal. Thus, by optimizing the interval clock signal, the pulse width of the first level output by the output subcircuit can be adjusted, and the interval between the output subcircuits of adjacent driving circuits in the scanning circuit can be adjusted. In addition, the technical solution provided in this application is improved on the basis of the shift register sub-circuit. By adding an output sub-circuit connected to the output of the shift register sub-circuit, the relevant functions of the driving circuit can be realized, thereby reducing the design difficulty of the driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0021] Figure 1 A circuit diagram of a driving circuit provided in an embodiment of the present application;

[0022] Figure 2 A circuit diagram of another driving circuit provided in an embodiment of the present application;

[0023] Figure 3 A circuit diagram of another driving circuit provided in an embodiment of the present application;

[0024] Figure 4 A circuit diagram of another driving circuit provided in an embodiment of the present application;

[0025] Figure 5 A circuit diagram of another driving circuit provided in an embodiment of the present application;

[0026] Figure 6A circuit diagram of another driving circuit provided in an embodiment of the present application;

[0027] Figure 7 A circuit diagram of another driving circuit provided in an embodiment of the present application;

[0028] Figure 8 A circuit diagram of another driving circuit provided in an embodiment of the present application;

[0029] Figure 9 A circuit diagram of another driving circuit provided in an embodiment of the present application;

[0030] Figure 10 A circuit diagram of another driving circuit provided in an embodiment of the present application;

[0031] Figure 11 A timing diagram provided for an embodiment of the present application;

[0032] Figure 12 Another timing diagram provided for an embodiment of the present application;

[0033] Figure 13 A circuit diagram of a scanning circuit provided in an embodiment of the present application;

[0034] Figure 14 Another timing diagram provided in an embodiment of the present application;

[0035] Figure 15 Another timing diagram provided in an embodiment of the present application;

[0036] Figure 16 A schematic structural diagram of a display device provided in an embodiment of the present application;

[0037] Figure 17 A schematic structural diagram of another display device provided in an embodiment of the present application;

[0038] Figure 18 This is a structural schematic diagram of another display device provided in an embodiment of the present application.

[0039] Reference numerals:

[0040] 10 - scanning circuit; 11 - repeating unit; 20 - fingerprint recognition circuit; 100 - driving circuit; 101 - first driving circuit; 102 - second driving circuit; 103 - third driving circuit; 110 - shift register subcircuit; 111 - circuit reset module; 112 - start module; 113 - first output module; 114 - second output module; 115 - scanning reset module; 120 - output subcircuit; 121 - pull-up output module; 122 - pull-down output module; 1000 - display device; CK1-first control clock signal; CK2-second control clock signal; CK3-third control clock signal; STV-start control signal; QST-reset control signal; VG1-first level terminal; VG2-second level terminal; XCK-interval clock signal; M1-first transistor; M2-second transistor; M3-third transistor; M4-fourth transistor; M5-fifth transistor; M6-sixth transistor; M7-seventh transistor; M8-eighth transistor; M9-ninth transistor; M10-tenth transistor; M11-eleventh transistor; M12-twelfth transistor; M13-thirteenth transistor; M14-fourteenth transistor; M15-fifteenth transistor; M16-sixteenth transistor; M17-seventeenth transistor; M18-eighteenth transistor; M19-nineteenth transistor; C1-first capacitor; C2-second capacitor; T1-reset phase; T1'-scan reset phase; T2-start phase; T3-output phase; T4-end phase; Ty-preset time interval; CK1S-first clock signal line; CK2S-second clock signal line; CK3S-third clock signal line; XCK1S-first interval clock signal line; XCK2S-second interval clock signal line; XCK3S-third interval clock signal line; SYVS-start control signal line; QSTS-reset control signal line; D1-first stage; D2-second stage; D3-third stage; D4-fourth stage; D5-fifth stage; D6-sixth stage; D7-seventh stage; D8-eighth stage. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0042] As described in the background technology, with the development of electronic technology, display devices have been widely used in various fields and various electronic products, and have become an indispensable part of people's lives and work, such as televisions, mobile phones, computers, personal digital assistants, etc. In a display device, the display device generally includes a driving circuit, a scanning circuit, a pixel circuit, a fingerprint recognition circuit, etc. The pixel circuit is used to provide a corresponding driving current for the light-emitting element, the fingerprint recognition circuit is used to collect and identify fingerprints, the driving circuit is mainly used to provide a corresponding driving signal for the pixel circuits or fingerprint recognition circuits belonging to the same group, and the scanning circuit is to cascade these driving circuits, thereby providing driving signals to pixel circuits or fingerprint circuits belonging to different groups according to a set timing. The quality of these circuits directly affects the performance of the display device. As an important component of the display device, it is one of the key research directions of those skilled in the art.

[0043] Based on this, the embodiments of the present application provide a driving circuit and driving method, a scanning circuit and scanning method, and a display device, which effectively solve the technical problems existing in the prior art. The driving circuit realizes the phase conversion control from the effective level of the first control clock signal output by the shift register subcircuit to the first level output by the output subcircuit, and realizes the end time control of the first level output by the output subcircuit based on the control of the interval clock signal, thereby achieving the purpose of adjusting the pulse width of the first level output by the output subcircuit of the driving circuit, and achieving the purpose of adjusting the interval of the first level output by the output subcircuit of adjacent driving circuits in the scanning circuit.

[0044] To achieve the above purpose, the technical solutions provided in the embodiments of the present application are as follows, specifically combined with Figures 1 to 18 The technical solutions provided in the embodiments of the present application are described in detail.

[0045] refer to Figure 1, which is a circuit diagram of a driving circuit provided in an embodiment of the present application, wherein the driving circuit 100 provided in an embodiment of the present application includes a shift register subcircuit 110 and an output subcircuit 120. The first control terminal of the shift register subcircuit 110 is connected to the first control clock signal CK1, the second control terminal of the shift register subcircuit 110 is connected to the second control clock signal CK2, the third control terminal of the shift register subcircuit 110 is connected to the third control clock signal CK3, the start control terminal of the shift register subcircuit 110 is connected to the start control signal STV, the first input terminal of the shift register subcircuit 110 is electrically connected to the first level terminal VG1, and the second input terminal of the shift register subcircuit 110 is electrically connected to the second level terminal VG2; the shift register subcircuit 110 is based on the first control clock signal CK1. The first level of the first level end VG1 is output based on the effective level of the second control clock signal CK2, the inactive level of the first control clock signal CK1 is output based on the effective levels of the third control clock signal CK3 and the start control signal STV, and then the effective level of the first control clock signal CK1 is output, the first level and the second level of the second level end VG2 are opposite in phase, and the effective levels of the first control clock signal CK1, the second control clock signal CK2, the third control clock signal CK3 and the interval clock signal XCK are all in phase with the second level. The first control terminal of the output sub-circuit 120 is electrically connected to the output terminal of the shift register sub-circuit 110, and the second control terminal of the output sub-circuit 120 is connected to the interval clock signal XCK. The first input terminal of the output sub-circuit 120 is electrically connected to the first level terminal VG1, and the second input terminal of the output sub-circuit 120 is electrically connected to the second level terminal VG2. The output sub-circuit 120 outputs the first level based on the active level of the first control clock signal CK1 output by the shift register sub-circuit 110, and outputs the second level based on the active level of the interval clock signal XCK. During a driving cycle of the driving circuit 100, the active levels of the second control clock signal CK2, the third control clock signal CK3, the first control clock signal CK1, and the interval clock signal XCK are arranged in chronological order. That is, during a driving cycle of the driving circuit 100, the second control clock signal CK2 is first at an active level, followed by the third control clock signal CK3, and finally the first control clock signal CK1 is at an active level.

[0046] As can be understood, the driver circuit 100 provided in the embodiment of the present application implements phase conversion control from the active level of the first control clock signal CK1 output by the shift register subcircuit 110 to the first level output by the output subcircuit 120, and controls the end time of the first level output by the output subcircuit 120 based on the control of the interval clock signal XCK. Thus, by optimizing the interval clock signal XCK, the pulse width of the first level output by the output subcircuit 120 can be adjusted, and the interval between the outputs of the first level by the output subcircuits 120 of adjacent driver circuits 100 in the scanning circuit can be adjusted. Furthermore, the technical solution provided in the embodiment of the present application improves upon the shift register subcircuit 110. By adding an output subcircuit 120 connected to the output of the shift register subcircuit 110, the relevant functions of the driver circuit 100 can be implemented, thereby reducing the design difficulty of the driver circuit 100. Optionally, the driving circuit 100 provided in the embodiment of the present application can be used to provide a reset control signal (reset) for the fingerprint recognition circuit. Fingerprint recognition requires different exposure times when the finger is recognized and when the finger is not recognized, and the time required to read data is different. Therefore, the driving circuit 100 provided in the embodiment of the present application can realize the function of adjustable pulse width of the first level and the function of adjustable interval of the first level output by adjacent driving circuits, and can provide an adapted driving signal for the fingerprint recognition circuit. The applicable scenarios of the driving circuit 100 are not limited to the fingerprint recognition circuit. In other embodiments, it can also be used to provide relevant driving signals for other circuits. This application does not impose specific restrictions on this.

[0047] During a driving cycle of the driver circuit 100, a preset time gap exists between the active level of the first control clock signal CK1 and the active level of the interval clock signal XCK provided in the embodiment of the present application. Since the output sub-circuit 120 outputs the first level based on the active level of the first control clock signal CK1 output by the shift register sub-circuit 110, and the output sub-circuit 120 also outputs the second level based on the active level of the interval clock signal XCK, the driver circuit 100 controls the phase transition from the active level of the first control clock signal CK1 output by the shift register sub-circuit 110 to the first level output by the output sub-circuit 120, and controls the end time of the first level output by the output sub-circuit 120 based on the control of the interval clock signal XCK. Therefore, by adjusting the time gap between the active level of the first control clock signal CK1 and the active level of the interval clock signal XCK, the duration of the first level output by the output sub-circuit 120 can be adjusted, that is, the pulse width of the first level output by the output sub-circuit 120 can be adjusted.

[0048] The specific circuit composition and connection of the driving circuit 100 provided in the embodiment of the present application are described in detail below with reference to the accompanying drawings. It should be noted that the embodiment of the present application is described by taking the transistors included in the driving circuit 100 as P-type transistors as an example, wherein the first level is a high level, the second level is a low level, and the effective levels of the first control clock signal CK1, the second control clock signal CK2, the third control clock signal CK3, the interval clock signal XCK and the start control signal STV are all low levels (the invalid level is a high level). In other embodiments of the present application, the transistors included in the driving circuit 100 provided in the embodiment of the present application can also be N-type transistors, or part of them are P-type transistors and part of them are N-type transistors, and this application does not make specific restrictions on this; wherein when the transistor is a P-type transistor, the effective level of the control signal connected to the gate of the P-type transistor is a low level (the invalid level is a high level); or when the transistor is an N-type transistor, the effective level of the control signal connected to the gate of the N-type transistor is a high level (the invalid level is a low level).

[0049] refer to Figure 2 As shown, it is a circuit diagram of another driving circuit provided in an embodiment of the present application, wherein the shift register sub-circuit 110 provided in an embodiment of the present application includes: a circuit reset module 111, an opening module 112, a first output module 113 and a second output module 114, the output ends of the first output module 113 and the second output module 114 are the output ends of the shift register sub-circuit 120, that is, the output ends of the first output module 113 and the second output module 114 are both electrically connected to the first control end of the output sub-circuit 120. The circuit reset module 111 receives the second control clock signal CK2 and is electrically connected to both the first node N1 and the second node N2. The circuit reset module 111 is also electrically connected to both the first level terminal VG1 and the second level terminal VG2. Based on the active level of the second control clock signal CK2, the circuit reset module 111 controls the level of the first node N1 to be the first level and the level of the second node N2 to be the second level. That is, based on the active level of the second control clock signal CK2, the circuit reset module 111 controls the second level terminal VG2 to be connected to the second node N2, and controls the first level terminal VG1 to be connected to the first node N1 based on the second level of the second node N2. The second output module 114 is electrically connected to the first level terminal VG1 and the second node N2. Based on the second level of the second node N2, the second output module 114 outputs the first level. That is, based on the second level of the second node N2, the second output module 114 controls the output of the shift register sub-circuit 110 to be connected to the first level terminal VG1.

[0050] Continue as Figure 2 As shown, the start-up module 112 is connected to the third control clock signal CK3 and the start-up control signal STV, the start-up module 112 is electrically connected to the first node N1 and the second node N2, and the start-up module 112 is electrically connected to the first level end VG1 and the second level end VG2; the start-up module 112 controls the level of the first node N1 to be the second level and controls the level of the second node N2 to be the first level based on the effective level of the third control clock signal CK3 and the start-up control signal STV; that is, the start-up module 112 connects the second level end VG2 to the first node N1 based on the effective level of the third control clock signal CK3 and the start-up control signal STV; and connects the first level end VG1 to the second node N2 based on the effective level of the start-up control signal STV and the second level of the first node N1. The first output module 113 is connected to the first control clock signal CK1, and the first output module 113 is electrically connected to the first node N1; the first output module 113 outputs the invalid level of the first control clock signal CK1 based on the second level of the first node N1, and then outputs the valid level of the first control clock signal CK1; that is, the first output module 113 transmits the first control clock signal CK1 to the output end of the shift register sub-circuit 110 based on the second level control of the first node N1.

[0051] Further references Figure 3 The components and connection relationships of each module in the shift register sub-circuit 110 provided in an embodiment of the present application are described. Figure 3A circuit diagram of another driving circuit provided in an embodiment of the present application, wherein the circuit reset module 111 provided in an embodiment of the present application includes a first transistor M1 and a second transistor M2. The first end of the first transistor M1 is electrically connected to the second level terminal VG2, the second end of the first transistor M1 is electrically connected to the second node N2, and the gate of the first transistor M1 is connected to the second control clock signal CK2. The first end of the first transistor M1 serves as the second input terminal of the shift register subcircuit 110, and the gate of the first transistor M1 serves as the second control terminal of the shift register subcircuit 110. The first transistor M1 is turned on based on the active level of the second control clock signal CK2 to connect the second level terminal VG2 to the second node N2, so that the level of the second node N2 is the second level. The first end of the second transistor M2 is electrically connected to the first level terminal VG1, the second end of the second transistor M2 is electrically connected to the first node N1, and the gate of the second transistor M2 is electrically connected to the second node N2. The first terminal of the second transistor M2 serves as the first input terminal of the shift register sub-circuit 110. The second transistor M2 is turned on based on the second level of the second node N2, connecting the first level terminal VG1 to the first node N1, thereby maintaining the level of the first node N1 at the first level. In some embodiments, at least one of the first transistor M1 and the second transistor M2 provided in the embodiments of the present application may be a dual-gate transistor, thereby increasing the response speed of the first transistor M1 and the second transistor M2, improving power consumption and leakage issues of the shift register sub-circuit 110, and enhancing the performance of the driver circuit 100.

[0052] like Figure 3 As shown, the second output module 114 provided in this embodiment of the present application includes a fourth transistor M4. A first terminal of the fourth transistor M4 is electrically connected to the first level terminal VG1, a second terminal of the fourth transistor M4 serves as the output terminal of the second output module 114, and a gate of the fourth transistor M4 is electrically connected to the second node N2. The first terminal of the fourth transistor M4 serves as the first input terminal of the shift register sub-circuit 110, and the second terminal of the fourth transistor M4 serves as the output terminal of the shift register sub-circuit 110. The fourth transistor M4 is controlled to be turned on based on the second level of the second node N2, connecting the output terminal of the shift register sub-circuit 110 to the first level terminal VG1.

[0053] like Figure 3As shown, the start-up module 112 provided in the embodiment of the present application includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor M8. The first end of the fifth transistor M5 is electrically connected to the second end of the sixth transistor M6, the second end of the fifth transistor M5 is electrically connected to the first node N1, and the gate of the fifth transistor M5 is connected to the third control clock signal CK3; the first end of the sixth transistor M6 is electrically connected to the second level end VG2, and the gate of the sixth transistor M6 is connected to the start-up control signal STV; the first end of the seventh transistor M7 is electrically connected to the first level end VG1, the second end of the seventh transistor M7 is electrically connected to the second node N2, and the gate of the seventh transistor M7 is electrically connected to the first node N1; the first end of the eighth transistor M8 is electrically connected to the first level end VG1, the second end of the eighth transistor M8 is electrically connected to the second node N2, and the gate of the eighth transistor M8 is connected to the start-up control signal STV. The gate of the fifth transistor M5 serves as the third control terminal of the shift register sub-circuit 110, and the gates of the sixth transistor M6 and the eighth transistor M8 are electrically connected to serve as the start control terminal of the shift register sub-circuit 110. The fifth transistor M5 is turned on based on the active level of the third control clock signal CK3, and the sixth transistor M6 is turned on based on the active level of the start control signal STV, thereby connecting the second level terminal VG2 to the first node N1. At this time, the seventh transistor M7 is turned on based on the second level of the first node N1, and the eighth transistor M8 is turned on based on the active level of the start control signal STV, thereby connecting the first level terminal VG1 to the second node N2. In some embodiments, at least one of the seventh transistor M7 and the eighth transistor M8 provided in the embodiments of the present application can be a dual-gate transistor, thereby improving the response speed of the seventh transistor M7 and the eighth transistor M8, and improving the power consumption and leakage of the shift register sub-circuit 110, thereby improving the performance of the driver circuit 100.

[0054] Continue as Figure 3As shown, the first output module 113 provided in the embodiment of the present application includes a tenth transistor M10 and a first capacitor C1. The first terminal of the tenth transistor M10 is connected to the first control clock signal CK1, the second terminal of the tenth transistor M10 serves as the output terminal of the first output module 113, and the gate of the tenth transistor M10 is electrically connected to the first node N1. The first plate of the first capacitor C1 is electrically connected to the gate of the tenth transistor M10, and the second plate of the first capacitor C1 is electrically connected to the second terminal of the tenth transistor M10. The first terminal of the tenth transistor M10 serves as the first control terminal of the shift register sub-circuit 110, and the second terminal of the tenth transistor M10 serves as the output terminal of the shift register sub-circuit 110. The tenth transistor M10 is controlled to be turned on based on the second level of the first node N1, transmitting the first control clock signal CK1 to the output terminal of the shift register sub-circuit 110.

[0055] refer to Figure 4 , which is a circuit diagram of another drive circuit provided in an embodiment of the present application, wherein the circuit reset module 111 provided in an embodiment of the present application further includes a third transistor M3, which is connected in series between the second transistor M2 and the first node N1. A first end of the third transistor M3 is electrically connected to the second end of the second transistor M2, a second end of the third transistor M3 is electrically connected to the first node N1, and a gate of the third transistor M3 is electrically connected to the second level terminal VG2. The gate of the third transistor M3 is the second input terminal of the shift register sub-circuit 110. Because the gate of the third transistor M3 is connected to the second level of the second level terminal VG2, the third transistor M3 is normally on after the drive circuit 100 is powered on, and can serve to divide the voltage of the branch where the second transistor M2 is located, thereby improving the safety and performance of the drive circuit 100. In addition, the start-up module 112 provided in the embodiment of the present application further includes a ninth transistor M9, which is connected in series between the fifth transistor M5 and the first node N1. A first end of the ninth transistor M9 is electrically connected to the second end of the fifth transistor M5, a second end of the ninth transistor M9 is electrically connected to the first node N1, and a gate of the ninth transistor M9 is electrically connected to the second level terminal VG2. The gate of the ninth transistor M9 serves as the second input terminal of the shift register sub-circuit 110. Because the gate of the ninth transistor M9 is connected to the second level of the second level terminal VG2, the ninth transistor M9 is normally on after the driving circuit 100 is powered on. It can divide the voltage of the branch containing the fifth transistor M5 and the sixth transistor M6, thereby further improving the safety and performance of the driving circuit 100.

[0056] refer to Figure 5FIG. 1 is a circuit diagram of another driving circuit according to an embodiment of the present application. The shift register sub-circuit 110 according to the embodiment of the present application further includes a scanning reset module 115, which receives a reset control signal QST and is electrically connected to the first level terminal VG1. The scanning reset module 115 controls the level of the first node N1 to the first level based on the active level of the reset control signal QST. Specifically, the scanning reset module 115 connects the first level terminal VG1 to the first node N1 based on the active level of the reset control signal QST. Optionally, during a driving cycle of the driving circuit 100, the active level of the reset control signal QST precedes the active level of the second control clock signal CK2. This allows the first node N1 to be reset before the circuit reset module 111. This prevents residual signal at the node during subsequent operation of the driving circuit 100, thereby improving the performance of the driving circuit 100. Alternatively, within a driving cycle of the driving circuit 100, the effective level of the reset control signal QST starts earlier than the effective level of the second control clock signal CK2, and the effective level of the reset control signal QST and the effective level of the second control clock signal CK2 partially overlap in time sequence. Similarly, the scanning reset module 115 resets the first node N1 before the circuit reset module 111, thereby avoiding the problem of residual signal at the node when the driving circuit 100 performs subsequent operations, thereby improving the performance of the driving circuit 100. Alternatively, within a driving cycle of the driving circuit 100, the effective level of the reset control signal QST and the effective level of the second control clock signal CK2 overlap in time sequence. This is not specifically limited in this application, and the timing design of the reset control signal QST and the second control clock signal CK2 needs to be carried out according to actual applications.

[0057] It should be noted that when the driving circuit 100 provided in the embodiment of the present application is applied to a scanning circuit, wherein the scanning circuit includes a plurality of cascaded driving circuits 100, the reset control signal QST is set in timing compared to the second control clock signal CK2 corresponding to the first-stage driving circuit 100. That is, in at least one scanning cycle (one scanning cycle is the time for scanning all cascaded driving circuits), the effective level of the reset control signal QST is before the effective level of the second control clock signal CK2 corresponding to the first-stage driving circuit 100; or, the starting moment of the effective level of the reset control signal QST is earlier than the starting moment of the effective level of the second control clock signal CK2 corresponding to the first-stage driving circuit 100, and the effective level of the reset control signal QST and the effective level of the second control clock signal CK2 corresponding to the first-stage driving circuit 100 partially overlap in time sequence; or, the effective level of the reset control signal QST and the effective level of the second control clock signal CK2 corresponding to the first-stage driving circuit 100 overlap in time sequence, thereby enabling the first node N1 of all driving circuits 100 to be reset first in the at least one scanning cycle, thereby avoiding the problem of residual signals at the nodes when the driving circuit 100 performs subsequent work, thereby improving the performance of the driving circuit 100.

[0058] refer to Figure 6 FIG. 1 is a circuit diagram of another driving circuit provided in an embodiment of the present application, wherein the scan reset module 115 provided in an embodiment of the present application may include an eleventh transistor M11, wherein a first end of the eleventh transistor M11 is electrically connected to the first level end VG1, a second end of the eleventh transistor M11 is electrically connected to the first node N1, and a gate of the eleventh transistor M11 is connected to the reset control signal QST. The eleventh transistor M11 is turned on based on the active level control of the reset control signal QST, connecting the first level end VG1 to the first node N1 to reset the first node N1 to the first level. In some embodiments, the eleventh transistor M11 provided in an embodiment of the present application may be a dual-gate transistor, thereby improving the response speed of the eleventh transistor M11, and improving the power consumption and leakage of the shift register sub-circuit 110, thereby improving the performance of the driving circuit 100.

[0059] refer to Figure 7FIG. 1 is a circuit diagram of another drive circuit provided in an embodiment of the present application. The scan reset module 115 provided in an embodiment of the present application further includes a twelfth transistor M12, which is connected in series between the eleventh transistor M11 and the first node N1. The first end of the twelfth transistor M12 is electrically connected to the second end of the eleventh transistor M11, the second end of the twelfth transistor M12 is electrically connected to the first node N1, and the gate of the twelfth transistor M12 is electrically connected to the second level terminal VG2. Since the gate of the twelfth transistor M12 is connected to the second level terminal VG2, the twelfth transistor M12 is in a normally-on state after the drive circuit 100 is powered on. The twelfth transistor M12 can divide the voltage of the branch where the eleventh transistor M1 is located, thereby further improving the safety and performance of the drive circuit 100.

[0060] above Figures 3 to 7 The present invention mainly illustrates the circuit composition and connection relationship of the shift register sub-circuit 110 provided in the embodiment of the present invention. The present invention is not limited to the above Figures 3 to 7 The shift register subcircuit 110 shown is only a few of all the shift register subcircuits 110 applicable to this application. In other embodiments of the present application, the shift register subcircuit 110 may also include other applicable circuit components and connection relationships, which need to be specifically designed according to the actual application. The circuit components and connection relationships of the output subcircuit 120 provided in the embodiment of the present application are described in detail below in conjunction with the accompanying drawings. Similarly, the present application is not limited to the circuit components and connection relationships of the output subcircuit 120 described below. In other embodiments of the present application, the output subcircuit 120 may also include other applicable circuit components and connection relationships.

[0061] refer to Figure 8FIG. 1 is a circuit diagram of another driving circuit provided in an embodiment of the present application, wherein the output sub-circuit 120 provided in the embodiment of the present application includes: a pull-up output module 121 and a pull-down output module 122. The output ends of the pull-up output module 121 and the pull-down output module 122 serve as the output end of the output sub-circuit 120. The pull-up output module 121 is electrically connected to the output end of the shift register sub-circuit 110 and the first level end VG1. The pull-up output module 121 outputs the first level based on the active level of the first control clock signal CK1 output by the shift register sub-circuit 110. That is, the pull-up output module 121 controls the active level of the first control clock signal CK1 output by the shift register sub-circuit 110 to connect the first level end VG1 with the output end of the output sub-circuit 120, thereby achieving phase conversion control from the active level of the first control clock signal CK1 output by the shift register sub-circuit 110 to the first level output by the output sub-circuit 120. The pull-down output module 122 is connected to the interval clock signal XCK, and is electrically connected to the second level terminal VG2; the pull-down output module 122 outputs the second level based on the effective level of the interval clock signal XCK; that is, the pull-down output module 122 connects the second level terminal VG2 to the output terminal of the output sub-circuit 120 based on the control of the effective level of the interval clock signal XCK, thereby realizing the end time control of the first level output by the output sub-circuit 120.

[0062] refer to Figure 9FIG. 1 is a circuit diagram of another driving circuit provided in an embodiment of the present application. The pull-up output module 121 provided in an embodiment of the present application includes a thirteenth transistor M13, a fourteenth transistor M14, and a fifteenth transistor M15. A first end of the thirteenth transistor M13 is electrically connected to the first level terminal VG1, and a second end of the thirteenth transistor M13 is electrically connected to the pull-down output module 122 to control the pull-down output module 122 to stop operation. A gate of the thirteenth transistor M13 is electrically connected to the output end of the shift register sub-circuit 110. A first end of the fourteenth transistor M14 is electrically connected to the first level terminal VG1, a second end of the fourteenth transistor M14 is electrically connected to the first end of the fifteenth transistor M15, and a gate of the fourteenth transistor M14 is electrically connected to the output end of the shift register sub-circuit 110. A second end of the fifteenth transistor M15 serves as the output end of the pull-up output module 121, and a gate of the fifteenth transistor M15 is electrically connected to the output end of the shift register sub-circuit 110. The gates of the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 are electrically connected to the first control terminal of the output sub-module 120, the first terminal of the thirteenth transistor M13 and the first terminal of the fourteenth transistor M14 are electrically connected to the first input terminal of the output sub-module 120, and the output terminal of the pull-up output module 121 is the output terminal of the output sub-module 120; wherein, the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 are turned on based on the control of the effective level of the first control clock signal CK1 output by the shift register sub-circuit 110, connecting the first level terminal VG1 to the output terminal of the output sub-module 120, so that the output sub-module 120 outputs the first level.

[0063] Continue as Figure 9As shown, the pull-down output module 122 provided in the embodiment of the present application includes a seventeenth transistor M17, an eighteenth transistor M18, a nineteenth transistor M19 and a second capacitor C2; the first end of the seventeenth transistor M17 is electrically connected to the second level end VG2, the second end of the seventeenth transistor M17 is electrically connected to the second end of the eighteenth transistor M18 and the gate of the nineteenth transistor M19, and the gate of the seventeenth transistor M17 is connected to the interval clock signal XCK; the first end of the eighteenth transistor M18 is electrically connected to the second level end VG2, and the gate of the eighteenth transistor M18 is electrically connected to the second end of the nineteenth transistor M19; the first end of the nineteenth transistor M19 is electrically connected to the second level end VG2, the second end of the nineteenth transistor M19 is the output end of the pull-down output module 122, the first plate of the second capacitor C2 is electrically connected to the gate of the nineteenth transistor M19, and the second plate of the second capacitor C2 is electrically connected to the second end of the nineteenth transistor M19. The gate of the seventeenth transistor M17 serves as the second control terminal of the output submodule 120. The first terminal of the seventeenth transistor M17, the first terminal of the eighteenth transistor M18, and the first terminal of the nineteenth transistor M19 are electrically connected to serve as the second input terminal of the output submodule 120. The output terminal of the pull-down output module 122 also serves as the output terminal of the output submodule 120. The seventeenth transistor M17 is turned on based on the active level of the interval clock signal XCK, connecting the second level terminal VG2 to the gate of the nineteenth transistor M19, thereby controlling the nineteenth transistor M19 to be turned on, thereby connecting the second level terminal VG2 to the output terminal of the output submodule 120, so that the output submodule 120 outputs the second level.

[0064] refer to Figure 10, which is a circuit diagram of another drive circuit provided in an embodiment of the present application, wherein the pull-up output module 121 provided in an embodiment of the present application further includes a sixteenth transistor M16; a first end of the sixteenth transistor M16 is electrically connected to the second end of the fourteenth transistor M14, a second end of the sixteenth transistor M16 is electrically connected to the second level terminal VG2, and a gate of the sixteenth transistor M16 is electrically connected to the second end of the fifteenth transistor M15. The sixteenth transistor M16 can improve the leakage problem of the fourteenth transistor M14, thereby improving the reliability of the drive circuit 100. Specifically, when the output level of the output sub-circuit 120 switches from the first level to the second level, a large voltage difference occurs; that is, when the output end of the output sub-circuit 120 outputs the second level, there is a large voltage difference between it and the first level terminal VG1, resulting in the fourteenth transistor M14 being prone to leakage after the drive circuit 100 has been operating for a long time. The gate of the sixteenth transistor M16 is electrically connected to the second end of the fifteenth transistor M15, that is, the gate of the sixteenth transistor M16 is electrically connected to the output end of the output sub-circuit 120. The sixteenth transistor M16 can be controlled to be in an on state when the output end of the output sub-circuit 120 outputs the second electrical level, thereby conducting leakage current of the fourteenth transistor M14 and improving the reliability of the driving circuit 100.

[0065] Based on the same inventive concept, the embodiment of the present application further provides a driving method for driving the driving circuit 100 provided in any of the above embodiments. Figure 11 FIG. 1 is a timing diagram provided by an embodiment of the present application, wherein a driving cycle of the driving method provided by the embodiment of the present application includes a reset phase T1, a start phase T2, an output phase T3 and an end phase T4 which are performed in chronological order.

[0066] In the reset phase T1, the shift register sub-circuit 110 outputs the first level of the first level terminal VG1 based on the active level of the second control clock signal CK2, and the output sub-circuit 120 outputs the second level of the second level terminal. Figure 11 OUTY indicates the output signal of the shift register sub-circuit 110, and OUTS indicates the output signal of the output sub-circuit 120.

[0067] In the start-up phase T2 , the shift register sub-circuit 110 outputs the inactive level of the first control clock signal CK1 based on the active levels of the third control clock signal CK3 and the start-up control signal STV, and the output sub-circuit 120 outputs the second level.

[0068] In the output phase T3 , the shift register sub-circuit 110 outputs the active level of the first control clock signal CK1 , and the output sub-circuit 120 outputs the first level based on the active level of the first control clock signal CK1 output by the shift register sub-circuit 110 .

[0069] In the end stage T4 , the shift register sub-circuit 110 outputs the inactive level of the first control clock signal CK1 , and the output sub-circuit 120 outputs the second level based on the active level of the interval clock signal XCK.

[0070] Furthermore, the driving circuit 100 provided in the embodiment of the present application may further include a scanning reset module 115, and the driving circuit also includes a scanning reset phase T1'. Figure 11 The timing shown takes the overlap of the effective level of the reset control signal QST and the effective level of the second control clock signal CK2 in time sequence in a driving cycle as an example. In the scanning reset phase T1', the scanning reset module 115 resets the driving circuit 100 based on the effective level of the reset control signal QST, that is, the scanning reset module 115 controls the level of the first node N1 to be the first level based on the effective level of the reset control signal QST.

[0071] Specific combination Figure 10 The driving circuit 100 and Figure 11 The timing diagram shown in FIG. 1 is used to describe the driving process of the driving circuit 100 provided in the embodiment of the present application in more detail. Figure 11In the illustrated scan reset phase T1′ (which overlaps with the reset phase T1), the reset control signal QST is at an active level, controlling the eleventh transistor M11 to be turned on, and the gate of the twelfth transistor M12 is connected to the second level of the second level terminal VG2 and is in a normally-on state. At this time, the eleventh transistor M11 and the twelfth transistor M12 connect the first level terminal VG1 to the first node N1. Furthermore, the second control clock signal CK2 is at an active level, controlling the first transistor M1 to be turned on, connecting the second level terminal VG2 to the second node N2. The second level of the second node N2 can control the second transistor M2 to be turned on. Since the gate of the third transistor M3 is connected to the second level of the second level terminal VG2 and is in a normally-on state, the second transistor M2 and the third transistor M3 connect the first level terminal VG1 to the first node N1. Simultaneously, the second level of the second node N2 can control the fourth transistor M4 to be turned on, connecting the first level terminal VG1 to the output terminal of the shift register sub-circuit 110. OUTY indicates that the shift register sub-circuit 110 outputs the first level. At this time, the second capacitor C2 is maintained by the storage voltage to control the conduction of the sixteenth transistor M16 and the eighteenth transistor M18. The eighteenth transistor M18 transmits the second level of the second level terminal VG2 to the gate of the nineteenth transistor M19, controls the conduction of the nineteenth transistor M19, and connects the second level terminal VG2 with the output terminal of the output sub-circuit 120. OUTS indicates that the output sub-circuit 120 outputs the second level. In the start-up phase T2, the third control clock signal CK3 and the start-up control signal STV are at the active level, and accordingly control the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 to be turned on. Since the gate of the ninth transistor M9 is connected to the second level of the second level terminal VG2 and is in the normally-on state, the fifth transistor M5, the sixth transistor M6, and the ninth transistor M9 connect the second level terminal VG2 and the first node N1, and the eighth transistor M8 connects the first level terminal VG1 and the second node N2. The second level of the first node N1 can control the seventh transistor M7 and the tenth transistor M10 to be turned on. The seventh transistor M7 connects the first level terminal VG1 and the second node N2, and the tenth transistor M10 transmits the first control clock signal CK1 to the output terminal of the shift register sub-circuit 110. OUTY indicates that the output of the shift register sub-circuit 110 is the inactive level of the first control clock signal CK1 at this time. At this time, the second capacitor C2 is maintained by the storage voltage to control the conduction of the sixteenth transistor M16 and the eighteenth transistor M18. The eighteenth transistor M18 transmits the second level of the second level terminal VG2 to the gate of the nineteenth transistor M19, controls the conduction of the nineteenth transistor M19, and connects the second level terminal VG2 with the output terminal of the output sub-circuit 120. OUTS indicates that the output sub-circuit 120 outputs the second level.

[0072] During output phase T3, the first control clock signal CK1 is at an active level. At this time, the first capacitor C1 maintains the control of the tenth transistor M10, which transmits the first control clock signal CK1 to the output terminal of the shift register sub-circuit 110. OUTY indicates the active level of the first control clock signal CK1 output by the shift register sub-circuit 110 at this time. The active level is the same as the second level. The active level of the first control clock signal CK1 output by the shift register sub-circuit 110 controls the thirteenth transistor M13, the fourteenth transistor M14, and the fifteenth transistor M15 to conduct. The thirteenth transistor M13 transmits the first level of the first level terminal VG1 to the gate of the nineteenth transistor M19, thereby turning off the nineteenth transistor M19. The fourteenth transistor M14 and the fifteenth transistor M15 connect the first level terminal VG1 to the output terminal of the output sub-circuit 120. OUTS indicates that the output sub-circuit 120 outputs the first level.

[0073] At the end stage T4, the first control clock signal CK1 is at an inactive level. At this time, the first capacitor C1 maintains the control of the tenth transistor M10, which transmits the first control clock signal CK1 to the output terminal of the shift register sub-circuit 110. OUTY indicates that the shift register sub-circuit 110 outputs the inactive level of the first control clock signal CK1. The interval clock signal XCK is at an active level, which controls the seventeenth transistor M17 to be conductive. The seventeenth transistor M17 transmits the second level of the second level terminal VG2 to the gate of the nineteenth transistor M19, controlling the nineteenth transistor M19 to be conductive. The nineteenth transistor M19 connects the second level terminal VG2 to the output terminal of the output sub-circuit 120. OUTS indicates that the output sub-circuit 120 outputs the second level.

[0074] refer to Figure 12FIG. 1 shows another timing diagram provided by an embodiment of the present application. Within a driving cycle of the driving circuit, a preset time interval Ty exists between the active level of the first control clock signal CK1 and the active level of the interval clock signal XCK. During the preset time interval Ty, the shift register sub-circuit 110 outputs an inactive level of the first control clock signal CK1, and the output sub-circuit 120 maintains outputting the first level. Specifically, during the preset time interval Ty, the first control clock signal CK1 is inactive. At this time, the first capacitor C1 maintains control of the tenth transistor M10, which is turned on. The tenth transistor M10 transmits the first control clock signal CK1 to the output terminal of the shift register sub-circuit 110. OUTY indicates that the shift register sub-circuit 110 outputs the inactive level of the first control clock signal CK1 at this time. The second capacitor C2 maintains control of the nineteenth transistor M19, which is turned off, while maintaining the output level of the output sub-circuit 120 in phase with the first level. It can be seen that the driving circuit 100 provided in the embodiment of the present application can realize the phase conversion control from the effective level of the first control clock signal CK1 output by the shift register sub-circuit 110 to the first level output by the output sub-circuit 120, and based on the control of the interval clock signal XCK, the end time control of the first level output by the output sub-circuit 120 is realized, and by optimizing the interval clock signal XCK, the purpose of adjusting the pulse width of the first level output by the output sub-circuit 120 and the purpose of adjusting the interval of the first level output by the output sub-circuit 120 of the adjacent driving circuits 100 in the scanning circuit are realized.

[0075] Based on the same inventive concept, the embodiment of the present application further provides a scanning circuit 10, the scanning circuit 10 comprising: a plurality of cascaded driving circuits 100, wherein the driving circuit 100 is the driving circuit 100 provided by any of the above embodiments. Figure 13, which is a circuit diagram of a scanning circuit provided in an embodiment of the present application, specifically a circuit diagram of a repeating unit 11. The scanning circuit 10 provided in an embodiment of the present application includes: a start control signal line STVS, a first clock signal line CK1S, a second clock signal line CK2S, a third clock signal line CK3S, a first interval clock signal line XCK1S, a second interval clock signal line XCK2S, a third interval clock signal line XCK3S, and at least one repeating circuit unit 11. The second clock signal line CK2S, the third clock signal line CK3S, and the first clock signal line CK1S sequentially output valid levels in time sequence, and the i-th interval clock signal line outputs a valid level after the i-th clock signal line outputs a valid level, where i is a positive integer not greater than 3. That is, in one driving cycle of the driving circuit 100, the clock control signal provided by the clock signal line can make the second control clock signal CK2 connected to the driving circuit 100 first be at an effective level, then the third control clock signal CK3 be at an effective level, and finally the first control clock signal CK1 be at an effective level; and in one cycle of the repeating unit 11, the interval clock signal XCK output by the first interval clock signal line XCK1S is first at an effective level, then the interval clock signal XCK output by the second interval clock signal line XCK2S is at an effective level, and finally the interval clock signal XCK output by the third interval clock signal line XCK3S is at an effective level.

[0076] The repeating unit 11 includes three cascaded drive circuits 100, defined as a first drive circuit 101, a second drive circuit 102, and a third drive circuit 103. In the first drive circuit 101, the first control terminal of the shift register subcircuit 110 is electrically connected to the first clock signal line CK1S, the second control terminal of the shift register subcircuit 110 is electrically connected to the second clock signal line CK2S, the third control terminal of the shift register subcircuit 110 is electrically connected to the third clock signal line CK3S, and the second control terminal of the output subcircuit 120 is electrically connected to the first intermittent clock signal line XCK1S. Specifically, the first clock signal line CK1S provides the first control clock signal CK1 to the first drive circuit 101, the second clock signal line CK2S provides the second control clock signal CK2 to the first drive circuit 101, the third clock signal line CK3S provides the third control clock signal CK3 to the first drive circuit 101, and the first intermittent clock signal line XCK1S provides the intermittent clock signal XCK to the first drive circuit 101.

[0077] In the second driver circuit 102, the first control terminal of the shift register sub-circuit 110 is electrically connected to the second clock signal line CK2S, the second control terminal of the shift register sub-circuit 110 is electrically connected to the third clock signal line CK3S, the third control terminal of the shift register sub-circuit 110 is electrically connected to the first clock signal line CK1S, and the second control terminal of the output sub-circuit 120 is electrically connected to the second intermittent clock signal line XCK2S. That is, the second clock signal line CK2S provides the first control clock signal CK1 to the second driver circuit 102, the third clock signal line CK3S provides the second control clock signal CK2 to the second driver circuit 102, the first clock signal line CK1S provides the third control clock signal CK3 to the second driver circuit 102, and the second intermittent clock signal line XCK2S provides the intermittent clock signal XCK to the second driver circuit 102.

[0078] In the third driver circuit 103, the first control terminal of the shift register sub-circuit 110 is electrically connected to the third clock signal line CK3S, the second control terminal of the shift register sub-circuit 110 is electrically connected to the first clock signal line CK1S, the third control terminal of the shift register sub-circuit 110 is electrically connected to the second clock signal line CK2S, and the second control terminal of the output sub-circuit 120 is electrically connected to the third intermittent clock signal line XCK3S. That is, the third clock signal line CK3S provides the first control clock signal CK1 to the third driver circuit 103, the first clock signal line CK1S provides the second control clock signal CK2 to the third driver circuit 103, the second clock signal line CK2S provides the third control clock signal CK3 to the third driver circuit 103, and the third intermittent clock signal line XCK3S provides the intermittent clock signal XCK to the second driver circuit 103.

[0079] In all the cascaded driving circuits 100, the start control terminal of the shift register sub-circuit 110 of the first-stage driving circuit 100 is electrically connected to the start control signal line STVS, and the output terminal of the shift register sub-circuit 110 of the previous-stage driving circuit 100 is electrically connected to the start control terminal of the shift register sub-circuit 110 of the next-stage driving circuit 100. Figure 13When the illustrated first driver circuit 101 is a first-stage driver circuit 100, the first driver circuit 101 is electrically connected to a start-up control signal line STVS. The start-up control signal line STVS provides a start-up control signal STV to the first-stage driver circuit 100 (e.g., the first driver circuit 101). Furthermore, in the first to third driver circuits 101 to 103, the output of the shift register sub-circuit 110 of the first driver circuit 101 provides the start-up control signal STV to the second driver circuit 102, and the output of the shift register sub-circuit 110 of the second driver circuit 102 provides the start-up control signal STV to the third driver circuit 103, and so on.

[0080] Continue as Figure 13 As shown, the driving circuit 100 provided in the embodiment of the present application may further include a scanning reset module 115, wherein the scanning circuit 10 also includes a reset control signal line QSTS, and the reset control signal line QSTS is electrically connected to the gate of the eleventh transistor M11 of all driving circuits 100 to provide a reset control signal QST for all driving circuits 100.

[0081] Based on the same inventive concept, the embodiment of the present application further provides a scanning method, which is used for the scanning circuit 10 provided in any of the above embodiments. The scanning method provided in the embodiment of the present application includes: controlling the plurality of cascaded driving circuits 100 to output the first level step by step, wherein the time interval between the outputs of the first level by two adjacent cascaded driving circuits 100 includes: the effective level duration of the interval clock signal XCK connected to the previous stage driving circuit 100. Figure 13 The schematic diagram of the scanning circuit 10 and Figure 14 The scanning process of the scanning circuit 10 provided in the embodiment of the present application is described in detail with reference to the schematic timing diagram. The scanning process of the repeating unit 11 in the scanning circuit 10 includes the first stage D1 to the eighth stage D8. Figure 13 The first to third driving circuits 101 to 103 shown correspond to the first to third driving circuits 100 in the cascaded driving circuit 100, respectively, and are described by taking the example that the active level of the reset control signal QST overlaps with the reset phase T1 of the first driving circuit 100.

[0082] In the first stage, D1:

[0083] The first phase D1 corresponds to the scan reset phase T1' and the reset phase T1 of the first driver circuit 101. In the first driver circuit 101, the eleventh transistor M11 and the twelfth transistor M12 are turned on, connecting the first level terminal VG1 to the first node N1. Furthermore, the first transistor M1 is turned on, connecting the second level terminal VG2 to the second node N2. The second level of the second node N2 controls the second transistor M2 to turn on. Since the gate of the third transistor M3 is connected to the second level of the second level terminal VG2 and is in a normally-on state, the second transistor M2 and the third transistor M3 connect the first level terminal VG1 to the first node N1. Simultaneously, the second level of the second node N2 controls the fourth transistor M4 to turn on, connecting the first level terminal VG1 to the output terminal of the shift register sub-circuit 110. OUTY1 indicates that the shift register sub-circuit 110 of the first driver circuit 101 outputs the first level. At this time, the second capacitor C2 is maintained by the storage voltage to control the conduction of the sixteenth transistor M16 and the eighteenth transistor M18. The eighteenth transistor M18 transmits the second level of the second level terminal VG2 to the gate of the nineteenth transistor M19, controls the conduction of the nineteenth transistor M19, and connects the second level terminal VG2 with the output terminal of the output sub-circuit 120. OUTS1 indicates that the output sub-circuit 120 of the first driving circuit 101 outputs the second level.

[0084] In the second stage D2:

[0085] The second phase D2 corresponds to the start-up phase T2 of the first driver circuit 101 and the reset phase T1 of the second driver circuit 102. In the first driver circuit 101, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 are turned on. Since the gate of the ninth transistor M9 is connected to the second level of the second level terminal VG2 and is in a normally-on state, the fifth transistor M5, the sixth transistor M6, and the ninth transistor M9 connect the second level terminal VG2 to the first node N1, and the eighth transistor M8 connects the first level terminal VG1 to the second node N2. The second level of the first node N1 can control the seventh transistor M7 and the tenth transistor M10 to be turned on. The seventh transistor M7 connects the first level terminal VG1 to the second node N2, and the tenth transistor M10 transmits the first control clock signal CK1 to the output terminal of the shift register sub-circuit 110. OUTY1 indicates that the output of the shift register sub-circuit 110 of the first driver circuit 101 is the inactive level of the first control clock signal CK1 at this time. At this time, the second capacitor C2 is maintained by the storage voltage to control the conduction of the sixteenth transistor M16 and the eighteenth transistor M18. The eighteenth transistor M18 transmits the second level of the second level terminal VG2 to the gate of the nineteenth transistor M19, controls the conduction of the nineteenth transistor M19, and connects the second level terminal VG2 with the output terminal of the output sub-circuit 120. OUTS1 indicates that the output sub-circuit 120 of the first driving circuit 101 outputs the second level.

[0086] In the second driving circuit 102: the eleventh transistor M11 and the twelfth transistor M12 are turned on, and the eleventh transistor M11 and the twelfth transistor M12 connect the first level terminal VG1 to the first node N1; and the first transistor M1 is turned on, connecting the second level terminal VG2 to the second node N2. The second level of the second node N2 can control the second transistor M2 to be turned on. Since the gate of the third transistor M3 is connected to the second level of the second level terminal VG2 and is in a normally-on state, the second transistor M2 and the third transistor M3 connect the first level terminal VG1 to the first node N1; at the same time, the second level of the second node N2 controls the fourth transistor M4 to be turned on, and the fourth transistor M4 connects the first level terminal VG1 to the output terminal of the shift register sub-circuit 110. OUTY2 indicates that the shift register sub-circuit 110 of the second driving circuit 102 outputs the first level. At this time, the second capacitor C2 is maintained by the storage voltage to control the conduction of the sixteenth transistor M16 and the eighteenth transistor M18. The eighteenth transistor M18 transmits the second level of the second level terminal VG2 to the gate of the nineteenth transistor M19, controls the conduction of the nineteenth transistor M19, and connects the second level terminal VG2 with the output terminal of the output sub-circuit 120. OUTS2 indicates that the output sub-circuit 120 of the second driving circuit 102 outputs the second level.

[0087] In the third stage D3:

[0088] The third phase D3 corresponds to the output phase T3 of the first driver circuit 101, the start-up phase T2 of the second driver circuit 102, and the reset phase T1 of the third driver circuit 103. In the first driver circuit 101, the first control clock signal CK1 is at an active level. At this time, the first capacitor C1 maintains the control of the tenth transistor M10, which is turned on. The tenth transistor M10 transmits the first control clock signal CK1 to the output terminal of the shift register sub-circuit 110. OUTY1 indicates that the output of the shift register sub-circuit 110 of the first driver circuit 101 is the active level of the first control clock signal CK1 at this time. The effective level of the first control clock signal CK1 output by the shift register sub-circuit 110 can control the thirteenth transistor M13, the fourteenth transistor M14 and the fifteenth transistor M15 to be turned on. The thirteenth transistor M13 transmits the first level of the first level terminal VG1 to the gate of the nineteenth transistor M19, and controls the nineteenth transistor M19 to be turned off; the fourteenth transistor M14 and the fifteenth transistor M15 connect the first level terminal VG1 with the output terminal of the output sub-circuit 120, and OUTS1 indicates that the output sub-circuit 120 of the first driving circuit 101 outputs the first level.

[0089] In the second driving circuit 102, the fifth transistor M5, the sixth transistor M6, and the eighth transistor M8 are turned on. Since the gate of the ninth transistor M9 is connected to the second level of the second level terminal VG2 and is in a normally-on state, the fifth transistor M5, the sixth transistor M6, and the ninth transistor M9 connect the second level terminal VG2 and the first node N1, and the eighth transistor M8 connects the first level terminal VG1 and the second node N2. The second level of the first node N1 can control the seventh transistor M7 and the tenth transistor M10 to be turned on. The seventh transistor M7 connects the first level terminal VG1 and the second node N2, and the tenth transistor M10 transmits the first control clock signal CK1 to the output terminal of the shift register sub-circuit 110. OUTY2 indicates that the output of the shift register sub-circuit 110 of the second driving circuit 102 is the inactive level of the first control clock signal CK1 at this time. At this time, the second capacitor C2 is maintained by the storage voltage to control the conduction of the sixteenth transistor M16 and the eighteenth transistor M18. The eighteenth transistor M18 transmits the second level of the second level terminal VG2 to the gate of the nineteenth transistor M19, controls the conduction of the nineteenth transistor M19, and connects the second level terminal VG2 with the output terminal of the output sub-circuit 120. OUTS2 indicates that the output sub-circuit 120 of the second driving circuit 102 outputs the second level.

[0090] In the third driving circuit 103, the eleventh transistor M11 and the twelfth transistor M12 are turned on, connecting the first level terminal VG1 and the first node N1. Furthermore, the first transistor M1 is turned on, connecting the second level terminal VG2 and the second node N2. The second level of the second node N2 can control the second transistor M2 to be turned on. Since the gate of the third transistor M3 is connected to the second level of the second level terminal VG2 and is in a normally-on state, the second transistor M2 and the third transistor M3 connect the first level terminal VG1 and the first node N1. Simultaneously, the second level of the second node N2 controls the fourth transistor M4 to be turned on, connecting the first level terminal VG1 to the output terminal of the shift register sub-circuit 110. OUTY3 indicates that the shift register sub-circuit 110 of the third driving circuit 103 outputs the first level. At this time, the second capacitor C2 is maintained by the storage voltage to control the conduction of the sixteenth transistor M16 and the eighteenth transistor M18. The eighteenth transistor M18 transmits the second level of the second level terminal VG2 to the gate of the nineteenth transistor M19, controls the conduction of the nineteenth transistor M19, and connects the second level terminal VG2 with the output terminal of the output sub-circuit 120. OUTS3 indicates that the output sub-circuit 120 of the third driving circuit 103 outputs the second level.

[0091] In the fourth stage D4:

[0092] The fourth stage D4 corresponds to the end stage T4 of the first driver circuit 101. In the first driver circuit 101, the first control clock signal CK1 is at an inactive level. At this time, the first capacitor C1 maintains the control of the tenth transistor M10, which transmits the first control clock signal CK1 to the output terminal of the shift register sub-circuit 110. OUTY1 indicates that the output of the shift register sub-circuit 110 of the first driver circuit 101 is the inactive level of the first control clock signal CK1 at this time. The interval clock signal XCK is at an active level, which controls the seventeenth transistor M17 to be conductive. The seventeenth transistor M17 transmits the second level of the second level terminal VG2 to the gate of the nineteenth transistor M19, controlling the nineteenth transistor M19 to be conductive. The nineteenth transistor M19 connects the second level terminal VG2 to the output terminal of the output sub-circuit 120. OUTS1 indicates that the output sub-circuit 120 of the first driver circuit 101 outputs the second level.

[0093] In the fifth stage D5:

[0094] The fifth phase D5 corresponds to the output phase T3 of the second driver circuit 102 and the start-up phase T2 of the third driver circuit 103. The output phase T3 of the second driver circuit 102 and the start-up phase T2 of the third driver circuit 103 operate in the same manner as the output phase T3 and the start-up phase T2 of the first driver circuit 101 described above, and are therefore not further described here. For example, OUTS2 indicates that the output sub-circuit 120 of the second driver circuit 102 outputs a first level; OUTY2 indicates that the shift register sub-circuit 110 of the second driver circuit 102 outputs the active level of the first control clock signal CK1 at this time. Furthermore, OUTS3 indicates that the output sub-circuit 120 of the third driver circuit 103 outputs a second level; OUTY2 indicates that the shift register sub-circuit 110 of the second driver circuit 101 outputs the inactive level of the first control clock signal CK1 at this time. It can be seen that the time interval between two adjacent cascaded driving circuits 100 outputting the first level includes: the effective level duration of the interval clock signal XCK connected to the driving circuit 100 of the previous stage; for example, the time interval between the first driving circuit 101 and the second driving circuit 102 outputting the first level includes: the effective level duration of the interval clock signal XCK provided by the first interval clock signal line XCK1S to the first driving circuit 101.

[0095] On D6 of the sixth stage:

[0096] The sixth stage D6 corresponds to the end stage T4 of the second driver circuit 102. The operation process of the end stage T4 of the second driver circuit 102 is consistent with the end stage T4 of the first driver circuit 101 described above, and therefore is not further described here. OUTY2 indicates that the shift register sub-circuit 110 of the second driver circuit 102 outputs the inactive level of the first control clock signal CK1 at this time, and OUTS2 indicates that the output sub-circuit 120 of the second driver circuit 102 outputs the second level.

[0097] On D7 of the seventh stage:

[0098] The seventh stage D7 corresponds to the output stage T3 of the third driver circuit 103. The operation of the output stage T3 of the third driver circuit 103 is consistent with the output stage T3 of the first driver circuit 101 described above, so a detailed description is omitted here. OUTS3 indicates that the output sub-circuit 120 of the third driver circuit 103 outputs the first level; OUTY3 indicates that the shift register sub-circuit 110 of the third driver circuit 103 outputs the active level of the first control clock signal CK1 at this time. It can be seen that the time interval during which the second driver circuit 102 and the third driver circuit 103 output the first level includes the active level duration of the interval clock signal XCK provided by the second interval clock signal line XCK2S to the second driver circuit 102.

[0099] On D8 of the eighth stage:

[0100] The eighth stage D8 corresponds to the end stage T4 of the third driver circuit 103. The operation process of the end stage T4 of the third driver circuit 103 is consistent with the end stage T4 of the first driver circuit 101 described above, and therefore is not further described here. OUTY3 indicates that the shift register sub-circuit 110 of the third driver circuit 103 outputs the inactive level of the first control clock signal CK1 at this time, and OUTS3 indicates that the output sub-circuit 120 of the third driver circuit 103 outputs the second level.

[0101] refer to Figure 15 As shown, it is another timing diagram provided by an embodiment of the present application. In one driving cycle of the driving circuit, there is a preset time gap Ty between the effective level of the first control clock signal CK1 and the effective level of the interval clock signal XCK; in the preset time gap Ty, the shift register subcircuit 110 outputs the invalid level of the first control clock signal CK1, and the output subcircuit 120 keeps outputting the first level. In addition, the time interval for the output subcircuit 120 of the two adjacent driving circuits 100 to output the first level is: the first time tx1 between the end moment of the effective level of the first control clock signal CK1 connected to the upper-level driving circuit 100 and the start moment of the effective level of the first control clock signal CK1 connected to the lower-level driving circuit 100, and the difference tx1-tx2 between the time tx2 of the preset time gap Ty. Combined Figure 14 and Figure 15As shown, in the first driver circuit 101, there is a preset time interval Ty between the active level provided by the first clock signal line CK1S and the active level provided by the first interval clock signal line XCK1S. During the preset time interval Ty between the third stage D3 and the fourth stage D4, the first clock signal line CK1S is at an inactive level. At this time, the first capacitor C1 controls the tenth transistor M10 to be turned on, and the tenth transistor M10 transmits the inactive level provided by the first clock signal line CK1S to the output of the shift register sub-circuit 110. OUTY1 indicates that the output of the shift register sub-circuit 110 of the first driver circuit 101 is the inactive level of the first clock signal line CK1S at this time. The second capacitor C2 controls the nineteenth transistor M19 to be turned off, while maintaining the output level of the output sub-circuit 120 in phase with the first level. OUTS1 indicates that the output sub-circuit 120 of the first driver circuit 101 outputs the first level. Similarly, in the second driver circuit 102, during the preset time interval Ty between the fifth stage D5 and the sixth stage D6, OUTY2 indicates that the shift register sub-circuit 110 of the second driver circuit 102 outputs an inactive level on the second clock signal line CK2S, and OUTS2 indicates that the output sub-circuit 120 of the second driver circuit 102 outputs a first level. Furthermore, in the third driver circuit 103, during the preset time interval Ty between the seventh stage D7 and the eighth stage D8, OUTY3 indicates that the shift register sub-circuit 110 of the third driver circuit 103 outputs an inactive level on the third clock signal line CK3S, and OUTS3 indicates that the output sub-circuit 120 of the third driver circuit 103 outputs a first level. It can be seen that the driving circuit 100 provided in the embodiment of the present application can realize the phase conversion control from the effective level of the first control clock signal CK1 output by the shift register subcircuit 110 to the first level output by the output subcircuit 120, and realize the end time control of the first level output by the output subcircuit 120 based on the control of the interval clock signal XCK, and realize the purpose of adjusting the pulse width of the first level output by the output subcircuit 120 by optimizing the interval clock signal XCK, and realize the purpose of adjusting the interval of the output of the first level by the output subcircuit 120 of the adjacent driving circuit 100 in the scanning circuit 10. Based on the same inventive concept, the embodiment of the present application also provides a display device 1000, which includes the scanning circuit 10 provided by any of the above embodiments. Figure 16 FIG. 1 is a schematic diagram of a structure of a display device provided in an embodiment of the present application, wherein the display device 1000 includes a scanning circuit 10 provided in any of the above embodiments, and the scanning circuit 10 can be arranged on one side of the display device 1000. Figure 17 In the display device 1000 shown, a scanning circuit 10 is disposed on two opposite sides of the display device 1000 , and this application does not impose any specific limitation on this.

[0102] refer to Figure 18 As shown, it is a structural schematic diagram of another display device provided in an embodiment of the present application. The display device 1000 provided in an embodiment of the present application includes a scanning circuit 10; and a fingerprint recognition circuit 20 electrically connected to the scanning circuit 10. Among them, the scanning circuit 10 can be used to provide a corresponding scanning signal to the fingerprint recognition circuit 20. The fingerprint recognition circuit 20 may include multiple rows of circuit modules, and each row of circuit modules may be electrically connected to a first-level driving circuit 100 in the scanning circuit 10. This is the same as the existing connection method, and this application will not elaborate on this. In addition, in other embodiments of the present application, the scanning circuit 20 can also be used to provide corresponding scanning signals for other applicable circuits, and this application does not impose specific restrictions on this.

[0103] In some embodiments, the display device 1000 provided in the embodiment of the present application can be a large or small device such as a mobile terminal, a notebook, a tablet computer, a computer, a wearable device, etc., and this application does not make any specific restrictions on this.

[0104] In summary, the embodiments of the present application provide a driving circuit and driving method, a scanning circuit and scanning method, and a display device. The driving circuit includes a shift register subcircuit and an output subcircuit, wherein the first control terminal of the output subcircuit is electrically connected to the output terminal of the shift register subcircuit, the second control terminal of the output subcircuit receives an interval clock signal, the first input terminal of the output subcircuit is electrically connected to the first level terminal, and the second input terminal of the output subcircuit is electrically connected to the second level terminal; the output subcircuit outputs the first level based on the effective level of the first control clock signal output by the shift register subcircuit, and outputs the second level at the second level terminal based on the effective level of the interval clock signal. The driving circuit provided in the embodiments of the present application implements phase conversion control from the effective level of the first control clock signal output by the shift register subcircuit to the first level output by the output subcircuit, and implements end time control of the first level output by the output subcircuit based on control of the interval clock signal. Thus, by optimizing the interval clock signal, the pulse width of the first level output by the output subcircuit of the driving circuit can be adjusted, and the interval between the output subcircuits of adjacent driving circuits in the scanning circuit can be adjusted. In addition, the technical solution provided in the embodiment of the present application is improved on the basis of the shift register sub-circuit. By adding an output sub-circuit connected to the output of the shift register sub-circuit, the relevant functions of the driving circuit can be realized, thereby reducing the design difficulty of the driving circuit.

[0105] In the description of the embodiments of the present application, it should be understood that the orientation or position relationship indicated by terms such as "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", and "circumferential" are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.

[0106] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the embodiments of the present application, the meaning of "plurality" is at least two, for example, two, three, etc., unless otherwise clearly specified.

[0107] In the embodiments of this application, unless otherwise specified or limited, terms such as "installed," "connected," "connected," and "fixed" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integration; mechanical connections, electrical connections, or communication between them; direct connections, indirect connections through an intermediate medium, and internal connections between two components or interactions between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0108] In the embodiments of the present application, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, a first feature being "above," "above," and "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0109] In the embodiments of the present application, if the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" appear, it means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction.

[0110] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A driving circuit, characterized in that: The driving circuit includes a shift register subcircuit and an output subcircuit; The first control terminal of the shift register subcircuit is connected to a first control clock signal, the second control terminal of the shift register subcircuit is connected to a second control clock signal, the third control terminal of the shift register subcircuit is connected to a third control clock signal, and the start control terminal of the shift register subcircuit is connected to a start control signal. The first input terminal of the shift register subcircuit is electrically connected to the first level terminal, and the second input terminal of the shift register subcircuit is electrically connected to the second level terminal. The shift register subcircuit outputs a first level at the first level terminal based on an effective level of the second control clock signal, outputs an inactive level of the first control clock signal based on effective levels of the third control clock signal and the start control signal, and then outputs an effective level of the first control clock signal. The first level and the second level of the second level terminal have opposite phases, and the effective level of the first control clock signal and the second level have the same phase. The first control terminal of the output subcircuit is electrically connected to the output terminal of the shift register subcircuit, the second control terminal of the output subcircuit receives the interval clock signal, the first input terminal of the output subcircuit is electrically connected to the first level terminal, and the second input terminal of the output subcircuit is electrically connected to the second level terminal; the output subcircuit outputs the first level based on the valid level of the first control clock signal output by the shift register subcircuit, and outputs the second level based on the valid level of the interval clock signal; In one driving cycle of the driving circuit, effective levels of the second control clock signal, the third control clock signal, the first control clock signal and the interval clock signal are arranged in time sequence.

2. The driving circuit according to claim 1, wherein: In one driving cycle of the driving circuit, there is a preset time gap between the effective level of the first control clock signal and the effective level of the interval clock signal.

3. The driving circuit according to claim 1, wherein: The shift register subcircuit includes: a circuit reset module, a start module, a first output module and a second output module, wherein the output ends of the first output module and the second output module are output ends of the shift register subcircuit; The circuit reset module receives the second control clock signal and is electrically connected to the first level terminal and the second level terminal; the circuit reset module controls the level of the first node to be the first level and the level of the second node to be the second level based on the effective level of the second control clock signal; The second output module is electrically connected to the first level terminal and the second node; the second output module outputs the first level based on the second level of the second node; The start-up module receives the third control clock signal and the start-up control signal, and is electrically connected to the first level end and the second level end; the start-up module controls the level of the first node to be the second level, and controls the level of the second node to be the first level based on the effective levels of the third control clock signal and the start-up control signal; The first output module receives the first control clock signal and is electrically connected to the first node; the first output module outputs an invalid level of the first control clock signal based on the second level of the first node, and then outputs a valid level of the first control clock signal.

4. The driving circuit according to claim 3, wherein: The circuit reset module includes a first transistor and a second transistor; The first terminal of the first transistor is electrically connected to the second level terminal, the second terminal of the first transistor is electrically connected to the second node, and the gate of the first transistor is connected to the second control clock signal; A first terminal of the second transistor is electrically connected to the first level terminal, a second terminal of the second transistor is electrically connected to the first node, and a gate of the second transistor is electrically connected to the second node.

5. The driving circuit according to claim 4, wherein: The circuit reset module further includes a third transistor, wherein the third transistor is connected in series between the second transistor and the first node; The first end of the third transistor is electrically connected to the second end of the second transistor, the second end of the third transistor is electrically connected to the first node, and the gate of the third transistor is electrically connected to the second level end.

6. The driving circuit according to claim 3, wherein: The second output module includes a fourth transistor; A first end of the fourth transistor is electrically connected to the first level end, a second end of the fourth transistor is an output end of the second output module, and a gate of the fourth transistor is electrically connected to the second node.

7. The driving circuit according to claim 3, wherein: The turn-on module includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; The first end of the fifth transistor is electrically connected to the second end of the sixth transistor, the second end of the fifth transistor is electrically connected to the first node, and the gate of the fifth transistor is connected to the third control clock signal; The first end of the sixth transistor is electrically connected to the second level end, and the gate of the sixth transistor is connected to the start control signal; A first terminal of the seventh transistor is electrically connected to the first level terminal, a second terminal of the seventh transistor is electrically connected to the second node, and a gate of the seventh transistor is electrically connected to the first node; A first end of the eighth transistor is electrically connected to the first level end, a second end of the eighth transistor is electrically connected to the second node, and a gate of the eighth transistor is connected to the start-up control signal.

8. The driving circuit according to claim 7, wherein: The start-up module further includes a ninth transistor, which is connected in series between the fifth transistor and the first node; A first terminal of the ninth transistor is electrically connected to the second terminal of the fifth transistor, a second terminal of the ninth transistor is electrically connected to the first node, and a gate of the ninth transistor is electrically connected to the second level terminal.

9. The driving circuit according to claim 3, wherein: The first output module includes a tenth transistor and a first capacitor; A first terminal of the tenth transistor is connected to the first control clock signal, a second terminal of the tenth transistor is an output terminal of the first output module, and a gate of the tenth transistor is electrically connected to the first node; The first plate of the first capacitor is electrically connected to the gate of the tenth transistor, and the second plate of the first capacitor is electrically connected to the second end of the tenth transistor.

10. The driving circuit according to claim 3, wherein: The shift register sub-circuit further includes: a scanning reset module, which receives a reset control signal and is electrically connected to the first level end; the scanning reset module controls the level of the first node to be the first level based on the effective level of the reset control signal.

11. The driving circuit according to claim 10, wherein: In one driving cycle of the driving circuit, the effective level of the reset control signal is prior to the effective level of the second control clock signal; or The starting time of the effective level of the reset control signal is earlier than the starting time of the effective level of the second control clock signal, and the effective level of the reset control signal and the effective level of the second control clock signal partially overlap in time sequence; or, An active level of the reset control signal and an active level of the second control clock signal overlap in time sequence.

12. The driving circuit according to claim 10, wherein: The scan reset module includes an eleventh transistor, a first end of the eleventh transistor is electrically connected to the first level end, a second end of the eleventh transistor is electrically connected to the first node, and a gate of the eleventh transistor is connected to the reset control signal.

13. The driving circuit according to claim 12, wherein: The scan reset module further includes a twelfth transistor, wherein the twelfth transistor is connected in series between the eleventh transistor and the first node; The first end of the twelfth transistor is electrically connected to the second end of the eleventh transistor, the second end of the twelfth transistor is electrically connected to the first node, and the gate of the twelfth transistor is electrically connected to the second level end.

14. The driving circuit according to claim 1, wherein: The output sub-circuit comprises: a pull-up output module and a pull-down output module, wherein the output ends of the pull-up output module and the pull-down output module are the output ends of the output sub-circuit; The pull-up output module is electrically connected to the output terminal of the shift register sub-circuit and the first level terminal; the pull-up output module outputs the first level based on the effective level of the first control clock signal output by the shift register sub-circuit; The pull-down output module receives the interval clock signal and is electrically connected to the second level end; the pull-down output module outputs the second level based on the effective level of the interval clock signal.

15. The driving circuit according to claim 14, wherein: The pull-up output module includes a thirteenth transistor, a fourteenth transistor and a fifteenth transistor; A first end of the thirteenth transistor is electrically connected to the first level end, a second end of the thirteenth transistor is electrically connected to the pull-down output module, and a gate of the thirteenth transistor is electrically connected to the output end of the shift register sub-circuit; A first terminal of the fourteenth transistor is electrically connected to the first level terminal, a second terminal of the fourteenth transistor is electrically connected to the first terminal of the fifteenth transistor, and a gate of the fourteenth transistor is electrically connected to the output terminal of the shift register sub-circuit; The second end of the fifteenth transistor is the output end of the pull-up output module, and the gate of the fifteenth transistor is electrically connected to the output end of the shift register sub-circuit.

16. The driving circuit according to claim 15, wherein: The pull-up output module further includes a sixteenth transistor; The first end of the sixteenth transistor is electrically connected to the second end of the fourteenth transistor, the second end of the sixteenth transistor is electrically connected to the second level end, and the gate of the sixteenth transistor is electrically connected to the second end of the fifteenth transistor.

17. The driving circuit according to claim 14, wherein: The pull-down output module includes a seventeenth transistor, an eighteenth transistor, a nineteenth transistor and a second capacitor; The first end of the seventeenth transistor is electrically connected to the second level end, the second end of the seventeenth transistor is electrically connected to the second end of the eighteenth transistor and the gate of the nineteenth transistor, and the gate of the seventeenth transistor is connected to the interval clock signal; The first end of the eighteenth transistor is electrically connected to the second level end, and the gate of the eighteenth transistor is electrically connected to the second end of the nineteenth transistor; The first end of the nineteenth transistor is electrically connected to the second level end, the second end of the nineteenth transistor is the output end of the pull-down output module, the first plate of the second capacitor is electrically connected to the gate of the nineteenth transistor, and the second plate of the second capacitor is electrically connected to the second end of the nineteenth transistor.

18. A driving method, characterized in that: Used to drive the driving circuit according to any one of claims 1 to 17, wherein one driving cycle of the driving method comprises a reset phase, a start phase, an output phase and an end phase performed in chronological order; In the reset phase, the shift register subcircuit outputs the first level of the first level end based on the valid level of the second control clock signal, and the output subcircuit outputs the second level of the second level end; In the start-up phase, the shift register sub-circuit outputs an inactive level of the first control clock signal based on the active levels of the third control clock signal and the start-up control signal, and the output sub-circuit outputs the second level; In the output stage, the shift register sub-circuit outputs the valid level of the first control clock signal, and the output sub-circuit outputs the first level based on the valid level of the first control clock signal output by the shift register sub-circuit; In the end phase, the shift register sub-circuit outputs an inactive level of the first control clock signal, and the output sub-circuit outputs the second level based on the active level of the interval clock signal.

19. The driving method according to claim 18, wherein: In one driving cycle of the driving circuit, there is a preset time gap between the effective level of the first control clock signal and the effective level of the interval clock signal; During the preset time interval, the shift register sub-circuit outputs an inactive level of the first control clock signal, and the output sub-circuit keeps outputting the first level.

20. A scanning circuit, characterized in that: The scanning circuit includes: a plurality of cascaded driving circuits, wherein the driving circuit is the driving circuit according to any one of claims 1 to 17.

21. The scanning circuit according to claim 20, wherein: The scanning circuit includes: a start control signal line, a first clock signal line, a second clock signal line, a third clock signal line, a first interval clock signal line, a second interval clock signal line, a third interval clock signal line and at least one repeating circuit unit; The second clock signal line, the third clock signal line, and the first clock signal line sequentially output valid levels in time sequence, and the i-th interval clock signal line outputs a valid level after the i-th clock signal line outputs a valid level, where i is a positive integer not greater than 3; The repeating unit includes three cascaded drive circuits, and is defined as a first drive circuit, a second drive circuit, and a third drive circuit that are cascaded in sequence; in the first drive circuit, a first control terminal of the shift register subcircuit is electrically connected to the first clock signal line, a second control terminal of the shift register subcircuit is electrically connected to the second clock signal line, a third control terminal of the shift register subcircuit is electrically connected to the third clock signal line, and a second control terminal of the output subcircuit is electrically connected to the first interval clock signal line; In the second driving circuit, the first control terminal of the shift register subcircuit is electrically connected to the second clock signal line, the second control terminal of the shift register subcircuit is electrically connected to the third clock signal line, the third control terminal of the shift register subcircuit is electrically connected to the first clock signal line, and the second control terminal of the output subcircuit is electrically connected to the second interval clock signal line; In the third driving circuit, the first control terminal of the shift register subcircuit is electrically connected to the third clock signal line, the second control terminal of the shift register subcircuit is electrically connected to the first clock signal line, the third control terminal of the shift register subcircuit is electrically connected to the second clock signal line, and the second control terminal of the output subcircuit is electrically connected to the third interval clock signal line; In all the cascaded driving circuits, the start control end of the shift register sub-circuit of the first-level driving circuit is electrically connected to the start control signal line, and the output end of the shift register sub-circuit of the previous-level driving circuit is electrically connected to the start control end of the shift register sub-circuit of the next-level driving circuit.

22. A scanning method, characterized in that: The scanning method is used in the scanning circuit according to claim 20 or 21, wherein the scanning method includes: The multiple cascaded driving circuits are controlled to output the first level step by step, wherein the time interval between two adjacent cascaded driving circuits outputting the first level includes: the effective level duration of the interval clock signal connected to the previous stage driving circuit.

23. The scanning method according to claim 22, characterized in that: In one driving cycle of the driving circuit, there is a preset time gap between the effective level of the first control clock signal and the effective level of the interval clock signal; During the preset time interval, the shift register sub-circuit outputs an inactive level of the first control clock signal, and the output sub-circuit keeps outputting the first level.

24. A display device, characterized in that: The display device includes the scanning circuit according to claim 20 or 21.

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