Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a plurality of sub-pixels and a pixel circuit connected with the sub-pixels. The driving circuit comprises a plurality of cascaded shift registers, and the shift registers are used for outputting primary scanning signals based on the clock signals; the gating circuits correspond to the shifting registers, the shifting registers are connected with the pixel circuits through the gating circuits, and the gating circuits provide scanning signals for the pixel circuits; the display area comprises a first sub-display area and a second sub-display area, and the data refreshing frequency of the first sub-display area is larger than that of the second sub-display area; in the first display mode, data refreshing is carried out on each sub display area; in the second display mode, the first sub-display area performs data refreshing, and the second sub-display area performs data retention; in the first display mode and the second display mode, the shift registers corresponding to the first sub-display area and the second sub-display area receive clock signals of the first clock frequency.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to a display panel and a display device. Background Art

[0002] With the advancement of science and technology, more and more electronic devices with display functions are being widely used in people's daily lives and work, bringing great convenience to people's daily lives and work, and becoming an indispensable tool for people today. The main component of electronic devices that realize the display function is the display panel. To meet users' demand for multi-scene display functions, display panels need to be able to display in different areas. Summary of the Invention

[0003] In view of the above problems, the present application provides a display panel and a display device to achieve the purpose of partitioned display on the display panel. The specific solution is as follows:

[0004] In a first aspect, the present application provides a display panel, comprising:

[0005] a plurality of sub-pixels and pixel circuits connected to the sub-pixels;

[0006] A driving circuit, the driving circuit comprising a plurality of cascaded shift registers, the shift registers being configured to output a primary scanning signal based on a clock signal;

[0007] A plurality of gating circuits, the gating circuits corresponding to the shift registers, and the shift registers connected to the pixel circuits through the gating circuits, the gating circuits providing scanning signals to the pixel circuits;

[0008] The display area includes a plurality of sub-display areas, the plurality of sub-display areas include a first sub-display area and a second sub-display area, and a data refresh frequency of the first sub-display area is greater than a data refresh frequency of the second sub-display area;

[0009] The display panel includes a first display mode and a second display mode; in the first display mode, each sub-display area performs data refresh; in the second display mode, the first sub-display area performs data refresh and the second sub-display area performs data retention;

[0010] In the first display mode and the second display mode, the shift registers corresponding to the first sub-display area and the second sub-display area both receive a clock signal of a first clock frequency.

[0011] A second aspect of the present application provides a display device comprising the above-mentioned display panel.

[0012] By utilizing the above technical solution, in the display panel and display device provided by this application, the shift register in the driving circuit is connected to the pixel circuit via the gating circuit. Thus, the pixel circuits in the first and second sub-display areas can each receive a scanning signal via the corresponding gating circuit. In the second display mode, the first and second sub-display areas can each receive scanning signals of different frequencies, enabling the display panel to achieve a partitioned display function with different data refresh frequencies. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0014] The structures, proportions, sizes, etc. depicted in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not intended to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modifications, changes in proportional relationships, or adjustments in size, without affecting the efficacy and objectives that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0015] Figure 1 A schematic structural diagram of a display panel provided in an embodiment of the present application;

[0016] Figure 2 A schematic structural diagram of a pixel circuit provided in an embodiment of the present application;

[0017] Figure 3 for Figure 2 The working timing diagram of the pixel circuit shown;

[0018] Figure 4 A schematic diagram of the layout principle of a driving circuit in a display panel provided in an embodiment of the present application;

[0019] Figure 5 A circuit diagram of a shift register and a first gating circuit connected thereto in a first driving circuit provided in an embodiment of the present application;

[0020] Figure 6 A circuit diagram of a shift register and a third gating circuit connected thereto in a third driving circuit provided in an embodiment of the present application;

[0021] Figure 7 A circuit diagram of a shift register in a fourth driving circuit provided in an embodiment of the present application;

[0022] Figure 8 A schematic diagram of the principle of partition display of a display panel provided in an embodiment of the present application;

[0023] Figure 9 for Figure 8 The timing diagram of the display panel shown in FIG.

[0024] Figure 10 A schematic diagram showing the principle of partition display of another display panel provided in an embodiment of the present application;

[0025] Figure 11 for Figure 10 The timing diagram of the display panel shown in FIG.

[0026] Figure 12 A timing diagram of a display panel in a third display mode provided by an embodiment of the present application;

[0027] Figure 13 A schematic structural diagram of another display panel provided in an embodiment of the present application;

[0028] Figure 14 A schematic structural diagram of a display device provided in an embodiment of the present application.

[0029] Reference numerals:

[0030] 100 - sub-pixel; 101 - first sub-display area; 102 - second sub-display area; 103 - pixel circuit; 104 - driving circuit; 1041 - first driving circuit; 1042 - second driving circuit; 1043 - third driving circuit; 1044 - fourth driving circuit; 1045 - fifth driving circuit; 105 - shift register; 106 - gating circuit; 1061 - first gating circuit; 1062 - second gating circuit; 1063 - third gating circuit; 107 - control chip; 108 - display device; AA - display area; PVDD - first power supply signal; PVEE - second power supply signal; T1 - first control chip Body transistor; T2-data writing transistor; T3-driving transistor; T4-threshold compensation transistor; T5-first reset transistor; T6-second control transistor; T7-second reset transistor; T8-bias adjustment transistor; Cst-storage capacitor; VREF1-first reset voltage; VREF2-second reset voltage; VDATA-data signal; DVH-bias adjustment signal; N1-first node; N2-second node; N3-third node; N4-fourth node; S1N-first scan signal; S2N-second scan signal; SP-third scan signal; SP*-fourth scan signal; EM-luminescence control signal. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments of the present application. Those skilled in the art will know that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0032] Obviously, the embodiments described are only some of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts are within the scope of protection of this application. The terms used in the embodiments of this application are only used to explain the specific embodiments of this application, and are not intended to limit this application.

[0033] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] refer to Figure 1 , Figure 1 A schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown, wherein the display panel includes:

[0035] A plurality of sub-pixels 100 and a pixel circuit 103 connected to the sub-pixels 100;

[0036] A driving circuit 104, the driving circuit 104 includes a plurality of cascaded shift registers 105, and the shift registers 105 are used to output a primary scanning signal based on a clock signal;

[0037] A plurality of gating circuits 106 , the gating circuits 106 corresponding to the shift registers 105 , and the shift registers 105 are connected to the pixel circuits 103 via the gating circuits 106 , and the gating circuits 106 provide scanning signals to the pixel circuits 103 ;

[0038] Display area AA, display area AA includes multiple sub-display areas, the multiple sub-display areas include a first sub-display area 101 and a second sub-display area 102, and the data refresh frequency of the first sub-display area 101 is greater than the data refresh frequency of the second sub-display area 102;

[0039] The display panel includes a first display mode and a second display mode; in the first display mode, each sub-display area performs data refresh; in the second display mode, the first sub-display area 101 performs data refresh and the second sub-display area 102 performs data retention;

[0040] In the first display mode and the second display mode, the shift registers 105 corresponding to the first sub-display area 101 and the second sub-display area 102 both receive a clock signal of the first clock frequency.

[0041] In the display panel, the gating circuit 106 and shift register 105 corresponding to the pixel circuits 103 in the sub-display area can provide a scanning signal of the required frequency to control the data refresh frequency of the sub-display area, so that the display area AA is formed into multiple sub-display areas. Each row of pixel circuits 103 in the same sub-display area is connected to the scanning signal of the same frequency. If the two sub-displays have different data refresh frequencies, the pixel circuits 103 in the two sub-display areas are connected to the scanning signals of different frequencies.

[0042] In the embodiment of the present application, the shift register 105 in the driving circuit 104 is connected to the pixel circuit 103 via the gating circuit 106. In this way, the pixel circuits 103 in the first sub-display area 101 and the second sub-display area 102 can each be provided with a scanning signal via the corresponding gating circuit 106. The first sub-display area 101 and the second sub-display area 102 can each receive scanning signals of different frequencies in the second display mode, and the display panel can implement a partitioned display function with different data refresh frequencies.

[0043] The pixel circuit 103 includes a plurality of interconnected transistors, Figure 1 The pixel circuit 103 is simply illustrated by using a transistor. The pixel circuit can adopt a 7T1C (a circuit structure of 7 transistors and 1 capacitor), or an 8T1C (a circuit structure of 8 transistors and 1 capacitor), or other circuit structures. The embodiment of the present application does not limit the structure of the pixel circuit 103.

[0044] refer to Figure 2 and Figure 3 , Figure 2 This is a schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application. Figure 3 for Figure 2 The pixel circuit 103 includes a driving transistor T3 configured to transmit a driving current to the sub-pixel 100; a first reset transistor T5 having a first electrode electrically connected to the gate of the driving transistor T3, the gate of which is configured to receive a first scanning signal S1N; and a threshold compensation transistor T4 having a first electrode electrically connected to the first electrode of the driving transistor T3, a second electrode electrically connected to the gate of the driving transistor T3, and the gate of which is configured to receive a second scanning signal S2N.

[0045] The gate of the driving transistor T3 is connected to the first node N1, the first electrode is connected to the third node N3, and the second electrode is connected to the second node N2. The second electrode of the first reset transistor T5 receives the first reset voltage VREF1. For the same transistor, one of the first electrode and the second electrode is the source of the transistor, and the other is the drain of the transistor.

[0046] The pixel circuit 103 further includes a data writing transistor T2 , a first electrode of which is electrically connected to a second electrode of the driving transistor T3 , a gate of which receives a third scanning signal SP, and a second electrode of which receives a data signal VDATA.

[0047] The pixel circuit 103 further includes a first control transistor T1 and a second control transistor T6. The first control transistor T1 has a first electrode that receives a first power signal PVDD, a second electrode that is connected to a second node N2, and a gate that receives a light emission control signal EM. The second control transistor T6 has a first electrode that is connected to a third node N3, a second electrode that is connected to a fourth node N4, and a gate that receives a light emission control signal EM. The sub-pixel 100 may be an OLED, with an anode electrode of the sub-pixel 100 connected to the fourth node N4 and a cathode electrode that receives a second power signal PVEE. The first power signal PVDD may be at a high level, and the second power signal PVEE may be at a low level.

[0048] The pixel circuit 103 further includes a second reset transistor T7 , wherein a first electrode of the second reset transistor T7 receives a second reset voltage VREF2 , a second electrode is connected to the fourth node N4 , and a gate of the second reset transistor T7 receives a fourth scan signal SP*.

[0049] The pixel circuit 103 further includes a storage capacitor Cst. The storage capacitor Cst is connected between the first node N1 and the first electrode of the first control transistor T1.

[0050] The pixel circuit 103 further includes a bias adjustment transistor T8 , wherein a first electrode of the bias adjustment transistor T8 is connected to the second node N2 , a second electrode receives the bias adjustment signal DVH , and a gate receives the fourth scan signal SP*.

[0051] exist Figure 2 In the pixel circuit 103 shown, the first reset transistor T5 and the threshold compensation transistor T4 can be NMOS made of IGZO, and the other transistors can be PMOS made of LTPS. The working timing of the pixel circuit 103 is as follows: Figure 3 As shown, a working cycle of the pixel circuit 103 includes four stages, which are a reset stage t1 , a threshold compensation and data writing stage t2 , a bias adjustment stage t3 and a light emitting stage t4 .

[0052] In the reset phase t1 , the first scan signal S1N is at a high level, the first reset transistor T5 is turned on, and the voltage of the first node N1 is reset based on the first reset voltage VREF1 .

[0053] During the threshold compensation and data writing phase t2, the voltage at the first node N1 is the first reset voltage VREF1, turning on the driving transistor T3 and raising the voltage on the driving transistor T3 until the driving transistor T3 turns off. When the driving transistor T3 turns off, the gate voltage is VDATA + Vth, where Vth is the threshold voltage of the driving transistor T3. During this phase, the second scan signal S2N is at a high level, turning on the threshold compensation transistor T4 to perform threshold compensation on the driving transistor T3. When the third scan signal SP is at a low level, the data writing transistor T2 is turned on to write the data signal VDATA to the first node N1.

[0054] In the bias adjustment phase t3, the fourth scan signal SP* is at a low level, so that the bias adjustment transistor T8 is turned on to adjust the bias state of the driving transistor T3. In this phase, the second reset transistor T7 is also turned on to reset the fourth node N4 through the second reset voltage VREF2.

[0055] In the light emitting stage t4 , the light emitting control signal switches to a low level, so that the first control transistor T1 and the second control transistor T7 form a driving current, and transmit the driving current to the fourth node N4 to control the sub-pixel 100 to emit light.

[0056] Figure 2 and Figure 3 The operating timing of the pixel circuit 103 is described with reference to the 8T1C circuit structure. The operating timing of pixel circuits 103 with other structures can be set according to the pixel circuit structure, and will not be further described in the present embodiment. For example, the pixel circuit can have a 7T1C circuit structure that does not include the bias adjustment transistor T8. In this case, the operating cycle of the pixel circuit 103 does not include the bias adjustment phase t3.

[0057] Optionally, the scanning signal provided by the driving circuit 104 to the pixel circuit 103 through the gating circuit 106 includes at least one of the first scanning signal S1N to the fourth scanning signal SP*.

[0058] Unlike conventional display panels that directly provide various scanning signals to the pixel circuit 103 through the driving circuit 104, in the embodiment of the present application, the driving circuit 104 provides the first scanning signal S1N to the third scanning signal SP to the pixel circuit 103 through the gating circuit 106. Based on the gating circuit 106, the frequency of each scanning signal can be adjusted, thereby dividing the display area AA into multiple sub-display areas, and making each sub-display area have the required data refresh frequency.

[0059] refer to Figure 4 , Figure 4This is a schematic diagram illustrating the layout principle of a drive circuit in a display panel provided in an embodiment of the present application. The drive circuit 104 includes a first drive circuit 1041 and a second drive circuit 1042. The first drive circuit 1041 is configured to output a first primary scanning signal based on a first set of clock signals. The second drive circuit 1042 is configured to output a second primary scanning signal based on a second set of clock signals. The first set of clock signals and the second set of clock signals may each include two clock signals with opposite phases. The two clock signals in the first set of clock signals may be a first clock signal SN_CK and a second clock signal SN_XCK.

[0060] The gating circuit 106 includes a first gating circuit 1061 and a second gating circuit 1062. The first driving circuit 1041 is connected to the corresponding pixel circuit 103 via the first gating circuit 1061, and the second driving circuit 1042 is connected to the corresponding pixel circuit 103 via the second gating circuit 1062. The first gating circuit 1061 is configured to provide a first scanning signal S1N to the pixel circuit 103 based on a first control signal Ctrl1. The second gating circuit 1062 is configured to provide a second scanning signal S2N to the pixel circuit 103 based on a second control signal Ctrl2.

[0061] like Figure 4 As shown, the driving circuit 104 further includes a third driving circuit 1043, which is configured to output a third primary scanning signal based on a third set of clock signals. The third set of clock signals may include two clock signals with opposite phases. The two clock signals in the third set of clock signals may be a third clock signal SP_CK and a fourth clock signal SP_XCK.

[0062] The gating circuit 106 further includes a third gating circuit 1063 . The third driving circuit 1043 is connected to the corresponding pixel circuit 103 via the third gating circuit 1063 . The third gating circuit 1063 is configured to provide a third scanning signal SP to the pixel circuit 103 based on a third control signal Ctrl3 .

[0063] In order to reduce the border width, the driving circuit 104 can be divided into two parts. The two opposite sides of the display area AA in the row direction are respectively the first border area (such as Figure 4 The non-display area on the left side of the middle display area AA) and the second frame area (such as Figure 4 The two driving circuits 104 may be disposed in the first frame area and the second frame area, respectively.

[0064] Display area AA includes multiple rows of pixel circuits 103. One of the first drive circuit 1041 and the second drive circuit 1042 is located in the first border area, and the other is located in the second border area. Each shift register in the first drive circuit 1041 is connected to a corresponding row of pixel circuits 103 through a first selection circuit 1061.

[0065] Each shift register stage in the first driving circuit 1041 is connected to two rows of pixel circuits 103 via a first gating circuit 1061, i.e., each shift register stage in the first driving circuit 1041 drives two rows of pixel circuits 103. Each shift register stage in the second driving circuit 1042 is connected to two rows of pixel circuits 103 via a second gating circuit 1062, i.e., each shift register stage in the second driving circuit 1042 drives two rows of pixel circuits 103.

[0066] The multiple shift registers in the third driver circuit 1043 are divided into two groups. One group of shift registers in the third driver circuit 1043 is located in the first border area, and each shift register is connected to a row of pixel circuits 103 via a third gating circuit 1063, that is, each shift register drives a row of pixel circuits 103. Another group of shift registers in the third driver circuit 1043 is located in the second border area, and each shift register is connected to a row of pixel circuits 103 via a third gating circuit 1063, that is, each shift register drives a row of pixel circuits 103. In this manner, the two ends of each row of pixel circuits 103 can be connected to a shift register of the third driver circuit 1043 located in the first border area and to a shift register of the third driver circuit 1043 located in the second border area via a third gating circuit 1063, respectively, which can improve the driving capability of the third driver circuit 1043 for the pixel circuits 103.

[0067] The driving circuit includes a fifth driving circuit 1045 for providing a light-emitting control signal EM and a fourth scanning signal SP*. One of the fifth driving circuit 1045 and the fourth driving circuit 1044 can be located in the first border area, and the other can be located in the second border area to reduce the border width. In other embodiments, the two can also be located in the same side border area. The fifth driving circuit 1045 and the fourth driving circuit 1044 each include a plurality of shift registers. Each shift register in the fifth driving circuit 1045 and the fourth driving circuit 1044 can be directly connected to the pixel circuit 103 without being connected to the selection circuit 106.

[0068] Each stage of the shift registers in the fourth driving circuit 1044 can be connected to two rows of pixel circuits 103, respectively. That is, each stage of the shift registers in the fourth driving circuit 1044 drives two rows of pixel circuits 103. Each stage of the shift registers in the fifth driving circuit 1045 can be connected to two rows of pixel circuits 103, respectively. That is, each stage of the shift registers in the fifth driving circuit 1045 drives two rows of pixel circuits 103.

[0069] refer to Figure 5 , Figure 5 A circuit diagram of a shift register in a first driving circuit and a first gating circuit connected thereto provided in an embodiment of the present application.

[0070] like Figure 5 As shown, the shift register in the first driving circuit 1041 includes fifteen transistors and three capacitors. The fifteen transistors are sequentially M1 to M15, and the three capacitors are sequentially CN1 to CN3. The output terminal of the shift register in the first driving circuit 1041 is OUT SN0 , for outputting a first primary scanning signal. The shift register in the first driving circuit 1041 generates the first primary scanning signal based on the first input signal STV1, the first clock signal SN_CK, the second clock signal SN_XCK, the high level VGH, and the low level VGL.

[0071] like Figure 5 As shown, each level of the shift register in the first driving circuit 1041 is connected to a first gating circuit 1061. The first gating circuit 1061 includes five transistors and three capacitors. The five transistors are sequentially M16 to M20, and the three capacitors are sequentially CN4 to CN6. The output terminal of the first gating circuit 1061 is OUT SN , for outputting a first scanning signal S1N. The first gating circuit 1061 generates the first scanning signal S1N based on the first primary scanning signal, the high level VGH, the low level VGL and the first control signal Ctrl1.

[0072] Each level of shift register in the first driving circuit 1041 can be connected to the same first control signal Ctr1. The first control signal Ctr1 is at a low level when data is refreshed and at a high level when data is retained.

[0073] The circuit structure of the shift register in the second driving circuit 1042 is the same as that of the shift register in the first driving circuit 1041. The second gating circuit 1062 connected to the shift register in the second driving circuit 1042 is the same as the first gating circuit 1061 connected to the shift register in the first driving circuit 1041. The circuit structures of the shift register in the second driving circuit 1042 and the second gating circuit 1062 connected thereto are not further described in this embodiment of the application.

[0074] The shift register in the second driving circuit 1042 can generate a second primary scanning signal based on the second input signal STV2, a set of clock signals, a high level VGH, and a low level VGL. The second gating circuit 1062 generates a second scanning signal S2N based on the second primary scanning signal, the high level VGH, the low level VGL, and the second control signal Ctrl2.

[0075] Each level of shift register in the second driving circuit 1042 can be connected to the same second control signal Ctrl2. The second control signal Ctrl2 is at a low level when data is refreshed and at a high level when data is retained.

[0076] refer to Figure 6 , Figure 6 A circuit diagram of a shift register and a third gating circuit connected thereto in a third driving circuit provided in an embodiment of the present application.

[0077] like Figure 6 As shown, the shift register in the third driving circuit 1043 includes eight transistors and two capacitors. The eight transistors are sequentially Q1 to Q8, and the two capacitors are sequentially CP1 to CP2. The output terminal of the shift register in the third driving circuit 1043 is OUT SP0 , for outputting a third primary scanning signal. The shift register in the third driving circuit 1043 generates the third primary scanning signal based on the third input signal STV3, the third clock signal SP_CK, the fourth clock signal SP_XCK, the high level VGH and the low level VGL.

[0078] like Figure 6 As shown, each level of the shift register in the third driving circuit 1043 is connected to a third gating circuit 1063. The third gating circuit 1063 includes three transistors and a capacitor. The three transistors are sequentially Q9 to Q11, and the capacitor is CP3. The output terminal of the third gating circuit 1063 is OUT SP , for outputting the third scan signal SP. The third gating circuit 1063 generates the third scan signal SP based on the high level VGH, the low level VGL and the third control signal Ctrl3.

[0079] For two adjacent shift register stages in the third driver circuit 1043, the third control signal Ctrl3 connected to the third gating circuit 1063 connected to one shift register is SP_CK_Ctrl, and the third control signal Ctrl3 connected to the third gating circuit 1063 connected to the other shift register stage is SP_XCK_Ctrl. During data refresh, SP_CK_Ctrl and SP_XCK_Ctrl are clock signals with opposite phases. During data retention, SP_CK_Ctrl and SP_XCK_Ctrl can be high.

[0080] refer to Figure 7 , Figure 7 This is a circuit diagram of a shift register in a fourth drive circuit provided in an embodiment of the present application. The shift register in the fourth drive circuit 1044 includes twelve transistors and three capacitors. The twelve transistors are sequentially K1 to K12, and the three capacitors are sequentially CP*1 to CP*3. K3 is a dual-gate transistor including two sub-transistors K31 and K32. The output terminal of the shift register in the fourth drive circuit 1044 is OUT SP* The shift register in the fourth driving circuit 1044 generates the fourth scanning signal SP* based on the fourth input signal STV4, the high level VGH, the low level VGL, and the fourth set of clock signals (including SP*_CK and SP*_XCK).

[0081] The circuit structure of the shift register in the fifth driving circuit 1045 can be the same as the circuit structure of the shift register in the fourth driving circuit 1044. The embodiment of the present application will not further describe the circuit structure of the shift register in the fifth driving circuit 1045. The shift register in the fifth driving circuit can generate the light emission control signal EM based on the fifth input signal STV5, the high level VGH, the low level VGL, and a set of clock signals.

[0082] When the display panel displays an image, a plurality of sub-display cycles are included in a unit time, such as N sub-display cycles are included in a unit time, and N is a positive integer greater than 1. N is related to the maximum data refresh frequency of the display panel. If the maximum data refresh frequency is 120Hz, then N=120. For a certain display panel, its maximum data refresh frequency is determined, so the number of sub-display cycles per unit time is determined, that is, for a certain display panel, N is a certain constant. In the subsequent embodiments of this application, the maximum refresh frequency of the display panel is 120Hz as an example for illustration. It is easy to know that the maximum data refresh frequency of the display panel can be set according to demand and is not limited to 120Hz. For example, it can also be 144Hz or other frequency values.

[0083] The first clock frequency is related to the maximum data refresh frequency of the display panel. In one embodiment, the first clock frequency can be the maximum clock frequency, and the display panel can achieve the maximum data refresh frequency based on the maximum clock frequency. Therefore, for a specific display panel, its maximum data refresh frequency and maximum clock frequency are determining parameters, and the corresponding first clock frequency is the determining parameter. In the first display mode and the second display mode, the frequency of the clock signal received by the shift register in the driver circuit 104 is the first clock frequency, which can enable the entire display area AA to be displayed and driven with normal timing within a sub-display cycle.

[0084] refer to Figure 8 and Figure 9 , Figure 8 A schematic diagram of the principle of partition display of a display panel provided in an embodiment of the present application, Figure 9 for Figure 8 The timing diagram of the display panel shown in the partition display.

[0085] Figure 8 For illustration, an example is provided in which the display area AA of the display panel is divided into three sub-display areas along the column direction of the sub-pixels 100. Of the three sub-display areas, the central sub-display area may be the first sub-display area 101, and the data refresh rate of the first sub-display area 101 may be 120 Hz. The other two sub-display areas may both be the second sub-display area 102, and the data refresh rate of the second sub-display area 102 may be 1 Hz. The first sub-display area 101 may be used to display video, and the second sub-display area 102 may be used to display text.

[0086] If the display area AA in the display panel is Figure 8 As shown, it is divided into three sub-display areas. At this time, the display timing in the three sub-display areas is as follows Figure 9 As shown. For 120 consecutive sub-display cycles in a unit time, since the data refresh frequency of the first sub-display area 101 is 120Hz, the first sub-display area 101 refreshes data in the 120 sub-display cycles. Since the data refresh frequency of the second sub-display area 102 is 1Hz, the second sub-display area 102 refreshes data only in the first sub-display cycle and maintains data in the other 119 sub-display cycles. Each display cycle includes an effective display phase (i.e. Figure 9 Active phase) and blanking phase (i.e. Figure 9 The blanking phase is the gap between two adjacent active display phases. For the 120 consecutive sub-display cycles within a unit time, data is refreshed in all three sub-display areas during the first sub-display cycle. That is, the first frame is the refresh frame for all sub-display areas.

[0087] The second to 120th sub-display periods are all sub-display area skip frames. In the second to 120th sub-display periods, the first sub-display area 101 is refreshed, while the second sub-display area 102 is kept. Figure 9 Only the first sub-display period and the second sub-display period are shown in the figure, and the second sub-display period to the 120th sub-display period are 119 sub-display periods repeated 119 times.

[0088] Figure 9 In the display, V_Sync is the timing reference signal. It has a low-level pulse during each blanking phase and remains high between two adjacent low-level pulses. The display IC can distinguish the duration of a frame based on the timing reference signal V_Sync.

[0089] like Figure 9 As shown, in the 1st sub-display period to the 120th sub-display period, for the first sub-display area 101, the SP_CK_Ctrl and SP_XCK_Ctrl received by the third selection circuit 1063 connected to its pixel circuit 103 are both clock signals that perform normal timing jumps, and data can be refreshed in each sub-display period, thereby realizing data refresh at a frequency of 120 Hz; for the second sub-display area 102, the SP_CK_Ctrl and SP_XCK_Ctrl received by the third selection circuit 1063 connected to its pixel circuit 103 are clock signals that perform normal timing jumps only in the 1st sub-display period, and are fixed high levels from the 2nd sub-display period to the 120th sub-display period, so the second sub-display area 102 only refreshes data in the 1st sub-display period, maintains data in the subsequent 119 sub-display periods, and is refreshed only once per unit time, thereby realizing data refresh at a frequency of 1 Hz.

[0090] like Figure 9 As shown, in the first sub-display period, each sub-display area performs data refresh, so the display panel is in the first display mode in the first sub-display period; in the second sub-display period to the 120th sub-display period, the first sub-display area 101 with a data refresh frequency of 120Hz performs data refresh, and the second sub-display area 102 with a data refresh frequency of 1Hz performs data retention, so the display panel is in the second display mode in the second sub-display period to the 120th sub-display period.

[0091] In the first display mode and the second display mode, the frequency of the clock signal received by the shift register in the driving circuit 104 is the first clock frequency. Figure 9As shown, in the first display mode and the second display mode, the third group of clock signals (SP_CK and SP_XCK) received by the shift register in the third driving circuit 1043 and the first group of clock signals (SN_CK and SN_XCK) received by the first driving circuit 1041 both undergo normal timing jumps, that is, the first group of clock signals and the second group of clock signals both have the first clock frequency.

[0092] When the display panel is partitioned for display, the data refresh frequencies of any two adjacent sub-display areas among the multiple sub-display areas are different. The one with a larger data refresh frequency among the two adjacent sub-display areas is the first sub-display area 101, and the one with a smaller data refresh frequency is the second sub-display area 102.

[0093] refer to Figure 10 and Figure 11 , Figure 10 A schematic diagram of the principle of partition display of another display panel provided in an embodiment of the present application, Figure 11 for Figure 10 The timing diagram of the display panel shown in the partition display.

[0094] Figure 10 Similarly, the following example illustrates a display panel where display area AA is divided into three sub-display areas along the column direction of sub-pixels 100. Of these three sub-display areas, the central sub-display area may be the first sub-display area 101, and the data refresh rate of the first sub-display area 101 may be 60 Hz. The other two sub-display areas may both be the second sub-display area 102, and the data refresh rate of the second sub-display area 102 may be 1 Hz. The first sub-display area 101 may be used to display video, and the second sub-display area 102 may be used to display text.

[0095] If the display area AA in the display panel is Figure 10 As shown, it is divided into three sub-display areas. At this time, the display timing in the three sub-display areas is as follows Figure 11 As shown. For the 120 consecutive sub-display periods within a unit time, since the data refresh frequency of the first sub-display area 101 is 60 Hz, the first sub-display area 101 alternately refreshes and retains data during these 120 sub-display periods. For example, data refresh may be performed during all odd-numbered sub-display periods, and data retention may be performed during all even-numbered sub-display periods. Since the data refresh frequency of the second sub-display area 102 is 1 Hz, the second sub-display area 102 refreshes data only during the first sub-display period and retains data during the remaining 119 sub-display periods.

[0096] In the 2nd to 120th sub-display periods, the first sub-display area 101 holds data in each even-numbered sub-display period and refreshes data in each odd-numbered sub-display period; while the second sub-display area 102 holds data in each sub-display period. Figure 11 Only the 1st to 4th sub-display periods are shown in the figure. Every two sub-display periods in the 3rd to 120th sub-display periods constitute a period unit, which is repeated 59 times in total.

[0097] like Figure 11 As shown, for the first sub-display area 101, in each odd sub-display cycle, the SP_CK_Ctrl and SP_XCK_Ctrl received by the third selection circuit 1063 connected to its pixel circuit 103 are both clock signals for normal timing jumps, and in each even sub-display cycle, the SP_CK_Ctrl and SP_XCK_Ctrl received by the third selection circuit 1063 connected to its pixel circuit 103 are both fixed high levels, realizing the alternating distribution of data refresh and data retention, thereby realizing data refresh at a frequency of 60 Hz. For the second sub-display area 102, the clock signals SP_CK_Ctrl and SP_XCK_Ctrl received by the third selection circuit 1063 connected to its pixel circuit 103 are normally time-shifted only in the first sub-display cycle, and are a fixed high level from the second sub-display cycle to the 120th sub-display cycle. Therefore, the second sub-display area 102 only refreshes data in the first sub-display cycle and maintains data in the subsequent 119 sub-display cycles, and is refreshed only once per unit time, thereby achieving a data refresh frequency of 1 Hz.

[0098] like Figure 11 As shown, during the first sub-display period, each sub-display area performs data refresh, so the display panel is in the first display mode during the first sub-display period. During each odd-numbered sub-display period from the third sub-display period to the 120th sub-display period, the first sub-display area 101 performs data refresh, and the second sub-display area 102 performs data retention, so the display panel is in the second display mode during these sub-display periods.

[0099] In the embodiment of the present application, the display panel also includes a third display mode; in the third display mode, each sub-display area holds data; in the third display mode, the clock frequency of the clock signal received by the shift register 105 corresponding to the second sub-display area 102 does not exceed the first clock frequency. Figure 11 As shown, in each even-numbered sub-display period, each sub-display area holds data, that is, the display panel is in the third display mode in each even-numbered sub-display period.

[0100] In the embodiment of the present application, based on any of the above implementations, in the third display mode, the data signal is at a high level or a low level. In the third display mode, since each sub-display area retains data and does not require data writing, the data signal can be set to a fixed high level or a fixed low level to reduce power consumption caused by data signal transitions, thereby reducing power consumption of the display panel. Figure 11 The data signal is represented by Source, and in the third display mode corresponding to each even-numbered sub-display period, the data signal is set to a high level.

[0101] When a conventional display panel performs partition display, the clock signal received by the shift register in the driving circuit 104 performs timing jumps based on the first clock frequency. However, when the sub-display area performs low-frequency display (the data refresh frequency is less than the maximum data refresh frequency), it is controlled by the corresponding selection circuit 106 and can drive the sub-display area for low-frequency display through the scan signal. The shift register of the corresponding driving circuit 104 can correspondingly reduce the frequency of the primary scan signal, so the power consumption of the display panel can be reduced by reducing the clock frequency of the clock signal received by the shift register. Based on this, in an embodiment of the present application, when the display panel is in the third display mode, the second sub-display area 102 for low-frequency display has a clock frequency not exceeding the first clock frequency. For example, the clock frequency of the clock signal received by the shift register 105 corresponding to the second sub-display area 102 can be made less than the first clock frequency, thereby reducing the power consumption of the display panel.

[0102] Optionally, in the third display mode, the clock frequency of the clock signal received by the shift register corresponding to each sub-display area can be made not to exceed the first clock frequency, and the clock frequencies of the clock signals received by the shift registers corresponding to at least two sub-display areas are different. In this way, the clock frequencies of the clock signals received by the shift registers corresponding to different sub-display areas can be reduced through differentiation, thereby optimizing the display effect while reducing power consumption.

[0103] Optionally, in the third display mode, the clock frequency of the clock signal received by the shift register 105 corresponding to each sub-display area does not exceed the first clock frequency. For example, the clock frequency of the clock signal received by the shift register 105 corresponding to each sub-display area can be made smaller than the first clock frequency, thereby significantly reducing the power consumption of the display panel. Figure 11 As shown, during each even-numbered sub-display period, the display panel is in the third display mode, the clock frequencies of SN_CK and SN_XCK are lower than the first clock frequency, and the clock frequencies of SP_CK and SP_XCK are lower than the first clock frequency. In this way, the shift register of the first driving circuit 1041 and the shift register of the third driving circuit 1043 can reduce power consumption by reducing the frequency of the received clock signal, thereby reducing the display power consumption of the display panel.

[0104] Optionally, in the third display mode, the shift registers 105 corresponding to at least two sub-display areas all receive clock signals of a second clock frequency, and the second clock frequency is lower than the first clock frequency. Figure 10 and Figure 11 As shown, during each even-numbered sub-display period, the display panel is in the third display mode. For the two second sub-display areas 102, both of which have a data refresh rate of 1 Hz, the corresponding SP_CK and SP_XCK clock frequencies are both the second clock frequency, and the second clock frequency is lower than the first clock frequency. Thus, the shift registers in the third driver circuit 1043 corresponding to the two second sub-display areas 102 can both use the SP_CK and SP_XCK clock frequencies with the lower clock frequency for timing control, thereby reducing the power consumption of the shift registers in the third driver circuit 1043 corresponding to the two second sub-display areas 102 in the third display mode.

[0105] In one embodiment, the clock signal of the second clock frequency is a fixed level, that is, the clock signal is a DC voltage during the period corresponding to the third display mode, and the clock signal does not have a high or low level jump. Optionally, the fixed level can be a high level of the clock signal, or a low level of the clock signal, or other voltage values between the high level and the low level. Figure 11 As shown, in each even-numbered sub-display period, for the two second sub-display areas 102, both of which have a data refresh rate of 1 Hz, the corresponding SP_CK and SP_XCK clock frequencies are both at a low level. In this approach, the clock signal is at a fixed level in the third display mode, eliminating the need for timing transitions. This reduces clock signal power consumption while maximally simplifying the clock signal, facilitating display control of the display panel in the third display mode.

[0106] Optionally, the driver circuit 104 is electrically connected to the first signal line, which is used to transmit a DC voltage; the DC voltage is reused as the fixed voltage level. In this manner, in the third display mode, the existing DC voltage in the driver circuit 104 can be reused as the fixed voltage level. This allows the DC voltage to be used as a clock signal in the third display mode, eliminating the need for additional fixed voltage levels and reducing the number of signal pins on the display IC.

[0107] Optionally, the clock signal of the second clock frequency is a square wave signal. Figure 10 and Figure 11 As shown, for the second sub-display area 102 with two data refresh frequencies of 1 Hz, in each even sub-display period, SN_CK and SN_XCK are both square wave signals, and the frequency of the square wave signal is less than the first clock frequency.

[0108] In the third display mode, the clock frequency of the clock signal received by the shift register corresponding to at least one sub-display area is smaller than the first clock frequency, which can reduce the power consumption of the high-frequency timing jump of the clock signal of the shift register, thereby reducing the power consumption of the display panel.

[0109] In the second display mode, the first sub-display area 101 performs data refresh and the second sub-display area 102 performs data retention. Although the second sub-display area 102 is in a low-frequency display state relative to the first sub-display area, the shift register corresponding to the second sub-display area 102 can reduce power consumption by reducing the clock frequency of the received clock signal. However, this will cause the driving circuit 104 to be unable to display the pixel circuit 103 in the first sub-display area 101 based on the normal timing, thereby causing display abnormality. In order to avoid this problem, in the second display mode, the clock signal received by the shift register corresponding to each sub-display area has the first clock frequency, such as Figure 11 As shown, in the second display mode corresponding to the third sub-display period and subsequent sub-display periods, SP_CK and SP_XCK as well as SN_CK and SN_XCK all perform timing jumps based on the first clock frequency.

[0110] In one embodiment, in the third display mode, the shift registers in the driving circuit 104 may input clock signals of the same clock frequency, so as to simplify the timing control of each shift register. Figure 10 and Figure 11 As shown, the display panel is in the third display mode in each even sub-display area, and the SP_CK and SP_XCK received by the shift register corresponding to the third drive circuit 1043 of each sub-display area are both constant low-level clock signals, and the SN_CK and SN_XCK received by the shift register corresponding to the first drive circuit 1041 of each sub-display area are both clock signals with a set low clock frequency (less than the first clock frequency).

[0111] In an embodiment of the present application, when data is held in full screen mode, SP_CK and SP_XCK can be frequency-reduced, and SN_CK and SN_XCK can be frequency-reduced. When data is held in full screen mode, all sub-display areas also hold data, and the display panel is in the third display mode. Optionally, in this method, the clock period of the clock signal corresponding to the shift register can be increased to a positive multiple of the initial clock period. The initial clock period is the clock period corresponding to the maximum clock frequency.

[0112] Optionally, the clock cycles of SP_CK and SP_XCK may be increased to 32 times of the initial clock cycle or set to a low level, and the clock cycles of SN_CK and SN_XCK may be increased to 2 times of the initial clock cycle or set to a high level.

[0113] Optionally, the control signal and data signal connected to the gating circuit 106 can reduce the frequency not only in the third display mode but also in the second display mode. Figure 11 As shown, in the third sub-display cycle, the two first sub-display areas with a data refresh frequency of 1 Hz both maintain data, and their corresponding SP_CK_Ctrl, SP_XCK_Ctrl and Source can be set to high levels to reduce their timing jumps, thereby reducing power consumption.

[0114] The embodiment of the present application can selectively reduce the signal frequency based on the display mode of the display panel, and can maximize the reduction of power consumption of the sub-display area of the display panel that is locally refreshed at a low frequency. At the same frequency, when the display panel performs full-screen low-data refresh and local area low-data refresh, the power consumption in the same sub-display area is basically the same.

[0115] refer to Figure 12 , Figure 12 A timing diagram of a display panel in a third display mode provided by an embodiment of the present application, Figure 12 The display partitions of the display panel can be as follows Figure 10 As shown, it is divided into two second sub-display areas 102 with a data refresh rate of 1 Hz and one first sub-display area 101 with a data refresh rate of 60 Hz. As mentioned above, in the third display mode, SP_CK_Ctrl and SP_XCK_Ctrl are both high.

[0116] like Figure 12 As shown, in the third display mode, the shift register 105 corresponding to the first sub-display area 101 and the shift register 105 corresponding to the second sub-display area 102 receive clock signals with different clock frequencies. For example, for the same set of clock signals, such as SP_CK and SP_XCK, the SP_CK and SP_XCK received by the shift register corresponding to the first sub-display area 101 and the SP_CK and SP_XCK received by the shift register corresponding to the second sub-display area 102 can be set to have different clock frequencies. This allows the clock frequencies of the clock signals received by the shift registers corresponding to the first sub-display area 101 and the second sub-display area 102 to be differentially reduced, thereby optimizing the display effect while reducing power consumption.

[0117] In the third display mode, contrast Figure 11 and Figure 12 Two ways: Figure 11 In the illustrated embodiment, the display panel is in the third display mode during an even sub-display period. Corresponding to the same set of clock signals, the clock frequencies of the clock signals received by the shift registers corresponding to the first sub-display area 101 and the second sub-display area are the same. For example, SP_CK and SP_XCK are both at low levels in the third display mode. Figure 12In the manner shown, for the same set of clock signals, the clock frequencies of the clock signals received by the corresponding shift registers of the first sub-display area 101 and the second sub-display area are different. For example, the clock frequencies of SP_CK and SP_XCK received by the corresponding shift register of the first sub-display area 101 are different from the clock frequencies of SP_CK and SP_XCK received by the corresponding shift register of the second sub-display area 102.

[0118] Optionally, in the third display mode, if the shift register 105 corresponding to the first sub-display area 101 and the shift register 105 corresponding to the second sub-display area 102 receive clock signals of different clock frequencies, the clock frequency of the clock signal received by the shift register 105 is positively correlated with the data refresh frequency of the corresponding sub-display area. For the same set of clock signals SP_CK and SP_XCK, since the data refresh frequency of 1 Hz is less than the data refresh frequency of 60 Hz, Figure 12 As shown, the clock frequency of the clock signal of the shift register corresponding to the second sub-display area 102 is lower than the clock frequency of the clock signal of the shift register corresponding to the first sub-display area 101. For the same set of clock signals, the clock frequency of the clock signal received by the shift register 105 corresponding to the first sub-display area 101 can be set to be higher than the clock frequency of the clock signal received by the shift register 105 corresponding to the second sub-display area 102, so as to improve the image display quality of the display panel in the third display mode.

[0119] As described above, a unit time includes multiple sub-display cycles. For example, if the maximum data refresh frequency of the display panel is 120Hz, then a unit time may include 120 sub-display cycles. The unit time may be 1s. At least two sub-display cycles are in the third display mode, such as Figure 11 As shown, in each even-numbered sub-display period, all sub-display areas hold data, that is, the display panel is in the third display mode in each even-numbered sub-display period.

[0120] In one embodiment, for the same sub-display area, in the third display mode corresponding to at least two sub-display periods, the shift register 105 corresponding to the sub-display area receives a clock signal of the same clock frequency. Figure 11 As shown, for the same set of clock signals, in each even-numbered sub-display period, the shift registers corresponding to the same sub-display area receive clock signals with the same clock frequency. In this manner, in multiple third sub-display modes, the shift registers corresponding to the same sub-display area receive clock signals with the same clock frequency, facilitating timing control of the shift registers of the sub-display area in each third display mode.

[0121] Figure 11SN_CK and SN_XCK are the same set of clock signals, and the display panel is in the third display mode during each even-numbered sub-display period. That is, each even-numbered sub-display period corresponds to a third display mode. In this method, for the same sub-display period, the SN_CK and SN_XCK received by the corresponding shift register in different third display modes are clock signals with the same clock frequency (this clock frequency is less than the first clock frequency).

[0122] In another embodiment, for the same sub-display area, in the third display mode corresponding to at least two sub-display periods, the shift register 105 corresponding to the sub-display area receives clock signals having different clock frequencies. In this embodiment, for a sub-display area, the corresponding shift register receives clock signals having different clock frequencies in different third display modes. By differentially designing the clock frequencies of the clock signals received by the corresponding shift registers of the same sub-display area in different third display modes, the sub-display area can achieve different degrees of clock signal frequency reduction in different third display modes. This reduces power consumption while optimizing the image display quality of the display panel in the third display mode based on the different degrees of clock signal frequency reduction.

[0123] For the same sub-display area, in the third display mode corresponding to at least two sub-display cycles, if the shift register 105 corresponding to the sub-display area receives clock signals with different clock frequencies, in multiple consecutive third display modes, for the same sub-display area, the clock frequency of the clock signal received by its corresponding shift register can be set to be successively reduced from the first clock frequency to the target frequency, and then successively increased to the first clock frequency.

[0124] by Figure 10 Taking the display partition shown as an example, if the maximum data refresh frequency of the display panel is 120H, there are 120 sub-display cycles in a unit time, and all even-numbered sub-display cycles in the 120 sub-display cycles are the third display mode. The display panel has 60 third display modes in a unit time. In the 60 third display modes, the clock signals of the first three third display modes can be sequentially reduced from the first clock frequency to the target frequency, and the clock signals of the last thirty third display modes can be sequentially increased from the target frequency to the first clock frequency. In this way, the display panel takes a unit time as a display cycle, and the clock frequencies of the clock signals received by the shift register in two adjacent display cycles are both the maximum first clock frequency. Only the clock signal is gradually reduced in frequency within the display cycle. This can reduce power consumption while avoiding a large clock frequency mutation between two adjacent display cycles, so as to avoid the clock frequency mutation affecting the display quality, thereby improving the image display quality of the display panel.

[0125] Optionally, for the same sub-display area, in each third display mode, the shift register 105 corresponding to the sub-display area alternately receives a clock signal of a third clock frequency and a clock signal of a fourth clock frequency; wherein the third clock frequency is not equal to the fourth clock frequency, and at least one of the third clock frequency and the fourth clock frequency is less than the first clock frequency. Figure 10 Taking the display partition shown as an example, if the maximum data refresh frequency of the display panel is 120H, then in the 60 third display modes of a display cycle, each third display down-shift register 105 alternately receives the clock signal of the third clock frequency and the clock signal of the fourth clock frequency, and the image display quality of the display panel can be improved by the clock signal with periodically distributed clock frequency.

[0126] It should be noted that when a display panel is partitioned for display, at least two sub-display areas may have different data refresh rates. The data refresh rates of the multiple sub-display areas of the display panel may be different; alternatively, at least two sub-display areas may have different data refresh rates, at least two sub-display areas may have the same data refresh rate, and two adjacent sub-display areas may have different data refresh rates. Taking a maximum data refresh rate of 120 Hz as an example, Table 1 below provides the display modes corresponding to the first to twelfth sub-display periods for four different partitioned display modes of the display panel.

[0127] Table 1

[0128]

[0129] As shown in Table 1, the four partition display modes are the first to fourth partition modes, respectively. In the first partition mode, the display panel includes at least three sub-display areas, wherein the data refresh frequencies of the three sub-display areas are 60 Hz, 30 Hz, and 10 Hz, respectively. In the second partition mode, the display panel includes at least three sub-display areas, wherein the data refresh frequencies of the three sub-display areas are 30 Hz, 20 Hz, and 10 Hz, respectively. In the third partition mode, the display panel includes at least two sub-display areas, wherein the data refresh frequencies of the two sub-display areas are 30 Hz and 10 Hz, respectively.

[0130] As shown in Table 1, the data refresh phase of a sub-display area is indicated by REFRSH. In the first sub-display cycle, each sub-display area requires its first data refresh, so the first through fourth partitioning modes are all in the REFRSH state during the first sub-display cycle. The data hold phase of a sub-display area is indicated by SKIP1 or SKIP2. If all sub-display areas of the display panel are in the data hold phase during the same sub-display cycle, SKIP1 represents the data hold state of each sub-display area. If some sub-display areas of the display panel are in data refresh and some are in data hold, SKIP2 represents the state of the sub-display areas in data hold.

[0131] For sub-display areas with a data refresh frequency of 60 Hz, data is refreshed every other sub-display period. Therefore, the sub-display period is in the REFRSH state during odd-numbered sub-display periods and in the SKIP1 state during even-numbered sub-display periods. For example, in Table 1, the 1st, 3rd, 5th, 7th, 9th, and 11th sub-display periods are in the REFRSH state, and the remaining sub-display periods are in the SKIP1 state.

[0132] For the sub-display area with a data refresh frequency of 30 Hz, data is refreshed every three sub-display cycles, so the sub-display cycle is in the REFRSH state in the 4i-3 sub-display cycle, where i is a positive integer. For example, in Table 1, the 1st, 5th, and 9th sub-display cycles are in the REFRSH state, and the other sub-display cycles are in the SKIP1 or SKIP2 state.

[0133] For the sub-display area with a data refresh frequency of 20 Hz, data is refreshed every five sub-display cycles, so the sub-display cycle is in the REFRSH state in the 6i-5 sub-display cycle, where i is a positive integer. For example, in Table 1, the 1st and 7th sub-display cycles are in the REFRSH state, and the other sub-display cycles are in the SKIP1 or SKIP2 state.

[0134] For the sub-display area with a data refresh frequency of 10 Hz, data is refreshed every eleven sub-display cycles, so the sub-display cycle is in the REFRSH state in the 12i-11 sub-display cycle, where i is a positive integer. For example, in Table 1, the 1st sub-display cycle is in the REFRSH state, and the other sub-display cycles are in the SKIP1 or SKIP2 state.

[0135] As shown in Table 1, for the same partition display mode, in the same sub-display period, if all sub-display areas are in the REFRSH state, the display panel is in the first display mode; if all sub-display areas are in the SKIP1 state, the display panel is in the third display mode; if some sub-display areas are in the REFRSH state and if some sub-display areas are in the state 2, the display panel is in the second display mode.

[0136] As shown in Table 1, in the second and fourth partitioning modes, there are three consecutive third display modes from the 2nd to the 4th sub-display periods, and there are three consecutive third display modes from the 10th to the 12th sub-display periods.

[0137] In one embodiment, for the same sub-display area, three adjacent sub-display periods are in the third display mode, and the shift register 105 corresponding to the sub-display area alternately receives a clock signal having a fifth clock frequency and a clock signal having a sixth clock frequency; wherein the fifth clock frequency is not equal to the sixth clock frequency, and at least one of the fifth and sixth clock frequencies is less than the first clock frequency. In this embodiment, in multiple consecutive third display modes, the shift register 105 corresponding to the same sub-display area alternately receives clock signals having two different clock frequencies, and the frequency of at least one clock signal is less than the first clock frequency. In this manner, power consumption can be reduced by lowering the clock frequency in the third display mode, and the clock signal can be prevented from being in a low clock frequency state for a long time, thereby improving the image display quality of the display panel in the third display mode.

[0138] In another approach, for the same sub-display area, the third display mode is maintained during three adjacent sub-display periods, and the frequency of the clock signal received by the shift register 105 corresponding to the sub-display area is first reduced and then increased. This approach can also reduce power consumption by reducing the clock frequency in the third display mode, and can also prevent the clock signal from being in a low clock frequency state for a long time, thereby improving the image display quality of the display panel in the third display mode.

[0139] Set the maximum clock frequency of the clock signal to f max For determining the display panel, the maximum clock frequency f of its clock signal max To determine the constant. In the third display mode, the clock frequency of the clock signal received by the shift register 105 corresponding to the sub-display area is m / f max , m is a positive integer greater than 1. f max The reciprocal of is the maximum clock period. This method can achieve integer-multiple clock signal frequency reduction by increasing the clock signal period by an integer multiple. This method can directly use the maximum clock frequency as a reference to achieve clock signal frequency reduction in the third display mode by reducing the frequency by an integer multiple, facilitating clock signal frequency reduction control in the third display mode.

[0140] refer to Figure 13 , Figure 13 This is a schematic diagram of the structure of another display panel provided in an embodiment of the present application. Based on the above implementation, Figure 13 The display panel shown also includes: a control chip 107 (which can be the above-mentioned display IC); the control chip 107 includes a first pin and a second pin; the first pin is used to transmit a clock signal with adjustable frequency; the second pin is used to transmit a control signal to the selection circuit 106.

[0141] When the display panel is performing a partitioned display, different sub-display areas of the display panel can have different data refresh frequencies corresponding to the corresponding sub-display areas according to the dynamic and static images being displayed, thereby achieving power saving during the partitioned display. Because the display panel has multiple data refresh frequencies, the data writing frames corresponding to the sub-display areas with different data refresh frequencies are different, and power consumption reduction processing is continuously implemented. This is because at multiple different data refresh frequencies, the scan signal connected to the pixel circuit cannot be continuously set high or low at a low data refresh frequency, while maintaining the normal writing of the data signal VDATA.

[0142] In the technical solution of the embodiment of the present application, in the third display mode in which data is retained in all sub-display areas, the clock frequency of the clock signal received by the shift register is reduced to achieve continuous power consumption reduction in the third display mode. In the first display mode and the second display mode, the shift register performs clock signal jumps based on normal timing to ensure the normal writing of the data signal VDATA. While achieving the purpose of reducing power consumption, it can also ensure the normal display effect of the display panel during partition display.

[0143] Based on the above embodiment, another embodiment of the present application further provides a display device 108. Figure 14 shown.

[0144] refer to Figure 14 , Figure 14 This is a schematic diagram of the structure of a display device provided in an embodiment of the present application. The display device 108 shown includes a display panel provided in any of the above embodiments. The display device can be an electronic device with a display function, such as a mobile phone, tablet computer, laptop computer, or wearable device. The embodiment of the present application does not limit the type of electronic device.

[0145] The display device provided in the embodiment of the present application includes the display panel provided in the above embodiment, which can reduce power consumption while performing partitioned display.

[0146] The various embodiments in the specification of this application are described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other. The embodiments provided in the embodiments of this application can be combined with each other if there is no contradiction.

[0147] It should be noted that in the description of this application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same figure numbers throughout the embodiments of the specification identify the same structure. In addition, for the purpose of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially mean positioning on the upper side of another element according to the direction of gravity.

[0148] The terms "upper," "lower," "top," "bottom," "inner," "outer," and the like, indicating positions or locations, are based on the positions or locations shown in the accompanying drawings and are intended solely to facilitate and simplify the description of this application. They are not intended to indicate or imply that the devices or elements referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally located component.

[0149] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the aforementioned elements.

[0150] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: include: a plurality of sub-pixels and pixel circuits connected to the sub-pixels; A driving circuit comprising a plurality of cascaded shift registers, wherein the shift registers are configured to output a primary scanning signal based on a clock signal; a plurality of gating circuits, the gating circuits corresponding to the shift registers, the shift registers connected to the pixel circuits via the gating circuits, the gating circuits providing scanning signals to the pixel circuits; The display area includes a plurality of sub-display areas, the plurality of sub-display areas include a first sub-display area and a second sub-display area, and a data refresh frequency of the first sub-display area is greater than a data refresh frequency of the second sub-display area; The display panel includes a first display mode and a second display mode; in the first display mode, each of the sub-display areas performs data refresh; in the second display mode, the first sub-display area performs data refresh and the second sub-display area performs data retention; In the first display mode and the second display mode, the shift registers corresponding to the first sub-display area and the second sub-display area both receive the clock signal of the first clock frequency.

2. The display panel according to claim 1, wherein: The display panel further includes a third display mode; in the third display mode, each of the sub-display areas holds data; In the third display mode, a clock frequency of a clock signal received by the shift register corresponding to the second sub-display area does not exceed the first clock frequency.

3. The display panel according to claim 1, wherein: The display panel further includes a third display mode; in the third display mode, each of the sub-display areas holds data; In the third display mode, the clock frequency of the clock signal received by the shift register corresponding to each of the sub-display areas does not exceed the first clock frequency.

4. The display panel according to claim 3, wherein: In the third display mode, the shift registers corresponding to at least two of the sub-display areas all receive the clock signal of a second clock frequency, where the second clock frequency is lower than the first clock frequency.

5. The display panel according to claim 4, wherein: The clock signal of the second clock frequency is at a fixed level.

6. The display panel according to claim 5, wherein: The driving circuit is electrically connected to a first signal line, and the first signal line is used to transmit a DC voltage; the DC voltage is multiplexed as the fixed level.

7. The display panel according to claim 4, wherein: The clock signal of the second clock frequency is a square wave signal.

8. The display panel according to claim 3, wherein: In the third display mode, the shift register corresponding to the first sub-display area and the shift register corresponding to the second sub-display area receive clock signals with different clock frequencies.

9. The display panel according to claim 8, wherein: In the third display mode, the clock frequency of the clock signal received by the shift register is positively correlated with the data refresh frequency of the corresponding sub-display area.

10. The display panel according to claim 3, wherein: A unit time includes a plurality of sub-display periods; at least two of the sub-display periods are in the third display mode; For the same sub-display area, in the third display mode corresponding to at least two sub-display periods, the shift register corresponding to the sub-display area receives the clock signal with the same clock frequency.

11. The display panel according to claim 3, wherein A unit time includes a plurality of sub-display periods; at least two of the sub-display periods are in the third display mode; For the same sub-display area, in the third display mode corresponding to at least two sub-display periods, the shift register corresponding to the sub-display area receives the clock signals with different clock frequencies.

12. The display panel according to claim 11, wherein: For the same sub-display area, in each of the third display modes, the shift register corresponding to the sub-display area alternately receives the clock signal of the third clock frequency and the clock signal of the fourth clock frequency; wherein the third clock frequency is not equal to the fourth clock frequency, and at least one of them is less than the first clock frequency.

13. The display panel according to claim 11, wherein: For the same sub-display area, the three adjacent sub-display periods are all in the third display mode, and the shift register corresponding to the sub-display area alternately receives the clock signal of the fifth clock frequency and the clock signal of the sixth clock frequency; wherein the fifth clock frequency is not equal to the sixth clock frequency, and at least one of them is less than the first clock frequency.

14. The display panel according to claim 11, wherein: For the same sub-display area, three adjacent sub-display periods are all in the third display mode, and the frequency of the clock signal received by the shift register corresponding to the sub-display area first decreases and then increases.

15. The display panel according to claim 3, wherein: The maximum clock frequency of the clock signal is f max In the third display mode, the clock frequency of the clock signal received by the shift register corresponding to the sub-display area is m / f max , m is a positive integer greater than 1.

16. The display panel according to claim 3, wherein: The pixel circuit includes: a driving transistor for transmitting a driving current to the sub-pixel; a first reset transistor, wherein a first electrode of the first reset transistor is electrically connected to a gate of the driving transistor, and the gate of the first reset transistor is configured to receive a first scanning signal; a threshold compensation transistor, wherein a first electrode of the threshold compensation transistor is electrically connected to a first electrode of the driving transistor, a second electrode of the threshold compensation transistor is electrically connected to the gate of the driving transistor, and the gate of the threshold compensation transistor is configured to receive a second scanning signal; The driving circuit includes a first driving circuit and a second driving circuit; the first driving circuit is used to output a first primary scanning signal based on a first set of clock signals; the second driving circuit is used to output a second primary scanning signal based on a second set of clock signals; The gating circuit includes a first gating circuit and a second gating circuit, the first driving circuit is connected to the corresponding pixel circuit through the first gating circuit, and the second driving circuit is connected to the corresponding pixel circuit through the second gating circuit; the first gating circuit is used to provide a first scanning signal to the pixel circuit based on a first control signal; the second gating circuit is used to provide a second scanning signal to the pixel circuit based on a second control signal.

17. The display panel according to claim 16, wherein: The pixel circuit further includes a data writing transistor, wherein a first electrode of the data writing transistor is electrically connected to a second electrode of the driving transistor, a gate of the data writing transistor receives a third scanning signal, and a second electrode of the data writing transistor is used to receive a data signal; The driving circuit further includes a third driving circuit, wherein the third driving circuit is configured to output a third primary scanning signal based on a third set of clock signals; The gating circuit further includes a third gating circuit, and the third driving circuit is connected to the corresponding pixel circuit through the third gating circuit; the third gating circuit is used to provide a third scanning signal to the pixel circuit based on a third control signal.

18. The display panel according to claim 17, wherein: In the third display mode, the data signal is at a high level or a low level.

19. The display panel according to claim 1, wherein Also includes: Control chip; The control chip includes a first pin and a second pin; the first pin is used to transmit a clock signal with adjustable frequency; the second pin is used to transmit a control signal to the gating circuit.

20. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 19.

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