High-speed serial signal testing method and system and semiconductor testing equipment

Abstract

The invention is suitable for the technical field of signal testing, and provides a high-speed serial signal testing method and system and semiconductor testing equipment, and the high-speed serial signal testing method comprises the steps: carrying out the time sequence adjustment of a testing signal through a phase-adjustable clock reference, actively introducing controllable jitter, and carrying out the jitter tolerance testing; a target test signal is sent to a receiving end through an emission driver, after a receiving signal is obtained, a target sampling time sequence is extracted based on clock recovery, a programmable receiving delay chain is controlled to carry out time scanning, and receiving data at multiple sampling moments are obtained; comparing each sampling data with the test signal, counting the bit error rate under each delay setting, and completing signal quality evaluation; the scheme has the advantages of modularization, high precision, low cost and the like, and the comprehensive test efficiency and reliability of the semiconductor test equipment on high-speed serial signals are improved.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor testing technology, and in particular relates to a high-speed serial signal testing method, system and semiconductor testing equipment. Background Art

[0002] As integrated circuits and electronic systems evolve toward higher speeds, lower power consumption, and smaller form factors, high-speed serial interfaces are increasingly used in chip interconnects and system communications. These interfaces utilize high-speed serial transmission, differential signaling, and embedded clocks to achieve higher data rates with a limited number of channels, significantly improving signal channel utilization. However, high-speed serial signals are susceptible to noise, jitter, crosstalk, and distortion during transmission, which can degrade signal integrity and, in turn, affect system stability and protocol compatibility. Therefore, testing high-speed serial signals has become a critical task in chip design verification, system debugging, and mass production testing.

[0003] Currently, mass production testing of high-speed serial signals primarily relies on ATE (automatic test equipment). However, existing ATE equipment has significant shortcomings when addressing these requirements. On the one hand, ATE's inherent test resources are limited, making it difficult to support key functions such as high-speed data driving, clock recovery, and bit error rate statistics required by high-speed serial interfaces. On the other hand, its closed architecture and delayed updates make it difficult to adapt to evolving high-speed protocol standards and complex debugging mechanisms. Mass production environments, in particular, place extremely high demands on test stability, consistency, and throughput efficiency, but traditional ATE lacks effective test paths and strategies for high-speed serial signal links. Summary of the Invention

[0004] In view of this, the embodiments of the present application provide a high-speed serial signal testing method, system and semiconductor testing equipment, which realize comprehensive testing of the electrical characteristics, protocol behavior and jitter tolerance of high-speed serial signals in a modular, high-precision and low-cost manner, and are applied in semiconductor testing equipment, thereby improving the testing efficiency of semiconductor testing equipment for high-speed serial signals.

[0005] A first aspect of an embodiment of the present application provides a high-speed serial signal testing method, which is applied to a high-speed serial signal testing system. The high-speed serial signal testing method includes: The test signal is adjusted in timing by a clock reference with adjustable phase to obtain a target test signal; Sending the target test signal to the receiving end via the transmitting driver to obtain a receiving signal; Based on clock recovery, a target sampling timing is extracted from the received signal, and a programmable receiving delay chain is controlled to adjust the delay of the received signal, and time scanning is performed within a signal cycle to obtain sampling data of the received signal at multiple sampling moments; The sampling data at the multiple sampling moments are compared with the target test signal, and the bit error rate under each delay setting is counted to complete the signal quality evaluation.

[0006] The embodiment of the present application adjusts the timing of the test signal through a clock reference with adjustable phase, actively introduces controllable jitter for jitter tolerance testing; sends the target test signal to the receiving end through the transmitting driver, obtains the received signal, extracts the target sampling timing based on clock recovery, and controls the programmable receiving delay chain to perform time scanning to obtain the received data at multiple sampling moments; by comparing each sampling data with the test signal, the bit error rate under each delay setting is calculated to complete the signal quality assessment; this solution has the advantages of modularity, high precision, and low cost, and can improve the comprehensive testing efficiency and reliability of semiconductor test equipment for high-speed serial signals.

[0007] In a possible implementation manner, before performing timing adjustment on the test signal using the phase-adjustable clock reference to obtain the target test signal, the method further includes: Based on preset test configuration parameters, a test signal that conforms to the target protocol format is generated. The test configuration parameters include at least the protocol type, transmission rate, and voltage swing parameters. The valid data field of the test signal is generated based on a pseudo-random number generator to simulate actual business data.

[0008] In a possible implementation manner, the step of adjusting the timing of the test signal using a clock reference with an adjustable phase to obtain a target test signal includes: Based on a preset phase jump control instruction, the reference clock is phase-switched to obtain multiple phase-switched clocks; The test signal is driven to be emitted at a timing according to the multiple phase-switching clocks and the reference clock, thereby generating a target test signal with controllable jitter.

[0009] In a possible implementation, extracting a target sampling timing from the received signal based on clock recovery includes: Perform clock recovery based on high and low level flip information in the received signal to obtain an embedded recovered clock of the received signal; A target sampling timing is determined according to the embedded recovered clock of the received signal.

[0010] In a possible implementation, when the target sampling timing is used as a sampling reference, controlling the programmable receiving delay chain to adjust the delay of the received signal, performing time scanning within a signal cycle, and obtaining sampling data of the received signal at multiple sampling times includes: According to a preset fixed delay step size, setting a plurality of different delay configuration values for the programmable receiving delay chain to evenly distribute a plurality of sampling moments within a receiving signal cycle; The received signal is sampled at each sampling moment to obtain sampling data of the received signal at the multiple sampling moments.

[0011] In one possible implementation, comparing the sampled data at the multiple sampling moments with the test signal, calculating bit error rates under various delay settings, and determining a target sampling moment based on the bit error rates to complete signal quality assessment includes: Compare the sampled data at each sampling moment with the test signal one by one, and calculate the bit error rate corresponding to each delay setting; constructing an eye diagram of the received signal based on the bit error rate distribution; Signal quality evaluation is completed according to the eye diagram of the received signal.

[0012] In a possible implementation, comparing the received data at each sampling moment with the test signal one by one and counting the bit error rate corresponding to each delay setting includes: Performing protocol analysis on the sampled data at each sampling moment, identifying the preamble field and the synchronization sequence field, and determining the valid data starting position of each sampled data; Extracting valid data fields from the sampled data at each sampling moment based on a valid data starting position of each sampled data; The valid data field is compared with the valid data field of the test signal, and the bit error rate corresponding to each delay setting is counted.

[0013] In one possible implementation, the method further includes: Test multiple high-speed serial channels in parallel and set the sampling timing and reception delay configuration values corresponding to each channel separately.

[0014] A second aspect of an embodiment of the present application provides a high-speed serial signal testing system, the system being constructed based on an FPGA, the system comprising: The transmitting jitter module is used to adjust the timing of the test signal through a clock reference with adjustable phase to obtain the target test signal; A transmitting driver module is used to send the target test signal to the receiving end via the transmitting driver to obtain a receiving signal; A receiving scanning module is used to extract the target sampling timing of the received signal based on clock recovery, and control the programmable receiving delay chain to adjust the delay of the received signal, perform time scanning within a signal cycle, and obtain sampling data of the received signal at multiple sampling moments; The signal testing module is used to compare the sampled data at the multiple sampling moments with the target test signal, calculate the bit error rate under each delay setting, and complete the signal quality evaluation.

[0015] A third aspect of an embodiment of the present application provides a semiconductor testing device, which includes at least a control device and the high-speed serial signal testing system as described in the second aspect above; the control device is used to control the test function of the high-speed serial signal testing system to be activated.

[0016] A fourth aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the high-speed serial signal testing method described in the first aspect is implemented.

[0017] A fifth aspect of the embodiments of the present application provides a computer program product. When the computer program product is run on a semiconductor testing device, the semiconductor testing device executes the high-speed serial signal testing method described in the first aspect.

[0018] The beneficial effects of the second to fifth aspects mentioned above can all refer to the beneficial effects described in the first aspect mentioned above, and this application will not repeat them here. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0020] Figure 1 This is a structural diagram of a high-speed serial signal testing system provided in an embodiment of the present application; Figure 2 This is a structural diagram of another high-speed serial signal testing system provided in an embodiment of the present application; Figure 3 It is the specific implementation process of CDR; Figure 4 This is a flow chart of a high-speed serial signal testing method provided in an embodiment of the present application; Figure 5This is a schematic diagram of the structure of the serial-to-parallel conversion module and the DDS-based low-speed jitter clock generation module; Figure 6 This is a diagram of the jitter of a low-speed clock; Figure 7 This is a schematic diagram of the output driver; Figure 8 This is a schematic diagram of clock recovery for different channels; Figure 9 This is a flowchart of another high-speed serial signal testing method provided by an embodiment of the present application; Figure 10 This is a schematic structural diagram of a semiconductor testing device provided in an embodiment of the present application; Figure 11 This is a structural diagram of another semiconductor testing device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0021] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0022] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0023] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0024] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0025] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0026] It should be understood that the size of the serial numbers of each step in this embodiment does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of this application.

[0027] As integrated circuits and electronic systems evolve toward higher speeds, lower power consumption, and smaller form factors, high-speed serial interfaces are increasingly used in chip interconnects and system communications. These interfaces utilize high-speed serial transmission, differential signaling, and embedded clocks to achieve higher data rates with a limited number of channels, significantly improving signal channel utilization. However, high-speed serial signals are susceptible to noise, jitter, crosstalk, and distortion during transmission, which can degrade signal integrity and timing characteristics, impacting system stability and protocol compatibility. Therefore, testing high-speed serial signals has become a critical task in chip design verification, system debugging, and production testing.

[0028] Currently, mass production testing of high-speed serial signals primarily relies on ATE (automatic test equipment). However, existing ATE equipment has significant shortcomings when addressing these requirements. On the one hand, ATE's inherent test resources are limited, making it difficult to support key functions such as high-speed data driving, clock recovery, and bit error rate statistics required by high-speed serial interfaces. On the other hand, its closed architecture and delayed updates make it difficult to adapt to evolving high-speed protocol standards and complex debugging mechanisms. Mass production environments, in particular, place extremely high demands on test stability, consistency, and throughput efficiency, but traditional ATE lacks effective test paths and strategies for high-speed serial signal links.

[0029] In order to solve the above problems, the present application proposes a high-speed serial signal testing method, system, semiconductor test equipment and storage medium, which adjusts the timing of the test signal through a programmable transmit delay chain and actively introduces controllable jitter for jitter tolerance testing; the target test signal is sent to the receiving end through the transmit driver, and after obtaining the received signal, the sampling timing is extracted based on clock recovery, and the programmable receive delay chain is controlled to perform time scanning to obtain the received data at multiple sampling moments; by comparing each sampling data with the test signal, the bit error rate under each delay setting is statistically analyzed to complete the signal quality evaluation; this solution has the advantages of modularity, high precision, and low cost, and can improve the comprehensive testing efficiency and reliability of semiconductor test equipment for high-speed serial signals.

[0030] The high-speed serial signal testing method, system, semiconductor testing equipment, and storage medium, namely, computer program, provided in embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0031] Figure 1 The schematic diagram of a high-speed serial signal test system provided by an embodiment of the present application is shown. The high-speed serial signal test system is built on an FPGA and may include a transmit jitter module, a transmit driver module, a receive scan module, and a signal test module.

[0032] The transmitting jitter module is used to adjust the timing of the test signal through a clock reference with adjustable phase to obtain the target test signal; The transmitting driver module is used to send the target test signal to the receiving end via the transmitting driver and obtain the receiving signal; The receiving scanning module is used to extract the target sampling timing of the received signal based on clock recovery, and control the programmable receiving delay chain to adjust the delay of the received signal, perform time scanning within a signal cycle, and obtain the sampling data of the received signal at multiple sampling moments; The signal test module is used to compare the sampled data at multiple sampling moments with the test signal, calculate the bit error rate under each delay setting, and complete the signal quality assessment.

[0033] The transmit jitter module uses an internal, phase-adjustable clock reference to adjust the timing of the test signal. This means that by varying the test signal's phase offset, the output edge of the test signal undergoes a controlled shift, thereby generating a target test signal with controllable jitter characteristics. This signal incorporates a designed phase shift, facilitating subsequent jitter tolerance testing and eye diagram evaluation.

[0034] It should be noted that the high-speed serial signal testing system in this application is applied to existing semiconductor testing equipment to improve the semiconductor testing equipment's ability to conduct comprehensive tests on the electrical characteristics, protocol behavior, and jitter tolerance of high-speed serial signals, and to improve the testing efficiency of high-speed serial signals.

[0035] It should also be noted that the method of adjusting the timing of the test signal through a clock reference with adjustable phase in this application can be implemented through a programmable phase-agile clock reference. Specifically, it can be implemented by combining a phase-locked loop and a delay-locked loop, and can also be implemented using the MMCM (mixed-mode clock manager) inside the FPGA. This application does not limit this.

[0036] like Figure 1As shown, after the target test signal is output by the transmit jitter module, it is sent to the receiver by the transmit driver module. The received signal is then sent to the receive scanning module. After receiving the received signal, the receive scanning module first extracts the embedded clock information through a clock recovery (CDR) mechanism to obtain the target sampling timing. It then controls the programmable receive delay chain to perform a time scan at a preset step size within a signal cycle, acquiring sampled data at multiple sampling times for constructing a bit error rate distribution and eye diagram. The sampled data collected at multiple sampling times is then compared bit by bit with the valid data field of the test signal. The bit error rate at each delay setting is calculated, forming an eye diagram for signal quality assessment, including eye opening analysis and jitter tolerance analysis.

[0037] As a possible implementation, see Figure 2 FIG. 1 is a schematic diagram showing another high-speed serial signal test system provided by an embodiment of the present application. Figure 2 As shown, the system includes multiple modules integrated in the FPGA and a transmitting driving module and a receiving comparison module connected to the outside of the FPGA.

[0038] The protocol processing module generates test data based on user-defined test configuration parameters and packages the test data into data frames that conform to the target high-speed serial communication protocol format. This module supports protocols such as MIPI, PCIe, USB, and SATA. This module also adds frame headers, embeds synchronization sequences, and generates pseudo-random codes for use by the signal transmission module. Furthermore, it identifies the valid data fields in the received signal and compares them with the valid data fields in the test signal to determine the bit error rate and output the final signal quality indicator.

[0039] Signal transmission module: receives the test data frame output by the protocol processing module, controls the data rhythm and logic level conversion, and passes it to the transmission jitter module.

[0040] Transmitter Jitter Module: This module injects jitter into the test signal through a phase-adjustable clock reference, changing the edge timing of the test signal to generate a target test signal with controllable jitter.

[0041] Transmitter driver module (external): Receives the target test signal from the FPGA and performs voltage swing driving, and then transmits the target test signal after voltage swing driving to the receiving end (i.e., the receiving comparison module) through the physical link.

[0042] The receive and compare module compares the analog target test signal with a set voltage threshold, converting the analog received signal into a digital signal and outputting it to the data receiving module. This module typically consists of a high-speed comparator and determines whether the signal is high or low based on threshold voltages (such as VOH and VOL).

[0043] Data receiving module: used to receive digital signals from the receiving and comparing module, serving as the basis for subsequent clock recovery and sampling processing.

[0044] Clock recovery module: It is used to recover the clock of the digital signal output by the data receiving module, extract the embedded clock signal from it, and generate the target sampling timing. This module can be implemented using CDR (Clock and Data Recovery) logic based on data flip point. The specific implementation process of CDR can be found in Figure 3 , that is, according to the received signal ( Figure 3 The input data in the signal is detected and the phase of the signal is determined to extract the clock information and determine the correct target sampling position.

[0045] Receive Scan Module: This module performs a time scan of the received signal using the clock reference output by the clock recovery module. By configuring a programmable receive delay chain, it introduces different delays to the received signal and acquires received data at multiple sampling times. Delayed step sampling is performed within a signal cycle, forming a mapping between bit error rate and time (which can be used for eye diagram analysis).

[0046] In this embodiment, the signal transmission module, the data receiving module, and the clock recovery module can all be implemented using the SERDES IP provided by the FPGA, such as Xilinx's GTH.

[0047] For example, taking the test of MIPI C-PHY three-level differential signals as an example, the user can first enter the test configuration parameters in the host computer interface, including the protocol type (MIPI C-PHY), transmission rate (such as 16.3Gbps), differential swing (such as 200mV), and pseudo-random code pattern (such as PRBS7). The system's protocol processing module generates a data frame containing a preamble and synchronization sequence, and maps it into a logical bit stream that complies with the C-PHY three-level specification (low level V_L, middle level V_M, high level V_H). It is then output to the transmission jitter module inside the FPGA under the rhythm control of the signal transmission module.

[0048] The transmit jitter module uses a phase-adjustable clock reference (such as a programmable phase-agile clock reference) to apply periodic (±5ps) and random (±2ps) phase offsets to each bit period (UI), generating a target test signal with controllable jitter. The external transmit driver module completes the differential voltage swing and transmits it to the receiver. The comparator module on the receiver converts the incoming analog three-level signal into a digital bit stream based on a preset threshold. The data receiver module buffers the signal and feeds it into the clock recovery (CDR) module, extracting the embedded clock and determining the target sampling point. Based on this target sampling point, the receive scan module adjusts the signal phase within a range of ±UI / 2 in 2ps steps to acquire sampled data at multiple phases.

[0049] The protocol processing module compares the sampled data under different phase signals with the original PRBS7 data bit by bit, calculates and summarizes the bit error rate-timing offset mapping curve, and digitally generates an eye diagram based on this. By observing the critical point where the bit error rate changes with the jitter amplitude, the receiver's timing tolerance and signal quality under the MIPI C-PHY three-level protocol can be accurately evaluated.

[0050] In the embodiment of the present application, the above system does not require an expensive oscilloscope and has the advantages of high precision, low cost and high automation testing.

[0051] See also Figure 4 , shows a flow chart of a high-speed serial signal testing method provided by an embodiment of the present application; the high-speed serial signal testing method is applied to Figure 1 The high-speed serial signal test system shown in FIG. Figure 4 As shown, the method may include the following steps: Step 401 : Adjust the timing of a test signal using a phase-adjustable clock reference to obtain a target test signal.

[0052] The phase-adjustable clock reference refers to a reference clock source that can dynamically change the output clock phase through control logic.

[0053] By way of example, and not limitation, the present application implements timing adjustment of test signals using a phase-adjustable clock reference. This can be implemented using a phase-locked loop (PLL), mixed-mode clock manager (MMCM), delay-locked loop (DLL) module integrated in an FPGA, or a direct digital frequency synthesizer (DDFS). PLL and MMCM modules typically implement discrete phase selection through multi-phase outputs, while DDFS utilizes a phase accumulator for continuous phase control, resulting in higher phase adjustment accuracy. For example, in a DDFS architecture employing a 10-bit phase accumulator, the minimum phase step can reach 360° / 1024, meeting the requirements of high-precision jitter simulation.

[0054] This type of clock reference can jump between multiple preset phases or adjust the phase in fine-grained steps. It is used to drive the test signal generation module, thereby achieving controllable offset of signal edge positions and forming output waveforms with different jitter characteristics. A programmable phase-agile clock reference is a clock control mechanism that supports rapid phase switching and jump configurations. It is suitable for constructing test signal systems with adjustable timing and adjustable jitter characteristics.

[0055] Timing adjustment refers to the time shifting operation on the rising or falling edge of the test signal. Specifically, it can be achieved by phase switching and jumping through a programmable phase-agile clock reference to generate a target test signal with controllable jitter.

[0056] Specifically, the high-speed serial signal test system first adjusts the timing of the test signal using a programmable phase-agile clock reference to achieve precise control of the test signal timing. The programmable phase-agile clock reference consists of a clock management module with multi-phase output capability. This module can rapidly switch between multiple preset phases through configuration registers or control instructions. Each phase state corresponds to a clock output with a fixed phase offset relative to the reference clock. By dynamically switching the output clocks of different phases, the timing of the test signal's edge emission can be adjusted without changing the clock frequency, achieving precise control of the rising and falling edge timing, thereby generating the target test signal with controllable jitter characteristics.

[0057] For example, a programmable phase-agile clock reference can be composed of a clock management module with multi-phase output capability (such as an MMCM or PLL (phase-locked loop) in an FPGA). It supports fixed-phase step switching of the output clock from 0° to 360°, with a phase resolution of up to 5°, corresponding to a timing accuracy of approximately 10ps (using a 200MHz clock as an example). By loading configuration registers or issuing digital control commands, it can quickly jump between multiple preset phases, thereby achieving dynamic adjustment of the reference clock phase, which is used to drive edge control of test signals and realize high-precision, jitter-controlled timing generation.

[0058] In one possible implementation, the system, based on a serial-to-parallel converter module, can combine multiple low-speed digital signals into a single high-speed serial output signal, driven by a reference clock. Before generating the test signal, a low-speed reference clock signal is first processed by a clock management module with multi-phase output capabilities to generate multiple low-speed clock signals with fixed phase differences. These phase-shifted low-speed clocks are used to drive multiple low-speed parallel data channels, ensuring that the parallel data is fed into the serial-to-parallel converter according to the set timing relationship, thereby achieving high-speed signal construction and precise timing control.

[0059] To further simulate the jitter characteristics of real signals in the time domain, the system can integrate a low-speed jitter clock generation module based on DDS (Direct Digital Synthesizer). The DDS module includes a phase accumulator, a waveform lookup table, a digital-to-analog converter (DAC), and a filtering module to output a continuous, frequency-controllable clock waveform. By dynamically providing the step value of each DDS phase accumulation through a random codeword generator, the phase of the output clock can be modulated to inject controllable jitter into the low-speed reference clock. Its serial-to-parallel conversion module and the low-speed jitter clock generation module based on DDS (Direct Digital Synthesizer) can be found in Figure 5 , the jitter diagram of the low-speed clock can be seen in Figure 6 This jitter is ultimately inherited by the serial-to-parallel conversion module and reflected in the final target test signal, providing a real and adjustable source of timing disturbance for subsequent signal quality scanning and bit error rate analysis.

[0060] Ultimately, under the further control of a phase-adjustable clock reference, the target test signal possesses the required rising / falling edge timing characteristics and artificially injected phase jitter, which is used to accurately simulate signal changes in actual high-speed transmission systems and provide ideal test input for reception analysis in subsequent steps.

[0061] In one possible implementation, timing adjustment of a test signal is performed using a phase-adjustable clock reference to obtain a target test signal, including: Based on a preset phase jump control instruction, the reference clock is phase-switched to obtain multiple phase-switched clocks; According to the sending timing of the test signal driven by multiple phase switching clocks and the reference clock, a target test signal with controllable jitter is generated.

[0062] The controllable jitter implementation includes presetting the jitter amplitude, jitter frequency and jitter waveform type, wherein the waveform type includes a sine wave, a triangle wave or a random jitter pattern.

[0063] Specifically, the clock control module dynamically configures the reference clock according to the preset phase jump control instruction, so that it periodically switches between multiple discrete phase values, generating multiple phase switching clocks with different phase offsets. The driving timing of the test signal is determined by these phase switching clocks and the original reference clock, forming a controllable edge offset trajectory, thereby realizing dynamic adjustment of the test signal timing. The phase switching process is equivalent to superimposing a periodic time offset on the signal edge position, thereby constructing a target test signal with a set jitter pattern. For example, when the phase jump control instruction is cyclically switched within the phase offset range of ±10 degrees at a frequency of 1kHz, the corresponding test signal will exhibit deterministic jitter with an amplitude of approximately 20ps and a frequency of 1kHz. The entire adjustment process is executed in real time by the clock management logic embedded in the FPGA to ensure that the stability and resolution of the phase switching meet the accuracy requirements of high-speed timing control.

[0064] In one possible implementation, if the test signal is a three-level signal, such as for MIPI C-PHY multi-level transmission protocol testing, the target test signal generation process in step 401 may include the following detailed operations: The output voltages of low level, middle level and high level are set by the digital-to-analog converter; Controlling the transmit drive circuit to map the logic bit to the corresponding level; Controllable timing jitter is introduced through a phase-adjustable clock reference to achieve timing adjustment of multi-level test signals.

[0065] In this embodiment, the low, medium, and high levels can be set to 150mV, 300mV, and 450mV, respectively. The transmit delay chain adds periodic jitter with a peak value of 5% in 10ps steps, thereby generating a target test signal with both level diversity and controllable jitter characteristics, significantly enhancing the test coverage of the receiving end protocol compatibility and jitter robustness.

[0066] Step 402: Send the target test signal to the receiving end via the transmitting driver to obtain a received signal.

[0067] In the embodiment of the present application, the target test signal is sent to the receiving end via the transmit driver circuit, which converts the digital logic level into a voltage swing and impedance matching characteristic that meets the requirements of the target protocol.

[0068] For example, refer to Figure 7 As shown in the output driver schematic, the output driver circuit can adopt a two-stage structure, including a low-speed driver and a high-speed driver, which are respectively responsible for the reference setting of the output voltage and the rapid conversion of the relative level.

[0069] The low-speed driver outputs a stable voltage reference level. Its output voltage is determined by control bit 1 and can be configured to multiple reference values (for example, 1V or 2.5V). The high-speed driver, based on the voltage reference provided by the low-speed driver, outputs high-speed voltage variations within a range of ±ΔV, where ΔV is a preset voltage variation (for example, ±0.5V). Its output is driven by control bit 0, achieving high-speed signal modulation.

[0070] For example, if the voltage reference is 1V or 2.5V and the voltage variation is ±0.5V, the overall output drive can achieve four different level combinations.

[0071] bit1=0, bit0=0; reference 1V + 0.5V = 1.5V.

[0072] bit1=0, bit0=1; reference 1V - 0.5V = 0.5V.

[0073] bit1=1, bit0=0; reference 2.5V + 0.5V = 3.0V.

[0074] bit1=1, bit0=1; reference 2.5V - 0.5V = 2.0V.

[0075] By combining different bit1 and bit0 configurations, the output driver circuit can quickly and stably generate multiple high-speed voltage levels to support high-speed signal transmission requirements under different protocols or voltage standards. This structure decouples the voltage reference from the fast transition, improving the integrity and adjustability of the drive signal. It also facilitates coordination with the comparator threshold at the receiving end, enhancing the overall test flexibility and robustness of the system.

[0076] Step 403 : Based on clock recovery, extract the target sampling timing of the received signal, control the programmable receiving delay chain to adjust the delay of the received signal, perform time scanning within one signal cycle, and obtain sampling data of the received signal at multiple sampling moments.

[0077] Among them, clock recovery refers to extracting clock information synchronized with the data from the received signal. Specifically, a phase-locked loop or digital clock manager can be used to track the edge transitions of the received signal to determine the reference timing of sampling at the receiving end.

[0078] The programmable receiving delay chain refers to a receiving-end time adjustment circuit, which can be implemented using a programmable digital delay line in an FPGA. It is used to continuously adjust the position of the sampling point within a signal cycle to achieve time scanning.

[0079] Among them, time scanning refers to changing the sampling time with a fixed step size within a single signal cycle. It can be achieved by gradually increasing or decreasing the delay value of the receiving delay chain to obtain the sampling data distribution of the received signal at different time points. Specifically, after acquiring the received signal, the receiver first extracts the target sampling timing of the received signal using clock recovery technology. The clock recovery circuit tracks the data transition edges of the received signal and reconstructs a sampling clock synchronized with the data. Next, it controls the programmable receive delay chain to adjust the delay of the received signal. The programmable receive delay chain consists of multiple stages of adjustable delay units, with different delay configurations set via digital control signals. Within a signal cycle, the receive delay chain changes the delay setting in fixed steps, achieving high-density time scanning of the received signal. At each delay setting, the received signal is sampled, acquiring sampled data at multiple sampling instants.

[0080] For example, a high-speed comparator (i.e., a receive comparator module) at the receiving end can convert a differential signal into a single-ended digital signal. The comparator's threshold voltages are set by a digital-to-analog converter and include a high threshold voltage (VOH) and a low threshold voltage (VOL). Its clock recovery module can employ a digital phase-locked loop (DPLL) architecture to track the data transition edges of the received signal and reconstruct a sampling clock synchronized with the data. The sampling clock's frequency matches the data rate, and its phase is center-aligned with the data center. A programmable receive delay chain can consist of 32 adjustable delay units. The delay time of each delay unit is adjustable from 0 to 5 ps, with a delay resolution of 0.05 ps. Within a signal cycle, the receive delay chain adjusts the delay setting in fixed steps of 0.5 ps to achieve 32 evenly distributed sampling times. The protocol processing module then processes the sampled data at these 32 sampling times.

[0081] In one possible implementation, extracting a target sampling timing from a received signal based on clock recovery includes: Perform clock recovery based on the high and low level flip information in the received signal to obtain the embedded recovered clock of the received signal; The target sampling timing is determined based on the embedded recovered clock of the received signal.

[0082] Among them, high-low level flip information is obtained by detecting the transition point of the logic state from high to low or low to high in the received signal. The transition point carries the clock phase information; the embedded recovered clock can be generated by periodically tracking the transition point interval through a phase-locked loop, and its frequency is consistent with the actual transmission rate of the received signal; the target sampling timing is determined by taking the rising edge or falling edge of the recovered clock as the reference point and superimposing a fixed phase offset.

[0083] Specifically, during the received signal transmission process, a high-speed comparator continuously monitors the signal level. When it detects that the interval between two consecutive transition points is equal to the preset signal period, it triggers the clock recovery module to activate the phase-locked loop circuit. The phase-locked loop circuit adjusts the internal oscillator frequency to align the recovered clock edge with the transition point, ultimately outputting a phase-synchronized embedded recovered clock. Subsequently, the digital control logic divides the clock cycle into multiple equally spaced sampling windows based on the recovered clock edge position, with each sampling window corresponding to a sampling instant. For example, in PCIe 5.0 protocol testing, the recovered clock frequency is 16 GHz. The sampling window is based on the recovered clock rising edge, with a sampling point set every 6.25 ps to cover the signal variation region within the entire bit period.

[0084] In one possible implementation, with a target sampling timing as a sampling reference, controlling a programmable receiving delay chain to adjust a delay of a received signal, performing time scanning within a signal cycle, and acquiring sampling data of the received signal at multiple sampling moments includes: According to a preset fixed delay step size, a plurality of different delay configuration values are set for the programmable receiving delay chain to evenly distribute a plurality of sampling moments within a receiving signal cycle; At each sampling moment, the received signal is sampled to obtain sampling data of the received signal at multiple sampling moments.

[0085] The fixed delay step size is set to evenly space the receive signal period. For example, within a 200ps signal period at 5Gbps, 20 delay configuration values are set in 10ps steps. Delay configuration values are written to the programmable receive delay chain via registers, with each configuration value corresponding to a specific phase offset within the receive signal period. Uniform distribution of sampling times is achieved through fixed-step accumulation, ensuring consistent time intervals between adjacent sampling points.

[0086] Specifically, the delay of the programmable receive delay chain is linearly controlled by the configuration value, with each step increasing the delay by a fixed value. During the time scan, the delay configuration value is loaded sequentially in increments of the step size, gradually moving the sampling point from the beginning to the end of the signal cycle. For example, with the initial configuration value, the sampling point is located at 0ps of the signal cycle; when the configuration value is increased by one step, the sampling point is delayed by 10ps; when the configuration value reaches the maximum value, the sampling point is located at 190ps. Because the step size is fixed and evenly accumulated, the sampling points are evenly spaced within the signal cycle. This approach ensures that the sampled data covers the rising and falling edges of the signal, as well as the steady-state period, avoiding errors in the identification of the eye opening area due to uneven sampling point distribution. By iterating through all delay configuration values, the voltage changes of the received signal over a complete cycle are fully captured, providing a high-resolution data foundation for bit error rate statistics.

[0087] Step 404 : Compare the sampled data at multiple sampling moments with the test signal, calculate the bit error rate under each delay setting, and complete the signal quality assessment.

[0088] Among them, bit error rate statistics refer to comparing the received signal with the test signal bit by bit and calculating the error ratio. Specifically, hardware logic can be used to implement a real-time comparison counter to quantify the difference in signal quality under different delay settings.

[0089] Specifically, the sampled data at multiple sampling times is compared with the test signal, and the bit error rate (BER) for each delay setting is calculated. By analyzing the BER distribution, the eye diagram characteristics of the received signal can be constructed. Signal quality is assessed based on the characteristics of the eye opening area. This high-density scanning-based evaluation method accurately reflects the timing margin and voltage noise tolerance of the received signal.

[0090] In one possible implementation, the sampled data at multiple sampling times are compared with the test signal, and the bit error rate under each delay setting is calculated to complete the signal quality assessment, including: Compare the sampled data at each sampling moment with the test signal one by one, and calculate the bit error rate corresponding to each delay setting; Construct an eye diagram of the received signal based on the bit error rate distribution; Signal quality assessment is completed based on the eye diagram of the received signal.

[0091] Among them, bit error rate statistics are achieved by comparing the received data with the original test sequence bit by bit, and each delay setting corresponds to a specific sampling phase; eye diagram construction forms a two-dimensional distribution by mapping the bit error rate onto the time axis, with the horizontal axis representing the sampling time offset and the vertical axis representing the bit error rate value; open area identification uses a threshold comparison algorithm to screen continuous areas with a bit error rate lower than one millionth; center position calculation determines the midpoint of the time interval through linear interpolation.

[0092] Exemplarily, the received data at each sampling moment is compared with the test signal one by one, and the bit error rate corresponding to each delay setting is counted. Specifically, multiple sampling moments can be set, for example, 16 sampling points are evenly distributed within a signal cycle. For each sampling point, the sampled data is compared with the data at the corresponding position of the original test signal to calculate the number of bit errors. The bit error rate corresponding to each sampling point is then calculated based on the total number of bits. An eye diagram of the received signal is constructed based on the bit error rate distribution. The bit error rate data of each sampling point is plotted into a two-dimensional graph, with the horizontal axis representing the sampling time and the vertical axis representing the bit error rate. The eye diagram contour is formed by connecting adjacent points. Based on the eye diagram contour, the signal quality assessment is completed. Quality assessments such as bit error rate testing and jitter analysis can also be performed.

[0093] In one possible implementation, the received data at each sampling moment is compared with the test signal one by one, and the bit error rate corresponding to each delay setting is calculated, including: Perform protocol analysis on the sampled data at each sampling moment, identify the preamble field and synchronization sequence field, and determine the valid data starting position of each sampled data; Extracting valid data fields from the sampled data at each sampling moment based on the valid data starting position of each sampled data; Compare the valid data field with the valid data field of the test signal, and calculate the bit error rate corresponding to each delay setting.

[0094] Protocol parsing is implemented through hardware logic or firmware. The preamble field is a fixed bit sequence specified by the specific protocol, indicating the start of a data frame. The synchronization sequence field is used for clock alignment and symbol boundary calibration. The starting position of valid data is determined by detecting the offset between the end position of the preamble and the end position of the synchronization sequence. After the valid data field is extracted, the bit error rate is calculated through bit-by-bit comparison or block check.

[0095] Specifically, the received signal, after being sampled at the target sampling timing, is input into the protocol parsing module. The preamble detection circuit matches the fixed bit sequence and determines the end of the preamble when the number of consecutive matches exceeds a preset threshold. The synchronization sequence detection circuit searches for symbol boundaries based on the symbol interval specified by the protocol and determines the symbol alignment point. The starting position of the valid data is calculated by the relative offset between the end position of the preamble and the synchronization sequence alignment point. The valid data field is intercepted from the received signal based on the starting position and the preset length. It is then sent to the bit error rate statistics module for bit-by-bit comparison with the original test signal data. The bit error rate calculation results are used to evaluate signal quality, ensuring that the test results reflect the actual transmission performance.

[0096] In a possible implementation, the high-speed serial signal testing method further includes: performing parallel testing on multiple high-speed serial channels, and respectively setting a sampling timing and a receiving delay configuration value corresponding to each channel.

[0097] Since different routing delays and device delays will result in different timings for different lanes, different lanes require different CDRs to independently recover the clock in order to determine their own optimal sampling moments. Figure 8 .

[0098] In an embodiment of the present application, the above steps 401 to 404 adjust the timing of the test signal through a programmable transmit delay chain, actively introduce controllable jitter for jitter tolerance testing; the target test signal is sent to the receiving end via the transmit driver, and after the received signal is obtained, the sampling timing is extracted based on clock recovery, and the programmable receive delay chain is controlled to perform time scanning to obtain the received data at multiple sampling moments; by comparing each sampled data with the test signal, the bit error rate under each delay setting is counted to complete the signal quality evaluation; this solution has the advantages of modularity, high precision, and low cost, and improves the comprehensive test efficiency and accuracy of high-speed serial signals.

[0099] See also Figure 9 , shows a flow chart of another high-speed serial signal testing method provided by an embodiment of the present application. Figure 9 As shown, the method may include the following steps: Step 901: Generate a test signal that complies with a target protocol format based on preset test configuration parameters.

[0100] In an embodiment of the present application, the preset test configuration parameters can be set by a control device of the semiconductor testing equipment.

[0101] The test configuration parameters include at least protocol type, transmission rate, and voltage swing parameters. The valid data field of the test signal is generated based on a pseudo-random number generator to simulate actual business data.

[0102] Specifically, the protocol type parameter ensures that the test signal conforms to the target interface specification, the transmit rate parameter controls the signal timing frequency, and the voltage swing parameter defines the signal amplitude range. The valid data field generated by the pseudo-random number generator contains a randomized sequence of 0s and 1s, covering a variety of data combinations and simulating real-world service data flows. Test configuration parameters are set via configuration registers. The protocol type parameter selects the frame structure of different interfaces, such as MIPI, PCIe, or USB; the transmit rate parameter sets the signal baud rate; and the voltage swing parameter adjusts the driver output amplitude. The pseudo-random number generator uses an LFSR structure to generate a PRBS7 or PRBS31 sequence to fill the valid data field, simulating the random data distribution found in real-world transmission scenarios. The resulting test signal not only meets the target protocol format requirements but also exhibits statistical characteristics similar to actual service data, ensuring that subsequent timing adjustments and bit error rate statistics accurately reflect the performance of the system under test in real-world scenarios.

[0103] Step 902: Perform timing adjustment on the test signal using a clock reference with adjustable phase to obtain a target test signal.

[0104] Step 903: Send the target test signal to the receiving end via the transmitting driver to obtain a received signal.

[0105] Step 904 : Based on clock recovery, extract the target sampling timing of the received signal, control the programmable receiving delay chain to adjust the delay of the received signal, perform time scanning within one signal cycle, and obtain sampling data of the received signal at multiple sampling moments.

[0106] Step 905 : Compare the sampled data at multiple sampling moments with the test signal, calculate the bit error rate under each delay setting, and complete the signal quality assessment.

[0107] The implementation of steps 902 to 905 in the embodiment of the present application is the same as that of steps 401 to 404 in the above embodiment, and they can refer to each other, and the present application will not repeat them here.

[0108] Compared to the aforementioned embodiments, the present embodiment can flexibly generate test signals that comply with a variety of high-speed serial interface protocols, improving the versatility and configurability of the test system for semiconductor test equipment. By using pseudo-random data to simulate actual service data, the authenticity of the test is enhanced, helping to identify potential signal integrity issues. Furthermore, the preset test configuration parameters allow the test process to quickly adapt to different application scenarios and test requirements, improving test efficiency.

[0109] Figure 10 Schematic diagram of a semiconductor testing device provided by an embodiment of the present application. Figure 10 As shown, the semiconductor testing equipment of this embodiment includes at least a control device and a high-speed serial signal testing system, wherein the control device is used to control the activation of the test function of the high-speed serial signal testing system. For example, when the high-speed serial signal of the chip needs to be tested, the high-speed serial signal testing function of the semiconductor testing equipment can be activated by the control device.

[0110] The high-speed serial signal test system at least includes a transmitting jitter module, a transmitting driving module, a receiving scanning module and a signal testing module.

[0111] In an embodiment of the present application, the high-speed serial signal testing system further includes: A test signal generation module is used to generate a test signal that conforms to the target protocol format based on preset test configuration parameters. The test configuration parameters include at least the protocol type, transmission rate, and voltage swing parameters. The valid data field of the test signal is generated based on a pseudo-random number generator to simulate actual business data.

[0112] In the embodiment of the present application, the transmission jitter module may further include: A phase switching unit, configured to perform phase switching on a reference clock based on a preset phase jump control instruction to obtain a plurality of phase switching clocks; The driving unit is used to drive the sending timing of the test signal according to the multiple phase switching clocks and the reference clock to generate a target test signal with controllable jitter.

[0113] In the embodiment of the present application, the receiving scanning module may specifically include: A clock recovery unit, configured to perform clock recovery based on high- and low-level flip information in the received signal to obtain an embedded recovered clock of the received signal; The target sampling determination unit is used to determine the target sampling timing according to the embedded recovered clock of the received signal.

[0114] In the embodiment of the present application, when the target sampling timing is used as the sampling reference, the receiving scanning module may further include: a delay value configuration unit, configured to set a plurality of different delay configuration values for the programmable receiving delay chain according to a preset fixed delay step size, so as to evenly distribute a plurality of sampling moments within a receiving signal cycle; The sampling and obtaining unit is used to sample the received signal at each sampling moment and obtain sampling data of the received signal at the multiple sampling moments.

[0115] In the embodiment of the present application, the signal testing module may specifically include: A comparison unit, configured to compare the sampled data at each sampling moment with the test signal one by one, and to calculate the bit error rate corresponding to each delay setting; An eye diagram construction unit, configured to construct an eye diagram of the received signal based on the bit error rate distribution; The quality evaluation unit is used to complete signal quality evaluation according to the eye diagram of the received signal.

[0116] In the embodiment of the present application, the sampling acquisition unit can be specifically used to: Performing protocol analysis on the sampled data at each sampling moment, identifying the preamble field and the synchronization sequence field, and determining the valid data starting position of each sampled data; Extracting valid data fields from the sampled data at each sampling moment based on a valid data starting position of each sampled data; The valid data field is compared with the valid data field of the test signal, and the bit error rate corresponding to each delay setting is counted.

[0117] In an embodiment of the present application, the high-speed serial signal testing system further includes: The parallel test module is used to perform parallel testing on multiple high-speed serial channels and set the sampling timing and receiving delay configuration values corresponding to each channel respectively.

[0118] Figure 11 This is a schematic diagram of the structure of another semiconductor testing device provided by an embodiment of the present application. Figure 11 As shown, the semiconductor testing device 1100 of this embodiment includes: at least one processor 1110 ( Figure 11 Only one is shown in the figure) a processor, a memory 1120, and a computer program 1121 stored in the memory 1120 and executable on the at least one processor 1110. When the processor 1110 executes the computer program 1121, the steps in the above-mentioned high-speed serial signal testing method embodiment are implemented.

[0119] The semiconductor testing device 1100 may be a server, a physical server, a computing device, etc. The semiconductor testing device may include, but is not limited to, a processor 1110 and a memory 1120. It will be understood by those skilled in the art that Figure 11 This is merely an example of the semiconductor testing device 1100 and does not constitute a limitation on the semiconductor testing device 1100 . The semiconductor testing device 1100 may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the semiconductor testing device 1100 may also include input and output devices, network access devices, etc.

[0120] The processor 1110 may be a central processing unit (CPU), or may be another general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor may be a microprocessor or any conventional processor.

[0121] In some embodiments, the memory 1120 may be an internal storage unit of the semiconductor testing device 1100, such as a hard drive or memory of the semiconductor testing device 1100. In other embodiments, the memory 1120 may also be an external storage device of the semiconductor testing device 1100, such as a plug-in hard drive, a Smart Media Card (SMC), a Secure Digital (SD) card, a flash memory card, etc. equipped on the semiconductor testing device 1100. Furthermore, the memory 1120 may include both the internal storage unit of the semiconductor testing device 1100 and an external storage device. The memory 1120 is used to store an operating system, application programs, a boot loader, data, and other programs, such as the program code of the computer program. The memory 1120 may also be used to temporarily store data that has been output or is about to be output.

[0122] In a specific implementation, the processor 1110, memory 1120, and computer program 1121 described in the embodiments of the present application can execute the embodiments of the high-speed serial signal testing method of the present application, which will not be described in detail here.

[0123] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated into one processing unit, or each unit can exist physically alone, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0124] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0125] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0126] In the embodiments provided in this application, it should be understood that the disclosed devices / semiconductor testing equipment and methods can be implemented in other ways. For example, the device / semiconductor testing equipment embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0127] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0128] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0129] If the integrated module / unit is implemented as a software functional unit and sold or used as a standalone product, it can be stored in a computer-readable storage medium. Based on this understanding, the present application can implement all or part of the process steps in the above-mentioned method embodiments by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When executed by a processor, the computer program can implement the steps of each of the above-mentioned method embodiments. The computer program includes computer program code, which can be in source code form, object code form, executable file, or some intermediate form. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal, and software distribution medium. It should be noted that the content of the computer-readable medium can be appropriately increased or decreased based on the requirements of legislation and patent practice in a jurisdiction. For example, in some jurisdictions, based on legislation and patent practice, computer-readable media does not include electric carrier signals and telecommunication signals.

[0130] The present application implements all or part of the processes in the above-mentioned embodiment method, and can also be completed through a computer program product. When the computer program product is run on a semiconductor testing device, the semiconductor testing device can implement the steps in the above-mentioned method embodiments when executed.

[0131] The above embodiments are intended only to illustrate the technical solutions of the present application and are not intended to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they may still modify the technical solutions described in the above embodiments or replace some of the technical features therein with equivalents; and such modifications or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present application and should be included within the scope of protection of the present application.

Claims

1. A high-speed serial signal testing method, characterized in that: Applied to a high-speed serial signal test system, the method includes: The test signal is adjusted in timing by a clock reference with adjustable phase to obtain a target test signal; Sending the target test signal to the receiving end via the transmitting driver to obtain a receiving signal; Based on clock recovery, a target sampling timing is extracted from the received signal, and a programmable receiving delay chain is controlled to adjust the delay of the received signal, and time scanning is performed within a signal cycle to obtain sampling data of the received signal at multiple sampling moments; The sampling data at the multiple sampling moments are compared with the test signal, and the bit error rate under each delay setting is counted to complete the signal quality evaluation.

2. The method according to claim 1, wherein Before adjusting the timing of the test signal by using the phase-adjustable clock reference to obtain the target test signal, the method further includes: Based on preset test configuration parameters, a test signal that conforms to the target protocol format is generated. The test configuration parameters include at least the protocol type, transmission rate, and voltage swing parameters. The valid data field of the test signal is generated based on a pseudo-random number generator to simulate actual business data.

3. The method according to claim 2, wherein The step of adjusting the timing of the test signal by using a clock reference with an adjustable phase to obtain a target test signal includes: Based on a preset phase jump control instruction, the reference clock is phase-switched to obtain multiple phase-switched clocks; The test signal is driven to be emitted at a timing according to the multiple phase-switching clocks and the reference clock, thereby generating a target test signal with controllable jitter.

4. The method according to claim 1, wherein The extracting a target sampling timing from the received signal based on clock recovery includes: Perform clock recovery based on high and low level flip information in the received signal to obtain an embedded recovered clock of the received signal; A target sampling timing is determined according to the embedded recovered clock of the received signal.

5. The method according to claim 4, wherein In a case where the target sampling timing is used as a sampling reference, controlling the programmable receiving delay chain to adjust the delay of the received signal, performing time scanning within a signal cycle, and obtaining sampling data of the received signal at multiple sampling moments, including: According to a preset fixed delay step size, setting a plurality of different delay configuration values for the programmable receiving delay chain to evenly distribute a plurality of sampling moments within a receiving signal cycle; The received signal is sampled at each sampling moment to obtain sampling data of the received signal at the multiple sampling moments.

6. The method according to claim 1, wherein The comparing the sampled data at the plurality of sampling moments with the test signal, calculating the bit error rate under each delay setting, and completing the signal quality assessment includes: Compare the sampled data at each sampling moment with the test signal one by one, and calculate the bit error rate corresponding to each delay setting; constructing an eye diagram of the received signal based on the bit error rate distribution; Signal quality evaluation is completed according to the eye diagram of the received signal.

7. The method according to claim 6, wherein The step of comparing the received data at each sampling moment with the test signal one by one and calculating the bit error rate corresponding to each delay setting includes: Performing protocol analysis on the sampled data at each sampling moment, identifying the preamble field and the synchronization sequence field, and determining the valid data starting position of each sampled data; Extracting valid data fields from the sampled data at each sampling moment based on a valid data starting position of each sampled data; The valid data field is compared with the valid data field of the test signal, and the bit error rate corresponding to each delay setting is counted.

8. The method according to claim 1, wherein The method further comprises: Test multiple high-speed serial channels in parallel and set the sampling timing and reception delay configuration values corresponding to each channel separately.

9. A high-speed serial signal testing system, characterized in that: The system is built based on FPGA and includes: The transmitting jitter module is used to adjust the timing of the test signal through a clock reference with adjustable phase to obtain the target test signal; A transmitting driver module is used to send the target test signal to the receiving end via the transmitting driver to obtain a receiving signal; A receiving scanning module is used to extract the target sampling timing of the received signal based on clock recovery, and control the programmable receiving delay chain to adjust the delay of the received signal, perform time scanning within a signal cycle, and obtain sampling data of the received signal at multiple sampling moments; The signal testing module is used to compare the sampled data at the multiple sampling moments with the test signal, calculate the bit error rate under each delay setting, and complete the signal quality evaluation.

10. A semiconductor testing device, characterized in that: The semiconductor test equipment comprises at least a control device and the high-speed serial signal test system according to claim 9; The control device is used to control the test function of the high-speed serial signal test system to start.

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