A feeder automation terminal board communication system

Abstract

The present application belongs to the technical field of feeder automation terminal board communication, and particularly relates to a feeder automation terminal board communication system. The system comprises a master board and a slave board, the master board and the slave board are connected through a data line, and the slave board is connected with a CPU. The master board is used for sending data, the slave board is used for receiving data, detecting whether the received data is correct, and transmitting the detection result to the CPU, the CPU decides whether to start a self-detection adaptive function, and if the self-detection adaptive function needs to be started, the slave board adjusts the data phase according to the detection result to reduce the occurrence of data transmission errors, and significantly improves the reliability of data transmission.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of feeder automation terminal device board communication, and particularly relates to a feeder automation terminal board communication system. BACKGROUND

[0002] As a key monitoring device of the power system, the feeder automation terminal device deeply participates in the power transmission and distribution process and undertakes the core task of data acquisition and processing. It plays an irreplaceable role in ensuring the stable operation of the power system, which is specifically embodied in three key functions of real-time monitoring, fault isolation and self-healing network construction. Through real-time data acquisition and processing, the device can accurately master the operation state of the power system and ensure that it is always in normal operation mode. When a fault occurs in the feeder terminal, the isolation mechanism can be quickly started to effectively contain the fault spread and maintain the overall stability of the power grid. With the self-healing technology, the device can realize the autonomous repair of the monitoring network, ensure the communication reliability and significantly improve the overall reliability of the power system.

[0003] The feeder automation terminal device is cooperatively worked by multiple boards, and the boards interact with each other through a bus. The current inter-board communication bus is mainly divided into two types of parallel bus and serial bus. Regardless of which type of bus is used, the frequency and phase of the communication signal are strictly tested and fixed before leaving the factory, and cannot be self-detected and adaptively adjusted according to the actual working environment. This fixed communication parameter setting method limits the adaptability of the device to the complex and variable field environment to some extent, and also hides hidden dangers for subsequent system operation and maintenance.

[0004] The parallel bus has many disadvantages in the inter-board communication of the feeder automation terminal device. First, due to the use of multi-data line parallel transmission mode, the number of signal lines is large, which occupies a large number of pins and wiring space, increases the system complexity and cost, and lacks self-detection and adaptive function, further increasing the debugging difficulty and time cost. Secondly, the mutual interference between the signal lines limits the transmission speed. In order to avoid signal attenuation and distortion, the transmission speed has to be reduced to adapt to all situations. Thirdly, the parallel bus has strict requirements on the transmission performance and circuit structure of the device, and the overall design difficulty is high, which further increases the system complexity and cost. Finally, the characteristics of many signal lines and easy interference reduce the reliability of the parallel bus, and data transmission errors occur frequently, which requires an additional error detection and correction mechanism to ensure data accuracy, and when the transmission continues to be wrong due to environmental changes, self-detection and adaptive adjustment cannot be performed.

[0005] The serial bus also has obvious deficiencies in the inter-board communication of the feeder automation terminal device. On the one hand, limited by the data bit mode of transmission bit by bit, its transmission speed is relatively limited. On the other hand, when the transmission continues to be wrong due to environmental changes, it also lacks self-detection and adaptive ability. SUMMARY

[0006] In order to overcome the problems in the prior art, the present application provides a feeder automation terminal board piece communication system.

[0007] The technical scheme for solving the above technical problems is as follows:

[0008] The present application provides a feeder automation terminal board piece communication system, comprising a main board piece and a slave board piece, the main board piece and the slave board piece are connected through a data line, the slave board piece is connected with a CPU;

[0009] The main board piece is used for sending data; the slave board piece is used for receiving data, detecting whether the received data is correct, and transmitting the detection result to the CPU, the CPU decides whether to start the self-detection adaptive function, and if the self-detection adaptive function needs to be started, the slave board piece adjusts the data phase according to the detection result.

[0010] Further, the main board piece adds a CRC check code after sending data.

[0011] Further, the slave board piece comprises an FPGA, the FPGA comprises a data receiving module, a signal detection module, a signal adjustment module and a register module;

[0012] The data receiving module is used for receiving the data transmitted by the main board piece; the signal detection module is used for detecting the received data, detecting whether the received data is correct, and transmitting the detection result to the CPU through the register module; the CPU decides whether to start the self-detection adaptive function according to the detection result, and if the self-detection adaptive function needs to be started, the CPU configures the corresponding signal through the register module to start the self-detection adaptive function.

[0013] The signal adjustment module is used for completing the detection and adaptive adjustment of the signal after the self-detection adaptive function is started.

[0014] Further, the signal detection module compares the CRC check code in the received data with the check code calculated through the received data, if they are inconsistent, the error counter value is increased by 1, the CPU reads the error counter value, if the error counter value exceeds a preset threshold, it is judged that the communication has a problem and the self-detection adaptive function needs to be started.

[0015] Further, the starting of the self-detection adaptive function comprises:

[0016] Comparing the received clock signal with the preset normal test data signal, if they are inconsistent, or the clock signal appears irregular change, it is judged that the clock signal has a problem;

[0017] If the clock signal does not need to be adjusted, the received control signal is compared with the preset control signal, and if they are inconsistent, it is determined that the control signal has a problem;

[0018] If the clock signal and the control signal do not need to be adjusted, the received data signal is compared with the preset data signal, and if they are inconsistent, it is determined that the data signal has a problem.

[0019] Further, if the clock signal has a problem, the adjustment method comprises:

[0020] The FPGA calls an internal phase delay module to generate a clock signal delay 1 as a clock signal for collecting a data signal, and the CPU starts a self-detection adaptive function to detect the collected data signal and determine whether the collected data signal is correct. If the collected data signal is incorrect, the above process is repeated, and if the collected data signal is correct, the clock signal delay value at this time is recorded and determined as a clock minimum delay value.

[0021] Clock signal delays 2 to n are sequentially generated, and the self-detection adaptive function is sequentially executed. If the self-detection adaptive function is executed using the clock signal delay n and the collected data signal is incorrect, it is determined that the maximum clock signal delay capable of correctly completing data signal collection is n-1, the clock signal delay value at this time is recorded, and the clock maximum delay value is determined.

[0022] According to the intermediate value algorithm, the clock delay intermediate value = (clock minimum delay value + clock maximum delay value) / 2 is calculated, and the calculated clock delay intermediate value is fixed as the adjusted optimal clock signal.

[0023] Further, if the control signal has a problem, the adjustment method comprises:

[0024] If the control signal is advanced, the FPGA calls an internal phase delay module to generate a control signal delay 1 as a control signal for collecting a data signal, and the CPU starts a self-detection adaptive function to detect the collected data signal and determine whether the collected data signal is correct. If the collected data signal is incorrect, the above process is repeated, and if the collected data signal is correct, the control signal delay value at this time is recorded and determined as a control minimum delay value.

[0025] Control signal delays 2 to n are sequentially generated, and the self-detection adaptive function is sequentially executed. When the self-detection adaptive function is executed using the control signal delay n, if the collected data signal is incorrect, it is determined that the maximum control signal delay capable of correctly completing data signal collection is n-1, the control signal delay value at this time is recorded, and the control maximum delay value is determined.

[0026] According to the intermediate value algorithm, the control intermediate value = (control minimum delay value + control maximum delay value) / 2 is calculated, and the calculated control intermediate value is fixed as the adjusted optimal control signal.

[0027] Further, the adjustment method for judging that the control signal is problematic comprises:

[0028] If the transmission of the control signal is delayed by more than a preset threshold value relative to other signals, the clock signal is delayed, clock signal delay 1 is generated as the clock signal for collecting data signals, the CPU starts the self-detection adaptive function, detects the collected data signals, judges whether the collected data signals are correct, if not, repeats the above process, if correct, records the clock signal delay value at this time, and determines the clock minimum delay value; clock signal delay 2 to clock signal delay n are generated in turn, and the self-detection adaptive function is executed in turn; if the self-detection adaptive function is executed using clock signal delay n, and if the collected data signals are incorrect, it is judged that the maximum clock signal delay capable of correctly completing data signal collection is n-1, and the clock signal delay value at this time is recorded and determined as the clock maximum delay value.

[0029] According to the intermediate value algorithm, the clock delay intermediate value=(clock minimum delay value+clock maximum delay value) / 2 is calculated, and the calculated clock delay intermediate value is fixed as the adjusted optimal clock signal.

[0030] Further, the adjustment method for judging that the data signal is problematic comprises:

[0031] If one of the data signals is problematic, the data signal is advanced relative to other data signals, then it is decided to delay the data signal for adjustment;

[0032] The FPGA calls the internal phase delay module to generate data signal delay 1, which is used as the data signal; whether the data signal is correct is judged, if not, the above process is repeated, if correct, data signal delay 1 is recorded as the minimum delay value;

[0033] The above process is repeated to gradually generate data signal delay 2, data signal delay 3, …, data signal delay n, and each time the newly generated delay signal is used as the data signal; when the self-detection adaptive function is completed using data signal delay n, the collected data signal is incorrect, it is judged that the maximum delay value capable of correctly completing data collection is data signal delay n-1, and is recorded;

[0034] According to the intermediate value algorithm, the data signal intermediate value=(data signal minimum delay value+data signal maximum delay value) / 2 is calculated; the calculated data signal intermediate value is fixed as the adjusted optimal data signal.

[0035] Compared with the prior art, the present application has the following technical effects:

[0036] The application introduces a self-detection and self-adaptation function, which can detect and adjust data phase and other parameters when environmental changes cause continuous errors in transmission, effectively improving the adaptability of the device in complex field environments and reducing communication failures caused by environmental factors. After starting the self-detection and self-adaptation function, the system can detect and adjust the clock signal, control signal and data signal respectively. This adaptive adjustment mechanism can optimize signal parameters according to actual communication conditions, reduce signal interference and attenuation, reduce data transmission errors, and significantly improve the reliability of data transmission. BRIEF DESCRIPTION OF DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, and the advantages thereof, a brief introduction will be given to the drawings needed in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative effort.

[0038] Figure 1 It is a schematic diagram of the overall structure of the present application;

[0039] Figure 2 It is a timing diagram of each signal in an ideal state;

[0040] Figure 3 It is a timing diagram when the clock signal has a problem;

[0041] Figure 4 It is a timing diagram when the control signal has a first problem;

[0042] Figure 5 It is a timing diagram when the data signal 0 has a first problem;

[0043] Figure 6 It is a working flowchart of the self-detection and self-adaptation function;

[0044] Figure 7 It is a clock signal adjustment timing diagram when the clock signal has a problem;

[0045] Figure 8 It is a block diagram of the entire system;

[0046] Figure 9 It is a clock signal adjustment timing diagram when the control signal has a first problem;

[0047] Figure 10 It is a timing diagram when the control signal has a second problem;

[0048] Figure 11 It is a control signal adjustment timing diagram when the control signal has a second problem;

[0049] Figure 12 Data signal 0 adjustment timing diagram when the first problem occurs

[0050] Figure 13 Timing diagram when the second problem occurs for data signal 0

[0051] Figure 14 Control signal adjustment timing diagram when the second problem occurs for data signal 0

[0052] Figure 15 Data signal 1 adjustment timing diagram when the second problem occurs for data signal 0

[0053] Figure 16 Data signal 2 adjustment timing diagram when the second problem occurs for data signal 0

[0054] Figure 17 Data signal 3 adjustment timing diagram when the second problem occurs for data signal 0 DETAILED DESCRIPTION

[0055] In order to further clarify the technical means and effects taken by the present application to achieve the predetermined object of the application, the specific embodiments, structures, features and effects of the technical solutions proposed by the present application are described in detail below in combination with the drawings and preferred embodiments. The specific features, structures or characteristics in one or more embodiments can be combined in any suitable form. Unless otherwise defined, all technical and scientific terms used in the present application have the same meaning as understood by those skilled in the art of the technology to which the present application belongs.

[0056] In the present embodiment, with reference to Figures 1-17 , a feeder automation terminal board communication system is provided, comprising a master board and a slave board, the master board and the slave board are connected through data lines, the slave board is connected with a CPU;

[0057] The master board is used for sending data; the slave board is used for receiving data, detecting whether the received data is correct, and transmitting the detection result to the CPU, the CPU decides whether to start the self-detection adaptive function, and if the self-detection adaptive function needs to be started, the slave board adjusts the data phase according to the detection result.

[0058] In the present embodiment, communication between the master board and the slave board adopts 6 equal-length lines, which are respectively a clock line, a control line and four data lines. The whole data channel is unidirectional transmission, i.e. can only be transmitted from the master board to the slave board. The master board controls the output of the clock signal, the control signal and the data signal, and the slave board completes the reception of the data signal according to the clock signal and the control signal transmitted by the master board.

[0059] In the embodiment, in order to prevent problems in data or command transmission caused by environmental changes or interference, CRC check is added after each set of transmission data; meanwhile, the CRC check result provides a reference for the CPU to determine whether the FPGA needs to start self-detection and self-adaptation tasks.

[0060] In the embodiment, the slave board includes an FPGA, and four modules in the FPGA complete the self-detection and self-adaptation process. The four modules are a data receiving module, a signal detection module, a signal adjustment module, and a register module. The data receiving module is used to receive data transmitted by the master board; the signal detection module is used to detect the received data, detect whether the received data is correct, and transmit the detection result to the CPU through the register module; the CPU determines whether to start the self-detection and self-adaptation function according to the detection result, and if the self-detection and self-adaptation function needs to be started, the CPU configures corresponding signals through the register module to start the self-detection and self-adaptation function; the signal adjustment module is used to complete signal detection and adaptive adjustment after the self-detection and self-adaptation function is started. The CPU configures corresponding signals through the register module, including: the CPU changes a register value in the FPGA through a write operation, and the FPGA starts the self-detection and self-adaptation function after detecting that the register value is a start self-detection and self-adaptation signal.

[0061] Specifically, the signal detection module compares the CRC check code in the received data with the check code calculated through the received data, and if they are inconsistent, it means that there is a problem in the inter-board communication; the FPGA increases the error counter value by 1, and the CPU reads the error counter value periodically, and if the error counter value changes too fast or exceeds a preset threshold, it can be determined that there is a problem in the communication, and the self-detection and self-adaptation function needs to be started. The error counter value is a signal in the FPGA, which can be accumulated, and this signal is copied to a register, and the CPU can determine the error counter value by reading the register value.

[0062] The calculation formula for generating the CRC check code used by the master board and the slave board is the same. The master board continuously generates the CRC check code with the transmitted data at the same time of transmitting the data, until the last data is transmitted, and then the finally generated CRC check code is transmitted to the slave board; the slave board receives the data and uses the received data to generate the CRC check code at the same time, until the last received data is used to generate the CRC check code. Because the calculation formula for generating the CRC check code used by the master board and the slave board is the same, the finally generated CRC check codes are consistent, and when there is a problem in the inter-board communication, the generated check codes will be different.

[0063] After starting the self-test adaptive function, the FPGA will automatically generate test data for related adjustments. These test times are changed according to the rising edge of the clock signal. The initial value is all 0. After starting the test, the data changes from all 0 to all 1 on the rising edge of the clock signal, and then changes from all 1 to all 0 on the next rising edge of the clock signal, and so on. Because the board design process will use the same length design of the data line, and before leaving the factory, it will be Figure 2 The timing shown in the figure is used to set the signal. The clock used is 100MHz, and the maximum delay for each signal adjustment is set to one clock cycle, that is, 10ns. If the signal delay exceeds 10ns, the corresponding adaptive process is stopped. Generally, the delay of the signal with problems does not exceed one clock cycle.

[0064] When the self-detection adaptive function is started, it first determines whether the clock signal needs to be adjusted. The received clock signal is compared with the preset normal test data signal. If they are inconsistent, it is determined that there is a problem with the clock signal and the clock signal needs to be adjusted. Otherwise, the clock signal does not need to be adjusted. Figure 2 As shown, the preset normal test data signal sequence is 4'h0, 4'hf, 4'h0, 4'hf, etc. Figure 3 As shown in the figure, the falling edge of the clock signal is exactly at the edge of the data change, which will cause the collected data to be unstable. If the received clock signal shows irregular changes, such as 4'h0, 4'h2, 4'hc, 4'hf, etc., it is considered that the received clock signal is unstable and it is determined that there is a problem with the clock signal.

[0065] If the clock signal does not need to be adjusted, then continue to determine whether the control signal needs to be adjusted, compare the received control signal with the preset control signal, if they are inconsistent, then determine that the control signal needs to be adjusted, and make relevant adjustments; after the control signal is adjusted, perform relevant verification; if the control signal verification is successful, then exit directly and notify the CPU that the self-test and self-adaptation are completed. If the control signal verification is unsuccessful, then continue to perform relevant detection and adjustment. Figure 4 As shown, the first signal collected is 4'h0, but the first signal actually received is 4'hf, followed by 4'h0, 4'hf, and 4'h0 in sequence. This indicates a problem with the control signal, which is caused by a significant delay in the control signal transmission relative to other signals. The verification process includes using the adjusted control signal as the control signal, continuously receiving data, and comparing the data.

[0066] If the clock signal and the control signal do not need to be adjusted, it is judged whether the data signal needs to be adjusted, the received data signal is compared with the preset data signal, if they are inconsistent, the data signal needs to be adjusted, and then corresponding adjustment is performed; the adjusted data signal is verified, if the verification is successful, the self-detection and self-adaptation are directly exited, and the CPU is informed that the self-detection and self-adaptation are completed, if the verification is unsuccessful, the related detection and adjustment are continuously performed. The whole process is circularly performed until the whole self-detection and self-adaptation are completed. As shown in Figure 5 , the received data signals are 4'h1, 4'he, 4'h1, 4'he in turn and are alternately exchanged, it can be judged that the first data signal has a problem.

[0067] In the specific embodiment, referring to Figure 2 and Figure 3 , if it is judged that the clock signal has a problem, adjustment needs to be performed: a phase delay module inside a signal adjustment module is called from the FPGA of the board, a clock signal delay 1 is generated as a clock signal for collecting data signals, the CPU starts the self-detection and self-adaptation function, detects the collected data signals, judges whether the collected data signals are correct, if they are incorrect, the above process is repeated, if they are correct, the clock signal delay value at this time is recorded, and is determined as the minimum clock delay value; the clock signal delay 2 to the clock signal delay n are generated in turn, and the self-detection and self-adaptation function is executed in turn; if the self-detection and self-adaptation function is executed using the clock signal delay n, if the collected data signals are incorrect, it is judged that the maximum clock signal delay capable of correctly completing the data signal collection is n-1, the clock signal delay value at this time is recorded, and is determined as the maximum clock delay value; according to the middle value algorithm, the clock delay middle value=(the minimum clock delay value+the maximum clock delay value) / 2 is calculated, the calculated clock delay middle value is fixed as the best clock signal after adjustment.

[0068] As shown in Figure 4 , the first signal that should be collected is 4'h0, but the first signal actually received is 4'hf, and then they are 4'h0, 4'hf, 4'h0 in turn and are alternately exchanged, it is judged that the control signal has a problem, which is caused by the fact that the transmission of the control signal is too large relative to other signals.

[0069] Because the received control signal cannot be processed in advance, only delay processing can be performed, so the problem in Figure 4 needs to be solved by delaying other signals. The delay of the clock signal is performed first, as shown in Figure 9As shown, the case of clock signal delay. Generate clock signal delay 1 as the clock signal of the collected data signal, the CPU starts the self-detection adaptive function, detects the collected data signal, judges whether the collected data signal is correct, if not, repeat the above process, if correct, record the clock signal delay value at this time, and determine the minimum clock delay value; Generate clock signal delay 2 to clock signal delay n in turn, execute the self-detection adaptive function in turn; If the self-detection adaptive function is executed using clock signal delay n, if the collected data signal is incorrect, the maximum clock signal delay that can correctly complete the data signal collection is judged to be n-1, the clock signal delay value at this time is recorded, and the maximum clock delay value is determined; According to the intermediate value algorithm, the clock delay intermediate value = (clock minimum delay value + clock maximum delay value) / 2 is calculated, and the calculated clock delay intermediate value is fixed as the adjusted optimal clock signal. Exit the self-detection and adaptive function.

[0070] For the above case of using only delayed clock signal to complete self-detection and adaptation, although the self-detection and adaptation is finally completed, since the data signal is not delayed, it cannot be guaranteed that the collected data signal is in the middle of the data.

[0071] Figure 10 As shown, the second problem of the control signal, from Figure 10 It can be seen that the first received data is 4 'h0, the second data is also 4 'h0, and then alternately 4 'hf, 4 'h0, 4 'hf. This case only needs to adjust the control signal. As Figure 11 , the FPGA calls the internal phase delay module to generate control signal delay 1 as the control signal of the collected data signal, the CPU starts the self-detection adaptive function, detects the collected data signal, judges whether the collected data signal is correct, if not, repeat the above process, if correct, record the control signal delay value at this time, and determine the minimum control delay value; Generate control signal delay 2 to control signal delay n in turn, execute the self-detection adaptive function in turn; When the self-detection adaptive function is executed using control signal delay n, if the collected data signal is incorrect, the maximum control signal delay that can correctly complete the data signal collection is judged to be n-1, the control signal delay value at this time is recorded, and the maximum control delay value is determined; According to the intermediate value algorithm, the control intermediate value = (control minimum delay value + control maximum delay value) / 2 is calculated, and the calculated control intermediate value is fixed as the adjusted optimal control signal, and the self-detection and adaptive function is exited.

[0072] Figure 5As shown, the received signals are observed in turn 4'h1, 4'he, 4'h1, 4'he alternately, it is judged that the data signal 0 has a problem, it is found that the data signal 0 is ahead of other signals, and it is decided to adjust the delay of the data signal 0. As shown in Figure 12 , the FPGA calls the internal phase delay module to generate data signal 0 delay 1, which is used as data signal 0; it is judged whether the data signal 0 is correct, if not, the above process is repeated, if correct, the data signal 0 delay 1 is recorded as the minimum delay value; the above process is repeated to gradually generate data signal 0 delay 2, data signal 0 delay 3... data signal 0 delay n, each time the newly generated delay signal is used as data signal 0; when using data signal 0 delay n to complete the self-detection and self-adaptive function, the collected data signal is incorrect, it is judged that the maximum delay value that can correctly complete data acquisition is data signal delay n-1, and it is recorded; according to the intermediate value algorithm, the data signal 0 intermediate value=(data signal minimum delay value+data signal maximum delay value) / 2 is calculated; the calculated data signal intermediate value is fixed as the adjusted optimal data signal. Thus, the adjustment of the data signal 0 delay is completed, and the self-detection and self-adaptive function is exited.

[0073] Figure 13 As shown, the first received data is 4'h0, followed by 4'he, 4'h1, 4'he alternately, which is different from Figure 5 , it is judged that the data signal 0 has a delay relative to other signals, and the data signal 0 cannot be directly advanced, but only the other signals can be delayed. As shown in Figure 14 , the control signal is first delayed to generate control signal delay 1, which is used as the control signal for data acquisition, and the CPU starts the self-detection and self-adaptive function to detect the collected data signal, judges whether the collected data signal is correct, if not, the above process is repeated, if correct, the control signal delay value at this time is recorded and determined as the control minimum delay value; control signal delay 2 to control signal delay n are generated in turn, and the self-detection and self-adaptive function is executed in turn; when the self-detection and self-adaptive function is executed using control signal delay n, if the data signal is incorrect, it is judged that the maximum control signal delay that can correctly complete the data signal acquisition is n-1, the control signal delay value at this time is recorded and determined as the control maximum delay value; according to the intermediate value algorithm, the control intermediate value=(control minimum delay value+control maximum delay value) / 2 is calculated, and the calculated control intermediate value is fixed as the adjusted optimal control signal.

[0074] The data signal 1 is delayed in the same way as the control signal delay method, as shown in FIG. 15, to generate the data signal 1 delay 1, which is used as the data signal 1 to determine whether the data signal 1 is correct. If not, the above process is repeated. If correct, the data signal 1 delay 1 is recorded as the minimum delay value, and the minimum delay value that meets the requirements is recorded. The delay of the data signal 1 is gradually increased to generate the data signal 1 delay 2, the data signal 1 delay 3, …, and the data signal 1 delay n. The test is performed in turn until the data acquisition error occurs. The maximum delay value (data signal 1 delay n-1) that can correctly complete data acquisition at this time is recorded. The optimal data signal 1 delay value is calculated and determined: according to the middle value algorithm, (data signal 1 minimum delay value + data signal 1 maximum delay value) / 2 is calculated, and the middle value is assumed to be data signal 1 delay m1. The data signal 1 delay m1 is fixed as the data signal 1.

[0075] As shown in FIG. 16, the data signal 2 is delayed in the same way as the data signal 1. Different delay values of the data signal 2 are generated, and the minimum delay value and the maximum delay value of the data signal 2 that meet the requirements are recorded. (Data signal 2 minimum delay value + data signal 2 maximum delay value) / 2 is calculated to obtain the data signal 2 delay m2, which is fixed as the data signal 2. Figure 16 Data signal 3 delay processing: as shown in FIG. 17, the data signal 3 is delayed in the same way as the data signal 1 and the data signal 2. Different delay values of the data signal 3 are generated, and the minimum delay value and the maximum delay value of the data signal 3 that meet the requirements are recorded. (Data signal 3 minimum delay value + data signal 3 maximum delay value) / 2 is calculated to obtain the data signal 3 delay m3, which is fixed as the data signal 3.

[0076] After the above delay adjustment and test of the control signal, the data signal 1, the data signal 2, and the data signal 3, the optimal control signal delay m, the data signal 1 delay m1, the data signal 2 delay m2, and the data signal 3 delay m3 are finally determined. In subsequent data reception, the optimal delay values are used, i.e., the optimal control signal delay m, the data signal 1 delay m1, the data signal 2 delay m2, and the data signal 3 delay m3 are used as the corresponding signals.

[0077]

[0078] ​After starting the self-detection and self-adaptation function, the system can detect and adjust the clock signal, the control signal and the data signal respectively. For example, for the clock signal, the self-detection and self-adaptation function is performed by generating clock signals with different delays to determine the optimal clock delay intermediate value; for the control signal and the data signal, similar methods are also used for adjustment. This adaptive adjustment mechanism can optimize the signal parameters according to the actual communication situation, reduce the influence of signal interference and attenuation, reduce the occurrence of data transmission errors, and significantly improve the reliability of data transmission.

[0079] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit it; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A feeder automation terminal board communication system, characterized in that: It includes a main board and a slave board, wherein the main board and the slave board are connected via a data line, and the slave board is connected to the CPU; Among them, the main board is used to send data; the slave board is used to receive data, detect whether the received data is correct, and pass the detection result to the CPU. The CPU decides whether to start the self-detection adaptive function. If the self-detection adaptive function needs to be started, the slave board adjusts the data phase according to the detection result.

2. A feeder automation terminal board communication system according to claim 1, characterized in that: The main board component adds a CRC check code after sending data.

3. A feeder automation terminal board communication system according to claim 2, characterized in that: The slave board includes an FPGA, and the FPGA includes a data receiving module, a signal detection module, a signal adjustment module and a register module; The data receiving module is used to receive data transmitted by the mainboard components; the signal detection module is used to detect the received data to determine whether it is correct and transmit the detection result to the CPU through the register module; the CPU decides whether to start the self-detection and adaptive function based on the detection result. If the self-detection and adaptive function needs to be started, the CPU configures the corresponding signal through the register module to start the self-detection and adaptive function; The signal adjustment module is used to complete signal detection and adaptive adjustment after the self-detection adaptive function is started.

4. A feeder automation terminal board communication system according to claim 3, characterized in that: The signal detection module compares the CRC check code in the received data with the check code calculated by the received data. If they are inconsistent, the error counter value is increased by 1. The CPU reads the error counter value. If the error counter value exceeds the preset threshold, it is determined that there is a problem with the communication and the self-detection and adaptive function needs to be started.

5. A feeder automation terminal board communication system according to claim 4, characterized in that: The startup self-detection adaptive function includes: Compare the received clock signal with the preset normal test data signal. If they are inconsistent, or the clock signal changes irregularly, it is determined that there is a problem with the clock signal. If the clock signal does not need to be adjusted, the received control signal is compared with the preset control signal. If they are inconsistent, it is determined that there is a problem with the control signal; If the clock signal and the control signal do not need to be adjusted, the received data signal is compared with the preset data signal. If they are inconsistent, it is determined that there is a problem with the data signal.

6. A feeder automation terminal board communication system according to claim 5, characterized in that: If there is a problem with the clock signal, the adjustment methods include: The FPGA calls the internal phase delay module to generate a clock signal delay of 1 as the clock signal for collecting data signals. The CPU starts the self-detection and adaptive function to detect the collected data signal and determine whether the collected data signal is correct. If not, the above process is repeated. If correct, the clock signal delay value at this time is recorded and determined as the minimum clock delay value. Generate clock signal delays 2 to n in sequence, and execute the self-detection and self-adaptation function in sequence; if the collected data signal is incorrect after executing the self-detection and self-adaptation function using clock signal delay n, determine that the maximum clock signal delay that can correctly complete data signal collection is n-1, record the clock signal delay value at this time, and determine it as the maximum clock delay value; According to the middle value algorithm, the middle value of the clock delay is calculated as (minimum clock delay value + maximum clock delay value) / 2. The calculated middle value of the clock delay is fixed and used as the adjusted optimal clock signal.

7. A feeder automation terminal board communication system according to claim 5, characterized in that: If there is a problem with the control signal, the adjustment methods include: If the control signal is advanced, the FPGA calls the internal phase delay module to generate a control signal delay of 1 as the control signal for the collected data signal. The CPU starts the self-detection and adaptive function to detect the collected data signal to determine whether the collected data signal is correct. If not, the above process is repeated. If correct, the control signal delay value at this time is recorded and determined as the minimum control delay value. Generate control signal delays 2 to n in sequence, and execute the self-detection and self-adaptation function in sequence; when executing the self-detection and self-adaptation function using control signal delay n, if a data signal error is detected, determine that the maximum control signal delay that can correctly complete data signal acquisition is n-1, record the control signal delay value at this time, and determine it as the maximum control delay value; According to the intermediate value algorithm, the control intermediate value = (control minimum delay value + control maximum delay value) / 2 is calculated, and the calculated control intermediate value is fixed as the adjusted optimal control signal.

8. The feeder automation terminal board communication system according to claim 5, characterized in that: If there is a problem with the control signal, the adjustment methods include: If the transmission delay of the control signal relative to other signals is greater than a preset threshold, the clock signal is delayed, and a clock signal delay of 1 is generated as the clock signal for collecting the data signal. The CPU starts a self-detection and adaptive function to detect the collected data signal to determine whether the collected data signal is correct. If not, the above process is repeated. If correct, the clock signal delay value at this time is recorded and determined as the minimum clock delay value; clock signal delays 2 to n are generated in sequence, and the self-detection and adaptive function is executed in sequence; if the collected data signal is incorrect after the self-detection and adaptive function is executed using clock signal delay n, it is determined that the maximum clock signal delay that can correctly complete the data signal collection is n-1, the clock signal delay value at this time is recorded, and determined as the maximum clock delay value; According to the middle value algorithm, the middle value of the clock delay is calculated as (minimum clock delay value + maximum clock delay value) / 2. The calculated middle value of the clock delay is fixed as the adjusted optimal clock signal.

9. A feeder automation terminal board communication system according to claim 5, characterized in that: If there is a problem with the data signal, the adjustment methods include: determining that a problem occurs with one of the data signals and that the data signal is ahead of the other data signals, and then deciding to adjust the delay of the data signal; The FPGA calls the internal phase delay module to generate a data signal delay of 1, which is used as the data signal. The FPGA determines whether the data signal is correct. If not, the above process is repeated. If correct, the data signal delay of 1 is recorded as the minimum delay value. Repeat the above process to gradually generate data signal delay 2, data signal delay 3, ... data signal delay n, and use the newly generated delay signal as the data signal each time; when the self-detection and adaptive function is completed using data signal delay n, the collected data signal is incorrect, and the maximum delay value that can correctly complete data collection is determined to be data signal delay n-1, and this value is recorded; According to the median algorithm, the median value of the data signal is calculated as (minimum delay value of the data signal + maximum delay value of the data signal) / 2; the calculated median value of the data signal is fixed as the adjusted optimal data signal.

Images