Technological method for manufacturing flash memory device

Abstract

The invention discloses a process method for manufacturing a flash memory device, which comprises the following steps of: forming a coupling oxide layer with the thickness of 50 angstroms to 150 angstroms on a substrate; forming a floating gate polycrystalline silicon layer on the coupling oxide layer, wherein the floating gate polycrystalline silicon layer is used for preparing a floating gate of the flash memory; forming a protective oxide layer on the floating gate polycrystalline silicon layer, wherein the protective oxide layer is used for protecting the floating gate polycrystalline silicon layer in a subsequent wet etching process; forming a nitride layer on the protective oxide layer; and removing the nitride layer through a wet etching process. In the manufacturing process of the flash memory device, after the floating gate polycrystalline silicon layer is formed, the protective oxide layer is formed on the floating gate polycrystalline silicon, so that the floating gate polycrystalline silicon layer can be protected in the subsequent wet etching process, the floating gate polycrystalline silicon layer is prevented from generating defects and being damaged, the uniformity of the floating gate polycrystalline silicon layer is improved, and the yield of the flash memory device is improved. The coupling of the word line and the control gate to the floating gate of the device is improved, and the leakage current phenomenon of the device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a process method for manufacturing flash memory devices. Background Art

[0002] In non-volatile memory (NVM), flash memory devices have been widely used due to their advantages of low cost, low power consumption and fast access speed.

[0003] Flash memory devices have three basic operations during operation: write (program), erase (erase), and read (read). Among them, the most commonly used method is to use Fowler Nordheim (FN) tunneling between the floating gate (FG) and the word line (WL) to erase electrons in the floating gate. The pointed structure of the floating gate assists FN tunneling, which has the advantages of low voltage, high electric field, fast speed, small current, and low power consumption.

[0004] For flash memory devices, the thickness of the coupling oxide layer formed on the substrate and the oxide layer formed on the floating gate are both critical parameters. A thicker coupling oxide layer helps prevent floating gate leakage and improves data retention, but it also slows device cell programming. A thinner coupling oxide layer, on the other hand, is more susceptible to floating gate leakage. During an erase operation, the word line has a high positive voltage, while the control gate has a high negative voltage, making it easier for the word line and control gate to couple with the floating gate.

[0005] In view of this, it is urgent to provide a process method that can reduce the floating gate leakage and the coupling between the word line, the control gate and the floating gate while retaining a relatively small thickness of the coupling oxide layer. Summary of the Invention

[0006] The present application provides a process method for manufacturing flash memory devices, which can solve the problem that the flash memory device manufacturing method provided in the related art easily causes device leakage and coupling after forming a relatively thin coupling oxide layer. The method comprises:

[0007] forming a coupling oxide layer on the substrate, wherein the coupling oxide layer has a thickness of 50 angstroms to 150 angstroms;

[0008] forming a floating gate polysilicon layer on the coupling oxide layer, wherein the floating gate polysilicon layer is used to prepare a floating gate of a flash memory;

[0009] forming a protective oxide layer on the floating gate polysilicon layer, wherein the protective oxide layer is used to protect the floating gate polysilicon layer in a subsequent wet etching process;

[0010] forming a nitride layer on the protective oxide layer;

[0011] The nitride layer is removed by a wet etching process.

[0012] In some embodiments, the protective oxide layer has a thickness of 20 angstroms to 50 angstroms.

[0013] In some embodiments, forming a nitride layer on the protective oxide layer includes:

[0014] The protective oxide layer is formed on the floating gate polysilicon layer through an RTO process.

[0015] In some embodiments, forming a nitride layer on the oxide layer includes:

[0016] The protective oxide layer is formed on the floating gate polysilicon layer by an ISSG process.

[0017] In some embodiments, forming a coupling oxide layer on the substrate includes:

[0018] Cleaning the substrate through a wet etching process;

[0019] forming a first oxide layer on the substrate through a furnace oxidation process;

[0020] removing the first oxide layer by a wet etching process;

[0021] Cleaning the substrate through a wet etching process;

[0022] A second oxide layer is formed on the substrate through a furnace oxidation process, and the second oxide layer constitutes the coupling oxide layer.

[0023] In some embodiments, the thickness of the first oxide layer is 150 angstroms to 450 angstroms.

[0024] The technical solution of this application has at least the following advantages:

[0025] By forming a protective oxide layer on the floating gate polysilicon layer after forming the floating gate polysilicon layer during the flash memory device manufacturing process, the floating gate polysilicon layer can be protected in the subsequent wet etching process, avoiding defects and damage to the floating gate polysilicon layer, improving the uniformity of the floating gate polysilicon layer, improving the coupling of the device's word line and control gate to the floating gate, and improving the device's leakage current. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1 This is a flowchart of an exemplary process method for manufacturing a flash memory device provided by the present application;

[0028] Figures 2 to 5 is a schematic diagram of a manufacturing process of a flash memory device provided by an exemplary embodiment of the present application;

[0029] Figure 6 is a schematic diagram of the leakage current of the sample without baking treatment;

[0030] Figure 7 is a schematic diagram of the operating current of the sample without baking treatment;

[0031] Figure 8 is a schematic diagram of the leakage current of the sample after baking;

[0032] Figure 9 Schematic diagram of the operating current of the sample after baking. DETAILED DESCRIPTION

[0033] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0034] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0035] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0036] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0037] refer to Figure 1 , which shows a flow chart of a process method for manufacturing a flash memory device provided by an exemplary embodiment of the present application, such as Figure 1 As shown, the method includes:

[0038] Step S1: forming a coupling oxide layer on a substrate, wherein the thickness of the coupling oxide layer is 50 angstroms to 150 angstroms.

[0039] Exemplarily, step S1 includes but is not limited to: cleaning the substrate by a wet etching process; forming a first oxide layer (with a thickness of 150 angstroms) on the substrate by a furnace oxidation process; to 450 angstroms); removing the first oxide layer by a wet etching process; cleaning the substrate by a wet etching process; forming a second oxide layer on the substrate by a furnace oxidation process, the second oxide layer constituting a coupling oxide layer.

[0040] Step S2: forming a floating gate polysilicon layer on the coupling oxide layer. The floating gate polysilicon layer is used to prepare a floating gate of the flash memory.

[0041] refer to Figure 2 , which shows a cross-sectional schematic diagram after forming a floating gate polysilicon layer. Figure 2 As shown, a coupling oxide layer 220 is formed on a substrate 210 , and a polysilicon layer can be deposited on the coupling oxide layer 220 through a deposition process in a furnace tube to form a floating gate polysilicon layer 230 .

[0042] Step S3 , forming a protective oxide layer on the floating gate polysilicon layer, wherein the protective oxide layer is used to protect the floating gate polysilicon layer in a subsequent wet etching process.

[0043] refer to Figure 3 , which shows a cross-sectional schematic diagram after forming a protective oxide layer. Figure 3As shown, a protective oxide layer 231 can be formed on the floating gate polysilicon 230 by a rapid thermal oxidation (RTO) process, wherein the process conditions of the RTO process can be: a temperature range of 850 degrees Celsius (°C) to 1100 degrees Celsius, a process time of 5 seconds (s) to 60 seconds, and the gas introduced is oxygen (O2), or oxygen and nitrogen (N2); or, a protective oxide layer 231 can be formed on the floating gate polysilicon 230 by an in-situ steam generation (ISSG) process, wherein the process conditions of the ISSG process can be: a temperature range of 900 degrees Celsius (°C) to 1100 degrees Celsius, a process time of 5 seconds (s) to 60 seconds, and the gas introduced is oxygen and hydrogen (H2), or nitrous oxide (N2O) and hydrogen.

[0044] Step S4: forming a nitride layer on the protective oxide layer.

[0045] refer to Figure 4 , which shows a cross-sectional schematic diagram after a nitride layer is formed on the protective oxide layer. For example, Figure 4 As shown, silicon nitride (Si3N4) can be deposited on the protective oxide layer 231 through a deposition process in a furnace to form a nitride layer 240. The nitride layer 240 is used to improve the void defects of the floating gate polysilicon layer.

[0046] Step S5: removing the nitride layer by a wet etching process.

[0047] refer to Figure 5 , which shows a cross-sectional schematic diagram after the nitride layer is removed by a wet etching process. Figure 5 As shown, since the protective oxide layer 231 protects the floating gate polysilicon layer 230 , defects and damages to the floating gate polysilicon layer 230 can be avoided during the wet etching process.

[0048] like Figure 6 and Figure 7 As shown, without baking treatment, the leakage current of the sample using the process of the embodiment of the present application is reduced by about 38.1% compared with the leakage current of the sample not using the process of the embodiment of the present application, and the operating current of the sample using the process of the embodiment of the present application is also improved compared with the operating current of the sample not using the process of the embodiment of the present application.

[0049] like Figure 8 and Figure 9As shown, after baking treatment, the leakage current of the sample using the process of the embodiment of the present application is reduced by about 22.6% compared with the leakage current of the sample not using the process of the embodiment of the present application, and the working current of the sample using the process of the embodiment of the present application is also improved compared with the working current of the sample not using the process of the embodiment of the present application.

[0050] The embodiment of the present application Figures 6 to 9 The horizontal axis is the current value and the vertical axis is Sigma.

[0051] To summarize, in the embodiments of the present application, a protective oxide layer is formed on the floating gate polysilicon after the floating gate polysilicon layer is formed during the manufacturing process of the flash memory device, so that the floating gate polysilicon layer can be protected in the subsequent wet etching process to avoid defects and damage to the floating gate polysilicon layer. While maintaining the coupling polysilicon layer at a relatively thin thickness (50 angstroms to 150 angstroms), the uniformity of the floating gate polysilicon layer is improved, the coupling of the word line and the control gate to the floating gate of the device is improved, and the leakage current phenomenon of the device is improved.

[0052] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A process method for manufacturing a flash memory device, characterized in that: include: forming a coupling oxide layer on the substrate, wherein the coupling oxide layer has a thickness of 50 angstroms to 150 angstroms; forming a floating gate polysilicon layer on the coupling oxide layer, wherein the floating gate polysilicon layer is used to prepare a floating gate of a flash memory; forming a protective oxide layer on the floating gate polysilicon layer, wherein the protective oxide layer is used to protect the floating gate polysilicon layer in a subsequent wet etching process; forming a nitride layer on the protective oxide layer; The nitride layer is removed by a wet etching process.

2. The method according to claim 1, characterized in that The thickness of the protective oxide layer is 20 angstroms to 50 angstroms.

3. The method according to claim 2, characterized in that The forming of a nitride layer on the protective oxide layer comprises: The protective oxide layer is formed on the floating gate polysilicon layer through an RTO process.

4. The method according to claim 2, characterized in that The forming of a nitride layer on the oxide layer comprises: The protective oxide layer is formed on the floating gate polysilicon layer by an ISSG process.

5. The method according to any one of claims 1 to 4, characterized in that: The step of forming a coupling oxide layer on the substrate comprises: Cleaning the substrate through a wet etching process; forming a first oxide layer on the substrate through a furnace oxidation process; removing the first oxide layer by a wet etching process; Cleaning the substrate through a wet etching process; A second oxide layer is formed on the substrate through a furnace oxidation process, and the second oxide layer constitutes the coupling oxide layer.

6. The method according to claim 5, characterized in that The thickness of the first oxide layer is 150 angstroms to 450 angstroms.

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