Equipment management system and server

Abstract

The invention discloses an equipment management system and a server, and relates to the technical field of servers, and the equipment management system is characterized in that a topology identifier storage assembly for storing slot position signal source identifiers is moved to a server mainboard end, so that the occupation of mainboard connector pins by information transmission is reduced; and meanwhile, the management control component establishes and stores a corresponding relation between the address of the arbitration component and the screen printing area of the case. The adapter card does not need to be pre-bound and configured, can automatically identify the screen printing area of the case through the relationship by inserting any communication interface of the mainboard, and generates slot screen printing information in combination with the pre-stored signal source identifier. The problems that a large number of pins are occupied due to the fact that the adapter card hardware address signal identification configuration needs to be transmitted through a connector, and the adapter card needs to be bound with the fixed configuration and lacks flexibility in the prior art are solved. The technical effects of reducing pin occupation, realizing flexible plugging of the adapter card and automatic identification of screen printing, reducing hardware development cost and meeting the requirement of the server for reserving more bus interfaces for the connector are achieved.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to a device management system and a server. Background Art

[0002] As digitalization accelerates, server expansion capabilities are crucial as the core of data processing. Riser cards (adapter cards) enable expansion card installation through the motherboard's MCIO (Multi-pair Cable I / O) interface. In related technologies, each MCIO interface requires at least seven dedicated pins to transmit CPU (Central Processing Unit) and VPP (Virtual PCIe Port) address signals and other signal source identifiers to the IO Expander (Input / Output Expander) chip on the downstream riser card. This is accessed by the BMC (Baseboard Management Controller) / BIOS (Basic Input / Output System) via I2C (Inter-Integrated Circuit Bus). This allows the riser card to identify the CPU and PCIe interface corresponding to each slot, generating the corresponding slot silkscreen for device location. However, the new generation of servers requires the MCIO interface to integrate more bus types. The existing design of exclusive 7-pin address signals leads to tight connector pin resources, which is insufficient to meet the needs of the new generation of servers that require the MCIO connector to reserve more types of bus interfaces.

[0003] Therefore, how to provide a solution to the above technical problems is a problem that those skilled in the art need to solve at present. Summary of the Invention

[0004] The present application provides a device management system and server to at least solve the problem of occupying a large number of pins due to the need to transmit the adapter card hardware address signal identification configuration through the connector, and the lack of flexibility of the adapter card due to the need to bind a fixed configuration.

[0005] The present application provides a device management system, comprising at least one arbitration component provided on a server mainboard, a mainboard communication interface connected to the arbitration component, a management control component, and a topology identification storage component, wherein the mainboard communication interface is detachably connected to an adapter card; the topology identification storage component is configured to store signal source identification information corresponding to the mainboard communication interface; the management control component is configured to store a correspondence between the address of at least one of the arbitration components and a silk-screen area of a server chassis; when the adapter card is connected to the mainboard communication interface, the chassis silk-screen area corresponding to the adapter card is determined by the correspondence, and slot silk-screen information of the slot of the adapter card is generated based on the chassis silk-screen area and the signal source identification information.

[0006] The present application also provides a server including a server mainboard, at least one adapter card, and the device management system as described above.

[0007] Through this application, since the topology identification storage component of the storage slot signal source identification is moved to the server motherboard end, the occupation of the motherboard connector pins by the information transmission is reduced, and at the same time, the management control component establishes and stores the correspondence between the arbitration component address and the chassis silk screen area. The adapter card does not need to be pre-bound and configured. It can automatically identify the chassis silk screen area where it is located through this relationship when inserted into any communication interface of the motherboard, and generate the slot silk screen information in combination with the pre-stored signal source identification. It solves the problem in the related art that a large number of pins are occupied due to the need to transmit the adapter card hardware address signal identification configuration through the connector, and the adapter card lacks flexibility due to the need to bind a fixed configuration. It achieves the technical effect of significantly reducing pin occupation, realizing flexible plug-in and automatic silk screen identification of the adapter card, reducing hardware development costs, and meeting the requirements of the new generation of servers for more bus interfaces reserved for connectors. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0009] Figure 1 A schematic diagram of the structure of the first device management system provided in an embodiment of the present application.

[0010] Figure 2 A schematic diagram of the silk screen printing on the rear window of a chassis provided in an embodiment of the present application.

[0011] Figure 3 A schematic diagram of the structure of the second device management system provided in an embodiment of the present application.

[0012] Figure 4A schematic diagram of the structure of the third device management system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0013] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0014] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0015] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0016] Please refer to Figure 1 An embodiment of the present application provides a device management system including at least one arbitration component 11 provided on a server motherboard, a motherboard communication interface 12, a management control component 13, and a topology identification storage component 14 connected to the arbitration component 11, wherein the motherboard communication interface 12 is detachably connected to an adapter card; the topology identification storage component 14 is configured to store signal source identification information corresponding to the motherboard communication interface 12; the management control component 13 is configured to store the correspondence between the address of at least one arbitration component 11 and the silk screen area of the server chassis. When the adapter card is connected to the motherboard communication interface 12, the chassis silk screen area corresponding to the adapter card is determined through the correspondence, and the slot silk screen information of the slot of the adapter card is generated based on the chassis silk screen area and the signal source identification information.

[0017] In this embodiment, the device management system includes an arbitration component 11, a mainboard communication interface 12, a management control component 13, and a topology identification storage component 14, which are arranged on the server mainboard, wherein the first end of the arbitration component 11 is connected to the management control component 13, and the second end of the arbitration component 11 is connected to the mainboard communication interface 12 and the topology identification storage component 14 respectively. As an optional embodiment, the device management system may include multiple arbitration components 11, multiple mainboard communication interfaces 12, and multiple topology identification storage components 14, wherein the arbitration components 11, the topology identification storage component 14, and the mainboard communication interface 12 may be in one-to-one correspondence.

[0018] The topology identification storage component 14 is set on the communication link of the motherboard connector (including but not limited to the motherboard communication interface 12 in this embodiment). If the motherboard connector communicates through an I2C link, a topology identification storage component 14 is independently configured on the I2C link of each motherboard connector. The topology identification storage component 14 is configured to store signal source identification information corresponding to the slot on the adapter card, wherein the signal source identification information includes the CPU_ADDR and VPP_ADDR corresponding to the motherboard communication interface 12.

[0019] As an optional embodiment, the topology identification storage component 14 fixedly stores the CPU_ADDR and VPP_ADDR of the corresponding motherboard communication interface 12 through pull-up and pull-down resistors. For example, for the first motherboard communication interface 12, the topology identification storage component 14 stores CPU0_ADDR+VPP1_ADDR, and for the second motherboard communication interface 12, the topology identification storage component 14 stores CPU1_ADDR+VPP2_ADDR.

[0020] In scenarios where an adapter card is connected to a single motherboard communication interface 12, when the management and control component 13 accesses the topology identification storage component 14 of a specific motherboard communication interface 12, the read CPU / VPP address is automatically inherited by all slots under that motherboard communication interface 12. For example, if a riser card has three slots (SLOT0-2) connected to the first motherboard communication interface 12, all slots on the riser card can share CPU0_ADDR+VPP1_ADDR. In scenarios where an adapter card is connected to multiple motherboard communication interfaces 12, the topology identification storage component 14 on the I2C link of each motherboard communication interface 12 stores the independent CPU_ADDR and VPP_ADDR for each motherboard communication interface 12. The management and control component 13 reads the CPU_ADDR and VPP_ADDR corresponding to each motherboard communication interface 12 and allocates them according to the physical connection of the slots.

[0021] As can be understood, this embodiment eliminates seven dedicated address signal pins and stores CPU_ADDR / VPP_ADDR in a motherboard-side topology identification storage component 14 (e.g., an IO Expander). Signal source identification is transmitted via the I2C bus. The released MCIO pin resources can be used to integrate new bus protocols, including but not limited to USB4 (Universal Serial Bus Generation 4) and CXL (Compute Express Link), meeting the expansion requirements of next-generation servers. The adapter card does not require pre-binding and fixed configuration. When inserted into a single motherboard communication interface 12, the slot automatically inherits the global address of that interface (e.g., the first motherboard communication interface 12 → all slots share CPU0_ADDR + VPP1_ADDR). When inserted into multiple motherboard communication interfaces 12, the management and control component 13 assigns independent addresses based on the physical connection. This enables plug-and-play silkscreen adaptation, resolving the silkscreen confusion caused by adapter card position binding in traditional solutions. It also eliminates the need for an MCU chip and decoding circuit, reducing hardware costs.

[0022] The topology identification storage component 14 may be implemented by an IO Expander chip, and the mainboard communication interface 12 may be an MCIO interface, which may be selected according to actual needs and is not specifically limited in this embodiment.

[0023] In this embodiment, the correspondence between the address of each arbitration component 11 on the server motherboard and the chassis silk screen area is pre-configured, and the correspondence is stored in the storage medium of the management control component 13. The management control component 13 accesses the address of the arbitration component 11 and can determine the chassis silk screen area corresponding to the adapter card connected to the server motherboard based on the address of the arbitration component 11. In addition to the correspondence between the address of the arbitration component 11 and the label of the chassis silk screen area, the above correspondence can also be the correspondence between the address of the arbitration component 11, the chassis silk screen area, and the front and rear windows of the chassis, such as Figure 2 As shown, Figure 2A schematic diagram of the silk screen printing on the rear window of a chassis is provided for an embodiment of the present application. For example, the first chassis silk screen area labeled LOC PIN0 corresponds to the chassis silk screen area including PC0, PC1, and PC2, and the second chassis silk screen area labeled LOC PIN1 corresponds to the chassis silk screen area including PC3, PC4, and PC5. Taking an arbitration component 11 as an example, the management control component 13 accesses the address of the arbitration component 11, and according to the preset correspondence, determines that the chassis silk screen area corresponding to the address is labeled LOC PIN0, then the chassis silk screen area corresponding to the adapter card includes PC0, PC1, and PC2. In this embodiment, the adapter card does not need to know which physical interface it is inserted into. The management control component 13 automatically derives its LOC_PIN (such as 0x70→LOC0) through the address of the arbitration chip, and then maps the LOC_PIN to a fixed chassis silk screen area to improve versatility.

[0024] In this embodiment, the adapter card includes at least one slot. The management control component 13 can generate the slot silk screen information CPU ID_PE PORT_front and rear windows_chassis slot silk screen for each slot on the adapter card based on the CPU_ADDR / VPP_ADDR obtained from the topology identification storage component 14 and the determined chassis silk screen area, wherein the CPU_ID is determined based on the CPU_ADDR, the PEPORT is determined based on the VPP_ADDR, and the front and rear windows and the chassis slot silk screen are determined based on a preset relationship and the chassis silk screen area. For example, the slot silk screen information of a certain slot can be CPU0_PORT1_rear window_PC2, so as to facilitate subsequent device positioning.

[0025] As an optional embodiment, the management control component 13 can be constructed by the BMC and CPU on the server motherboard.

[0026] It can be seen that in this embodiment, since the topology identification storage component 14 that stores the slot signal source identification is moved to the server mainboard end, the occupation of the mainboard connector pins by the information transmission is reduced, and at the same time, the management control component 13 establishes and stores the correspondence between the address of the arbitration component 11 and the chassis silk screen area. The adapter card does not need to be pre-bound and configured. It can automatically identify the chassis silk screen area where it is located through this relationship when inserted into any communication interface of the mainboard, and generate the slot silk screen information in combination with the pre-stored signal source identification. It solves the problem in the related art that a large number of pins are occupied due to the need to transmit the adapter card hardware address signal identification configuration through the connector, and the adapter card lacks flexibility due to the need to bind a fixed configuration. It achieves the technical effect of significantly reducing pin occupation, realizing flexible plug-in and automatic silk screen identification of the adapter card, reducing hardware development costs, and meeting the requirements of the new generation of servers for more bus interfaces reserved for connectors.

[0027] Based on the above examples, please refer to Figure 3The device management system also includes: an information recording component 21 provided on the adapter card, configured to store the physical position offset information of the slot of the adapter card; the management control component 13 is specifically configured to store the correspondence between the address of at least one arbitration component 11 and the silk screen area of the server chassis, when the adapter card is connected to the mainboard communication interface 12, the chassis silk screen area corresponding to the adapter card is determined through the correspondence, the chassis silk screen information corresponding to the slot in the chassis silk screen area is determined based on the physical position offset information, and the slot silk screen information of the slot is generated based on the chassis silk screen information corresponding to the slot and the signal source identification information.

[0028] In this embodiment, the adapter card is further provided with at least one information recording component 21, and the information recording component 21 stores the physical position offset information (SLOT LOC offset information) of the slot of the adapter card. The physical position offset information of the slot is used to determine the position relationship of each slot on the adapter card. For example, assuming that the adapter card includes three slots, namely the first slot, the second slot and the third slot, it can be determined according to the physical position offset information that the first slot, the second slot and the third slot are arranged in order from bottom to top on the adapter card. The management control component 13 can determine the binding relationship between each slot and each chassis silk screen in the chassis silk screen area according to the position relationship of the first slot, the second slot and the third slot on the adapter card. Assuming that the chassis silk screen area corresponding to the adapter card is LOC PIN0, then the first slot on the adapter card is bound to PC0, the second slot is bound to PC1, and the third slot is bound to PC2. Assuming the chassis silkscreen area corresponding to the adapter card is LOCPIN1, then the first slot on the adapter card is bound to PC3, the second slot is bound to PC4, and the third slot is bound to PC5. In this embodiment, the information recording component 21 can be implemented using a FRU (Field Replaceable Unit) chip.

[0029] As you can understand, automatically binding chassis silkscreen areas (PC0 → PC1 → PC2) based on physical position offset information (for example, from bottom to top, slot 1 → slot 2 → slot 3) improves positioning accuracy. Compared to related solutions that require position DIP switches and programmable chips in adapter cards, only the FRU chip needs to store static offset values, which is cost-effective. The binding relationship between each slot and the chassis silkscreen can be stored, improving the efficiency and accuracy of subsequent slot silkscreen information generation.

[0030] In an exemplary embodiment, there are multiple information recording components 21 and multiple mainboard communication interfaces 12, and multiple mainboard communication interfaces 12 correspond to multiple information recording components 21; the information recording component 21 is also configured to store the unique identification information of the adapter card; the management control component 13 is also configured to determine that the multiple mainboard communication interfaces 12 are connected to the same adapter card when the unique identification information stored in the information recording components 21 connected to the multiple mainboard communication interfaces 12 is the same.

[0031] In this embodiment, the information recording component 21 is also configured with independent identification information of the adapter card in which it is located, such as the PN (Part Number) code of the adapter card. The management and control component 13 accesses the adapter card and reads the PN number in the FRU chip. When the management and control component 13 detects that the FRU chips under different I2C links all record the PN code of the same adapter card, it is determined that the motherboard connectors corresponding to these I2C links are all connected to the same adapter card. The slot of the adapter card is then bound to the chassis silk screen through the SLOT LOC offset information in the FRU. If the PN code of any link is different, it is determined to be multiple independent adapter cards. Compared with the related art that requires additional pins to identify the subordinate relationship of multiple interfaces, this embodiment realizes logical association by reading the PN code, further saving the pin resources of the motherboard connector.

[0032] In an exemplary embodiment, referring to Figure 4 The device management system also includes: a presence information storage component 22 provided on the adapter card, configured to store the device presence signal of the slot of the adapter card; the management control component 13 is further configured to access the presence information storage component 22 and determine the number of devices in place according to the device presence signal.

[0033] In this embodiment, the adapter card is also provided with a presence information storage component 22, which can also be constructed through an IO Expander, in which the device presence signal of the slot is written. The management control component 13 reads the device presence signal in the IO Expander to confirm how many PCIe devices are in place under the current configuration, so that the management control component 13 can perform subsequent management, including but not limited to dynamically activating valid slots and allocating resources.

[0034] In an exemplary embodiment, referring to Figure 4, there are multiple information recording components 21, there are multiple mainboard communication interfaces 12, and multiple mainboard communication interfaces 12 correspond to multiple information recording components 21; the equipment management system also includes: a switching component 23, the first end of the switching component 23 is connected to the first mainboard communication interface, and the second end of the switching component 23 is respectively connected to the in-place information storage component 22 and the first information recording component; at least one second information recording component is correspondingly connected to at least one second mainboard communication interface; wherein, the second information recording component is an information recording component 21 among the multiple information recording components 21 except the first information recording component, and the second mainboard communication interface is a mainboard communication interface 12 among the multiple mainboard communication interfaces 12 except the first mainboard communication interface.

[0035] In this embodiment, the adapter card is further provided with a switching component 23. The first end of switching component 23 is connected to the first motherboard communication interface on the server motherboard via a cable. Switching component 23 includes multiple second ends, namely S0, S1, S2, and S3. S0 is respectively connected to the pull-up resistor, the first information recording component, the sensor, and the in-place information storage component 22; S1 is respectively connected to the pull-up resistor and the first slot; S2 is respectively connected to the pull-up resistor and the second slot; and S3 is respectively connected to the pull-up resistor and the third slot. The multiple second information recording components on the adapter card are connected in a one-to-one correspondence with the multiple second motherboard communication interfaces on the adapter card, thereby improving the efficiency of the management control component 13 in determining whether each MCIO interface is connected to the same adapter card.

[0036] The pull-up resistor ensures signal stability and level accuracy. At the same time, it allows for reasonable allocation of slot resources based on actual device requirements, allowing each slot to independently connect to devices without interfering with each other. S0 of the switching component 23 is connected to both the first information recording component and the in-place information storage component 22, enabling in-place information to be recorded and stored promptly. When a device is inserted into a slot, the in-place information storage component 22 quickly responds and stores the device's in-place status. The first information recording component also records this process, providing data support for subsequent device management and troubleshooting.

[0037] In an exemplary embodiment, the device management system further includes: a switching component configured to set a current control path of the management control component 13 according to the type of downstream device connected to the mainboard communication interface 12, wherein the control path includes a first control path corresponding to host control and a second control path corresponding to virtual control. Figure 4The switching component includes: a controller 15, configured to generate a control signal according to the type of the downstream device connected to the mainboard communication interface 12; a multiplexer 16, a first end of which is connected to the host control pin of the management control component 13, a second end of which is connected to the virtual control pin of the management control component 13, and a third end of which is connected to the arbitration component 11. The multiplexer 16 is configured to connect the first end with the third end or connect the second end with the third end in response to the control signal.

[0038] In this embodiment, the management control component 13 includes a processor (CPU) and a baseboard management computer (BMC). The CPU is provided with a host control pin HOST SMBUS I2C, which is connected to the first switching chip via a bus repeater (I2C Repeater). The CPU is provided with a virtual control pin VPP I2C, which is connected to the second switching chip via a bus repeater. The S0 pin of the first switching chip is connected to the first end of the multiplexer 16, the S0 pin of the second switching chip is connected to the second end of the multiplexer 16, the third end of the multiplexer 16 is connected to the second pin M1 of the arbitration component 11, the host control pin HOST SMBUS I2C of the BMC is connected to the first pin M0 of the arbitration component 11, and the third pin S of the arbitration component 11 serves as the second end of the arbitration component 11 to connect to the mainboard communication interface 12 and the topology identifier storage component 14. The CPU VPP I2C, CPU HOST SMBUS I2C, and BMC are connected. After I2C is integrated through a logic chip, one I2C link on each MCIO connector can transmit these three types of I2C signals, so that each MCIO connector only needs one set of pins (2 pins) to carry all control signals, reducing pin occupancy and directly freeing up space to integrate the new USB4 / CXL bus.

[0039] Specifically, the VPP I2C and CPU I2C first extend an I2C link connected to each MCIO using an I2C switch chip. The two I2C channels are then switched using an I2C multiplexer (multiplexer 16). The I2C multiplexer can expand a single I2C bus into multiple independent bus segments, enabling host-side switching for different downstream boards on the MCIO connector. The I2C multiplexer, controlled by a CPLD, performs channel selection and determines the downstream board type based on the riser card's presence signal. If the downstream board is a riser card, the host side switches to the CPU host SMBUS I2C. If the downstream board is a backplane card, the host side switches to the VPP I2C. The two scenarios prevent interference. Both the first and second switch chips are I2C switch chips.

[0040] In an exemplary embodiment, the management control component 13 includes: a processor and a management device; an arbitration component 11 is configured to arbitrate a first signal output by the processor and a second signal output by the management device, and transmit the arbitration successful signal to the mainboard communication interface 12 connected to itself.

[0041] In this embodiment, considering that the management control component 13 includes a processor CPU and a management device BMC, the I2C signal through the I2C MUX chip (multiplexer 16) is logically judged with the BMC I2C signal via the I2C arbitration chip (arbitration component 11). The function of the I2C arbitration chip is to resolve the conflict problem of the I2C bus in the communication scenario between the two master devices, the CPU and the BMC, to ensure normal communication.

[0042] In an exemplary embodiment, the device management system further includes: a display component configured to display slot silkscreen information corresponding to the device installed in the slot.

[0043] In this embodiment, the BMC in the management control component 13 binds all the above information to the corresponding slots, and displays the CPU ID_PE PORT_front and rear windows_chassis slot silkscreen of each PCIe device on the BMC WEB management interface.

[0044] In summary, the first aspect of this application can automatically identify the silkscreen configuration and optimize the commonly used hardware circuits of the server. The riser card does not need to be bound to a fixed configuration, and can automatically identify the silkscreen scheme under the current configuration when plugged into different interfaces of the motherboard. The second aspect of this application can reduce development costs. Compared with the hardware link using the MCU chip, the IO Expander chip of the riser card of this application is moved to the motherboard end, and only the FRU chip is added to the riser card, which is lower in cost. The third aspect of this application can reduce maintenance costs. Since the entire system does not increase the number of main control chips, there is no need to maintain the main control chip FW (Firmware), the hardware circuit is more reliable, and the number of connectors on the board is reduced. The use of standard cables can meet all wiring requirements, which is easier for hardware engineers to maintain.

[0045] An embodiment of the present application further provides a server, comprising a server mainboard, at least one adapter card, and a device management system as described in any one of the above embodiments.

[0046] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0047] The above is a detailed introduction to a device management system and server provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core ideas of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A device management system, characterized in that: It includes at least one arbitration component provided on a server mainboard, a mainboard communication interface connected to the arbitration component, a management control component, and a topology identification storage component, wherein the mainboard communication interface is detachably connected to an adapter card; The topology identification storage component is configured to store signal source identification information corresponding to the mainboard communication interface; The management control component is configured to store the correspondence between the address of at least one of the arbitration components and the silk screen area of the server chassis. When the adapter card is connected to the mainboard communication interface, the chassis silk screen area corresponding to the adapter card is determined through the correspondence, and the slot silk screen information of the slot of the adapter card is generated based on the chassis silk screen area and the signal source identification information.

2. The equipment management system according to claim 1, characterized in that: The equipment management system further includes: an information recording component provided on the adapter card, configured to store physical position offset information of the slot of the adapter card; The management and control component is specifically configured to store a correspondence between the address of at least one of the arbitration components and the silk-screen area of the server chassis. When the adapter card is connected to the communication interface of the mainboard, the chassis silk-screen area corresponding to the adapter card is determined through the correspondence, and the chassis silk-screen information corresponding to the slot in the chassis silk-screen area is determined based on the physical position offset information. The slot silk-screen information of the slot is generated based on the chassis silk-screen information corresponding to the slot and the signal source identification information.

3. The equipment management system according to claim 2, characterized in that: There are multiple information recording components, and there are multiple mainboard communication interfaces, and multiple mainboard communication interfaces correspond to multiple information recording components; The information recording component is further configured to store the unique identification information of the adapter card; The management control component is further configured to determine that the multiple mainboard communication interfaces are connected to the same adapter card when the unique identification information stored in the information recording component connected to the multiple mainboard communication interfaces is the same.

4. The equipment management system according to claim 2, characterized in that: The equipment management system further includes: a presence information storage component provided on the adapter card, configured to store a device presence signal of the slot of the adapter card; The management control component is further configured to access the presence information storage component and determine the number of present devices according to the device presence signal.

5. The equipment management system according to claim 4, characterized in that: There are multiple information recording components, and there are multiple mainboard communication interfaces, and multiple mainboard communication interfaces correspond to multiple information recording components; The equipment management system further includes: a switching component, wherein a first end of the switching component is connected to the first mainboard communication interface, and a second end of the switching component is connected to the in-place information storage component and the first information recording component respectively; At least one second information recording component is correspondingly connected to at least one second mainboard communication interface; Among them, the second information recording component is an information recording component among the multiple information recording components except the first information recording component, and the second mainboard communication interface is a mainboard communication interface among the multiple mainboard communication interfaces except the first mainboard communication interface.

6. The equipment management system according to claim 1, characterized in that: The equipment management system further includes: The switching component is configured to set the current control path of the management control component according to the type of the downstream device connected to the mainboard communication interface, and the control path includes a first control path corresponding to the host control and a second control path corresponding to the virtual control.

7. The equipment management system according to claim 6, characterized in that: The switching component includes: a controller configured to generate a control signal according to a type of a downstream device connected to the communication interface of the mainboard; A multiplexer, wherein a first end is connected to the host control pin of the management and control component, a second end is connected to the virtual control pin of the management and control component, and a third end is connected to the arbitration component, and the multiplexer is configured to connect the first end to the third end or connect the second end to the third end in response to the control signal.

8. The equipment management system according to claim 1, characterized in that: The management and control component includes: a processor and a management device; The arbitration component is configured to arbitrate the first signal output by the processor and the second signal output by the management device, and transmit the arbitration successful signal to the mainboard communication interface connected to itself.

9. The equipment management system according to any one of claims 1 to 8, characterized in that: The equipment management system further includes: The display component is configured to display the slot silkscreen information corresponding to the device installed in the slot.

10. A server, characterized in that: The device comprises a server mainboard, at least one adapter card, and the device management system according to any one of claims 1 to 9.

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