Boron diffusion method of TBC battery, preparation method of TBC battery and TBC battery

Abstract

The invention provides a boron diffusion method of a TBC battery, a preparation method of the TBC battery and the TBC battery, and relates to the technical field of photovoltaic batteries. The boron diffusion method of the TBC battery comprises the following steps: sequentially carrying out gradient heating pre-oxidation and intermittent oxygen introduction boron diffusion on the back surface of a silicon substrate to obtain a silicon substrate with a BSG layer; wherein the gradient heating pre-oxidation comprises at least five stages of heat preservation pre-oxidation, and the temperature rise amplitude of every two adjacent stages is 5-15 DEG C. According to the boron diffusion method, a compact layered pre-oxidation layer is formed by setting gradient temperature rise before boron diffusion deposition, and intermittent oxygen diffusion is set during boron diffusion deposition, so that rapid diffusion of boron atoms is blocked, interface boron accumulation is inhibited, the BRL concentration is reduced, Auger recombination is reduced, the open voltage is improved, and the cell conversion efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of photovoltaic cells, and in particular to a boron diffusion method for a TBC cell, a preparation method for the TBC cell, and the TBC cell. Background Art

[0002] The N-type Tunneling Oxide Passivated Contact (TBC) cell combines the structural advantages of the Thin Oxide Passivated Contact (TOPCon) cell and the Interdigitated Back Contact (IBC) cell, achieving the advantages of an unobstructed front surface, high open-circuit voltage, and large short-circuit current. The typical fabrication process for a conventional TBC cell includes double-sided polishing of the silicon wafer, deposition of the tunneling oxide layer and intrinsic polysilicon layer, boron diffusion to form a boron diffusion layer and a BSG layer, a single laser treatment, wet processing, deposition of the tunneling oxide layer and intrinsic polysilicon layer, phosphorus diffusion to form a phosphorus diffusion layer and a PSG layer, a second laser treatment, de-wrap plating, wet processing, coating, screen printing, and sintering.

[0003] As a high-efficiency back-contact structured cell, the boron diffusion process of the TBC cell is crucial to its performance. Boron diffusion is used to form a P-type doped region in the N-type silicon substrate, thereby constructing a PN junction. The quality of this junction directly affects the cell's open-circuit voltage (Voc) and fill factor (FF), which in turn determines the photoelectric conversion efficiency. However, the main problems faced by boron diffusion include the conflict between the boron-rich layer (BRL) and borosilicate glass (BSG). The BSG grown by boron diffusion needs to withstand wet acid and alkali corrosion to protect the integrity of the P-region P-poly film layer, so the BSG needs to maintain a certain thickness. However, while maintaining the BSG thickness, the BRL (boron-rich layer) on the silicon surface is difficult to control, resulting in high doping concentration, aggravated Auger recombination, reduced opening voltage, and reduced cell conversion efficiency.

[0004] In view of this, the present invention is proposed. Summary of the Invention

[0005] One objective of the present invention is to provide a boron diffusion method for TBC batteries. The boron diffusion method employs a gradient temperature ramp before boron deposition to form a dense, layered pre-oxidation layer. During deposition, intermittent oxygen diffusion is performed to prevent the rapid diffusion of boron atoms, inhibit interfacial boron accumulation, reduce BRL (boron-rich layer) concentration, mitigate Auger recombination, increase the opening voltage, and improve battery conversion efficiency.

[0006] A second object of the present invention is to provide a method for preparing a TBC battery.

[0007] A third object of the present invention is to provide a TBC battery, wherein the TBC battery is prepared by the boron diffusion method of the above-mentioned TBC battery or by the preparation method of the above-mentioned TBC battery.

[0008] In order to achieve the above-mentioned purpose of the present invention, the following technical solutions are adopted:

[0009] In a first aspect, the present invention provides a boron diffusion method for a TBC battery, the boron diffusion method for a TBC battery comprising:

[0010] The back side of the silicon substrate is subjected to sequential pre-oxidation with a gradient temperature increase and boron diffusion with intermittent oxygen flow to obtain a silicon substrate with a BSG layer;

[0011] The gradient temperature-increasing pre-oxidation includes at least five stages of heat-insulating pre-oxidation, and the temperature increase range between two adjacent stages is 5 to 15°C.

[0012] Furthermore, the silicon substrate includes an N-type crystalline silicon substrate, and the back surface of the N-type crystalline silicon substrate includes a tunneling oxide layer and an intrinsic amorphous silicon layer stacked in sequence.

[0013] Furthermore, the thickness of the tunnel oxide layer is 1.0 to 2.5 nm;

[0014] Furthermore, the thickness of the intrinsic amorphous silicon layer is 200-400 nm.

[0015] Furthermore, the pre-oxidation temperature range is 820-880°C.

[0016] Furthermore, the gradient temperature pre-oxidation includes five stages of heat preservation pre-oxidation:

[0017] The first stage: pre-oxidation at 825-835℃ for 1-5 minutes;

[0018] The second stage: pre-oxidation at 835-845℃ for 1-5 minutes;

[0019] The third stage: pre-oxidation at 845-855℃ for 1-5 minutes;

[0020] The fourth stage: pre-oxidation at 855-865℃ for 1-5 minutes;

[0021] The fifth stage: pre-oxidation at 865-875°C for 1-5 minutes.

[0022] Furthermore, the oxygen flow rate in each stage of the gradient temperature pre-oxidation is independently 100 to 400 sccm.

[0023] Furthermore, the thickness of the pre-oxidation layer formed by the gradient temperature increase pre-oxidation is 10 to 50 nm.

[0024] Furthermore, in the intermittent oxygen diffusion, the period ratio of oxygen on and oxygen off is 1:(3-5).

[0025] Furthermore, BCl3, O2 and N2 are introduced during the oxygen-passing process of the boron diffusion.

[0026] Furthermore, during the oxygen-passing process of the boron diffusion, the flow rate of the BCl 3 is 100 to 400 sccm.

[0027] Furthermore, during the oxygen-passing process of the boron diffusion, the flow rate of O2 is 700-1000 sccm.

[0028] Furthermore, during the oxygen-passing process of the boron diffusion, the N2 flow rate is 2000-3000 sccm.

[0029] Furthermore, BCl3 and N2 are introduced during the oxygen-cutoff process of the boron diffusion.

[0030] Furthermore, during the oxygen-cutoff process of the boron diffusion, the flow rate of BCl 3 is 100 to 400 sccm.

[0031] Furthermore, during the oxygen-cutoff process of the boron diffusion, the N2 flow rate is 2000-3000 sccm.

[0032] Furthermore, the total time of the boron diffusion is 2 to 4 hours.

[0033] Furthermore, the boron diffusion temperature is 800-1000°C.

[0034] Furthermore, the thickness of the BSG layer is 30-80 nm.

[0035] Furthermore, the sheet resistance of the silicon substrate with the BSG layer is 100-200Ω.

[0036] In a second aspect, the present invention provides a method for preparing a TBC battery, the method comprising the following steps:

[0037] (1) depositing a tunnel oxide layer and an intrinsic amorphous silicon layer on the back side of the silicon substrate;

[0038] (2) performing boron diffusion on the back side of the silicon substrate deposited in step (1); wherein the boron diffusion is performed using the boron diffusion method for the TBC battery described in the first aspect;

[0039] (3) The boron-diffused silicon substrate of step (2) is subjected to the first patterning, BSG removal, alkaline polishing, secondary deposition of a tunneling oxide layer and an intrinsic amorphous silicon layer, phosphorus diffusion, the second patterning, PSG removal, texturing, passivation treatment and electrode printing in sequence to obtain the preparation method of the TBC battery.

[0040] Furthermore, in step (1), depositing the tunnel oxide layer and the intrinsic amorphous silicon layer at one time comprises: depositing the tunnel oxide layer and the intrinsic amorphous silicon layer in sequence on the back side of the silicon substrate by LPCVD method:

[0041] Furthermore, in step (1), the silicon substrate comprises an N-type crystalline silicon substrate;

[0042] Furthermore, in step (1), the thickness of the tunnel oxide layer is 1.0 to 2.5 nm;

[0043] Furthermore, in step (1), the temperature for depositing the tunnel oxide layer is 500-650° C., and the time for depositing the tunnel oxide layer is 20-80 minutes;

[0044] Furthermore, in step (1), the thickness of the intrinsic amorphous silicon layer is 200 to 400 nm;

[0045] Furthermore, in step (1), the temperature for depositing the intrinsic amorphous silicon layer is 500-650° C., and the time for depositing the intrinsic amorphous silicon layer is 50-100 minutes.

[0046] Furthermore, in step (3), the first patterning includes: using a picosecond laser to remove a portion of the BSG layer on the back side of the silicon substrate into which boron was diffused in step (2) to form a patterned groove;

[0047] Furthermore, the power of the picosecond laser is 10 to 30 W; the pulse frequency of the picosecond laser is 300 to 1000 kHz; and the laser scanning speed of the picosecond laser is 20,000 to 50,000 mm / s.

[0048] Furthermore, the depth of the patterned groove is 30-80 nm.

[0049] Furthermore, the width of the patterned groove is 400-600 μm.

[0050] Furthermore, in step (3), the BSG wrap-around removal includes: using a chain wet method to remove the BSG layer on the front side of the silicon substrate after the first patterning.

[0051] Furthermore, in step (3), the alkali polishing includes: using a groove polishing method to remove the tunneling oxide layer and the P-type polysilicon layer on the front side of the silicon substrate after BSG coating, as well as the tunneling oxide layer and the P-type polysilicon layer at the position of the patterned groove on the back side, and increasing the depth of the patterned groove by 2 to 3 μm.

[0052] Furthermore, in step (3), the secondary deposition of the tunnel oxide layer and the intrinsic amorphous silicon layer includes: depositing the tunnel oxide layer and the intrinsic amorphous silicon layer in sequence on the back side of the alkali polished silicon substrate by LPCVD method.

[0053] Furthermore, in step (3), the thickness of the tunnel oxide layer is 1.0 to 2.5 nm.

[0054] Furthermore, in step (3), the temperature for depositing the tunnel oxide layer is 500-650°C.

[0055] Furthermore, in step (3), the time for depositing the tunnel oxide layer is 20 to 80 minutes.

[0056] Furthermore, in step (3), the thickness of the intrinsic amorphous silicon layer is 100 to 300 nm.

[0057] Furthermore, in step (3), the temperature for depositing the intrinsic amorphous silicon layer is 500-650°C.

[0058] Furthermore, in step (3), the time for depositing the intrinsic amorphous silicon layer is 50 to 100 minutes.

[0059] Furthermore, in step (3), the phosphorus diffusion includes: introducing a mixed gas of POCl3, O2 and N2 into the silicon substrate after secondary deposition to diffuse phosphorus, thereby obtaining a silicon substrate having a PSG layer.

[0060] Furthermore, in step (3), during the phosphorus diffusion process, the flow rate of POCl3 is 1000 to 2000 sccm.

[0061] Furthermore, in step (3), during the phosphorus diffusion process, the O2 flow rate is 500 to 1000 sccm.

[0062] Furthermore, in step (3), during the phosphorus diffusion process, the N2 flow rate is 500 to 1500 sccm.

[0063] Furthermore, the phosphorus diffusion temperature is 800-1000°C.

[0064] Furthermore, the phosphorus diffusion time is 1 to 3 hours.

[0065] Furthermore, the thickness of the PSG layer is 30-80 nm.

[0066] Furthermore, the sheet resistance of the silicon substrate with the PSG layer is 20-80Ω.

[0067] Furthermore, in step (3), the second patterning includes: retaining the PSG layer in the N region on the back side of the silicon substrate after phosphorus diffusion, and removing the PSG layer in the remaining area on the back side using a picosecond laser.

[0068] Furthermore, the power of the picosecond laser is 20 to 60 W; the pulse frequency of the picosecond laser is 300 to 1000 kHz; and the laser scanning speed of the picosecond laser is 20,000 to 50,000 mm / s.

[0069] Furthermore, the width of the retained PSG layer is 200-500 μm, and the thickness of the retained PSG layer is 30-80 nm.

[0070] Furthermore, in step (3), the PSG wrap-around removal includes: removing the PSG wrap-around layer on the front side of the silicon substrate after the second patterning.

[0071] Furthermore, in step (3), the texturing includes: retaining the N-type polysilicon layer and tunneling oxide layer in the N region on the back side of the silicon substrate after PSG coating, and the P-type polysilicon layer and tunneling oxide layer in the P region on the back side, and texturing is performed in the remaining front and back areas.

[0072] Furthermore, in step (3), the passivation treatment includes: depositing an aluminum oxide layer, a silicon nitride layer and a silicon oxide layer on the front side of the textured silicon substrate; and depositing an aluminum oxide layer and a silicon nitride layer on the back side of the textured silicon substrate.

[0073] Furthermore, the thickness of the aluminum oxide layer is 3 to 7 nm.

[0074] Furthermore, the thickness of the silicon nitride layer is 70-100 nm.

[0075] Furthermore, the thickness of the silicon oxide layer is 5 to 20 nm.

[0076] Furthermore, in step (3), the printing electrode includes: printing an N-region electrode on the N-region on the back side of the passivated silicon substrate, and printing a P-region electrode on the P-region on the back side of the passivated silicon substrate.

[0077] In a third aspect, the present invention provides a TBC battery, which is prepared by the boron diffusion method for the TBC battery described in the first aspect, or prepared by the preparation method for the TBC battery described in the second aspect.

[0078] Compared with the prior art, the present invention has the following beneficial effects:

[0079] The boron diffusion method of the TBC battery described in the present invention first forms a dense layered pre-oxidation layer by setting a gradient temperature increase before boron diffusion deposition, and sets intermittent oxygen diffusion during the boron diffusion deposition to block the rapid diffusion of boron atoms, inhibit interface boron accumulation, reduce the BRL (boron rich layer) concentration, alleviate Auger recombination, increase the opening voltage, and improve the battery conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0081] Figure 1 This is a schematic structural diagram of the silicon substrate obtained after depositing the tunneling oxide layer and the intrinsic amorphous silicon layer at one time in the preparation method of the TBC battery described in the present invention.

[0082] Figure 2 This is a schematic structural diagram of the silicon substrate obtained after boron diffusion in the preparation method of the TBC battery described in the present invention.

[0083] Figure 3 This is a schematic structural diagram of the silicon substrate obtained after the first patterning in the preparation method of the TBC battery described in the present invention.

[0084] Figure 4 This is a schematic structural diagram of the silicon substrate obtained by removing BSG winding plating and alkaline polishing in the preparation method of the TBC battery described in the present invention.

[0085] Figure 5 This is a schematic structural diagram of the silicon substrate obtained after secondary deposition of a tunneling oxide layer and an intrinsic amorphous silicon layer in the preparation method of the TBC battery described in the present invention.

[0086] Figure 6 This is a schematic structural diagram of the silicon substrate obtained after phosphorus diffusion in the preparation method of the TBC battery described in the present invention.

[0087] Figure 7 This is a schematic structural diagram of the silicon substrate obtained after the second patterning in the preparation method of the TBC battery described in the present invention.

[0088] Figure 8 This is a schematic structural diagram of the silicon substrate obtained after removing the PSG winding plating and texturing in the preparation method of the TBC battery described in the present invention.

[0089] Figure 9This is a schematic structural diagram of the TBC battery finally prepared by the TBC battery preparation method of the present invention.

[0090] Among them, 10 is an N-type crystalline silicon substrate, 20 is a first tunneling oxide layer, 21 is a second tunneling oxide layer, 30 is an intrinsic amorphous silicon layer, 31 is a P-type polysilicon layer, 32 is an N-type polysilicon layer, 40 is a BSG layer, 50 is a PSG layer, 60 is an aluminum oxide layer, 61 is a silicon nitride layer, 62 is a silicon oxide layer, 71 is an N-region electrode, and 72 is a P-region electrode. DETAILED DESCRIPTION

[0091] Unless otherwise defined herein, scientific and technical terms used in conjunction with the present invention shall have the meanings commonly understood by those of ordinary skill in the art. The meaning and scope of the terms should be clear; however, in the event of any potential ambiguity, the definitions provided herein take precedence over any dictionary or external definitions. In this application, the use of "or" means "and / or" unless otherwise stated. In addition, the use of the term "including" and other forms is non-limiting.

[0092] It should be noted that the following description sets forth specific details to facilitate a full understanding of the present invention. However, the present invention can be implemented in a variety of other ways than those described herein, and those skilled in the art may make similar generalizations without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0093] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0094] In a first aspect, the present invention provides a boron diffusion method for a TBC battery, the boron diffusion method for a TBC battery comprising:

[0095] The back side of the silicon substrate is subjected to sequential pre-oxidation with a gradient temperature increase and boron diffusion with intermittent oxygen flow to obtain a silicon substrate with a BSG layer;

[0096] The gradient temperature-increasing pre-oxidation includes at least five stages of heat-insulating pre-oxidation, and the temperature increase range between two adjacent stages is 5 to 15°C.

[0097] In the present invention, a dense layered pre-oxidation layer is first formed by setting at least 5 stages of heat preservation pre-oxidation, and then intermittent oxygen diffusion is set during the deposition of boron diffusion to block the rapid diffusion of boron atoms, inhibit interface boron accumulation, reduce the BRL (boron rich layer) concentration, reduce Auger recombination, increase the opening voltage, and improve the battery conversion efficiency.

[0098] As an optional embodiment, the gradient temperature pre-oxidation includes at least 5 stages of heat preservation pre-oxidation, for example, 5, 6, 7, 8, 9, 10, etc.

[0099] As an optional embodiment, the temperature rise range of the two adjacent stages is 5 to 15°C, for example, 5°C, 6°C, 7°C, 8°C, 9°C, 10°C, 11°C, 12°C, 13°C, 14°C, 15°C, etc.

[0100] As an optional embodiment, the silicon substrate includes an N-type crystalline silicon substrate, and the back surface of the N-type crystalline silicon substrate includes a tunneling oxide layer and an intrinsic amorphous silicon layer stacked in sequence.

[0101] As an optional embodiment, the thickness of the tunnel oxide layer is 1.0 to 2.5 nm, for example, it can be 1.0 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2.0 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, etc.

[0102] As an optional embodiment, the thickness of the intrinsic amorphous silicon layer is 200 to 400 nm, for example, it can be 20 nm, 22 nm, 24 nm, 25 nm, 26 nm, 28 nm, 30 nm, 32 nm, 34 nm, 36 nm, 38 nm, 40 nm, etc.

[0103] As an optional embodiment, the pre-oxidation temperature range is 820-880°C, for example, it can be 820°C, 825°C, 830°C, 835°C, 840°C, 845°C, 850°C, 855°C, 860°C, 865°C, 870°C, 875°C, 880°C, etc.

[0104] As a preferred embodiment, the gradient temperature pre-oxidation includes five stages of heat preservation pre-oxidation:

[0105] The first stage: pre-oxidation at 825-835℃ for 1-5 minutes;

[0106] The second stage: pre-oxidation at 835-845℃ for 1-5 minutes;

[0107] The third stage: pre-oxidation at 845-855℃ for 1-5 minutes;

[0108] The fourth stage: pre-oxidation at 855-865℃ for 1-5 minutes;

[0109] The fifth stage: pre-oxidation at 865-875°C for 1-5 minutes.

[0110] In the present invention, the above 5 stages of heat preservation pre-oxidation program with gradient temperature increase are preferably used to effectively control the growth rate of the oxide layer thickness in each stage, achieve nanometer-level precision, significantly reduce the total thickness error, and form a denser layered pre-oxidation layer. And because the thermal expansion coefficient (CTE) of Si and SiO2 is different, the staged temperature increase can release stress step by step to avoid microcracks. At the same time, the dense layered pre-oxidation layer can serve as a diffusion barrier, limiting the disordered diffusion of boron atoms by adjusting the size of the micropores in the layer. The layered structure can suppress the "edge effect", make the doping uniformity within the chip, and avoid Auger recombination caused by local high concentration.

[0111] As an optional embodiment, the oxygen flow rate in each stage of the gradient temperature pre-oxidation is independently 100-400sccm, for example, it can be 100sccm, 120sccm, 140sccm, 160sccm, 180sccm, 200sccm, 220sccm, 240sccm, 260sccm, 280sccm, 300sccm, 320sccm, 340sccm, 360sccm, 380sccm, 400sccm, etc.

[0112] As an optional embodiment, the thickness of the pre-oxidation layer formed by the gradient temperature pre-oxidation is 10 to 50 nm, for example, it can be 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc.

[0113] As an optional embodiment, the period ratio of oxygen on and oxygen off in the intermittent oxygen-on boron diffusion is 1:(3-5), for example, it can be 1:3, 1:3.2, 1:3.4, 1:3.6, 1:3.8, 1:4, 1:4.2, 1:4.4, 1:4.6, 1:4.8, 1:5, etc.

[0114] In the present invention, the above cycle of oxygen supply and oxygen cut-off is preferably compared with intermittent oxygen diffusion. The intermittent oxygen supply cycle process allows boron atoms to advance into the silicon body in stages, better blocking the rapid diffusion of boron atoms, inhibiting interface boron accumulation, reducing BRL (boron-rich layer) concentration, alleviating Auger recombination, and utilizing the periodic barrier effect of the oxide layer to balance the adsorption and diffusion dynamics of boron, thereby optimizing the doping distribution and interface quality, thereby further improving the opening voltage of the TBC battery finally prepared and its conversion efficiency.

[0115] As an optional embodiment, BCl 3 , O 2 and N 2 are introduced during the oxygen-passing process of the boron diffusion.

[0116] As an optional embodiment, during the oxygen diffusion process of the boron diffusion, the flow rate of BCl3 is 100-400sccm, for example, it can be 100sccm, 120sccm, 140sccm, 160sccm, 180sccm, 200sccm, 220sccm, 240sccm, 260sccm, 280sccm, 300sccm, 320sccm, 340sccm, 360sccm, 380sccm, 400sccm, etc.

[0117] As an optional embodiment, during the oxygen flow process of the boron diffusion, the O2 flow rate is 700-1000sccm, for example, it can be 700sccm, 725sccm, 750sccm, 775sccm, 800sccm, 825sccm, 850sccm, 875sccm, 900sccm, 925sccm, 950sccm, 975sccm, 1000sccm, etc.

[0118] As an optional embodiment, during the oxygen diffusion process of the boron diffusion, the N2 flow rate is 2000-3000sccm, for example, it can be 2000sccm, 2100sccm, 2200sccm, 2300sccm, 2400sccm, 2500sccm, 2600sccm, 2700sccm, 2800sccm, 2900sccm, 3000sccm, etc.

[0119] As an optional embodiment, BCl 3 and N 2 are introduced during the oxygen-depletion process of the boron diffusion.

[0120] As an optional embodiment, during the oxygen-cutoff process of the boron diffusion, the BCl3 flow rate is 100-400sccm, for example, it can be 100sccm, 120sccm, 140sccm, 160sccm, 180sccm, 200sccm, 220sccm, 240sccm, 260sccm, 280sccm, 300sccm, 320sccm, 340sccm, 360sccm, 380sccm, 400sccm, etc.

[0121] As an optional embodiment, during the oxygen-cutoff process of the boron diffusion, the N2 flow rate is 2000-3000sccm, for example, it can be 2000sccm, 2100sccm, 2200sccm, 2300sccm, 2400sccm, 2500sccm, 2600sccm, 2700sccm, 2800sccm, 2900sccm, 3000sccm, etc.

[0122] As an optional embodiment, the total time of the boron diffusion is 2 to 4 hours, for example, it can be 2 hours, 2.2 hours, 2.4 hours, 2.5 hours, 2.6 hours, 2.8 hours, 3 hours, 3.2 hours, 3.4 hours, 3.6 hours, 3.8 hours, 4 hours, etc.

[0123] As an optional embodiment, the boron diffusion temperature is 800-1000°C, for example, it can be 800°C, 820°C, 840°C, 850°C, 860°C, 880°C, 890°C, 900°C, 920°C, 940°C, 950°C, 960°C, 980°C, 1000°C, etc.

[0124] As an optional embodiment, the thickness of the BSG layer is 30 to 80 nm, for example, it can be 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, etc.

[0125] As an optional implementation manner, the sheet resistance of the silicon substrate with the BSG layer is 100-200Ω, for example, it can be 100Ω, 120Ω, 140Ω, 160Ω, 180Ω, 200Ω, etc.

[0126] In a second aspect, the present invention provides a method for preparing a TBC battery, the method comprising the following steps:

[0127] (1) depositing a tunnel oxide layer and an intrinsic amorphous silicon layer on the back side of the silicon substrate;

[0128] (2) performing boron diffusion on the back side of the silicon substrate deposited in step (1); wherein the boron diffusion is performed using the boron diffusion method for the TBC battery described in the first aspect;

[0129] (3) The boron-diffused silicon substrate of step (2) is subjected to the first patterning, BSG removal, alkaline polishing, secondary deposition of a tunneling oxide layer and an intrinsic amorphous silicon layer, phosphorus diffusion, the second patterning, PSG removal, texturing, passivation treatment and electrode printing in sequence to obtain the preparation method of the TBC battery.

[0130] As an optional embodiment, in step (1), depositing the tunneling oxide layer and the intrinsic amorphous silicon layer at one time includes: depositing the tunneling oxide layer and the intrinsic amorphous silicon layer in sequence on the back side of the silicon substrate by LPCVD method.

[0131] As an optional embodiment, in step (1), the silicon substrate includes an N-type crystalline silicon substrate.

[0132] As an optional embodiment, in step (1), the thickness of the tunnel oxide layer is 1.0 to 2.5 nm, for example, it can be 1.0 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2.0 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, etc.

[0133] As an optional embodiment, in step (1), the temperature for depositing the tunnel oxide layer is 500-650°C, for example, it can be 500°C, 520°C, 540°C, 550°C, 560°C, 580°C, 600°C, 620°C, 640°C, 650°C, etc.

[0134] As an optional embodiment, in step (1), the time for depositing the tunnel oxide layer is 20 to 80 minutes, for example, it can be 20 minutes, 25 minutes, 30 minutes, 35 minutes, 40 minutes, 45 minutes, 50 minutes, 55 minutes, 60 minutes, 65 minutes, 70 minutes, 75 minutes, 80 minutes, etc.

[0135] As an optional embodiment, in step (1), the thickness of the intrinsic amorphous silicon layer is 200 to 400 nm, for example, it can be 200 nm, 220 nm, 240 nm, 250 nm, 260 nm, 280 nm, 300 nm, 320 nm, 340 nm, 360 nm, 380 nm, 400 nm, etc.

[0136] As an optional embodiment, in step (1), the temperature for depositing the intrinsic amorphous silicon layer is 500-650°C, for example, it can be 500°C, 520°C, 540°C, 550°C, 560°C, 580°C, 600°C, 620°C, 640°C, 650°C, etc.

[0137] As an optional embodiment, in step (1), the time for depositing the intrinsic amorphous silicon layer is 50 to 100 minutes, for example, it can be 50 minutes, 55 minutes, 60 minutes, 65 minutes, 70 minutes, 75 minutes, 80 minutes, 85 minutes, 90 minutes, 95 minutes, 100 minutes, etc.

[0138] As an optional embodiment, in step (3), the first patterning includes: using a picosecond laser to remove the BSG layer on the back side of the silicon substrate diffused with boron in step (2) to form a patterned groove.

[0139] As an optional embodiment, the power of the picosecond laser is 10 to 30 W, for example, it can be 10 W, 15 W, 20 W, 25 W, 30 W, etc.; the pulse frequency of the picosecond laser is 300 to 1000 Hz, for example, it can be 300 Hz, 400 Hz, 500 Hz, 600 Hz, 700 Hz, 800 Hz, 900 Hz, 1000 Hz, etc.; the laser scanning speed of the picosecond laser is 20,000 to 50,000 mm / s, for example, it can be 20,000 mm / s, 25,000 mm / s, 30,000 mm / s, 35,000 mm / s, 40,000 mm / s, 45,000 mm / s, 50,000 mm / s, etc.

[0140] As an optional embodiment, the depth of the patterned groove is 30 to 80 nm, for example, it can be 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, etc.

[0141] As an optional embodiment, the width of the patterned groove is 400-600 μm, for example, it can be 400 μm, 420 μm, 440 μm, 460 μm, 480 μm, 500 μm, 520 μm, 540 μm, 560 μm, 580 μm, 600 μm, etc.

[0142] As an optional embodiment, in step (3), the BSG wrap-around removal includes: using a chain wet method to remove the BSG layer on the front side of the silicon substrate after the first patterning.

[0143] As an optional embodiment, in step (3), the alkali polishing includes: using a groove polishing method to remove the tunneling oxide layer and the P-type polysilicon layer on the front side of the silicon substrate after BSG coating, and the tunneling oxide layer and the P-type polysilicon layer at the position of the patterned groove on the back side, and increasing the depth of the patterned groove by 2 to 3 μm, for example, it can be 2 μm, 2.2 μm, 2.4 μm, 2.5 μm, 2.6 μm, 2.8 μm, 3 μm, etc.

[0144] As an optional embodiment, in step (3), the secondary deposition of the tunneling oxide layer and the intrinsic amorphous silicon layer includes: depositing the tunneling oxide layer and the intrinsic amorphous silicon layer in sequence on the back side of the alkali-polished silicon substrate by LPCVD.

[0145] As an optional embodiment, in step (3), the thickness of the tunnel oxide layer is 1.0 to 2.5 nm, for example, it can be 1.0 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2.0 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, etc.

[0146] As an optional embodiment, in step (3), the temperature for depositing the tunnel oxide layer is 500-650°C, for example, it can be 500°C, 520°C, 540°C, 550°C, 560°C, 580°C, 600°C, 620°C, 640°C, 650°C, etc.

[0147] As an optional embodiment, in step (3), the time for depositing the tunnel oxide layer is 20 to 80 minutes, for example, it can be 20 minutes, 25 minutes, 30 minutes, 35 minutes, 40 minutes, 45 minutes, 50 minutes, 55 minutes, 60 minutes, 65 minutes, 70 minutes, 75 minutes, 80 minutes, etc.

[0148] As an optional embodiment, in step (3), the thickness of the intrinsic amorphous silicon layer is 100 to 300 nm, for example, it can be 100 nm, 120 nm, 140 nm, 160 nm, 180 nm, 200 nm, 220 nm, 240 nm, 260 nm, 280 nm, 300 nm, etc.

[0149] As an optional embodiment, in step (3), the temperature for depositing the intrinsic amorphous silicon layer is 500-650°C, for example, it can be 500°C, 520°C, 540°C, 550°C, 560°C, 580°C, 600°C, 620°C, 640°C, 650°C, etc.

[0150] As an optional embodiment, in step (3), the time for depositing the intrinsic amorphous silicon layer is 50 to 100 minutes, for example, it can be 250 minutes, 55 minutes, 60 minutes, 65 minutes, 70 minutes, 75 minutes, 80 minutes, etc.

[0151] As an optional embodiment, in step (3), the phosphorus diffusion includes: introducing a mixed gas of POCl3, O2 and N2 into the silicon substrate after secondary deposition to diffuse phosphorus, thereby obtaining a silicon substrate having a PSG layer.

[0152] As an optional embodiment, in step (3), during the phosphorus diffusion process, the flow rate of POCl3 is 1000-2000sccm, for example, it can be 1000sccm, 1100sccm, 1200sccm, 1300sccm, 1400sccm, 1500sccm, 1600sccm, 1700sccm, 1800sccm, 1900sccm, 2000sccm, etc.

[0153] As an optional embodiment, in step (3), during the phosphorus diffusion process, the O2 flow rate is 500-1000sccm, for example, it can be 500sccm, 550sccm, 600sccm, 650sccm, 700sccm, 725sccm, 750sccm, 775sccm, 800sccm, 825sccm, 850sccm, 875sccm, 900sccm, 925sccm, 950sccm, 975sccm, 1000sccm, etc.

[0154] As an optional embodiment, in step (3), during the phosphorus diffusion process, the N2 flow rate is 500-1500sccm, for example, it can be 500sccm, 550sccm, 600sccm, 650sccm, 700sccm, 750sccm, 800sccm, 850sccm, 900sccm, 950sccm, 1000sccm, 1100sccm, 1200sccm, 1300sccm, 1400sccm, or 1500sccm.

[0155] As an optional embodiment, the phosphorus diffusion temperature is 800-1000°C, for example, it can be 800°C, 820°C, 840°C, 850°C, 860°C, 880°C, 890°C, 900°C, 920°C, 940°C, 950°C, 960°C, 980°C, 1000°C, etc.

[0156] As an optional embodiment, the phosphorus diffusion time is 1 to 3 hours, for example, it can be 1 hour, 1.2 hours, 1.4 hours, 1.5 hours, 1.6 hours, 1.8 hours, 2 hours, 2.2 hours, 2.4 hours, 2.5 hours, 2.6 hours, 2.8 hours, 3 hours, etc.

[0157] As an optional embodiment, the thickness of the PSG layer is 30 to 80 nm, for example, it can be 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, etc.

[0158] As an optional embodiment, the sheet resistance of the silicon substrate with the PSG layer is 20 to 80Ω, for example, it can be 20Ω, 25Ω, 30Ω, 35Ω, 40Ω, 45Ω, 50Ω, 55Ω, 60Ω, 65Ω, 70Ω, 75Ω, 80Ω, etc.

[0159] As an optional embodiment, in step (3), the second patterning includes: retaining the PSG layer in the N region on the back side of the silicon substrate after phosphorus diffusion, and removing the PSG layer in the remaining area on the back side using a picosecond laser.

[0160] As an optional embodiment, the power of the picosecond laser is 20 to 60 W, for example, it can be 20 W, 25 W, 30 W, 35 W, 40 W, 45 W, 50 W, 55 W, 60 W, etc.; the pulse frequency of the picosecond laser is 300 to 1000 Hz, for example, it can be 300 Hz, 400 Hz, 500 Hz, 600 Hz, 700 Hz, 800 Hz, 900 Hz, 1000 Hz, etc.; the laser scanning speed of the picosecond laser is 20,000 to 50,000 mm / s, for example, it can be 20,000 mm / s, 25,000 mm / s, 30,000 mm / s, 35,000 mm / s, 40,000 mm / s, 45,000 mm / s, 50,000 mm / s, etc.

[0161] As an optional embodiment, the width of the retained PSG layer is 200 to 500 μm, for example, it can be 200 μm, 250 μm, 300 μm, 350 μm, 400 μm, 450 μm, 500 μm, etc., and the thickness of the retained PSG layer is 30 to 80 nm, for example, it can be 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, etc.

[0162] As an optional embodiment, in step (3), the de-PSG wrap-around coating includes: removing the PSG wrap-around coating layer on the front side of the silicon substrate after the second patterning.

[0163] As an optional embodiment, in step (3), the texturing includes: retaining the N-type polysilicon layer and tunneling oxide layer in the N region on the back side of the silicon substrate after PSG coating, and the P-type polysilicon layer and tunneling oxide layer in the P region on the back side, and performing texturing in the remaining front and back areas.

[0164] As an optional embodiment, in step (3), the passivation treatment includes: depositing an aluminum oxide layer, a silicon nitride layer and a silicon oxide layer on the front side of the textured silicon substrate; and depositing an aluminum oxide layer and a silicon nitride layer on the back side of the textured silicon substrate.

[0165] As an optional embodiment, the thickness of the aluminum oxide layer is 3 to 7 nm, for example, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, etc.

[0166] As an optional embodiment, the thickness of the silicon nitride layer is 70 to 100 nm, for example, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, etc.

[0167] As an optional embodiment, the thickness of the silicon oxide layer is 5 to 20 nm, for example, 5 nm, 6 nm, 8 nm, 10 nm, 12 nm, 14 nm, 16 nm, 18 nm, 20 nm, etc.

[0168] As an optional embodiment, in step (3), the printing electrode includes: printing an N-region electrode on the N-region on the back side of the passivated silicon substrate, and printing a P-region electrode on the P-region on the back side of the passivated silicon substrate.

[0169] As an optional embodiment, the preparation method of the TBC battery includes the following steps:

[0170] S1. Primary deposition:

[0171] Depositing a tunnel oxide layer and an intrinsic amorphous silicon layer once on the back side of an N-type crystalline silicon substrate to obtain a silicon substrate 1;

[0172] like Figure 1 As shown, the silicon substrate 1 includes an N-type crystalline silicon substrate 10, and a first tunneling oxide layer 20 and an intrinsic amorphous silicon layer 30 sequentially deposited on the back side of the N-type crystalline silicon substrate 10; it should be noted that during the back side deposition process, a first tunneling oxide layer 20 and an intrinsic amorphous silicon layer 30 may be formed on the front side of the N-type crystalline silicon substrate 10.

[0173] S2. Boron diffusion:

[0174] Boron diffusion is performed on the back side of the silicon substrate 1 deposited in step S1 to obtain a silicon substrate 2 having a BSG layer; wherein the boron diffusion is performed using the boron diffusion method for the TBC battery described in the first aspect;

[0175] like Figure 2 As shown, the silicon substrate 2 includes an N-type crystalline silicon substrate 10, and a first tunneling oxide layer 20, a P-type polysilicon layer 31 and a BSG layer 40 sequentially deposited on the back side of the N-type crystalline silicon substrate 10; it should be noted that, while the boron is diffused, the intrinsic amorphous silicon layer 30 on the back side will form a P-type polysilicon layer 31 (in the boron diffusion process, a high temperature environment is usually required to activate the diffusion activity of boron atoms. In this process, high temperature provides energy for atomic migration, prompting the silicon atoms in the amorphous silicon to rearrange and gradually form an ordered lattice structure); in the process of back-side boron diffusion, a BSG layer 40 may be formed on the front side of the N-type crystalline silicon substrate 10.

[0176] S3, first graphics:

[0177] Using laser to remove the BSG layer on the back side of the second silicon substrate having the BSG layer obtained in step S2 to form a patterned groove, thereby obtaining a third silicon substrate having a patterned groove;

[0178] like Figure 3 As shown, the silicon substrate three includes an N-type crystalline silicon substrate 10, and a first tunneling oxide layer 20, a P-type polysilicon layer 31 and a BSG layer 40 sequentially deposited on the back side of the N-type crystalline silicon substrate 10; and a patterned groove is formed in the BSG layer 40 on the back side of the N-type crystalline silicon substrate 10.

[0179] S4, remove BSG plating and alkali polishing:

[0180] Removing the BSG layer on the front side of the silicon substrate having the patterned groove obtained in step S3, and then removing the tunneling oxide layer and the P-type polysilicon layer on the front side of the silicon substrate, as well as the tunneling oxide layer and the P-type polysilicon layer at the position of the patterned groove on the back side, and increasing the depth of the patterned groove to obtain the silicon substrate fourth;

[0181] like Figure 4 As shown, the silicon substrate four includes an N-type crystalline silicon substrate 10, and a first tunneling oxide layer 20, a P-type polysilicon layer 31 and a BSG layer 40 sequentially deposited on the back side of the N-type crystalline silicon substrate 10, and the depth of the patterned groove increases and extends to the interior of the N-type crystalline silicon substrate 10.

[0182] S5. Secondary deposition of tunnel oxide layer and intrinsic amorphous silicon layer:

[0183] A tunneling oxide layer and an intrinsic amorphous silicon layer are deposited on the back side of the silicon substrate 4 obtained in step S4 to obtain a silicon substrate 5;

[0184] like Figure 5 As shown, the silicon substrate five includes an N-type crystalline silicon substrate 10, and a first tunneling oxide layer 20, a P-type polysilicon layer 31, a BSG layer 40, a second tunneling oxide layer 21, and an intrinsic amorphous silicon layer 30 sequentially deposited on the back side of the N-type crystalline silicon substrate 10; and the second tunneling oxide layer 21 and the intrinsic amorphous silicon layer 30 are sequentially deposited at the patterned groove; it should be noted that during the back side deposition process, a second tunneling oxide layer 21 and an intrinsic amorphous silicon layer 30 may be formed on the front side of the N-type crystalline silicon substrate 10.

[0185] S6, Phosphorus Diffusion:

[0186] Phosphorus is diffused on the back of the silicon substrate 5 deposited in step S5 to obtain a silicon substrate 6 having a PSG layer;

[0187] like Figure 6As shown, the silicon substrate six includes an N-type crystalline silicon substrate 10, and a first tunneling oxide layer 20, a P-type polysilicon layer 31, a BSG layer 40, a second tunneling oxide layer 21, an N-type polysilicon layer 32 and a PSG layer 50 sequentially deposited on the back side of the N-type crystalline silicon substrate 10; and the second tunneling oxide layer 21, the N-type polysilicon layer 32 and the PSG layer 50 are sequentially deposited at the patterned groove; it should be noted that while the phosphorus is diffused, the intrinsic amorphous silicon layer 30 on the back side will form an N-type polysilicon layer 32 (in the phosphorus diffusion process, a high temperature environment is usually required to activate the diffusion activity of phosphorus atoms. In this process, high temperature provides energy for atomic migration, prompting the silicon atoms in the amorphous silicon to rearrange and gradually form an ordered lattice structure); in the process of phosphorus diffusion on the back side, a surrounding PSG layer 50 may be formed on the front side of the N-type crystalline silicon substrate 10.

[0188] S7, Second Graphicalization

[0189] Retaining the PSG layer in the N region on the back side of the silicon substrate 6 after the phosphorus diffusion in step S6, and removing the PSG layer in the remaining area on the back side using a picosecond laser to obtain a silicon substrate 7;

[0190] like Figure 7 As shown, the silicon substrate 7 is based on the silicon substrate 6, and only the PSG layer 50 in the back N region is retained.

[0191] S8, remove PSG plating and texturing:

[0192] The PSG layer on the front side of the silicon substrate 7 after the second patterning in step S6 is removed; the N-type polysilicon layer and the tunneling oxide layer in the N region and the P-type polysilicon layer and the tunneling oxide layer in the P region on the back side of the silicon substrate after the PSG coating is removed are retained, and the remaining front and back areas are textured to obtain the silicon substrate 8;

[0193] like Figure 8 As shown, the silicon substrate eight includes an N-type crystalline silicon substrate 10, the front side of the N-type crystalline silicon substrate 10 has a pyramid velvet surface, the P region on the back side of the N-type crystalline silicon substrate 10 includes a first tunneling oxide layer 20 and a P-type polysilicon layer 31 stacked in sequence, the N region on the back side of the N-type crystalline silicon substrate 10 includes a second tunneling oxide layer 21 and an N-type polysilicon layer 32 stacked in sequence, and the remaining back side area has a pyramid velvet surface.

[0194] S9, passivation treatment and printing electrodes:

[0195] In step S8, an aluminum oxide layer, a silicon nitride layer and a silicon oxide layer are deposited on the front side of the silicon substrate after the texturing; an aluminum oxide layer and a silicon nitride layer are deposited on the back side of the silicon substrate after the texturing; an N-region electrode is printed on the N-region on the back side of the passivated silicon substrate, and a P-region electrode is printed on the P-region on the back side of the passivated silicon substrate to obtain the TBC battery.

[0196] like Figure 9 As shown, the TBC battery includes an N-type crystalline silicon substrate 10, the front side of the N-type crystalline silicon substrate 10 has a pyramid velvet surface, and the front side of the N-type crystalline silicon substrate 10 includes an aluminum oxide layer 60, a silicon nitride layer 61 and a silicon oxide layer 62 stacked in sequence; the P region on the back side of the N-type crystalline silicon substrate 10 includes a first tunneling oxide layer 20, a P-type polysilicon layer 31, an aluminum oxide layer 60, and a silicon nitride layer 61 stacked in sequence, and the P region on the back side of the N-type crystalline silicon substrate 10 is also printed with a P region electrode 72; the N region on the back side of the N-type crystalline silicon substrate 10 includes a second tunneling oxide layer 21, an N-type polysilicon layer 32, a silicon nitride layer 61 and a silicon oxide layer 62 stacked in sequence, and the N region on the back side of the N-type crystalline silicon substrate 10 is also printed with an N region electrode 71, and the remaining back side area has a pyramid velvet surface.

[0197] In a third aspect, the present invention provides a TBC battery, which is prepared by the boron diffusion method for the TBC battery described in the first aspect, or prepared by the preparation method for the TBC battery described in the second aspect.

[0198] The present invention is further described below by way of examples. Unless otherwise specified, the materials in the examples were prepared according to existing methods or directly purchased from the market.

[0199] Example 1

[0200] This embodiment provides a method for preparing a TBC battery, which includes the following steps:

[0201] S1. Primary deposition:

[0202] The LPCVD method is used to deposit a tunnel oxide layer and an intrinsic amorphous silicon layer on the back side of a double-sided polished N-type crystalline silicon substrate;

[0203] The thickness of the tunnel oxide layer is 1.8 nm; the deposition temperature is 580° C., and the deposition time is 50 min; the thickness of the intrinsic amorphous silicon layer is 300 nm; the deposition temperature is 580° C., and the deposition time is 75 min.

[0204] S2. Boron diffusion:

[0205] The silicon substrate treated with S1 is subjected to boron diffusion;

[0206] S2-1: Before deposition, a gradient temperature rise is set to form a dense layered pre-oxidation layer with a thickness of 25nm:

[0207] ① The first temperature is 830℃, the time is 2min, and the O2 flow rate is 150sccm;

[0208] ② The second temperature is 840°C, the time is 2 minutes, and the O2 flow rate is 200 sccm;

[0209] ③ The third temperature is 850℃, the time is 2min, and the O2 flow rate is 250sccm;

[0210] ④ The fourth temperature is 860°C, the time is 2 minutes, and the O2 flow rate is 300 sccm;

[0211] ⑤ The fifth temperature is 870°C, the time is 2 minutes, and the O2 flow rate is 350 sccm.

[0212] S2-2: Deposition is performed on the pre-oxidation layer, and intermittent oxygen diffusion is set during deposition to form a BSG layer with a sheet resistance of 130Ω and a thickness of 45nm:

[0213] Among them, the oxygen on / off cycle ratio is 1:4, and the total time of the boron diffusion is 3 hours; BCl3, O2 and N2 are introduced during the oxygen on process of the boron diffusion, the flow rate of BCl3 is 250sccm, the flow rate of O2 is 850sccm, and the flow rate of N2 is 2500sccm; BCl3 and N2 are introduced during the oxygen off process of the boron diffusion, the flow rate of BCl3 is 300sccm, and the flow rate of N2 is 2500sccm; the temperature of the boron diffusion is 900°C.

[0214] S3, first graphics:

[0215] Removing part of the BSG layer on the back of the N-type crystalline silicon substrate obtained in step (2) (the BSG layer in the subsequent Gap region + N region) to form a patterned groove;

[0216] The removal is performed using a picosecond laser, the power of the picosecond laser is 20W, the pulse frequency of the picosecond laser is 500kHz, the laser scanning speed of the picosecond laser is 25000mm / s, the depth of the patterned groove is 50nm, and the width of the patterned groove is 500μm.

[0217] S4, remove BSG plating and alkali polishing:

[0218] A chain wet method is used to remove the BSG layer coated on the front side of the silicon substrate after the first patterning; a groove polishing method is used to remove the tunneling oxide layer and P-type polysilicon layer on the front side of the silicon substrate after the BSG coating is removed, as well as the tunneling oxide layer and P-type polysilicon layer at the patterned groove position on the back side, and the depth of the patterned groove is increased by 2.5μm.

[0219] S5. Secondary deposition:

[0220] The LPCVD method is used to deposit a tunnel oxide layer and an intrinsic amorphous silicon layer on the back side of a double-sided polished N-type crystalline silicon substrate;

[0221] The thickness of the tunnel oxide layer is 1.6 nm; the deposition temperature is 580° C., and the deposition time is 50 min; the thickness of the intrinsic amorphous silicon layer is 250 nm; the deposition temperature is 580° C., and the deposition time is 75 min.

[0222] S6, Phosphorus Diffusion:

[0223] A mixed gas of POCl3, O2, and N2 was introduced into the silicon substrate after the secondary deposition to diffuse phosphorus, thereby obtaining a silicon substrate with a PSG layer having a square resistance of 30Ω and a thickness of 50nm.

[0224] Among them, the POCl3 flow rate is 1500sccm, the O2 flow rate is 800sccm, the N2 flow rate is 1000sccm, the deposition temperature is 900℃, and the deposition time is 2h.

[0225] S7, Second Graphicalization:

[0226] The PSG layer in the N region on the back side of the silicon substrate after phosphorus diffusion is retained, and the PSG layer in the remaining area on the back side is removed using a picosecond laser;

[0227] The removal is performed using a picosecond laser, the power of the picosecond laser is 40W, the pulse frequency of the picosecond laser is 500kHz, and the laser scanning speed of the picosecond laser is 25000mm / s.

[0228] S8, remove PSG plating and texturing:

[0229] The PSG layer on the front side of the silicon substrate after the second patterning is removed; the N-type polysilicon layer and tunneling oxide layer in the N region and the P-type polysilicon layer and tunneling oxide layer in the P region on the back side of the silicon substrate after the PSG coating is removed are retained, and the remaining front and back areas are textured.

[0230] S9, passivation treatment and printing electrodes:

[0231] A 4nm aluminum oxide layer, an 80nm silicon nitride layer and an 8nm silicon oxide layer are deposited on the front side of the textured silicon substrate; a 4nm aluminum oxide layer and an 80nm silicon nitride layer are deposited on the back side of the textured silicon substrate; an N-region electrode is printed on the N-region on the back side of the passivated silicon substrate, and a P-region electrode is printed on the P-region on the back side of the passivated silicon substrate to obtain the TBC battery.

[0232] Example 2

[0233] This embodiment provides a method for preparing a TBC battery, which includes the following steps:

[0234] S1. Primary deposition:

[0235] The LPCVD method is used to deposit a tunnel oxide layer and an intrinsic amorphous silicon layer on the back side of a double-sided polished N-type crystalline silicon substrate;

[0236] The thickness of the tunnel oxide layer is 1.8 nm; the deposition temperature is 580° C., and the deposition time is 50 min; the thickness of the intrinsic amorphous silicon layer is 300 nm; the deposition temperature is 580° C., and the deposition time is 75 min.

[0237] S2. Boron diffusion:

[0238] The silicon substrate treated with S1 is subjected to boron diffusion;

[0239] S2-1: Before deposition, a gradient temperature rise is set to form a dense layered pre-oxidation layer with a thickness of 20nm:

[0240] ① The first temperature is 825℃, the time is 3min, and the O2 flow rate is 120sccm;

[0241] ② The second temperature is 835℃, the time is 3 minutes, and the O2 flow rate is 180sccm;

[0242] ③ The third temperature is 845°C, the time is 3 minutes, and the O2 flow rate is 240 sccm;

[0243] ④ The fourth temperature is 855°C, the time is 3 minutes, and the O2 flow rate is 300 sccm;

[0244] ⑤The fifth temperature is 865°C, the time is 3 minutes, and the O2 flow rate is 360 sccm.

[0245] S2-2: Deposition is performed on the pre-oxidation layer, and intermittent oxygen diffusion is set during deposition to form a BSG layer with a sheet resistance of 120Ω and a thickness of 50nm of the BSG layer:

[0246] Among them, the oxygen on / off cycle ratio is 1:3, and the total time of the boron diffusion is 4 hours; during the oxygen on process of the boron diffusion, BCl3, O2 and N2 are introduced, the flow rate of BCl3 is 300sccm, the flow rate of O2 is 900sccm, and the flow rate of N2 is 3000sccm; during the oxygen off process of the boron diffusion, BCl3 and N2 are introduced, the flow rate of BCl3 is 300sccm, and the flow rate of N2 is 3000sccm; the temperature of the boron diffusion is 850℃.

[0247] S3, first graphics:

[0248] Removing part of the BSG layer on the back of the N-type crystalline silicon substrate obtained in step (2) (the BSG layer in the subsequent Gap region + N region) to form a patterned groove;

[0249] The removal is performed using a picosecond laser, the power of the picosecond laser is 20W, the pulse frequency of the picosecond laser is 500kHz, the laser scanning speed of the picosecond laser is 25000mm / s, the depth of the patterned groove is 50nm, and the width of the patterned groove is 500μm.

[0250] S4, remove BSG plating and alkali polishing:

[0251] A chain wet method is used to remove the BSG layer coated on the front side of the silicon substrate after the first patterning; a groove polishing method is used to remove the tunneling oxide layer and P-type polysilicon layer on the front side of the silicon substrate after the BSG coating is removed, as well as the tunneling oxide layer and P-type polysilicon layer at the patterned groove position on the back side, and the depth of the patterned groove is increased by 2.5μm.

[0252] S5. Secondary deposition:

[0253] The LPCVD method is used to deposit a tunnel oxide layer and an intrinsic amorphous silicon layer on the back side of a double-sided polished N-type crystalline silicon substrate;

[0254] The thickness of the tunnel oxide layer is 1.6 nm; the deposition temperature is 580° C., and the deposition time is 50 min; the thickness of the intrinsic amorphous silicon layer is 250 nm; the deposition temperature is 580° C., and the deposition time is 75 min.

[0255] S6, Phosphorus Diffusion:

[0256] A mixed gas of POCl3, O2, and N2 was introduced into the silicon substrate after the secondary deposition to diffuse phosphorus, thereby obtaining a silicon substrate with a PSG layer having a square resistance of 30Ω and a thickness of 50nm.

[0257] Among them, the POCl3 flow rate is 1500sccm, the O2 flow rate is 800sccm, the N2 flow rate is 1000sccm, the deposition temperature is 900℃, and the deposition time is 2h.

[0258] S7, Second Graphicalization:

[0259] The PSG layer in the N region on the back side of the silicon substrate after phosphorus diffusion is retained, and the PSG layer in the remaining area on the back side is removed using a picosecond laser;

[0260] The removal is performed using a picosecond laser, the power of the picosecond laser is 40W, the pulse frequency of the picosecond laser is 500kHz, and the laser scanning speed of the picosecond laser is 25000mm / s.

[0261] S8, remove PSG plating and texturing:

[0262] The PSG layer on the front side of the silicon substrate after the second patterning is removed; the N-type polysilicon layer and tunneling oxide layer in the N region and the P-type polysilicon layer and tunneling oxide layer in the P region on the back side of the silicon substrate after the PSG coating is removed are retained, and the remaining front and back areas are textured.

[0263] S9, passivation treatment and printing electrodes:

[0264] A 4nm aluminum oxide layer, an 80nm silicon nitride layer and an 8nm silicon oxide layer are deposited on the front side of the textured silicon substrate; a 4nm aluminum oxide layer and an 80nm silicon nitride layer are deposited on the back side of the textured silicon substrate; an N-region electrode is printed on the N-region on the back side of the passivated silicon substrate, and a P-region electrode is printed on the P-region on the back side of the passivated silicon substrate to obtain the TBC battery.

[0265] Example 3

[0266] This embodiment provides a method for preparing a TBC battery, which includes the following steps:

[0267] S1. Primary deposition:

[0268] The LPCVD method is used to deposit a tunnel oxide layer and an intrinsic amorphous silicon layer on the back side of a double-sided polished N-type crystalline silicon substrate;

[0269] The thickness of the tunnel oxide layer is 1.8 nm; the deposition temperature is 580° C., and the deposition time is 50 min; the thickness of the intrinsic amorphous silicon layer is 300 nm; the deposition temperature is 580° C., and the deposition time is 75 min.

[0270] S2. Boron diffusion:

[0271] The silicon substrate treated with S1 is subjected to boron diffusion;

[0272] S2-1: Before deposition, a gradient temperature rise is set to form a dense layered pre-oxidation layer with a thickness of 23nm:

[0273] ① The first temperature is 835°C, the time is 1.5 minutes, and the O2 flow rate is 150 sccm;

[0274] ② The second temperature is 845°C, the time is 1.5 minutes, and the O2 flow rate is 200 sccm;

[0275] ③ The third temperature is 855°C, the time is 1.5 minutes, and the O2 flow rate is 250 sccm;

[0276] ④ The fourth temperature is 865°C, the time is 1.5 minutes, and the O2 flow rate is 300 sccm;

[0277] ⑤ The fifth temperature is 870°C, the time is 1.5 minutes, and the O2 flow rate is 350 sccm.

[0278] S2-2: Deposition is performed on the pre-oxidation layer, and intermittent oxygen diffusion is set during deposition to form a BSG layer with a sheet resistance of 125Ω and a thickness of 48nm:

[0279] Among them, the oxygen on / off cycle ratio is 1:5, and the total time of the boron diffusion is 2h; during the oxygen on process of the boron diffusion, BCl3, O2 and N2 are introduced, the flow rate of BCl3 is 100sccm, the flow rate of O2 is 700sccm, and the flow rate of N2 is 2000sccm; during the oxygen off process of the boron diffusion, BCl3 and N2 are introduced, the flow rate of BCl3 is 120sccm, and the flow rate of N2 is 2000sccm; the temperature of the boron diffusion is 1000℃.

[0280] S3, first graphics:

[0281] Removing part of the BSG layer on the back of the N-type crystalline silicon substrate obtained in step (2) (the BSG layer in the subsequent Gap region + N region) to form a patterned groove;

[0282] The removal is performed using a picosecond laser, the power of the picosecond laser is 20W, the pulse frequency of the picosecond laser is 500kHz, the laser scanning speed of the picosecond laser is 25000mm / s, the depth of the patterned groove is 50nm, and the width of the patterned groove is 500μm.

[0283] S4, remove BSG plating and alkali polishing:

[0284] A chain wet method is used to remove the BSG layer coated on the front side of the silicon substrate after the first patterning; a groove polishing method is used to remove the tunneling oxide layer and P-type polysilicon layer on the front side of the silicon substrate after the BSG coating is removed, as well as the tunneling oxide layer and P-type polysilicon layer at the patterned groove position on the back side, and the depth of the patterned groove is increased by 2.5μm.

[0285] S5. Secondary deposition:

[0286] The LPCVD method is used to deposit a tunnel oxide layer and an intrinsic amorphous silicon layer on the back side of a double-sided polished N-type crystalline silicon substrate;

[0287] The thickness of the tunnel oxide layer is 1.6 nm; the deposition temperature is 580° C., and the deposition time is 50 min; the thickness of the intrinsic amorphous silicon layer is 250 nm; the deposition temperature is 580° C., and the deposition time is 75 min.

[0288] S6, Phosphorus Diffusion:

[0289] A mixed gas of POCl3, O2, and N2 was introduced into the silicon substrate after secondary deposition to diffuse phosphorus, thereby obtaining a silicon substrate with a PSG layer having a square resistance of 30Ω and a PSG thickness of 50nm.

[0290] Among them, the POCl3 flow rate is 1500sccm, the O2 flow rate is 800sccm, the N2 flow rate is 1000sccm, the deposition temperature is 900℃, and the deposition time is 2h.

[0291] S7, Second Graphicalization:

[0292] The PSG layer in the N region on the back side of the silicon substrate after phosphorus diffusion is retained, and the PSG layer in the remaining area on the back side is removed using a picosecond laser;

[0293] The removal is performed using a picosecond laser, the power of the picosecond laser is 40W, the pulse frequency of the picosecond laser is 500kHz, and the laser scanning speed of the picosecond laser is 25000mm / s.

[0294] S8, remove PSG plating and texturing:

[0295] The PSG layer on the front side of the silicon substrate after the second patterning is removed; the N-type polysilicon layer and tunneling oxide layer in the N region and the P-type polysilicon layer and tunneling oxide layer in the P region on the back side of the silicon substrate after the PSG coating is removed are retained, and the remaining front and back areas are textured.

[0296] S9, passivation treatment and printing electrodes:

[0297] A 4nm aluminum oxide layer, an 80nm silicon nitride layer and an 8nm silicon oxide layer are deposited on the front side of the textured silicon substrate; a 4nm aluminum oxide layer and an 80nm silicon nitride layer are deposited on the back side of the textured silicon substrate; an N-region electrode is printed on the N-region on the back side of the passivated silicon substrate, and a P-region electrode is printed on the P-region on the back side of the passivated silicon substrate to obtain the TBC battery.

[0298] Example 4

[0299] This embodiment provides a method for preparing a TBC battery. The only difference from Example 1 is that the gradient temperature increase program in S2-1 is different, as shown below:

[0300] ① The first temperature is 830℃, the time is 1min, and the O2 flow rate is 150sccm;

[0301] ② The second temperature is 835°C, the time is 2 minutes, and the O2 flow rate is 200 sccm;

[0302] ③ The third temperature is 840°C, the time is 3 minutes, and the O2 flow rate is 250 sccm;

[0303] ④ The fourth temperature is 845°C, the time is 4 minutes, and the O2 flow rate is 300 sccm;

[0304] ⑤The fifth temperature is 850°C, the time is 5 minutes, and the O2 flow rate is 350 sccm.

[0305] The other steps are exactly the same as those in Example 1.

[0306] Example 5

[0307] This embodiment provides a method for preparing a TBC battery. The only difference from Example 1 is that the gradient temperature increase program in S2-1 is different, as shown below:

[0308] ① The first temperature is 810℃, the time is 2min, and the O2 flow rate is 200sccm;

[0309] ② The second temperature is 825°C, the time is 2 minutes, and the O2 flow rate is 200 sccm;

[0310] ③ The third temperature is 840°C, the time is 2 minutes, and the O2 flow rate is 200 sccm;

[0311] ④ The fourth temperature is 855°C, the time is 2 minutes, and the O2 flow rate is 200 sccm;

[0312] ⑤The fifth temperature is 870°C, the time is 2 minutes, and the O2 flow rate is 200 sccm.

[0313] The other steps are exactly the same as those in Example 1.

[0314] Example 6

[0315] This embodiment provides a method for preparing a TBC battery. The only difference from Example 1 is that the cycle ratio of oxygen on and oxygen off in the intermittent oxygen-on boron diffusion in S2-2 is 1:2, and the other steps are exactly the same as in Example 1.

[0316] Example 7

[0317] This embodiment provides a method for preparing a TBC battery. The only difference from Example 1 is that the cycle ratio of oxygen on and oxygen off in the intermittent oxygen-on boron diffusion in S2-2 is 1:6, and the other steps are exactly the same as in Example 1.

[0318] Comparative Example 1

[0319] This comparative example provides a method for preparing a TBC battery. The only difference from Example 1 is that S2-1 no longer performs gradient temperature increase, but directly increases the temperature to 850°C and performs pre-oxidation at a constant temperature of 850°C for 10 minutes. The other steps are exactly the same as Example 1.

[0320] Comparative Example 2

[0321] This comparative example provides a method for preparing a TBC battery. The only difference from Example 1 is that the gradient temperature increase program of S2-1 is different, as shown below:

[0322] ① The first temperature is 835°C, the time is 4 minutes, and the O2 flow rate is 200 sccm;

[0323] ② The second temperature is 855°C, the time is 4 minutes, and the O2 flow rate is 200 sccm;

[0324] ③The third temperature is 870°C, the time is 2 minutes, and the O2 flow rate is 200 sccm.

[0325] The other steps are exactly the same as those in Example 1.

[0326] Comparative Example 3

[0327] This comparative example provides a method for preparing a TBC battery. The only difference from Example 1 is that S2-2 no longer performs intermittent oxygen supply. Instead, O2 is continuously supplied at a flow rate of 850 sccm during the 3-h boron diffusion process. The other steps are consistent with Example 1.

[0328] Comparative Example 4

[0329] This comparative example provides a method for preparing a TBC battery. The only difference from Example 1 is that S2-2 no longer performs intermittent oxygen supply, but continuously introduces O2 during the boron diffusion process. However, the O2 flow rate is reduced to 500 sccm, and the total boron diffusion time is extended to 5 h. The other steps are consistent with Example 1.

[0330] Test Case

[0331] Test samples: TBC batteries provided in Examples 1 to 7, and TBC batteries provided in Comparative Examples 1 to 4;

[0332] Test method: Use Halm test system to test electrical performance.

[0333] The specific test results are shown in Table 1:

[0334] Table 1

[0335]

[0336]

[0337] As shown in Table 1, the boron diffusion method of the TBC battery described in the present invention first forms a dense layered pre-oxidation layer by setting a gradient temperature increase before boron diffusion deposition, and sets intermittent oxygen diffusion during the boron diffusion deposition to block the rapid diffusion of boron atoms, inhibit interface boron accumulation, reduce the BRL (boron rich layer) concentration, reduce Auger recombination, increase the opening voltage, and improve the battery conversion efficiency.

[0338] From the comparison between Example 1 and Examples 4 to 5, it can be seen that the present invention effectively controls the growth rate of the oxide layer thickness in each stage by preferably performing a specific 5-stage heat preservation pre-oxidation program with a gradient temperature increase, thereby achieving nanometer-level precision, significantly reducing the total thickness error, and forming a denser layered pre-oxidation layer, thereby further improving the battery's opening voltage and improving the battery conversion efficiency.

[0339] From the comparison between Example 1 and Examples 6 to 7, it can be seen that the period ratio of oxygen on and oxygen off in the intermittent oxygen-on boron diffusion is preferably 1:(3 to 5), thereby further optimizing the doping distribution and interface quality, and improving the opening voltage of the TBC battery finally prepared, as well as its conversion efficiency.

[0340] From the comparison between Example 1 and Comparative Examples 1 to 2, it can be seen that if staged pre-oxidation is not performed or the number of stages of heat preservation pre-oxidation is too few, the temperature rise of two adjacent stages is greater than 15°C. Since a dense stratified pre-oxidation layer cannot be formed, interface boron is easily accumulated during the subsequent boron diffusion deposition process, and the battery's opening voltage and conversion efficiency are significantly reduced.

[0341] From the comparison between Example 1 and Comparative Examples 3-4, it can be seen that without intermittent oxygen supply or by reducing the oxygen flow rate to prolong the diffusion time for boron diffusion, it is difficult to prevent the rapid diffusion of boron atoms, Auger recombination is obvious, and the battery's opening voltage and conversion efficiency are significantly reduced.

[0342] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A boron diffusion method for a TBC battery, characterized in that: The boron diffusion method of the TBC battery includes: The back side of the silicon substrate is subjected to sequential pre-oxidation with a gradient temperature increase and boron diffusion with intermittent oxygen flow to obtain a silicon substrate with a BSG layer; The gradient temperature-increasing pre-oxidation includes at least five stages of heat-insulating pre-oxidation, and the temperature increase range between two adjacent stages is 5 to 15°C.

2. The boron diffusion method for TBC battery according to claim 1, characterized in that: The silicon substrate comprises an N-type crystalline silicon substrate, and the back surface of the N-type crystalline silicon substrate comprises a tunneling oxide layer and an intrinsic amorphous silicon layer stacked in sequence; Preferably, the thickness of the tunnel oxide layer is 1.0 to 2.5 nm; Preferably, the thickness of the intrinsic amorphous silicon layer is 200-400 nm.

3. The boron diffusion method for TBC battery according to claim 1, characterized in that: The pre-oxidation temperature range is 820-880°C; Preferably, the gradient temperature pre-oxidation includes five stages of heat preservation pre-oxidation: The first stage: pre-oxidation at 825-835℃ for 1-5 minutes; The second stage: pre-oxidation at 835-845℃ for 1-5 minutes; The third stage: pre-oxidation at 845-855℃ for 1-5 minutes; The fourth stage: pre-oxidation at 855-865℃ for 1-5 minutes; The fifth stage: pre-oxidation at 865-875℃ for 1-5 minutes; Preferably, the oxygen flow rate in each stage of the gradient temperature pre-oxidation is independently 100 to 400 sccm; Preferably, the thickness of the pre-oxidation layer formed by the gradient temperature increase pre-oxidation is 10 to 50 nm.

4. The boron diffusion method for TBC battery according to claim 1, characterized in that: The period ratio of oxygen on and oxygen off in the intermittent oxygen-on boron diffusion is 1:(3-5); Preferably, during the oxygen diffusion process of the boron diffusion, BCl3, O2 and N2 are introduced, the flow rate of BCl3 is 100-400 sccm, the flow rate of O2 is 700-1000 sccm, and the flow rate of N2 is 2000-3000 sccm; Preferably, BCl3 and N2 are introduced during the oxygen-cutoff process of the boron diffusion, the flow rate of BCl3 is 100-400 sccm, and the flow rate of N2 is 2000-3000 sccm; Preferably, the total time of the boron diffusion is 2 to 4 hours; the temperature of the boron diffusion is 800 to 1000° C.; Preferably, the thickness of the BSG layer is 30-80 nm; and the sheet resistance of the silicon substrate having the BSG layer is 100-200Ω.

5. A method for preparing a TBC battery, characterized in that: The preparation method of the TBC battery comprises the following steps: (1) depositing a tunnel oxide layer and an intrinsic amorphous silicon layer on the back side of the silicon substrate; (2) performing boron diffusion on the back side of the silicon substrate deposited in step (1); wherein the boron diffusion is performed using the boron diffusion method for a TBC battery according to any one of claims 1 to 4; (3) The boron-diffused silicon substrate of step (2) is subjected to the first patterning, BSG removal, alkaline polishing, secondary deposition of a tunneling oxide layer and an intrinsic amorphous silicon layer, phosphorus diffusion, the second patterning, PSG removal, texturing, passivation treatment and electrode printing in sequence to obtain the preparation method of the TBC battery.

6. The method for preparing a TBC battery according to claim 5, wherein: In step (1), the single deposition of the tunnel oxide layer and the intrinsic amorphous silicon layer comprises: depositing the tunnel oxide layer and the intrinsic amorphous silicon layer in sequence on the back side of the silicon substrate by LPCVD method: Preferably, in step (1), the silicon substrate comprises an N-type crystalline silicon substrate; Preferably, in step (1), the thickness of the tunnel oxide layer is 1.0 to 2.5 nm; Preferably, in step (1), the temperature for depositing the tunnel oxide layer is 500-650° C., and the time for depositing the tunnel oxide layer is 20-80 minutes; Preferably, in step (1), the thickness of the intrinsic amorphous silicon layer is 200 to 400 nm; Preferably, in step (1), the temperature for depositing the intrinsic amorphous silicon layer is 500-650° C., and the time for depositing the intrinsic amorphous silicon layer is 50-100 minutes.

7. The method for preparing a TBC battery according to claim 5, wherein: In step (3), the first patterning includes: using a picosecond laser to remove the BSG layer on the back side of the silicon substrate diffused with boron in step (2) to form a patterned groove; Preferably, the power of the picosecond laser is 10 to 30 W; the pulse frequency of the picosecond laser is 300 to 1000 kHz; the laser scanning speed of the picosecond laser is 20,000 to 50,000 mm / s; Preferably, the depth of the patterned groove is 30 to 80 nm; the width of the patterned groove is 400 to 600 μm; Preferably, in step (3), the BSG wrap-around removal comprises: using a chain wet process to remove the BSG layer on the front side of the silicon substrate after the first patterning; Preferably, in step (3), the alkali polishing comprises: removing the tunneling oxide layer and the P-type polysilicon layer on the front side of the silicon substrate after BSG coating, and the tunneling oxide layer and the P-type polysilicon layer at the position of the patterned groove on the back side by using a groove polishing method, and increasing the depth of the patterned groove by 2 to 3 μm; Preferably, in step (3), the secondary deposition of the tunnel oxide layer and the intrinsic amorphous silicon layer comprises: depositing the tunnel oxide layer and the intrinsic amorphous silicon layer in sequence on the back side of the alkali-polished silicon substrate by LPCVD method: Preferably, in step (3), the thickness of the tunnel oxide layer is 1.0 to 2.5 nm; Preferably, in step (3), the temperature for depositing the tunnel oxide layer is 500-650° C., and the time for depositing the tunnel oxide layer is 20-80 minutes; Preferably, in step (3), the thickness of the intrinsic amorphous silicon layer is 100 to 300 nm; Preferably, in step (3), the temperature for depositing the intrinsic amorphous silicon layer is 500-650° C., and the time for depositing the intrinsic amorphous silicon layer is 50-100 minutes.

8. The method for preparing a TBC battery according to claim 5, wherein: In step (3), the phosphorus diffusion includes: introducing a mixed gas of POCl3, O2 and N2 into the silicon substrate after secondary deposition to diffuse phosphorus, thereby obtaining a silicon substrate having a PSG layer; Preferably, the flow rate of POCl3 is 1000-2000 sccm; the flow rate of O2 is 500-1000 sccm; the flow rate of N2 is 500-1500 sccm; Preferably, the phosphorus diffusion temperature is 800-1000° C.; the phosphorus diffusion time is 1-3 hours; Preferably, the thickness of the PSG layer is 30 to 80 nm; the sheet resistance of the silicon substrate with the PSG layer is 20 to 80 Ω; Preferably, in step (3), the second patterning includes: retaining the PSG layer in the N region on the back side of the silicon substrate after phosphorus diffusion, and removing the PSG layer in the remaining area on the back side using a picosecond laser; Preferably, the power of the picosecond laser is 20 to 60 W; the pulse frequency of the picosecond laser is 300 to 1000 kHz; the laser scanning speed of the picosecond laser is 20,000 to 50,000 mm / s; Preferably, the width of the retained PSG layer is 200 to 500 μm, and the thickness of the retained PSG layer is 30 to 80 nm; Preferably, in step (3), the PSG wrap-around removal comprises: removing the PSG wrap-around layer on the front side of the silicon substrate after the second patterning; Preferably, in step (3), the texturing includes: retaining the N-type polysilicon layer and tunneling oxide layer in the N region on the back side of the silicon substrate after PSG coating, and the P-type polysilicon layer and tunneling oxide layer in the P region on the back side, and texturing is performed in the remaining front and back areas.

9. The method for preparing a TBC battery according to claim 5, wherein: In step (3), the passivation treatment includes: depositing an aluminum oxide layer, a silicon nitride layer and a silicon oxide layer on the front surface of the silicon substrate after texturing; depositing an aluminum oxide layer and a silicon nitride layer on the back surface of the silicon substrate after texturing; Preferably, the thickness of the aluminum oxide layer is 3 to 7 nm; Preferably, the thickness of the silicon nitride layer is 70 to 100 nm; Preferably, the thickness of the silicon oxide layer is 5 to 20 nm; Preferably, in step (3), the printing electrode comprises: printing an N-region electrode on the N-region on the back side of the passivated silicon substrate, and printing a P-region electrode on the P-region on the back side of the passivated silicon substrate.

10. A TBC battery, characterized in that: The TBC battery is prepared by the boron diffusion method of a TBC battery according to any one of claims 1 to 4, or prepared by the preparation method of a TBC battery according to any one of claims 5 to 9.

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