Solar cell, manufacturing method thereof and photovoltaic module

Abstract

The invention discloses a solar cell and a manufacturing method thereof, and a photovoltaic module, and relates to the field of photovoltaic technology. The solar cell includes: a semiconductor substrate having a first surface including a first region and a second region; the second area comprises an edge area and a middle area, each of the edge area and the middle area comprises a step structure recessed towards the second surface, and the step depth of the step structure of the edge area of the second area is larger than that of the step structure of the middle area of the second area; and the first doping layer is arranged on the first region, and the height of the bottom wall of the step structure in the middle region of the second region is lower than that of the first doping layer. The first passivation layer is arranged on the side, away from the semiconductor substrate, of the first doping layer and arranged on the second area. According to the embodiment of the invention, the thickness along the splitting direction is reduced, so that the splitting difficulty is reduced, meanwhile, the recombination of current carriers is reduced, and the passivation effect is improved.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the Patent Office of China on June 12, 2025, with application number 202510792152.8, entitled “A solar cell, a method for manufacturing the same, and a photovoltaic module,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a manufacturing method thereof, and a photovoltaic module. Background Art

[0004] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight strikes the pn junction of the solar cell's semiconductor, forming new hole-electron pairs. Under the influence of the built-in electric field within the pn junction, the photogenerated holes flow to the p region, and the photogenerated electrons flow to the n region. Once the circuit is connected, current is generated.

[0005] Compared to full-cut cells, half-cut cells offer better power output and efficiency. Therefore, they are currently commonly used in photovoltaic module production. However, the process of cutting full-cut cells into half-cut cells can cause defects such as dangling bonds to form near the cut sides, increasing carrier recombination and reducing photoelectric conversion efficiency. Summary of the Invention

[0006] The purpose of the present application is to provide a solar cell and a manufacturing method thereof, and a photovoltaic module to improve the passivation effect near the cut side, reduce carrier recombination, and improve the photoelectric conversion efficiency.

[0007] In order to achieve the above objectives, this application provides the following technical solutions:

[0008] In a first aspect, a solar cell is provided, comprising:

[0009] A semiconductor substrate comprising a first surface and a second surface opposite to each other, a first cut side surface connecting the first surface and the second surface, the first surface comprising a first region and a second region adjacent to the first cut side surface; along an extension direction of the second region, the second region comprising an edge region and a middle region, the edge region and the middle region both comprising a step structure recessed toward the second surface, the step structure of the edge region of the second region having a greater step depth than the step structure of the middle region of the second region;

[0010] A first doped layer is provided on the first region; along the thickness direction of the semiconductor substrate, the height of the bottom wall of the step structure in the middle region of the second region is lower than the height of the first doped layer;

[0011] A first passivation layer is provided on a side of the first doped layer facing away from the semiconductor substrate and on the second region.

[0012] In the solar cell provided by the present application, the step depth of the step structure of the edge area of the second area is greater than the step depth of the step structure of the middle area, which makes it easier to split the cell from the edge area. The bottom wall height of the step structure in the middle area is lower than the height of the first doping layer, which is equivalent to the thickness of the cell along the splitting direction being thinned, thereby further reducing the difficulty of splitting. In addition, the bottom walls of the step structures in the middle area and the edge area are both lower than the height of the first doping layer, so that the position of the laser cutting is farther away from the first doping layer during the cutting process. Taking into account the formation of more dangling bonds during the cutting process, the bottom wall of the step structure is lower than the height of the first doping layer, which can also avoid carriers approaching the dangling bonds in the cutting area, reduce the recombination of carriers and dangling bonds, and improve the photoelectric conversion efficiency. In addition, the step structures in the middle area and the edge area are both lower than the height of the first doping layer, that is, the first doping layer is etched away at the step structures in the middle area and the edge area, making the passivation of the first passivation layer easier and improving the passivation effect near the cutting area.

[0013] In one implementation, the step structure in the middle area is a first step structure, and the step structure in the edge area is a second step structure, and the step depth of the second step structure is greater than the step depth of the first step structure.

[0014] In this embodiment, the shallow grooves do not penetrate the entire cell, but are only provided in the middle region of the cell, while the deep grooves are provided at the edge regions. In other words, the thickness of the cell is partially reduced along the cell cutting direction, which reduces the difficulty of breaking the cell from the deep grooves at the edge regions.

[0015] In one implementation, the step structure in the middle area and the step structure in the edge area are connected to form a first step structure, and a second step structure is provided on the bottom wall of the step structure in the edge area.

[0016] When the entire cell is cut along the cutting line, a deeper groove is opened in the edge area on the basis of the shallow groove in the middle area, so that the cell is thinned as a whole along the cutting direction, thereby further reducing the difficulty of splitting, and the through groove can reduce the laser alignment requirements compared to the non-through groove, thereby reducing the process complexity requirements. In addition, the depth of the laser again in the shallow through groove is less than the depth of the laser directly in the edge area, which reduces the requirements for laser intensity and reduces the cost of the laser, that is, reduces the overall process cost. In addition, in the scheme applied to the negative spacing between adjacent cell pieces (that is, the overlapping setting of the edge areas of adjacent cell pieces), the first step structure can also be used for negative spacing overlap to improve the flatness of the entire surface of adjacent cell pieces.

[0017] In one implementation, the first area is provided with a first type of pyramid structure, the bottom wall of the first step structure in the second area is provided with a first texture structure, and the second surface is provided with a second texture structure, and the one-dimensional size of the first texture structure is larger than the one-dimensional size of the second texture structure.

[0018] In one implementation, the solar cell further includes a second doped layer provided on the second surface, the second doped layer has a conductivity type opposite to that of the first doped layer, and the entire second surface is provided with the second texture structure; or

[0019] The solar cell further includes a second doping layer spaced apart on the second surface. The second doping layer has a conductivity type opposite to that of the first doping layer. The second texture structure is provided in the space between two adjacent second doping layers on the second surface.

[0020] In one implementation, the first area is provided with a first type of pyramid structure, and the bottom wall of the first step structure in the second area is provided with a second type of pyramid structure, and one dimension of the first type of pyramid structure is larger than one dimension of the second type of pyramid structure.

[0021] In one implementation, the solar cell further includes a second doped layer spaced apart on the second surface, the second doped layer having a conductivity type opposite to that of the first doped layer, and a third type of pyramid structure is provided in the spacing region between two adjacent second doped layers on the second surface, wherein the one-dimensional size of the third type of pyramid structure is smaller than the one-dimensional size of the second type of pyramid structure.

[0022] In one implementation, a depth range of a spacing region between two adjacent second doping layers on the second surface is the same as a step depth range of the first stepped structure.

[0023] In one implementation, along the extension direction of the first step sidewall, the first step sidewall is wavy or curved; and / or,

[0024] Along the extension direction of the side wall of the first step, the first step structure extends continuously or discontinuously; and / or,

[0025] Along a direction perpendicular to the first cutting side surface, a width of the first step structure is 20 μm to 500 μm.

[0026] In one implementation, the sidewall of the first step is parallel to the thickness direction of the semiconductor substrate; or,

[0027] An angle is formed between the sidewall of the first step and the thickness direction of the semiconductor substrate.

[0028] In one implementation, the first passivation layer is provided on the step sidewalls and the step bottom wall of the first step structure;

[0029] In one implementation, a second passivation layer is provided in the first region near the edge of the second region, the second region and the first cutting side, and in the first region near the edge of the second region and the first step structure, the second passivation layer is located on the side of the first passivation layer facing away from the semiconductor substrate.

[0030] In one implementation, a step width of the first step structure is greater than a width of the second step structure.

[0031] In one implementation, a third passivation layer is provided on the second surface, a second passivation layer is provided on the first cut side, and the second passivation layer extends to an edge region of the second surface and is located on a side of the third passivation layer away from the semiconductor substrate.

[0032] In one implementation, along the thickness direction of the semiconductor substrate, the depth of the middle region of the first step structure is 2um to 10um; the depth of the edge region of the first step structure is 30%H to 100%H, where H is the thickness of the solar cell.

[0033] In one implementation, the one-dimensional size of the first texture structure is 15um to 50um; the one-dimensional size of the second texture structure is 2um to 20um.

[0034] In one implementation, the semiconductor substrate also includes a second cutting side surface, which is arranged opposite to the first cutting side surface, and the first surface also includes a third area adjacent to the second cutting side surface, and the first area is located on the side of the third area away from the second cutting side surface; along the extension direction of the third area, the third area includes an edge area and a middle area, and the edge area and the middle area both include a step structure, the step depth of the step structure of the edge area of the third area is greater than the step depth of the step structure of the middle area of the third area, and the height of the bottom wall of the step structure in the middle area of the third area is lower than the height of the first doping layer.

[0035] In one implementation, the step depth of the step structure in the middle region of the second region is the same as the step depth of the step structure in the middle region of the third region; and / or

[0036] The step depth of the step structure in the edge region of the second region is the same as the step depth of the step structure in the edge region of the third region; and / or,

[0037] The step width of the step structure in the middle area of the second area is the same as the step width of the step structure in the middle area of the third area; and / or

[0038] The step width of the step structure in the edge region of the second region is the same as the step width of the step structure in the edge region of the third region.

[0039] In a second aspect, a solar cell is provided. The solar cell includes a groove, and slicing is performed at the groove to obtain any of the solar cells described above.

[0040] In one implementation, the groove is provided in a middle area of the second area along an extending direction of the second area.

[0041] In one implementation, a groove structure is provided in an edge region of the second region; the groove structure is a Y-shaped groove.

[0042] In one implementation, the depth of the trench structure is greater than the depth of the groove.

[0043] In a third aspect, a method for manufacturing a solar cell is provided, comprising:

[0044] Providing a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a first region and a second region;

[0045] forming a first doped layer and a first doped silicon glass layer on the first surface;

[0046] reducing the density of the first doped silicon glass layer in the second region by laser irradiation;

[0047] groove polishing the second surface and removing a portion of the first doped silicon glass layer in the second region, thereby forming a groove in the second region that is concave toward the second surface;

[0048] forming a second doped layer on the second surface, wherein the conductivity type of the second doped layer is opposite to that of the first doped layer;

[0049] The second doped silicon glass layer on the second surface is removed, and along the thickness direction of the semiconductor substrate, the height of the bottom wall of the groove is lower than the height of the first doped layer;

[0050] forming a first electrode on the first doped layer and forming a second electrode on the second doped layer;

[0051] forming a groove in an edge region of the second region, wherein a recessed depth of the groove is greater than a recessed depth of the groove;

[0052] The semiconductor substrate is sliced along the grooves to obtain a plurality of solar cells.

[0053] The grooves after cutting form step structures on the two solar cells respectively. Along the thickness direction of the semiconductor substrate, the height of the bottom wall of the step structure is lower than the height of the first doping layer, which makes it easier to split the cell from the edge area. The bottom wall height of the step structure in the middle area is lower than the height of the first doping layer, which is equivalent to the thickness of the cell along the splitting direction being partially or completely thinned, thereby further reducing the difficulty of splitting. In addition, the bottom wall of the step structure in the middle area close to the cutting surface is lower than the height of the first doping layer 12, and the position of the split cutting is farther away from the first doping layer 12 during the cutting process. Since more dangling bonds are formed during the cutting process, being farther away from the first doping layer 12 can prevent carriers from approaching the cutting area, reduce carrier recombination, and improve photoelectric conversion efficiency. In addition, in the embodiment of the present application, while reusing the process of polishing the back side, the first doped silicon glass layer in the groove is cleaned for the first time, which saves process flow and reduces process cost.

[0054] In one implementation, forming a groove in an edge region of the second region using a laser includes:

[0055] The groove is formed in an edge region within the recess.

[0056] In a fourth aspect, a method for manufacturing a solar cell is provided, comprising:

[0057] Providing a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a first region and a second region;

[0058] forming a first doped layer and a first doped silicon glass layer on the first surface;

[0059] forming a second doped layer and a second doped silicon glass layer on the second surface, wherein the second doped layer has a conductivity type opposite to that of the first doped layer;

[0060] Using laser to reduce the density of the first doped silicon glass layer in the second region and the second doped silicon glass layer in the interval;

[0061] removing the first doped silicon glass layer and the second doped silicon glass layer, and forming a groove in the second region that is recessed toward the second surface, wherein the bottom wall of the groove has a height lower than that of the first doped layer along the thickness direction of the semiconductor substrate;

[0062] forming a first electrode on the first doped layer and forming a second electrode on the second doped layer;

[0063] forming a groove in an edge region of the second region, wherein a recessed depth of the groove is greater than a recessed depth of the groove;

[0064] The semiconductor substrate is sliced along the grooves to obtain a plurality of solar cells.

[0065] In the same step, laser irradiation of the first doped silicon glass layer in the second region and the second doped silicon glass layer in the spacing region between the adjacent second doped layers facilitates the subsequent removal of the doped silicon glass layers in the second region and the spacing region, thereby avoiding the need to add a separate laser step, that is, reusing the laser step that was originally intended to be used to make the spacing region on the back.

[0066] In one implementation, forming a groove in an edge region of the second region using a laser includes:

[0067] The groove is formed in an edge region within the recess.

[0068] In a fifth aspect, a photovoltaic assembly is provided, comprising: a plurality of battery strings connected in series and / or in parallel, the battery strings comprising: an electrical connector and a first solar cell and a second solar cell, the first solar cell and the second solar cell being the solar cells described in the first aspect, or the solar cells obtained by the manufacturing method described in the second aspect, the first solar cell and the second solar cell being connected by the electrical connector, the distance between the starting end of the electrical connector and the edge of the first region being greater than the width of the step structure of the middle region, and the conductive member passing through the first surface and the second side surface of the first solar cell, and the second surface of the second solar cell, the second side surface being the side surface opposite to the first cutting surface in the first solar cell, and the edge of the first region being the boundary edge between the first region and the second region.

[0069] In some possible implementations, the distance between the starting end of the electrical connector and the edge of the first region is greater than or equal to 1 mm.

[0070] In some possible implementations, the second side surface is a non-cutting side surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0072] Figure 1 A schematic diagram of a photovoltaic module provided in an embodiment of the present application;

[0073] Figure 2 A microscopic schematic diagram of a solar cell provided in an embodiment of the present application;

[0074] Figure 3 A top view of the first surface of a whole cell before cutting provided in an embodiment of the present application;

[0075] Figure 4 A top view of the first surface of a whole solar cell before cutting provided in another embodiment of the present application;

[0076] Figure 5 A partial structural cross-sectional view of a whole battery cell before cutting provided in an embodiment of the present application;

[0077] Figure 6 A partial cross-sectional view of a solar cell provided in an embodiment of the present application;

[0078] Figure 7 A partial cross-sectional view of a solar cell provided in another embodiment of the present application;

[0079] Figure 8 A partial cross-sectional view of a solar cell provided in another embodiment of the present application;

[0080] Figure 9 A partial cross-sectional view of a solar cell provided in another embodiment of the present application;

[0081] Figure 10 A partial cross-sectional view of a solar cell provided in another embodiment of the present application;

[0082] Figure 11 A partial cross-sectional view of a solar cell provided in another embodiment of the present application;

[0083] Figure 12 A cross-sectional view of an assembly provided for an embodiment of the application.

[0084] Reference numerals:

[0085] 1-first region, 2-second region, 3-first step sidewall, 4-groove, 5-trench structure, 10-semiconductor substrate, 11-first interface layer, 12-first doped layer, 13-first passivation layer, 14-first electrode, 15-second interface layer, 16-second doped layer, 17-third passivation layer, 18-second electrode, 19-second passivation layer, 30-groove structure, 31-recess, 32-trench, 21-middle region, 22-edge region;

[0086] A-solar cell, a-slicing, C-cutting line. DETAILED DESCRIPTION

[0087] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0088] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0089] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0090] In the description of this application, it should be understood that the terms "up", "down", "front", "back", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limitations on this application.

[0091] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0092] It should be noted that the various embodiments of the present application can be independent embodiments, and can also be combined separately if there is no logical conflict, and the present application does not limit this.

[0093] An embodiment of the present application provides a photovoltaic module, which includes a plurality of parallel and / or series connected battery strings, each battery string including an electrical connector and a plurality of solar cells connected in series, wherein the electrical connector electrically connects at least two of the solar cells. For example, Figure 1 A schematic diagram of a plurality of solar cells electrically connected together is provided. Figure 1 As shown, multiple solar cells are arranged in sequence along direction A to form a cell string, and multiple solar cells in the cell string are connected in series. Two or more cell strings are arranged in sequence along direction A to form a group of cell strings, and multiple groups of cell strings are arranged in sequence along direction B.

[0094] Compared to full-cut cells, half-cut cells offer better power output and efficiency. Therefore, they are currently commonly used in photovoltaic module production. However, during the process of cutting full-cut cells into half-cut cells, laser loss can cause defects such as dangling bonds near the cut sides, increasing carrier recombination and reducing photoelectric conversion efficiency.

[0095] In view of the above situation, in order to improve the passivation effect near the cut side, reduce carrier recombination, and improve the photoelectric conversion efficiency, the present application also provides a solar cell and a preparation method thereof, which can be applied to the above-mentioned photovoltaic module.

[0096] The semiconductor substrate 10 includes a first surface and a second surface that are opposite to each other along the thickness direction of the semiconductor substrate 10. The first surface may correspond to the light-facing side of the solar cell, and the second surface may correspond to the backlight side of the solar cell; alternatively, the first surface may correspond to the backlight side of the solar cell, and the second surface may correspond to the light-facing side of the solar cell. In this application, the first surface corresponds to the light-facing side of the solar cell, and the second surface corresponds to the backlight side of the solar cell.

[0097] The semiconductor substrate 10 includes a first cut side surface, that is, the solar cell is a cut cell, at least one side surface of the semiconductor substrate 10 is a cut surface, and the first cut side surface is a cut surface. The following embodiment will be described by taking the cut cell as an example. Figure 2 As shown, the first surface includes a first region 1 and a second region 2, the second region 2 is adjacent to the first cutting side surface, and the first region 1 is located on the side of the second region 2 away from the first cutting side surface. That is, the second region 2 is closer to the first cutting side surface than the first region 1, and the second region 2 is located between the first region 1 and the first cutting side surface. Figure 2 As shown, the second region 2 includes a step structure that is recessed toward the second surface. The second region 2 can be recessed as a whole to form the step structure, or the second region 2 can be partially recessed to form the step structure. A step sidewall 3 is formed between the step structure and the first region 1. The step structure includes the step sidewall 3 and the step bottom wall. Figure 3 or Figure 4 The second region 2 includes a middle region 21 and an edge region 22. The middle region 21 and the edge region 22 can respectively form a step structure, and the step depth of the step structure of the edge region 22 is greater than the step depth of the step structure of the middle region 21, which helps to split from the step structure of the edge region.

[0098] In addition, if Figure 6As shown, the first doping layer 12 is provided in the first region 1. Specifically, the first doping layer 12 can cover the entire or part of the first region 1. The first doping layer 12 can be additionally formed on the semiconductor substrate 10 by deposition technology, or can be formed in the semiconductor substrate 10 by diffusion, ion implantation, etc. Along the thickness direction of the semiconductor substrate 10, the height of the bottom wall of the step structure in the middle region is lower than the height of the first doping layer 12. That is, when the first surface is facing upward, the bottom wall of the step structure in the middle region is lower than the bottom side of the first doping layer 12, or in other words, there is a height difference between the bottom wall of the step structure in the middle region and the first doping layer 12. It can be understood that if the step depth in the edge region is greater than the step depth in the middle region, the bottom wall of the edge region is also lower than the first doping layer 12. In this way, both the middle region and the edge region keep the first doping layer away from the first cutting surface to avoid the recombination of dangling bonds formed during the cutting process.

[0099] Reference Figure 6 , the first passivation layer 13 is provided on the side of the first doped layer 12 away from the semiconductor substrate 10, and is provided on the entire or part of the second region. For example, the first passivation layer 13 can be provided on the entire second region, that is, the bottom wall and side walls of the step structure in the middle region, and the bottom wall and side walls of the step structure in the edge region. Or the first passivation layer 13 can be provided on part of the second region, that is, the first passivation layer is provided only on the bottom wall and side walls of the step structure in the middle region, and the first passivation layer is not provided on the bottom wall and side walls of the step structure in the edge region. Alternatively, the first passivation layer can be provided on some other areas of the second region, which is not limited in this application. The first passivation layer 13 can protect the surface of the battery cell, prevent water vapor or oxygen from penetrating into the interior of the battery cell, thereby avoiding performance degradation of the battery cell due to oxidation or hydrolysis; and the provision of the first passivation layer 13 can reduce the surface recombination rate of the battery cell and reduce the reflectivity of light, thereby improving the photoelectric conversion efficiency of the battery.

[0100] It is understood that the first passivation layer 13 can be a single-layer structure; alternatively, the first passivation layer 13 can be a multi-layer structure. Specifically, the first passivation layer 13 is at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and an aluminum oxide layer, or a composite film formed by stacking these. Exemplarily, the first passivation layer 13 can be a double-layer structure, comprising an aluminum oxide layer and a silicon nitride layer, with the aluminum oxide layer located on the side of the silicon nitride layer closer to the semiconductor substrate 10.

[0101] Therefore, in the solar cell provided by the present application, the step depth of the step structure of the edge area of the second region is greater than the step depth of the step structure of the middle area, which makes it easier to split the cell from the edge area. The bottom wall height of the step structure in the middle area is lower than the height of the first doped layer, which is equivalent to the thickness of the cell along the splitting direction being thinned, thereby further reducing the difficulty of splitting. In addition, the bottom walls of the step structures in the middle area and the edge area are both lower than the height of the first doped layer, so that the position of the laser cutting is farther away from the first doped layer during the cutting process. Considering that more dangling bonds are formed during the cutting process, the bottom wall of the step structure is lower than the height of the first doped layer, which can also avoid carriers approaching the dangling bonds in the cutting area, reduce the recombination of carriers and dangling bonds, and improve the photoelectric conversion efficiency. In addition, the step structures in the middle area and the edge area are both lower than the height of the first doped layer, that is, the first doped layer is etched away at the step structures in the middle area and the edge area, making the passivation of the first passivation layer easier and improving the passivation effect near the cutting area.

[0102] It is understood that the first doped layer 12 can be a P-type doped layer or an N-type doped layer. The P-type doped layer can contain one or more elements from Group IIIA (for example, boron). The N-type doped layer can contain one or more elements from Group VA (for example, phosphorus). The materials of the N-type doped layer and the P-type doped layer can include any semiconductor material such as silicon, silicon germanium, germanium, or gallium arsenide. In terms of the arrangement of the materials, the crystalline phase of the doped layer can be amorphous, microcrystalline, nanocrystalline, single crystal, or polycrystalline. The materials of the N-type doped layer and the P-type doped layer can be the same or different. For example, the materials of the N-type doped layer and the P-type doped layer can both include doped polycrystalline silicon. For another example, the material of the P-type doped layer can include doped polycrystalline silicon, and the material of the N-type doped layer can include at least one of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon. The P-type doped layer can be obtained by in-situ doping on the surface of the silicon substrate or by deposition on the surface of the silicon substrate. The N-type doped layer can also be obtained by in-situ doping on the surface of the silicon substrate or by deposition on the surface of the silicon substrate. The silicon substrate 1 may be N-type single crystal silicon or P-type single crystal silicon, which can provide long-life carriers.

[0103] In some possible embodiments, when a PN junction is formed between the semiconductor substrate and the first doped layer 12, for example, the semiconductor substrate 10 is an N-type substrate and the first doped layer 12 is a P-type doped layer, a PN junction is formed between the semiconductor substrate 10 and the first doped layer 12. The height of the bottom wall of the step structure is lower than the height of the first doped layer 12. This can be understood as removing the PN junction in the edge region of the cell close to the cut surface, that is, removing the P-type doped layer (that is, removing the highly doped B atoms), which can effectively suppress the probability of carrier recombination in the second region, reduce the impact on the field passivation effect of the passivation layer on the subsequent cut surface, and improve the subsequent passivation effect, thereby helping to reduce the power loss caused by laser cutting.

[0104] In some possible embodiments, reference Figure 3 , Figure 3 A top view of the first surface of a whole cell before cutting is shown. The middle region 21 is recessed toward the second surface to form a first step structure, while the edge region 22 is recessed toward the second surface to form a second step structure. The depth of the second step structure is greater than that of the first step structure. In other words, the shallow groove (groove 31) of the entire cell does not penetrate the entire cell; it is only provided in the middle region 21, while the deep groove (groove 32) is provided in the edge region 22. This means that the thickness of the cell is partially reduced along the cell cutting direction, reducing the difficulty of splitting the cell from the deep groove in the edge region.

[0105] It should be noted that in the present application, the widths of the deep groove and the shallow groove can be the same, or the width of the deep groove can be smaller than the width of the shallow groove. For ease of description, the following embodiments are described as an example in which the width of the deep groove is smaller than the width of the shallow groove, but the present application is not limited to this.

[0106] It is understood that the edge region of the cell may be the two ends along the cutting direction (ie Figure 3 The edge areas 22 on the upper and lower sides of the middle part can also be one end along the cutting direction (i.e. Figure 3 The upper or lower edge area 22 is not limited in this application.

[0107] It can also be understood that in this embodiment, the second step structure and the first step structure may be connected or not connected, that is, the deep groove and the shallow groove of the entire battery cell may be connected or not connected, and this application does not limit this.

[0108] It is also understood that in this embodiment, the middle region 21 can be obtained by both laser and wet methods, as described in detail in the following preparation method. The edge region 22 can be obtained by laser or by using the same steps as the middle region 21, which is not limited in this application.

[0109] In some other possible embodiments, Figure 4 As shown ( Figure 4 ) shows another top view of the first surface of the whole cell before cutting. Along the extension direction of the second region, the second region includes an edge region 22 and a middle region 21. The middle region and the edge region include a first step structure that is connected and recessed toward the second surface, and a second step structure is provided on the bottom wall of the first step structure in the edge region. In other words, for the whole cell, the shallow groove is a through groove along the cutting direction, and the deep groove is provided in the shallow groove. For further reference Figure 5 , Figure 5 A partial structural cross-sectional view of a whole cell before cutting is shown, in which the step depth H2 of the edge region 22 of the second region is greater than the step depth H1 of the middle region 21 of the second region. In this way, when the whole cell is cut along the cutting line C, a deeper groove 32 is opened in the edge region 22 on the basis of the shallower groove 31 in the middle region 21, so that the cell is thinned as a whole along the cutting direction, thereby further reducing the difficulty of splitting. The through groove can reduce the laser alignment requirements compared to the non-through groove, thereby reducing the process complexity requirements. In addition, the depth of the laser impact in the shallow through groove is less than the depth of the laser impact directly in the edge region, which reduces the requirements for laser intensity and allows the laser to act directly on the surface of the silicon substrate with low doping concentration or no doping, making more efficient use of the laser, improving the precision of the splitting, reducing the cost of the laser, that is, reducing the overall process cost and reducing the impact of the laser on the active area. In addition, in the scheme applied to the negative spacing between adjacent cells (i.e., the overlapping edge regions of adjacent cells), the first step structure can also be used for negative spacing overlap to improve the flatness of the surface of adjacent cells in the entire assembly.

[0110] For example, a whole cell can be cut to obtain multiple solar cells, such as 2, 3, 4, 6... solar cells. In the first surface of the whole cell, grooves 31 (i.e., shallow grooves) and trenches 32 (i.e., shallow grooves) can be arranged along the extension direction of the cutting line C. Subsequent cutting based on the groove structure 30 can make the cutting operation easier, improve the cutting efficiency and the quality of the finished product after cutting, that is, the grooves 31 can reduce the overall thickness of the whole cell in the cutting extension direction, thereby further reducing the difficulty of splitting. Figure 3 、 4 5, two solar cells (i.e., half-cells) can be obtained after the whole cell is cut. Specifically, along the cutting line C, the first surface of the whole cell can be divided into two edge regions 22 at the edge and a middle region 21 in the middle. The groove structure 30 can include a shallow groove 31 that is mostly located in the middle region 21, and a deeper groove 32 located in the edge region 22.

[0111] In some possible embodiments, reference Figure 3 and Figure 5 The step width W2 of the edge region 22 is smaller than the step width W1 of the middle region 21. The step structure in the edge region is used for splitting and has a deeper depth. Therefore, the step width in the edge region is smaller than that in the middle region, which can avoid causing more damage to the solar cell.

[0112] In some possible embodiments, the first region 1 is provided with a first type of pyramid structure, and the second region 2 is provided with a first texture structure or a second type of pyramid structure. Figure 6 In the embodiment, the second region 2 is provided with a second type of pyramid structure; or, for example, Figure 7 In the embodiment, the second region 2 is provided with a first texture structure. The first type pyramid structure and / or the second type pyramid structure may include a pyramid with a sharp top angle, a pyramid with a smooth chamfered corner, or a pyramid with a flattened top angle. With this technical solution, the first type pyramid structure of the first region 1, the first texture structure or the second type pyramid structure of the second region 2 is conducive to improving the light trapping effect of the light-facing surface, reducing the reflectivity of light, and making more light be reflected into the semiconductor substrate 10 and utilized by the semiconductor substrate 10, thereby improving the light absorption utilization rate. The provision of the first texture structure or the second type pyramid structure of the second region 2 can increase the specific surface area and roughness of the second region 2, play a certain anchoring role, and is conducive to improving the adhesion of the second region 2 after lamination, preventing partial delamination or peeling of the second region 2 of the cell, and extending the service life of the solar cell.

[0113] It should be noted that the texture structure of this application can be the surface topography of a polished surface, or the structure of a tower base (for example, a raised structure or a recessed structure, etc.), and this application is not limited to this. For example, the first texture structure mentioned above, and the second and third texture structures described below, can be the same or different, and this application is not limited to this.

[0114] In some possible embodiments, the bottom wall of the first stepped structure is provided with a first textured structure. Since the first textured structure has a relatively small undulation (which can be understood as having no spire), in combination with the aforementioned embodiment, the bottom wall of the first stepped structure is provided with a second stepped structure. When the second stepped structure is formed by laser on the bottom wall of the first stepped structure, the laser concentration at the tip is reduced, resulting in a more uniform laser effect and less damage to the cell.

[0115] In some possible embodiments, the one-dimensional size of the first-type pyramid structures is different from the one-dimensional size of the second-type pyramid structures, or in other words, the size ranges are different. The second-type pyramid structures provided in the second region are smaller than the one-dimensional size of the first-type pyramid structures in the first region. This results in a smaller height of the pyramid structures in the second region, a smaller increase in specific surface area, and greater coverage by the passivation layer, thereby further improving the passivation effect of the second region.

[0116] It is understandable that the pyramid-like structure involved in the embodiments of the present application can be a pyramid structure with a spire, or a pyramid structure without a spire, and the present application does not limit this.

[0117] In some possible embodiments, the second region is provided with a plurality of second texture structures, with the second texture structures near the sidewall being denser and the second texture structures away from the sidewall being sparser. For example, the number of second texture structures near the sidewall is greater than the number of second texture structures away from the sidewall.

[0118] In some embodiments, the depth of the first step structure is set along the thickness direction of the semiconductor substrate 10. If the depth of the first step structure is too large, the mechanical strength of the semiconductor substrate 10 will be reduced. If the depth of the first step structure is too small, the first doped layer 12 will be greatly affected during the laser cutting process, affecting the passivation effect of the first doped layer 12. In this technical solution, in order to take into account the above two aspects, the depth of the middle area of the first step structure is 2um to 10um along the thickness direction of the semiconductor substrate, so as to ensure the mechanical strength of the semiconductor substrate 10 while reducing the impact of cutting on the passivation effect. The depth of the edge area of the first step structure is 30%H to 100%H, where H is the thickness of the solar cell. Such a depth range can ensure that the formed cutting guide area effectively divides the entire solar cell into two split solar cells. Furthermore, when the ratio is less than 100%, the damage to the solar cell caused by the lossy laser can be reduced.

[0119] It should be noted that, for the solution of setting a through shallow groove, the deep groove is inside the shallow groove, and the depth of the deep groove can be understood as being measured from the first surface of the battery cell.

[0120] Exemplarily, the depth of the first step structure is 2um, 3um, 4um, 5um, 6um, 7um, 8um, 9um or 10um.

[0121] The embodiments of the present application can be applied to bifacial cells (eg, TOPCon (passivated contact) cells) and can also be applied to back-contact cells (eg, BC cells).

[0122] In some embodiments, the solar cell further includes a second doped layer disposed on the second surface, the second doped layer having a conductivity type opposite to that of the first doped layer, and the entire second surface is provided with the second textured structure. In other words, embodiments of the present application can be applied to a solution in which the entire back surface is provided with the second doped layer.

[0123] It is understandable that the entire back surface does not necessarily mean that the second doping layer is provided on the entire back surface, and it is only used to distinguish from products with doping layers provided at intervals on the back surface.

[0124] In some embodiments, the solar cell further includes a second doped layer spaced apart on the second surface, the second doped layer having a conductivity type opposite to that of the first doped layer, and the second texture structure is provided in the spaced area between two adjacent second doped layers on the second surface.

[0125] The solar cell further includes a second doped layer 16 disposed on the second surface. The second doped layer 16 may be disposed entirely or partially on the second surface. The second doped layer 16 may be formed additionally on the semiconductor substrate 10 through deposition techniques, or may be formed within the semiconductor substrate 10 through diffusion, ion implantation, or the like. The second doped layer 16 has an opposite conductivity type to that of the first doped layer 12, so as to collect and conduct electrons and holes, respectively, thereby facilitating the formation of photocurrent.

[0126] When the second doped layer 16 is locally disposed on the second surface, the second doped layer 16 can be spaced apart along the first direction on the second surface. The second doped layer 16 extends along the second direction and can be distributed in a strip-like, "F"-like, or other shape. The first direction and the second direction intersect, and the angle between the first and second directions can be an acute angle or a right angle. The first direction can be the length direction of the semiconductor substrate 10 or the width direction of the semiconductor substrate 10. When the first direction is the length direction of the semiconductor substrate 10, the second direction is the width direction of the semiconductor substrate 10; when the first direction is the width direction of the semiconductor substrate 10, the second direction is the length direction of the semiconductor substrate 10.

[0127] like Figure 7 As shown, second doped layers 16 are spaced apart along the first direction on the second surface. When the first texture structure is provided in the second region 2, a second texture structure is provided in the space between two adjacent second doped layers 16 on the second surface. The second texture structure can have the same or different shapes as the first texture structure. Using this technical solution, the second texture structure helps to enhance the light trapping effect of the light-facing surface, reduce light reflectivity, and facilitate more light to be reflected into and utilized by the semiconductor substrate 10, thereby improving light absorption and utilization efficiency. Furthermore, the second texture structure can further reduce lateral recombination of carriers.

[0128] In some embodiments, the first region 1 is provided with a first type pyramid structure, the second region 2 is provided with a first texture structure, and the second surface is provided with a second texture structure, and the one-dimensional size of the first texture structure is larger than the one-dimensional size of the second texture structure.

[0129] Because the one-dimensional dimension of the first texture structure is larger than the one-dimensional dimension of the second texture structure, the light irradiating the second area 2 in this manner. The one-dimensional dimension can be a one-dimensional parameter such as the height, width, or spacing of the first or second texture structure; for example, the height of the first texture structure is larger than the height of the second texture structure, or the width of the first texture structure is larger than the width of the second texture structure. The fact that the first texture structure has a larger one-dimensional dimension than the second texture structure, i.e., the first texture structure has a smaller degree of undulation, can help cover the passivation layer in the cutting area, thereby further improving the passivation effect near the cutting area.

[0130] In some embodiments, the one-dimensional size of the first texture structure is set within a reasonable range of 15um to 50um to improve the light trapping effect and light absorption utilization rate of the second region 2 while preventing the one-dimensional size of the first texture structure from being too large, affecting the formation quality of the passivation layer in the second region 2, and avoiding the situation where the formation quality of the passivation layer is reduced and the passivation effect is poor. Exemplarily, the one-dimensional size of the first texture structure is 15um, 18um, 20um, 22um, 25um, 26um, 27um, 28um, 29um, 30um, 31um, 32um, 33um, 34um, 35um, 38um, 40um, 42um, 45um, 48um or 50um, etc.

[0131] In some embodiments, the one-dimensional size of the second texture structure is set within a reasonable range of 2um to 20um to prevent the second texture structure from being too large in the gap between two adjacent second doped layers 16 on the second surface. This would cause severe etching in the gap between the two adjacent second doped layers 16, forming excessive dangling bonds, leading to severe carrier recombination, which is not conducive to improving power generation efficiency and affecting the mechanical properties of the silicon wafer. Exemplary, the one-dimensional size of the second texture structure is 2um, 3um, 4um, 5um, 6um, 7um, 8um, 9um, 10um, 11um, 12um, 13um, 14um, 15um, 18um, or 20um.

[0132] In other embodiments, when the second region 2 is provided with a first texture structure, the second surface is provided with a second texture structure. That is, in this technical solution, the entire surface of the second surface is provided with a second texture structure. The first texture structure and the second texture structure may be the same or different. The first texture structure may include a tower base structure, which is conducive to forming a better quality passivation layer in the second region 2, improving the passivation effect of the second region 2, further reducing carrier recombination on the surface of the solar cell, and improving the photoelectric conversion efficiency. With this technical solution, the second texture structure is conducive to further improving the light trapping effect of the cell, reducing the reflectivity of light, and facilitating more light to be reflected into the semiconductor substrate 10 and utilized by the semiconductor substrate 10, thereby improving the light absorption and utilization rate. In addition, the entire second surface is provided with a second texture structure, which can be applied to a battery structure in which a tunneling oxygen layer and a doped polysilicon layer (i.e., a second doped layer) are made on the entire back surface. That is, a tunneling oxygen layer and a doped polysilicon layer are deposited on a semiconductor substrate provided with a second texture structure. Since the tunneling oxygen layer is difficult to grow, a smaller second texture structure is required. The bottom wall of the step in the second area on the front side is only used for depositing a passivation layer (such as aluminum oxide) and is not affected by the tunneling oxygen layer. Therefore, a larger tower base structure can be provided here to facilitate better deposition of the passivation layer.

[0133] Optionally, a prismatic structure is provided on the first step sidewall 3. In addition to a complete textured structure, other structures may also be formed on the first step sidewall 3, such as a raised strip structure, or a prismatic structure extending from the bottom to the top of the first step structure. This prismatic structure can increase the surface area of the first step sidewall 3, thereby increasing the adhesion of the first step sidewall 3 after lamination and preventing delamination at the edges of the cell.

[0134] like Figure 6 As shown, in other embodiments, the second doped layers 16 are spaced apart along the first direction on the second surface. When the second region 2 is provided with the second type of pyramid structure, a third type of pyramid structure is provided in the space between two adjacent second doped layers 16 on the second surface. Optionally, the third type of pyramid structure is smaller than the second type of pyramid structure. The base of the second type of pyramid is larger in volume and surface area, resulting in a better reflection and scattering effect of the pyramid-like top on light.

[0135] In some possible embodiments, the depth range of the spacing region between adjacent second doped layers is the same as the step depth range of the first step structure. The depth of the spacing region can be greater than or equal to the thickness of the tunneling oxygen layer and the second doped layer, plus the thickness of the inner expansion layer, so that the depth of the recess on the front and back sides can be basically consistent, thereby allowing the front and back sides to withstand relatively consistent pressure and ensuring the mechanical properties of the cell.

[0136] In some embodiments, a fourth type of pyramid structure is provided on the first step sidewall 3. The size range of the fourth type of pyramid structure can be the same as or different from the size range of the third type of pyramid structure. This technical solution helps the first step sidewall 3 to have a good light trapping effect, further improving the utilization rate of light by the solar cell. It is understood that in addition to forming a complete pyramid-like structure or an incomplete pyramid-like structure on the first step sidewall 3, other structures may also be formed, such as a raised strip structure or a prismatic structure extending from the bottom to the top of the first step structure.

[0137] The shapes of the third type of pyramid structure and the fourth type of pyramid structure can refer to the shape of the first type of pyramid structure, and will not be described in detail here.

[0138] Optionally, the size range of the fourth type of pyramid structures may be the same as the size range of the first type of pyramid structures.

[0139] In some embodiments, along the first step sidewall 3 (eg, Figure 2 In the extension direction (shown in FIG. 1 ), the first stepped sidewall 3 is wavy or curved. The extension direction of the first stepped sidewall 3 can be the same as the extension direction of the second region, that is, the first stepped sidewall 3 extends along the second direction. This technical solution can increase the overall extension length of the first stepped sidewall 3, which helps improve the adhesion of the first stepped sidewall 3 after lamination, thereby improving the stability of the solar energy. Of course, the first stepped sidewall 3 can also extend in a straight line along its extension direction, which is not limited here.

[0140] In some embodiments, the first stepped structure can extend continuously. Specifically, the first stepped structure can extend continuously along the first direction. With this technical solution, the first doped layer 12 at any position in the first region 1 can be located farther away from the cutting position, thereby minimizing the passivation effect of the first doped layer 12 near the edge of the second region 2 and further reducing carrier recombination.

[0141] In other embodiments, the first step structure extends discontinuously. Specifically, the first step structure may extend discontinuously along the first direction, that is, the first step structure is disposed intermittently.

[0142] In some embodiments, if the first step structure is too wide, the area of the first doped layer 12 will be reduced, affecting the current collection efficiency of the first doped layer 12; if the first step structure is too narrow, the transmission performance of the doped layer during the laser cutting process cannot be effectively cut off, and the passivation effect will be greatly affected, and the passivation effect will be significantly reduced. In order to take into account the above two aspects, in this technical solution, the width of the first step structure is 20μm to 500μm in the direction perpendicular to the first cutting side. In other words, the width of the first step structure is 20μm to 500μm in the second direction. In this technical solution, the width of the first step structure is set within a reasonable range of 20μm to 500μm to prevent the area of the first doped layer 12 from being reduced, to ensure the current collection efficiency of the first doped layer 12, and to avoid a significant reduction in the passivation effect of the first doped layer 12 during the laser cutting process, thereby ensuring a higher power generation efficiency.

[0143] Illustratively, the width of the first stepped structure is 20 μm, 50 μm, 100 μm, 150 μm, 200 μm, 250 μm, 300 μm, 550 μm, 400 μm, 450 μm or 500 μm, etc.

[0144] It can be understood that the width of the first stepped structure is 20 μm to 500 μm, and accordingly, the width of the entire second region is 40 μm to 1000 μm.

[0145] In some embodiments, the first step sidewall 3 is parallel to the thickness direction of the semiconductor substrate 10. Specifically, the first step sidewall 3 can be arranged perpendicular to the first surface of the semiconductor substrate 10. Such an arrangement is conducive to simplifying the processing technology and improving processing efficiency.

[0146] In other embodiments, referring to Figure 10 The first step sidewall 3 forms an angle with the thickness direction of the semiconductor substrate 10. Specifically, the first step sidewall 3 gradually tilts from bottom to top toward the first region 1, forming a slope. This configuration creates a smooth transition from the first step structure to the upper surface of the first doped layer 12, avoiding stress concentration near the first step sidewall 3 during the lamination process. This, in turn, prevents stress concentration from causing hidden cracks in the cell, thereby improving product yield. The angle between the first step sidewall 3 and the thickness direction of the semiconductor substrate 10 can be 15°, 30°, 45°, 60°, etc.

[0147] In some embodiments, multiple surfaces of the semiconductor substrate 10 are cut sides. For example, after a whole cell is cut into four slices, the two middle cell slices have two cut sides. Figure 10As shown, in this technical solution, the semiconductor substrate 10 also includes a second cut side surface, which is the side opposite the first cut side surface. The first surface also includes a third region adjacent to the second cut side surface, and the first region 1 is located on the side of the third region facing away from the second cut side surface. That is, the third region is closer to the first cut side surface than the first region 1, and is located between the first region 1 and the second cut side surface. Along the extension direction of the third region, the third region includes an edge region and a middle region. Both the edge region and the middle region of the third region include a step structure. The step depth of the step structure in the edge region of the third region is greater than the step depth of the step structure in the middle region of the third region, and the bottom wall height of the step structure in the middle region of the third region is lower than the height of the first doped layer. During the cutting process to form the second cut surface, the laser cutting position is further away from the first doped layer 12, thereby reducing the impact of the laser on the first doped layer 12, avoiding the formation of a large number of dangling bonds and carrier recombination, and reducing the impact of the passivation layer on the passivation effect of the cut area after the step structure etches away the first doped layer. In other words, the present embodiment can improve the passivation effect of half-cell cells with cut surfaces on both sides.

[0148] It should be noted that the third region may have the same implementation modes as the aforementioned second region, which will not be described in detail here for the sake of convenience.

[0149] In some embodiments, a step depth of the step structure in the middle region of the second region is the same as a step depth of the step structure in the middle region of the third region.

[0150] In other embodiments, the step depth of the step structure at the edge of the second region is the same as the step depth of the step structure at the edge of the third region. This can make the structures on both sides of the battery cell more consistent and the mechanical properties on both sides of the battery cell more balanced.

[0151] In some embodiments, the step width of the step structure in the middle area of the second region is the same as the step width of the step structure in the middle area of the third region. The width of the step structure in the second region refers to the size of the step structure in the direction perpendicular to the first cutting side; the width of the step structure in the third region refers to the size of the step structure in the direction perpendicular to the second cutting side. In this way, the width of the step structure can be set separately according to the laser energy for forming the first cutting side and the laser energy for forming the second cutting side, which helps to make the passivation effect of the cutting areas on both sides more consistent. In addition, if the first step structure or the second step structure is too wide, it will lead to a reduction in the area of the first doping layer 12, a reduction in the carrier collection efficiency, and a reduction in the mechanical properties of the solar cell.

[0152] In some other embodiments, the step width of the step structure in the edge region of the second region is the same as the step width of the step structure in the edge region of the third region.

[0153] It should be noted that the same width or depth of the step structures in the aforementioned embodiments can be understood as being the same within a range of error.

[0154] In some embodiments, the extended shape of the step sidewall 3 in the second region is the same as the extended shape of the step sidewall in the third region. The step structures on both sides can be completed in the same process flow, thereby improving processing efficiency.

[0155] In some embodiments, the edge region has a first chamfer structure, the sidewall edge between the first region and the second side has a second chamfer structure, the second side is a plane parallel to the first cutting side, and the size of the first chamfer structure is less than or equal to the size of the second chamfer structure. This configuration can avoid cracking at the corners of the cell when cutting the edge region, thereby improving product yield. In addition, setting chamfers of different sizes can be used to identify the cutting edge.

[0156] In actual application, the material of the semiconductor substrate 10 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs). Obviously, in terms of conductivity type, the semiconductor substrate 10 can be an intrinsic conductive substrate, an n-type conductive substrate or a p-type conductive substrate. Optionally, the semiconductor substrate 10 is a p-type conductive substrate or an n-type conductive substrate. Compared with the intrinsic conductive substrate, the p-type conductive substrate or the n-type conductive substrate has better conductivity, so that the final solar cell has a lower body resistivity, thereby improving the efficiency of the solar cell.

[0157] For example, the semiconductor substrate 10 may be a p-type substrate or an n-type substrate. The n-type substrate has the advantages of long minority carrier lifetime, no light decay, and good weak light performance.

[0158] The first doped layer 12 may include doped polycrystalline silicon. Doped polycrystalline silicon layers have enhanced carrier transport properties. Therefore, when the first doped layer 12 is a doped polycrystalline silicon layer, the carrier transport efficiency is higher, which helps improve the photoelectric conversion efficiency of the solar cell. Of course, the first doped layer 12 may also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0159] The second doping layer 16 may include doped polycrystalline silicon, or the second doping layer 16 may also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0160] In some embodiments, a first interface layer 11 is provided between the first doped layer 12 and the semiconductor substrate 10, and a second interface layer 15 is provided between the second doped layer 16 and the semiconductor substrate 10. The passivation contact structure composed of the interface layer and the doped layer has an excellent interface passivation effect and can achieve selective collection of carriers, reduce the carrier recombination rate in the region where the doped layer is formed on the surface of the semiconductor substrate 10, and further improve the photoelectric conversion efficiency of the solar cell. The material and thickness of the first interface layer 11 can be set according to the material of the first doped layer 12 and actual requirements, and the material and thickness of the second interface layer 15 can be set according to the material of the second doped layer 16 and actual requirements, and are not specifically limited here.

[0161] It should be noted that, referring to Figure 6 , the solar cell of the embodiment of the present application may not be provided with the first interface layer.

[0162] For example, the first doped layer 12 may be a doped polysilicon layer, the first interface layer 11 may be a tunneling oxide layer, the second doped layer 16 may be a doped polysilicon layer, and the second interface layer 15 may be a tunneling oxide layer.

[0163] The materials of the first doping layer 12 and the second doping layer 16 can be silicon (Si), germanium (Ge), silicon carbide (SiCx), or gallium arsenide (GaAs). In terms of conductivity type, the first doping layer 12 can be an n-type doping layer, and the second doping layer 16 can be a p-type doping layer; alternatively, the first doping layer 12 can be a p-type doping layer, and the second doping layer 16 can be an n-type doping layer.

[0164] In some possible embodiments, reference Figures 3 to 10 The first passivation layer is provided on the step sidewalls and the step bottom wall of the first step structure.

[0165] For example, in the case where the groove 31 is a non-through groove, Figure 3 In the non-through shallow trench solution shown, the first passivation layer 13 is disposed on the step sidewalls and the step bottom wall of the first step structure in the middle region 21 of the second region.

[0166] For example, refer to Figure 4 and Figure 9 ,correspond Figure 4 In the through-trench solution shown, the first passivation layer 13 is provided on the sidewalls and bottom wall of the first step structure. This first passivation layer, located on the bottom wall of the first step structure, protects the edge of the first step structure near the second step structure. This first passivation layer on the bottom wall of the first step provides a significant passivation effect, especially when the second step structure is formed using a lossy laser.

[0167] In some embodiments, reference Figures 3 to 10 The solar cell also includes a second passivation layer 19, which is disposed on the edge of the first region 1 near the second region 2, the second region 2, and the first cut side surface. The second passivation layer 19 is located on the side of the first passivation layer 13 facing away from the semiconductor substrate 10. The second passivation layer 19 can protect the second region 2 and the first cut side surface of the cell, and in particular, it can bypass the edge from the first cut side surface to the second region 2, as well as the sidewall edge from the second region 2 to the first region, enabling sufficient passivation, reducing recombination sites, and improving the photoelectric conversion efficiency of the cell. The technical features of the second passivation layer 19, such as the number of layers and material, can refer to the description of the first passivation layer 13. For example, the second passivation layer 19 can be a single-layer structure, and the single-layer structure is an aluminum oxide layer.

[0168] For example, combining the above Figure 3 In the embodiment shown, the second passivation layer 19 can protect the second area 2 and the first cutting side of the battery cell, especially the bottom wall of the step structure that bypasses the first cutting side to the middle area of the second area, and the side wall of the step structure that bypasses the middle area of the second area to the edge of the first area, as well as the bottom wall of the step structure that bypasses the first cutting side to the edge area of the second area, and the side wall of the step structure that bypasses the edge area of the second area to the edge of the first area.

[0169] For example, combining the above Figure 4 and Figure 9 In the embodiment shown, the second passivation layer 19 can protect the second region 2 and the first cut side of the cell, especially can bypass the edge from the first cut side to the bottom wall of the second step structure, the edge from the side wall of the second step structure to the bottom wall of the first step structure, and the edge from the side wall of the first step structure to the first region, and can fully passivate, reduce the recombination sites, and improve the photoelectric conversion efficiency of the cell.

[0170] In other embodiments, Figure 6-Figure 8As shown, a third passivation layer 17 is provided on the second surface, and a second passivation layer 19 is provided on the first cut side surface. The second passivation layer 19 extends to the edge of the second surface and is located on the side of the third passivation layer 17 facing away from the semiconductor substrate 10. The third passivation layer 17 not only protects the second surface of the cell, preventing moisture and oxygen from penetrating into the interior of the cell, thereby extending the service life of the solar cell, but also acts as an anti-reflection layer, improving the absorption and utilization efficiency of light. The technical features of the third passivation layer 17, such as the number of layers and material, can refer to the description of the first passivation layer 13. For example, the third passivation layer 17 can have a single-layer structure, such as a silicon nitride layer. The second passivation layer can passivate the first cut side surface and the back surface in the same step, thereby further improving the passivation effect and saving process steps. Alternatively, the second passivation layer can wrap around the edge of the first area of the first surface and the edge of the second surface in the same step, thereby further improving the passivation effect and saving process steps.

[0171] It should be noted that the second passivation layer on the first cut side surface may be the same passivation layer as that in the aforementioned embodiment, that is, the second passivation layer on the first cut side surface may be passivated toward both the front and back surfaces at the same time.

[0172] The present application also provides another solar cell, such as Figure 11 As shown, in some embodiments, as Figure 11 As shown, the shallow grooves at the edge of the second region can also be configured as Y-shaped grooves. This configuration can avoid cracking at the corners of the cell when cutting the edge region, thereby improving product yield. It is understood that after cutting along the Y-shaped grooves, the edges of the cell are formed into chamfers.

[0173] In some embodiments, the edge region has a first chamfer structure, the sidewall edge between the first region and the second side has a second chamfer structure, the second side is a plane parallel to the first cutting side, and the size of the first chamfer structure is less than or equal to the size of the second chamfer structure. This configuration can avoid cracking at the corners of the cell when cutting the edge region, thereby improving product yield. In addition, setting chamfers of different sizes can be used to identify the cutting edge.

[0174] Figure 12 Schematic diagram of a component in an embodiment of the present application is shown. Figure 12 As shown, an electrical connector is provided between the adjacent first solar cell 121 and the second solar cell 122. The first solar cell 121 is the solar cell involved in the above-mentioned embodiments. The connection method of the electrical connector is as follows Figure 12As shown, from the first surface and the second side surface of the first solar cell 121, and then through the second surface of the second solar cell, the second side surface is the side surface opposite to the first cutting surface. Wherein, the starting end of the electrical connector can be at a distance (such as Figure 12 The width of the step structure in the middle region is greater than the width of the step structure in the middle region. Considering that the starting end of the electrical connector may have burrs or other protrusions, the starting end of the electrical connector is set at a certain distance from the edge. This will not damage the passivation layer in the cutting area and ensure the passivation effect in the cutting area.

[0175] Optionally, the second solar cell 122 may also be the solar cell involved in the aforementioned embodiments.

[0176] Optionally, the second side is a non-cutting side. Figure 12 As shown, one side of the first solar cell 121 is a cut surface, and the other side is a non-cut surface. Thus, the electrical connector starts from the front side near the cut surface and extends around to the non-cut surface, squeezing the non-cut side. Compared to the electrical connector extending from the cut side with a stepped structure and squeezing the cut side, this embodiment of the application can avoid affecting the mechanical properties of the solar cell.

[0177] It can be understood that the second side surface may also be a cutting surface, for example, it may be the aforementioned second cutting side surface.

[0178] It is also understood that the electrical connector may be a soldering ribbon.

[0179] In some possible embodiments, the distance between the starting end of the electrical connector and the edge of the first region (ie, the boundary between the first region and the second region) is greater than or equal to 1 mm.

[0180] The embodiment of the present invention further provides a first method for manufacturing a solar cell, which can be used to prepare the solar cell described in any of the above embodiments. The method for manufacturing a solar cell includes the following steps:

[0181] S1 : providing a semiconductor substrate 10 , wherein the semiconductor substrate 10 includes a first surface and a second surface opposite to each other, wherein the first surface includes a first region 1 and a second region 2 .

[0182] The first region 1 is used to form a first type of pyramid structure.

[0183] Prior to this step, in some embodiments, the semiconductor substrate 10 may be placed in a polishing and cleaning machine to remove the cut damage layer of the semiconductor substrate 10 using a polishing liquid. Furthermore, in this step, the morphology of the first and second surfaces of the semiconductor substrate 10 after polishing and cleaning may be adjusted by controlling parameters such as temperature, time, cleaning liquid type, and cleaning liquid concentration. It should be noted that in some examples, the polishing and cleaning step may be omitted.

[0184] S2: forming a first type of pyramid structure on the first surface;

[0185] In this step, a first type of pyramid structure can be formed on the first surface by texturing.

[0186] S3: forming a first doped layer 12 and a first doped silicon glass layer on the first surface having the first type of pyramid structure.

[0187] The first doped layer 12 can be additionally formed on the first surface of the semiconductor substrate 10 by deposition technology, or formed in the semiconductor substrate 10 by diffusion, ion implantation, etc. During the formation of the first doped layer 12, a first doped silicon glass layer is simultaneously formed.

[0188] It should be noted that, when the solar cell further includes a first interface layer 11 , in this step, deposition and etching processes may be used to form the first interface layer 11 before forming the first doping layer.

[0189] S4: using laser irradiation to reduce the density of the first doped silica glass layer in the second region 2 .

[0190] In this step, the first doped silicon glass layer in the second region 2 is irradiated with laser to reduce the density of the first doped silicon glass layer in the second region 2 , which is more conducive to the subsequent removal of the first doped silicon glass layer in the second region 2 .

[0191] S5: groove-polishing the second surface and removing a portion of the first doped silicon glass layer in the second region 2 , and forming a groove in the second region 2 that is concave toward the second surface.

[0192] In this step, the first doped silica glass layer in the second region 2 can be removed by etching with an etchant. If the first doped silica glass layer is formed on both the second surface and the side surfaces, a chain conveyor is first used to remove the first doped silica glass layer from both the second surface and the side surfaces. The cell is then polished using a trough-type machine to polish the second surface. After removing the first doped silica glass layer in the second region 2, a groove is formed in the second region 2. This allows polishing and groove formation to occur in a single process step, allowing the polishing step to be reused for groove formation, saving process time.

[0193] S6: forming a second doping layer 16 on the second surface. The conductivity type of the second doping layer 16 is opposite to that of the first doping layer 12 .

[0194] The second doped layer 16 can be additionally formed on the second surface of the semiconductor substrate 10 through a deposition technique, or can be formed within the semiconductor substrate 10 through diffusion, ion implantation, or other methods. The second doped layer 16 can be disposed entirely or partially on the second surface. When the second doped layer 16 is partially disposed on the second surface, the second doped layer 16 can be spaced apart along the first direction and distributed on the second surface. The second doped layer 16 can extend along the second direction and can be distributed in a stripe shape, a "P"-shaped shape, or other similar shapes.

[0195] It should be noted that, when the solar cell further includes a second interface layer 15 , in this step, deposition and etching processes may be used to form the second interface layer 15 before forming the second doping layer.

[0196] When the second doped layer 16 is a doped polysilicon layer and the second interface layer 15 is a tunneling oxide layer, a tunneling oxide layer and an intrinsic polysilicon layer can be formed in sequence on the second surface, and then the intrinsic polysilicon layer is diffused to obtain a doped polysilicon layer. In the process of forming the doped polysilicon layer, a second doped glass silicon layer can be formed simultaneously.

[0197] S7: The second doped silica glass layer on the second surface is removed, and a first textured structure or a second-type pyramid structure is formed in the groove. Along the thickness direction of the semiconductor substrate, the bottom wall of the groove is lower than the height of the first doped layer. After this step, the remaining first doped silica glass layer and the entire second doped silica glass layer on the first surface can be simultaneously removed.

[0198] In step S7, the first doped silicon glass layer on the front side is partially removed using a chain-type etching process, and then the entire first doped silicon glass layer in the groove is completely removed using a trench-type etching process. In other words, multiple cleanings are required to remove the thicker first doped silicon glass layer in the groove.

[0199] S8 : forming a first electrode 14 on the first doping layer 12 , and forming a second electrode 18 on the second doping layer 16 .

[0200] The first electrode 14 and / or the second electrode 18 can be formed using processes such as screen printing, electroplating, sputtering, or evaporation. The first electrode 14 is electrically connected to the first doped layer 12 to conduct the current collected by the first doped layer 12, and the second electrode 18 is electrically connected to the second doped layer 16 to conduct the current collected by the second doped layer 16. The first electrode 14 and the second electrode 18 can be made of silver, copper, aluminum, or alloys thereof. The first electrode 14 and the second electrode 18 can be the same or different.

[0201] S9: forming a groove in an edge region of the second region, wherein a recessed depth of the groove is greater than a recessed depth of the groove.

[0202] The second region includes a middle region and the edge region along the direction in which the second region extends. In this step, before cutting the cell, a groove can be formed along the edge of the second region of the entire cell. The groove's depth is greater than the groove's depth. This thins the cell structure to a certain extent along the cutting direction. Subsequently, non-destructive laser cutting, water spraying, and other methods can be used to automatically disconnect the cutting line, completing the cut. This cutting method offers high efficiency and accuracy, ensuring the quality of the finished product.

[0203] It is understandable that in S9 , grooves may be formed in the edge region by laser.

[0204] In some embodiments, forming the groove in the edge region of the second region using a laser includes: forming the groove in the edge region within the groove.

[0205] In this case, the groove may be a through groove. When the through groove is formed, the requirement for laser alignment can be lowered, thereby reducing the complexity of the process.

[0206] S10: cutting the semiconductor substrate 10 along the grooves to obtain a plurality of solar cells.

[0207] Specifically, a laser can be used to cut the semiconductor substrate 10 along the groove to form multiple solar cells. The grooves after cutting form step structures on the two solar cells respectively. Along the thickness direction of the semiconductor substrate, the height of the bottom wall of the step structure is lower than the height of the first doped layer, which makes it easier to split the cell from the edge area. The bottom wall height of the step structure in the middle area is lower than the height of the first doped layer, which is equivalent to the thickness of the cell along the splitting direction being partially or completely thinned, thereby further reducing the difficulty of splitting. In addition, the bottom wall of the step structure in the middle area close to the cutting surface is lower than the height of the first doped layer 12, and the position of the splitting cut is farther away from the first doped layer 12 during the cutting process. Since more dangling bonds are formed during the cutting process, the further distance from the first doped layer 12 can prevent carriers from approaching the cutting area, reduce carrier recombination, and improve the photoelectric conversion efficiency. In addition, in the embodiment of the present application, while reusing the process of polishing the back side, the first doped silicon glass layer in the groove is cleaned for the first time, saving process steps and reducing process costs.

[0208] In some embodiments, S6 forms a second doped layer 16 on the second surface, including: S61 forming a second doped layer 16 and a second doped glass silicon layer on the second surface; S62 using laser irradiation to reduce the density of the second doped glass silicon layer in the gap area between two adjacent second doped layers 16; S63 removing all second doped glass silicon layers, and forming a second texture structure in the gap area between two adjacent second doped layers 16. Specifically, in this technical solution, a second doped glass silicon layer is formed while forming the second doped layer 16, and the second doped glass silicon layer is irradiated at intervals by laser irradiation to reduce the density and intervals of the second doped glass silicon layer, which is conducive to subsequent removal. The second doped glass silicon layer is removed by etching with a corrosive liquid, and a second texture structure is formed in the gap area between two adjacent second doped layers 16, and the first texture structure is formed in the groove. In addition, while removing the second doped glass silicon layer, the remaining first doped glass silicon layer on the first surface can be removed together, and specifically, chain cleaning and slot cleaning methods can be used. This technical solution forms a second textured structure within the spacing region of the second surface, which improves light trapping on the light-facing surface, reduces light reflectivity, and also reduces lateral carrier recombination. The second textured structure can be a tower-based structure, and the tower-based structure formed within the spacing region can have different dimensions from the tower-based structures formed within the second surface, side surfaces, and grooves of the semiconductor substrate 10.

[0209] In some embodiments, S6 forms a second doped layer 16 on the second surface, including: S61 forms a second doped layer 16 and a second doped glass silicon layer on the second surface; S62 uses laser irradiation to reduce the density of the second doped glass silicon layer in the spacing area between two adjacent second doped layers 16; S63 removes the second doped glass silicon layer, and forms a pyramid-like structure in the spacing area and groove between two adjacent second doped layers 16.

[0210] The present application also provides a second method for manufacturing a solar cell. The method can be used to manufacture the solar cell described in any of the above embodiments. The method comprises the following steps:

[0211] S1 ′: providing a semiconductor substrate 10 , wherein the semiconductor substrate 10 includes a first surface and a second surface opposite to each other, wherein the first surface includes a first region 1 and a second region 2 .

[0212] The description of step S1' can refer to the above description of step S1, which will not be repeated here.

[0213] S2': forming a first type of pyramid structure on the first surface.

[0214] The step S2' can refer to the description of the above step S2, which will not be repeated here.

[0215] S3 ′: forming a first doped layer 12 and a first doped silicon glass layer on the first surface having the first type of pyramid structure.

[0216] The step S3' can refer to the description of the above step S3, which will not be repeated here.

[0217] S4 ′: forming a second doped layer 16 and a second doped silicon glass layer on the second surface. The conductivity type of the second doped layer 16 is opposite to that of the first doped layer 12 .

[0218] The second doped layer 16 can be additionally formed on the second surface of the semiconductor substrate 10 via a deposition technique, or can be formed within the semiconductor substrate 10 via diffusion, ion implantation, or other methods. A second doped silicon glass layer is formed simultaneously with the formation of the second doped layer 16. The second doped layer 16 can be locally located on the second surface, or can be spaced apart along the first direction. The second doped layer 16 can extend along the second direction, or can be distributed in a stripe shape, a "P"-shaped shape, or other similar shapes.

[0219] It should be noted that, when the solar cell further includes a second interface layer 15 , in this step, deposition and etching processes may be used to form the second interface layer 15 before forming the second doping layer.

[0220] When the second doped layer 16 is a doped polysilicon layer and the second interface layer 15 is a tunneling oxide layer, a tunneling oxide layer and an intrinsic polysilicon layer can be formed in sequence on the second surface, and then the intrinsic polysilicon layer is diffused to obtain a doped polysilicon layer. In the process of forming the doped polysilicon layer, a second doped glass silicon layer can be formed simultaneously.

[0221] S5 ′: using a laser to reduce the density of the first doped silica glass layer in the second region 2 and the second doped silica glass layer in the interval.

[0222] In the same step, laser irradiation reduces the density of the first doped silica glass layer in the second region 2 and the second doped silica glass layer in the gap region between the adjacent second doped layer 16. Specifically, the first doped silica glass layer in the second region 2 can be lasered first, and then the cell can be turned over and the second doped silica glass layer in the gap region can be lasered. Alternatively, the second doped silica glass layer in the gap region can be lasered first, and then the cell can be turned over and the first doped silica glass layer in the second region 2 can be lasered.

[0223] S6': remove the first doped silicon glass layer and the second doped silicon glass layer, and form a groove recessed toward the second surface in the second region 2, and form a first texture structure or a second type pyramid structure in the groove, and along the thickness direction of the semiconductor substrate, the height of the bottom wall of the groove is lower than the height of the first doped layer.

[0224] In this step, the first and second doped silica glass layers can be removed by etching with an etching solution, and a groove recessed toward the second surface is formed in the second region 2, thereby forming a first texture structure or a second pyramid structure in the second region 2. Furthermore, the removal of the doped silica glass layer and the formation of the groove are accomplished in a single process step, and the removal operation is reused when forming the groove, thus saving process steps.

[0225] S7′: forming a first electrode on the first doped layer, and forming a second electrode on the second doped layer;

[0226] S8': forming a groove in the edge area of the second region, wherein the depression depth of the groove is greater than the depression depth of the groove; the second region includes a middle region along the extension direction of the second region and the edge region.

[0227] It is understandable that in S8 , grooves may be formed in the edge region by laser.

[0228] S9 ′: cutting the semiconductor substrate 10 along the grooves to obtain a plurality of solar cells, forming a first step structure in the second region 2 of the solar cell, and along the thickness direction of the semiconductor substrate 10 , the height of the bottom wall of the first step structure is lower than the height of the first doping layer.

[0229] The step S9' can refer to the description of the above step S10, which will not be repeated here.

[0230] The main difference between the above-mentioned second method for manufacturing solar cells and the first method for manufacturing solar cells is that in the same step, laser irradiation is performed on the first doped silicon glass layer in the second region 2 and the second doped silicon glass layer in the spacing region between the adjacent second doped layers 16, which is beneficial to the subsequent removal of the doped silicon glass layer in the second region 2 and the spacing region, thereby avoiding the need to add a separate laser step, that is, reusing the laser step that was originally intended to be used to make the spacing region on the back.

[0231] It should be noted that, in the embodiment of the present application, in step S5', the spacing area can also be made on the front side, or the spacing area can be made on both the front side and the back side, and the present application does not limit this.

[0232] In some embodiments, during the removal of the second doped glass silicon layer, a second textured structure is formed in the space between two adjacent second doped layers 16. Specifically, wet etching can be used to remove the second doped glass silicon layer and to etch a portion of the semiconductor substrate 10 to form the second textured structure in the space between the adjacent second doped layers 16. This helps to improve the light trapping effect of the light-facing surface and reduce light reflectivity.

[0233] In some embodiments, during the process of removing the second doped glass silicon layer, a third type of pyramid structure is formed in the gap area between two adjacent second doped layers 16. Specifically, the second doped glass silicon layer can be removed by wet etching, and a portion of the semiconductor substrate 10 can be etched to form a third type of pyramid structure in the gap area, which is beneficial to improving the light trapping effect of the light-facing surface and reducing the reflectivity of light. The base of the pyramid-like tower is large in volume and surface area, which is beneficial to ensuring the passivation effect of the passivation layer covering the base of the pyramid-like tower, while the top of the pyramid-like tower has a better reflection and scattering effect on light. In this technical solution, steps S61'-S62' are the same as S61-S62 in the above technical solution, and the specific description of S61 and S62 can be referred to above. In step S63', a chain cleaning method can be used to remove part of the second doped glass silicon layer, and then the pyramid-like structure is formed in the gap area and the groove 4 by texturing. The base of the pyramid-like tower has a large volume and a large surface area, which is conducive to ensuring the passivation effect of the passivation layer covering the base of the pyramid-like tower, while the top of the pyramid-like tower has a better reflection and scattering effect on light.

[0234] In the above two solar cell manufacturing methods, before step S8 or S7', the following steps may also be included: forming a first passivation layer 13 on the first surface, the first passivation layer 13 being located on a side of the first doped layer 12 facing away from the semiconductor substrate 10. Forming a third passivation layer 17 on the second surface, the third passivation layer 17 being located on a side of the second doped layer 16 facing away from the semiconductor substrate 10. In this technical solution, the first electrode 14 is electrically connected to the first doped layer 12 through the first passivation layer 13, and the second electrode 18 is electrically connected to the second doped layer 16 through the third passivation layer 17.

[0235] After step S10 or S9', the solar cell manufacturing method further includes forming a second passivation layer 19 on the edge of the first region 1 close to the second region 2, the second region 2 and the first cut side, and the second passivation layer 19 is located on the side of the first passivation layer 13 away from the semiconductor substrate 10.

[0236] The structures, materials and functions of the first passivation layer 13 , the second passivation layer 19 and the third passivation layer 17 can be referred to above and are not described in detail herein.

[0237] In some embodiments, the laser can use a green laser, and the laser spot diameter or spot width is 105μm to 410μm. Exemplarily, the laser spot diameter or spot width is 105μm, 120μm, 150μm, 200μm, 220μm, 250μm, 280μm, 300μm, 320μm, 350μm, 380μm, 400μm or 410μm, etc.

[0238] The frequency of the laser is 200KHz to 800KHz. For example, the frequency of the laser is 200KHz, 250KHz, 300KHz, 350KHz, 400KHz, 450KHz, 500KHz, 550KHz, 600KHz, 650KHz, 700KHz or 8000KHz.

[0239] The power of the laser can be 50W to 150W. Exemplarily, the power of the laser is 50W, 55W, 60W, 65W, 70W, 75W, 80W, 85W, 90W, 95W, 100W, 105W, 110W, 115W, 120W, 125W, 130W, 140W or 1500W, etc.

[0240] The power density of the laser is 100m / cm2 to 800m / cm2. For example, the power density of the laser is 100m / cm2, 200m / cm2, 300m / cm2, 400m / cm2, 500m / cm2, 600m / cm2, 700m / cm2 or 800m / cm2, etc.

[0241] During the laser irradiation process, the overlap rate of adjacent laser spots is 30% to 50%, for example, the overlap rate of adjacent laser spots is 30%, 35%, 40%, 45% or 50%.

[0242] The laser engraving speed is 20,000 mm / s to 40,000 mm / s. For example, the laser engraving speed is 20,000 mm / s, 22,000 mm / s, 25,000 mm / s, 27,000 mm / s, 29,000 mm / s, 30,000 mm / s, 32,000 mm / s, 35,000 mm / s, 38,000 mm / s, or 40,000 mm / s.

[0243] Of course, the laser used in the first method for manufacturing a solar cell and the laser used in the second method for manufacturing a solar cell may be different or the same, which is not limited here.

[0244] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0245] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate comprising a first surface and a second surface opposite to each other, a first cut side surface connecting the first surface and the second surface, the first surface comprising a first region and a second region adjacent to the first cut side surface; along an extension direction of the second region, the second region comprising an edge region and a middle region, the edge region and the middle region both comprising a step structure recessed toward the second surface, the step structure of the edge region of the second region having a greater step depth than the step structure of the middle region of the second region; A first doped layer is provided on the first region; along the thickness direction of the semiconductor substrate, the height of the bottom wall of the step structure in the middle region of the second region is lower than the height of the first doped layer; A first passivation layer is provided on a side of the first doped layer facing away from the semiconductor substrate and on the second region.

2. The solar cell according to claim 1, wherein The step structure in the middle area and the step structure in the edge area are connected to form a first step structure, and a second step structure is provided on the bottom wall of the step structure in the edge area.

3. The solar cell according to claim 1, wherein The step structure of the middle area is a first step structure, and the step structure of the edge area is a second step structure. The step depth of the second step structure is greater than the step depth of the first step structure.

4. The solar cell according to claim 2 or 3, characterized in that The first area is provided with a first type pyramid structure, the bottom wall of the first step structure in the second area is provided with a first texture structure, and the second surface is provided with a second texture structure. The one-dimensional size of the first texture structure is larger than the one-dimensional size of the second texture structure.

5. The solar cell according to claim 4, wherein The solar cell further includes a second doped layer provided on the second surface, the second doped layer has a conductivity type opposite to that of the first doped layer, and the entire second surface is provided with the second texture structure; or The solar cell further includes a second doping layer spaced apart on the second surface. The second doping layer has a conductivity type opposite to that of the first doping layer. The second texture structure is provided in the space between two adjacent second doping layers on the second surface.

6. The solar cell according to claim 2 or 3, characterized in that The solar cell further includes a second doped layer spaced apart from the second surface, the second doped layer having a conductivity type opposite to that of the first doped layer, the first region being provided with a first type pyramid structure, and the bottom wall of the first step structure in the second region being provided with a second type pyramid structure.

7. The solar cell according to claim 6, characterized in that One dimension of the first type of pyramid structure is greater than one dimension of the second type of pyramid structure; and / or The third type of pyramid structure is provided in the interval area between two adjacent second doping layers on the second surface, and one dimension of the third type of pyramid structure is smaller than one dimension of the second type of pyramid structure; and / or The depth range of the spacing region between two adjacent second doping layers on the second surface is the same as the step depth range of the first stepped structure.

8. The solar cell according to any one of claims 2 to 7, characterized in that Along the extension direction of the first step sidewall, the first step sidewall is wavy or curved; and / or, Along the extension direction of the side wall of the first step, the first step structure extends continuously or discontinuously; and / or, Along a direction perpendicular to the first cutting side surface, a width of the first step structure is 20 μm to 500 μm.

9. The solar cell according to any one of claims 2 to 8, characterized in that The sidewall of the first step is parallel to the thickness direction of the semiconductor substrate; or, An angle is formed between the sidewall of the first step and the thickness direction of the semiconductor substrate. Preferably, the angle is 15° to 60°.

10. The solar cell according to any one of claims 2 to 9, characterized in that The first passivation layer is provided on the step sidewalls and the step bottom wall of the first step structure.

11. The solar cell according to claim 10, characterized in that A second passivation layer is provided on the edge of the first region close to the second region, the second region and the first cut side surface. The second passivation layer is located on a side of the first passivation layer facing away from the semiconductor substrate.

12. The solar cell according to claim 4, wherein The one-dimensional size of the first texture structure is 15um to 50um, and the one-dimensional size of the second texture structure is 2um to 20um.

13. The solar cell according to any one of claims 2 to 12, characterized in that The step width of the first step structure is greater than the width of the second step structure.

14. The solar cell according to any one of claims 2 to 13, characterized in that Along the thickness direction of the semiconductor substrate, the step depth of the middle region of the first step structure is 2 μm to 10 μm; and / or The step depth of the edge region of the second step structure is 30%H to 100%H, where H is the thickness of the solar cell.

15. The solar cell according to any one of claims 1 to 14, characterized in that A third passivation layer is provided on the second surface, a second passivation layer is provided on the first cut side surface, and the second passivation layer extends to an edge region of the second surface and is located on a side of the third passivation layer away from the semiconductor substrate.

16. The solar cell according to any one of claims 1 to 15, characterized in that The semiconductor substrate also includes a second cutting side surface, which is arranged opposite to the first cutting side surface. The first surface also includes a third area adjacent to the second cutting side surface, and the first area is located on the side of the third area away from the second cutting side surface; along the extension direction of the third area, the third area includes an edge area and a middle area, and the edge area and the middle area both include a step structure. The step depth of the step structure of the edge area of the third area is greater than the step depth of the step structure of the middle area of the third area, and the height of the bottom wall of the step structure in the middle area of the third area is lower than the height of the first doping layer.

17. The solar cell according to claim 16, wherein: The step depth of the step structure in the middle area of the second area is the same as the step depth of the step structure in the middle area of the third area; and / or The step depth of the step structure in the edge region of the second region is the same as the step depth of the step structure in the edge region of the third region; and / or, The step width of the step structure in the middle area of the second area is the same as the step width of the step structure in the middle area of the third area; and / or The step width of the step structure in the edge region of the second region is the same as the step width of the step structure in the edge region of the third region.

18. A method for manufacturing a solar cell, characterized in that: include:: Providing a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a first region and a second region; Forming a first doped layer and a first doped silicon glass layer on the first surface; reducing the density of the first doped silicon glass layer in the second region by laser irradiation; groove polishing the second surface and removing a portion of the first doped silicon glass layer in the second region, thereby forming a groove in the second region that is concave toward the second surface; forming a second doped layer on the second surface, wherein the conductivity type of the second doped layer is opposite to that of the first doped layer; The second doped silicon glass layer on the second surface is removed, and along the thickness direction of the semiconductor substrate, the height of the bottom wall of the groove is lower than the height of the first doped layer; forming a first electrode on the first doped layer and forming a second electrode on the second doped layer; forming a groove in an edge region of the second region, wherein a recessed depth of the groove is greater than a recessed depth of the groove; The semiconductor substrate is sliced along the grooves to obtain a plurality of solar cells.

19. A method for manufacturing a solar cell, characterized in that: include:: Providing a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other, the first surface comprising a first region and a second region; Forming a first doped layer and a first doped silicon glass layer on the first surface; forming a second doped layer and a second doped silicon glass layer on the second surface, wherein the second doped layer has a conductivity type opposite to that of the first doped layer; Using laser to reduce the density of the first doped silicon glass layer in the second region and the second doped silicon glass layer in the interval; removing the first doped silicon glass layer and the second doped silicon glass layer, and forming a groove in the second region that is recessed toward the second surface, wherein the bottom wall of the groove has a height lower than that of the first doped layer along the thickness direction of the semiconductor substrate; forming a first electrode on the first doped layer and forming a second electrode on the second doped layer; forming a groove in an edge region of the second region, wherein a recessed depth of the groove is greater than a recessed depth of the groove; The semiconductor substrate is sliced along the grooves to obtain a plurality of solar cells.

20. A photovoltaic module, characterized in that: include: A plurality of battery strings connected in series and / or in parallel, the battery strings comprising: an electrical connector and a first solar cell and a second solar cell, the first solar cell being the solar cell according to any one of claims 1 to 17, or the solar cell obtained by the manufacturing method according to claim 18 or 19, the first solar cell and the second solar cell being connected by the electrical connector, the distance between the starting end of the electrical connector and the edge of the first region of the first solar cell being greater than the width of the step structure in the middle region of the second region, and the conductive member passing through the first surface and the second side surface of the first solar cell, and the second surface of the second solar cell, the second side surface being the side surface opposite to the first cut surface of the first solar cell, the edge of the first region being the boundary edge between the first region and the second region, preferably, the distance between the starting end of the electrical connector and the edge of the first region is greater than or equal to 1 mm.

21. The photovoltaic module according to claim 20, characterized in that The second side surface is a non-cutting surface.

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