Power failure data protection method and device, equipment, storage medium and product

Abstract

The invention provides a power failure data protection method and device, equipment, a storage medium and a product, applied to an RAID controller, the method comprises the steps that PCIe configuration spaces of all connected hard disks are read in the initialization stage, and at least one target hard disk conforming to a preset white list is screened; obtaining a base address register space mapped by the PMR of the target hard disk; verifying whether the total base address register space corresponding to all the target hard disks meets the total data volume of the cache; if yes, setting a backup enabling flag in the PCIe configuration space of the target hard disk to be in an enabled state, and enabling a power-down backup scheme; and when the RAID controller is in a power-down state, concurrently writing the cache data into a base address register space of the target hard disk, and backing up the cache data to the PMR, so that the hard disk controller stores the cache data of the PMR to a flash memory. Compared with a traditional scheme in which the capacity of a super capacitor is in direct proportion to the cost, the scheme does not need to depend on a high-capacity super capacitor, and the cost of the RAID storage system is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a power-off data protection method, device, equipment, storage medium, and product. Background Art

[0002] RAID technology significantly improves data read and write speeds by combining multiple physical hard drives into logical storage units, while also enhancing system fault tolerance through data redundancy. This technology is implemented by a RAID controller independent of the host system. Its built-in dedicated chip efficiently handles complex tasks such as data striping and parity checking, significantly reducing the burden on the host CPU. Furthermore, the RAID controller's integrated cache memory further enhances I / O performance. Most importantly, its power-loss protection prevents data loss caused by unexpected power outages, ensuring data integrity and improving storage system reliability.

[0003] The power-loss protection design of traditional RAID controllers is a key mechanism for ensuring data integrity during server power outages. This design relies primarily on two core components: supercapacitors and NAND Flash storage. When the server power supply is functioning normally, it provides power to the cache, enabling fast data reads and writes. However, if a server power outage occurs, the supercapacitor quickly takes over, providing power to the RAID controller card, NAND Flash, and cache, ensuring that data in the cache can be safely and quickly transferred to the NAND Flash for permanent data preservation.

[0004] The larger the cache to be backed up, the longer the data backup takes, and therefore the larger the supercapacitor capacity required. However, if the supercapacitor's power is insufficient to back up all the cached data, the unsaved data will be lost due to power outages. Furthermore, the price of a supercapacitor is proportional to its capacity, so a larger supercapacitor will undoubtedly increase the cost of the RAID storage system. Summary of the Invention

[0005] The present disclosure provides a power-off data protection method, device, equipment, storage medium and product to at least solve the above technical problems existing in the prior art.

[0006] According to a first aspect of the present disclosure, a power-off data protection method is provided, which is applied to a redundant array of independent disks (RAID) controller. The method includes:

[0007] During the initialization phase, the high-speed serial bus PCIe configuration space of all connected hard disks is read, and at least one target hard disk that meets the preset whitelist is selected;

[0008] Obtaining the base address register space mapped to the persistent memory region PMR of the target hard disk;

[0009] Verify whether the total base address register space corresponding to all target hard disks meets the total cache data capacity;

[0010] If the conditions are met, the backup enable flag in the PCIe configuration space of the target hard disk is set to enabled, and the power-off backup solution is enabled;

[0011] When the RAID controller is in a power-off state, the cache data is concurrently written into the base address register space of the target hard disk and backed up to the PMR, so that the hard disk controller stores the cache data of the PMR into the flash memory.

[0012] In one embodiment, the step of reading the PCIe configuration space of all connected hard disks and screening at least one target hard disk that meets a preset whitelist includes:

[0013] Read the magic number field in the PCIe configuration space of the hard disk;

[0014] The magic number field is compared with a preset whitelist to filter out at least one matching target hard disk.

[0015] In one possible implementation, obtaining the base address register space mapped by the PMR of the target hard disk includes:

[0016] Reading the base indication register field of the PMR capability register of the target hard disk;

[0017] The base address register space mapped by the PMR is obtained according to the base indication register field.

[0018] In one embodiment, the concurrently writing the cache data into the base address register space of the target hard disk includes:

[0019] Splitting the cache data into a plurality of data blocks by direct memory access transmission;

[0020] The data blocks are written in parallel into the base address register space mapped by the PMR of the target hard disk.

[0021] In one embodiment, the method further comprises:

[0022] Setting the storage data to PMR flag in the PCIe configuration space to a completion state, and triggering the target hard disk to start data persistence;

[0023] The target hard disk polls the store data to PMR flag, and if it is detected that the store data to PMR flag is in a completion state, writes the PMR data into the flash memory through the ONFI interface.

[0024] In one embodiment, the method further comprises:

[0025] After the target hard disk completes the persistent storage of the data, setting the storage completion flag in the PCIe configuration space to a completion state;

[0026] The RAID controller polls the storage completion flag, and if it is detected that the storage completion flag is in a completion state, turns off the capacitor switch.

[0027] According to a second aspect of the present disclosure, a power-off data protection device is provided, which is applied to a redundant array of independent disks (RAID) controller. The device includes:

[0028] A hard disk screening module is used to read the high-speed serial bus PCIe configuration space of all connected hard disks during the initialization phase and screen at least one target hard disk that meets the preset whitelist;

[0029] A base address acquisition module is used to obtain the base address register space mapped by the persistent memory area PMR of the target hard disk;

[0030] A verification module, used to verify whether the total base address register space corresponding to all target hard disks meets the total cache data capacity;

[0031] an enabling module, configured to set a backup enable flag in the PCIe configuration space of the target hard disk to an enabled state and enable a power-off backup solution if the total base address register space satisfies the total cache data volume;

[0032] A data writing module is used to concurrently write cache data into the base address register space of the target hard disk when the RAID controller is in a power-off state, and back it up to the PMR, so that the hard disk controller stores the cache data of the PMR into the flash memory.

[0033] In one embodiment, the hard disk screening module is specifically configured to:

[0034] Read the magic number field in the PCIe configuration space of the hard disk;

[0035] The magic number field is compared with a preset whitelist to filter out at least one matching target hard disk.

[0036] In one embodiment, the base address acquisition module is specifically configured to:

[0037] Reading the base indication register field of the PMR capability register of the target hard disk;

[0038] The base address register space mapped by the PMR is obtained according to the base indication register field.

[0039] In one embodiment, the data writing module is specifically configured to:

[0040] Splitting the cache data into a plurality of data blocks by direct memory access transmission;

[0041] The data blocks are written in parallel into the base address register space mapped by the PMR of the target hard disk.

[0042] In one embodiment, the device further includes a processing module configured to:

[0043] Setting the storage data to PMR flag in the PCIe configuration space to a completion state, and triggering the target hard disk to start data persistence;

[0044] The target hard disk polls the store data to PMR flag, and if it is detected that the store data to PMR flag is in a completion state, writes the PMR data into the flash memory through the ONFI interface.

[0045] In one embodiment, the processing module is further configured to:

[0046] After the target hard disk completes the persistent storage of the data, setting the storage completion flag in the PCIe configuration space to a completion state;

[0047] The RAID controller polls the storage completion flag, and if it is detected that the storage completion flag is in a completion state, turns off the capacitor switch.

[0048] According to a third aspect of the present disclosure, there is provided an electronic device, including:

[0049] at least one processor; and

[0050] a memory communicatively connected to the at least one processor; wherein,

[0051] The memory stores instructions that can be executed by the at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the method described in the present disclosure.

[0052] According to a fourth aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause the computer to execute the method described in the present disclosure.

[0053] According to a fifth aspect of the present disclosure, a computer program product is provided, comprising a computer program or instructions for causing a processor to implement the method when executing the computer program or instructions.

[0054] The present invention discloses a power-off data protection method, device, equipment, storage medium and product, which are applied to RAID controllers. Different from the traditional power-off protection design that relies on supercapacitors and Flash storage, this solution reads the hard disk PCIe configuration space during the initialization phase, screens the target hard disks that meet the preset whitelist; obtains the base address register space mapped by the target hard disk PMR; verifies whether the total base address register space can meet the total cache data volume; if so, enables the power-off backup solution; when power is off, the cache data is concurrently written to the target hard disk base address register space and backed up to the PMR, and finally stored in the flash memory by the hard disk controller. Compared with the traditional solution in which the supercapacitor capacity is proportional to the cost, this solution does not need to rely on large-capacity supercapacitors, reducing the cost of the RAID storage system. Secondly, by verifying whether the total base address register space of the target hard disk meets the total cache data volume, it ensures that there is enough space to store the data to be backed up, avoids data loss due to insufficient space, and improves the reliability of data protection in the event of a power outage. The concurrent transmission mechanism is used to write the cache data in parallel to the PMR of each target hard disk, which speeds up the data backup speed. Compared with the traditional solution, data protection can be completed in a shorter time, reducing the risk of data loss.

[0055] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example and not limitation, wherein:

[0057] In the drawings, the same or corresponding reference numerals denote the same or corresponding parts.

[0058] Figure 1 The schematic diagram of the implementation process of the power-off data protection method of the present disclosure is shown. Figure 1 ;

[0059] Figure 2 The schematic diagram of the implementation process of the power-off data protection method of the present disclosure is shown. Figure 2 ;

[0060] Figure 3 The schematic diagram of the implementation process of the power-off data protection method of the present disclosure is shown. Figure 3 ;

[0061] Figure 4 The schematic diagram of the implementation process of the power-off data protection method of the present disclosure is shown. Figure 4 ;

[0062] Figure 5 A schematic structural diagram of a power-off data protection system according to an embodiment of the present disclosure is shown;

[0063] Figure 6 A schematic structural diagram of a power-off data protection device according to an embodiment of the present disclosure is shown;

[0064] Figure 7 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0065] To make the purposes, features, and advantages of the present disclosure more apparent and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative work shall fall within the scope of protection of the present disclosure.

[0066] RAID (Redundant Array of Independent Disks) is a data storage technology that combines multiple independent physical hard drives into a single logical storage unit. This improves the storage system's data read and write speeds, enhances data redundancy, and improves fault tolerance. Different RAID levels can achieve different performance and security goals.

[0067] PCIe: A high-speed serial computer expansion bus standard, the full name is Peripheral Component Interconnect Express. It uses an efficient point-to-point connection protocol, has high-speed, low-latency, high-bandwidth transmission characteristics, supports hot plugging, and is widely used in various high-performance components and peripherals in modern computer systems. It has become the core technology for connecting modern high-performance hardware.

[0068] NVMe: NVMe (Non-Volatile Memory Express) is a communication protocol based on the PCIe interface, designed specifically for SSDs (solid-state drives) to provide high-speed, low-latency storage access.

[0069] NVMe PMR (NVMe Persistent Memory Region) refers to a persistent storage area on an NVMe device. Data in this area is retained even after a power outage, providing a more reliable data protection mechanism than traditional volatile cache.

[0070] ONFI: ONFI (Open NAND Flash Interface) is an open standards organization composed of multiple NAND flash memory manufacturers and related technology companies. Its goal is to develop standardized specifications for NAND flash memory interfaces. The ONFI specification defines the physical and electrical characteristics, operation commands, functions, and performance parameters of NAND flash memory chips to ensure compatibility and interoperability between NAND flash memory produced by different manufacturers.

[0071] The present disclosure provides a power-off data protection method, which is applied to a redundant array of independent disks RAID controller, such as Figure 1 As shown, the method includes:

[0072] Step 101: During the initialization phase, the PCIe configuration spaces of all connected hard disks are read to select at least one target hard disk that meets a preset whitelist.

[0073] In this example, during the initialization phase, when the RAID controller boots up, it needs to identify and configure connected hardware devices. During this phase, the controller actively scans all devices on the PCIe bus and simultaneously reads the high-speed serial bus PCIe configuration space of all connected hard drives. The PCIe configuration space contains a standardized register set for PCIe devices, along with key parameters such as the device's vendor ID, device ID, and base address register mapping information, as shown in Table 1 below. The preset whitelist is a predefined list of authorized hard drives, typically stored in the RAID controller's firmware or non-volatile memory. Target hard drives that meet the preset whitelist must be certified storage devices that support the persistent memory area function.

[0074] Table 1: PCIE configuration space custom field definition table

[0075]

[0076] Step 102: Obtain the base address register space mapped to the persistent memory region PMR of the target hard disk.

[0077] In this example, the PMR (Persistent Memory Region) is a standardized non-volatile storage area on an NVMe solid-state drive whose data is retained even after the device loses power. The Base Address Register Space (BAR space) is the physical address range used by PCIe devices to expose their hardware resources (such as memory or I / O ports) to the host system. According to the NVMe protocol specification, the PMR is defined by registers in the PCIe configuration space and mapped to the BAR space, allowing the host system to directly access this area through the PCIe bus.

[0078] Step 103: Verify whether the total base address register space corresponding to all target hard disks satisfies the total cache data volume.

[0079] In this example, the base address register space capacity mapped to the persistent memory area of ​​all target hard disks is accumulated and calculated to obtain the total available storage space. This total capacity needs to be compared and verified with the total amount of volatile cache data to be protected in the RAID controller. Specifically, the total available storage space is the sum of the BAR space capacity mapped to the PMR area of ​​each target hard disk. For example, when the PMRs of two target hard disks are mapped to BAR1 (4GB) and BAR2 (4GB) respectively, their total capacity is 8GB; and the total amount of volatile cache data to be backed up (such as 6GB of user data temporarily stored in DRAM) is used as the verification threshold.

[0080] Step 104: If the conditions are met, the backup enable flag in the PCIe configuration space of the target hard disk is set to an enabled state, and the power-off backup solution is enabled.

[0081] In this example, after the capacity check in step 103 passes, the RAID controller sets the target hard drive's offload enable flag (specifically corresponding to bit 2 in Table 1) to a logic high level (1) through a PCIe configuration space write transaction. This operation triggers the target hard drive's firmware layer logic, activates the backup function of its persistent memory area, and puts the system into power-off data protection mode. The specific implementation mechanism is: sending a configuration write request to the target hard drive via the PCIe bus, directly modifying the hardware register state of its BAR space mapping, and sending a ready instruction (Ready-for-Offload) to the target hard drive to notify it to start the pre-allocation and initialization process of the PMR area.

[0082] Step 105: When the RAID controller is in a power-off state, the cache data is concurrently written into the base address register space of the target hard disk and backed up to the PMR, so that the hard disk controller stores the cache data of the PMR into the flash memory.

[0083] In this example, when the RAID controller detects a main power anomaly, it immediately activates the backup power supply mechanism to maintain system operation and triggers the power-off backup plan: the data to be protected in the volatile cache is divided into multiple independent data blocks, which are then written in parallel to the persistent memory area mapped to the base address register space of each target hard drive using a concurrent transmission mechanism. After receiving the data, the target hard drive's firmware further persists the temporary data blocks received in the PMR area to the NAND flash media through the flash translation layer scheduling mechanism, completing the complete data protection chain from volatile storage to non-volatile storage.

[0084] This disclosure proposes a power-failure data protection method for RAID controllers. Unlike traditional power-failure protection designs that rely on supercapacitors and Flash storage, this solution reads the hard drive PCIe configuration space during the initialization phase, screens target hard drives that meet a preset whitelist, obtains the base address register space mapped by the target hard drive's PMR, verifies whether the total base address register space can accommodate the total cache data volume, and if so, activates a power-failure backup scheme. Upon a power failure, the cached data is concurrently written to the target hard drive's base address register space and backed up to the PMR, ultimately stored in the flash memory by the hard drive controller. Compared to traditional schemes where supercapacitor capacity is proportional to cost, this solution eliminates the need for large-capacity supercapacitors, reducing the cost of the RAID storage system. Secondly, by verifying whether the total base address register space of the target hard drive can accommodate the total cache data volume, sufficient space is ensured for the data to be backed up, preventing data loss due to insufficient space and improving data protection reliability during power failures. A concurrent transmission mechanism is used to write cached data in parallel to the PMRs of each target hard drive, accelerating data backup. Compared to traditional schemes, data protection can be completed in a shorter time, reducing the risk of data loss.

[0085] In one example, the high-speed serial bus PCIe configuration space of all connected hard disks is read to filter at least one target hard disk that meets the preset white list, such as Figure 2 As shown, including:

[0086] Step 201: Read the magic number field in the PCIe configuration space of the hard disk.

[0087] In this example, the RAID controller sends a configuration space read request to the target hard drive via the PCIe bus, reading a 32-bit register value from the manufacturer-agreed offset address 0x5C. According to the protocol specification jointly defined by the device manufacturer and the RAID controller, the magic number field (MagicNumber) is extracted from bits 31:19 of this register value using a bit mask (e.g., 0xFFF80000). This field serves as a unique identifier for the hard drive model and is used to determine whether it supports the persistent memory region (PMR) feature. Its encoding rules and bit width definition (13 bits in this example) are clearly stated by the device manufacturer in their technical documentation.

[0088] Step 202: Compare the magic number field with a preset whitelist to filter out at least one matching target hard disk.

[0089] In this example, the RAID controller compares the magic field extracted in step 201 with pre-stored identifiers in a preset whitelist. This whitelist is stored in the controller's non-volatile storage medium as a firmware image or configurable parameter file and contains the magic field identifiers corresponding to all legal hard drive models that support the persistent memory region (PMR) function. If the comparison result is an exact match, the hard drive is marked as a PMR backup target device and included in the subsequent PMR data persistence process. If there is no match, the PMR initialization process for the hard drive is skipped and a miss log is recorded, which contains the PCIe device identifier of the unmatched hard drive.

[0090] In one example, the base address register space mapped by the PMR of the target hard disk is obtained, such as Figure 3 Shown, including:

[0091] Step 301: Read the base indication register field of the PMR capability register of the target hard disk.

[0092] In this example, the PMR capability register (Persistent Memory Region Capability Register, PMRCAP) is a standardized register defined by the NVMe specification. It is located in the PCIe extended configuration space of the SSD (usually at offset 0x100) and is used to describe the configuration parameters and functional characteristics of the persistent memory region PMR of the solid-state drive.

[0093] The Base Indicator Register (BIR) field is a hardware register field defined in the NVMe specification. It is located in the PMR capability register of the hard disk (bit7 to bit5) and is used to indicate which base address register space of the PCIe device the persistent memory area is mapped to.

[0094] The RAID controller sends a configuration space read request to the target hard drive via the PCIe bus, accessing the persistent memory region capability register defined in the NVMe specification. The RAID controller extracts the base indication register field value from bits 7:5 of the PMRCAP register.

[0095] Step 302: Obtain the base address register space mapped by the PMR according to the base indication register field.

[0096] In this example, the RAID controller locates the target BAR space from the base address register area of ​​the PCIe configuration space based on the base indication register field value extracted in step 301: first, the target BAR number is determined based on the BIR field value, and the register corresponding to the BAR in the PCIe configuration space is accessed, and the mappable area length of the BAR space is calculated, thereby completing the base address and space resolution of the PMR mapping.

[0097] If the read 32-bit BAR register value is 0x000000A0, the base indicator register field value is 0x02, indicating that the PMR is mapped to BAR2 in the PCIe configuration space. At this time, the BAR2 register value is 0x80000000, and calculation shows that the mappable area length of this BAR space is 1GB.

[0098] In one example, the cache data is concurrently written into the base address register space of the target hard disk, such as Figure 4 As shown, including:

[0099] Step 401: Divide the cache data into multiple data blocks through direct memory access transmission.

[0100] In this example, Direct Memory Access (DMA) is a technology in which dedicated hardware (DMA engine) directly manages data transfer in a computer system, allowing external devices (such as SSDs, network cards, and RAID controllers) to directly read and write data with system memory or other device memory without relying on the intervention of the central processing unit. Specifically, the RAID controller uses a built-in direct memory access engine and a hardware-level data transfer mechanism to bypass the intervention of the CPU and operating system, and divides the data in the cache memory into preset block sizes: first, based on the independent hardware characteristics of the DMA controller, it allows external devices to directly access the system memory or device memory through the PCIe bus, realizing data reading and writing without the involvement of the CPU; then, the RAID controller configures the segmentation parameters through the DMA engine, and each data block is encapsulated as a PCIe transaction layer packet before transmission, and is transferred at high speed through the PCIe physical layer link, thereby completing the conversion and transmission of cached data into fixed-size data blocks.

[0101] Step 402: writing the data blocks in parallel into the base address register space mapped by the PMR of the target hard disk.

[0102] In this example, the RAID controller writes the segmented data blocks in parallel to the PMR-mapped base address register space of the target hard drives via a multi-channel PCIe interface. First, based on the BAR base address information obtained in step 302, the controller leverages the concurrent transmission capabilities of the multi-channel PCIe interface to simultaneously distribute the data blocks to the BAR spaces of multiple target hard drives. The RAID controller then dynamically allocates the data block transmission timing for each channel using a pipeline scheduling strategy, ensuring sequential data writes and avoiding multi-channel conflicts. It also enables an end-to-end CRC checksum mechanism to verify the integrity of the transmitted data, thereby achieving multi-drive parallel acceleration while ensuring data reliability. For example, four SSDs can receive data simultaneously, each processing 2GB of data, reducing the total transmission time to one-quarter that of a single drive.

[0103] In one example, the method further includes: setting the storage data to PMR flag in the PCIe configuration space to a completion state, and triggering the target hard disk to start data persistence; the target hard disk polls the storage data to PMR flag, and if it is detected that the storage data to PMR flag is in a completion state, writing the PMR data to the flash memory through the ONFI interface.

[0104] In this example, during the data backup process, after the RAID controller completes concurrent writes of cache data to the target hard drive's PMR-mapped BAR space, it sets the Store Data to PMR flag in the PCIe configuration space (bit 1 at offset 0x5C, as shown in Table 1) to 1 through a PCIe Memory Write TLP transaction. This flag update directly triggers the hard drive controller to initiate the data persistence process: the hard drive firmware polls this flag. Once it detects the set state, it immediately writes the PMR data to the physical block at the NAND flash page granularity through the parallel channel of the ONFI interface. During this process, the ONFI controller prioritizes PMR data transmission to ensure that the flash write operation is initiated during the SSD's internal cache. At the same time, an end-to-end CRC check mechanism is combined to ensure data integrity, ultimately achieving reliable transmission from the PMR buffer to the NAND flash memory particles.

[0105] In one example, the method further includes: after the target hard disk completes the persistent storage of data, setting the storage completion flag in the PCIe configuration space to a completion state; the RAID controller polls the storage completion flag, and if it is detected that the storage completion flag is in a completion state, turning off the capacitor switch.

[0106] In this example, after the SSD controller completes the persistent storage of PMR data in the NAND flash memory, it sets the storage completion flag in the PCIe configuration space (bit 0 at offset 0x5C, as shown in Table 1) to 1 through a PCIe Memory Write TLP transaction. This flag update uses atomic operations to ensure system state consistency. Subsequently, the RAID controller continuously checks this flag in a polling cycle. Once the set state is confirmed, it immediately triggers the capacitor switch shutdown command, terminating the temporary power supply to the cache and SSD. At this time, the capacitor discharge circuit immediately cuts off the power output after receiving the shutdown command. By eliminating the residual current path, the risk of data tampering is effectively avoided, ultimately achieving a secure closed loop from data persistence to power management.

[0107] In one example, combining Figure 5 The power-off data protection system architecture diagram shown in FIG. 1 is a diagram that describes in detail the process of the power-off data protection method described above:

[0108] S1: During the initialization phase, the RAID controller reads the PCIe configuration space of all attached SSDs and counts target hard drives that meet the whitelist requirements. Specifically, during the RAID controller initialization phase, the system performs hierarchical topology enumeration through the PCIe root complex, scanning the PCIe bus, device, and function numbers to locate attached NVMe SSDs. It then reads the magic field in the PCIe configuration space header of each drive and verifies its match against the pre-configured whitelist. Hard drives that meet the hardware identification matching and function expansion requirements are registered as whitelist members, providing a list of target hard drives for data backup and persistence operations during subsequent power-loss protection processes.

[0109] S2: The RAID controller reads the PMRCAP registers of the target hard drives that meet the whitelist requirements and calculates the PMR address space available for backing up cached data. If the PMR address space is larger than the amount of cached data to be backed up, the RAID controller notifies the whitelisted hard drives and sets the offload enable flag in the custom field of the PCIe configuration space to 1, indicating that the current system power-off scheme is the backup scheme. Specifically, during the initialization phase of the abnormal power-off protection process, the RAID controller sends a PMRCAP register read command to the registered whitelisted hard drives via the PCIe bus. It then parses the register value returned by each drive to determine the available address space range (starting address and capacity) of its PMR non-volatile storage area. If it detects that the total BAR space mapped by the target hard drive's PMR is larger than the total amount of cached data to be backed up, the RAID controller writes a control command to the drive via the PCIe configuration space, setting the offload enable flag in its custom field to logic 1, thereby notifying the drive that the system is currently using the backup scheme.

[0110] S3: The voltage monitoring module detects a voltage drop at the RAID controller's gold finger and initiates the abnormal power-off data protection process. During system operation, the voltage monitoring module continuously monitors the power supply voltage at the RAID controller's gold finger. If the main power supply voltage drops below a preset threshold, the module immediately triggers a hardware interrupt signal and simultaneously reports the voltage anomaly to the RAID controller. Upon receiving the interrupt, the RAID controller immediately initiates the abnormal power-off data protection process.

[0111] S4: The RAID controller concurrently writes the cache data to the BAR space mapped to the PMR area. The RAID controller concurrently initiates cache data backup operations via the PCIe bus, divides the cache data into fixed-size blocks, and writes each data block in parallel to the BAR space mapped to the PMR area based on the multi-channel DMA engine. During the write process, the RAID controller configures the request identifier and tag field of the PCIe transaction layer packet. Specifically: The RAID controller concurrently initiates cache data backup operations via the PCIe bus, first dividing the cache data into fixed-size data blocks according to a preset granularity, and based on the parallel transmission capability of the multi-channel DMA engine, simultaneously writes each data block to the BAR space mapped to the PMR area in the NVMe hard drive. During the write process, the RAID controller dynamically assigns a unique request identifier and tag field to each PCIe transaction layer packet. By combining the request IDs and tag values ​​of different channels, it achieves transmission stream isolation, avoiding data confusion or transmission conflicts between multiple hard drives.

[0112] S5: The RAID controller triggers a PCIe memory write TLP to concurrently back up data to the PMR area. After completing the data transfer, the RAID controller sets the store data to pmr flag in the custom field of the PCIe configuration space to 1. Specifically, the RAID controller also writes the cached data to the PMR area. After completing all data transfers, the RAID controller updates the PCIe configuration space, sets the store data to pmr flag in the custom field to logic 1, and simultaneously notifies the SSD and the system power management module of the data backup completion status.

[0113] S6: The NVMe hard drive polls the "store data to pmr" flag in the custom field of the PCIe configuration space. If the flag is set to 1, the hard drive uses the ONFI high-speed interface of the hard drive controller to store the data in the PMR area to the NAND flash memory chip. This completes the non-volatile storage of the cached data, ensuring data security and integrity and achieving high reliability for the entire storage system. After the hard drive completes the data storage, it sets the "store data complete" flag in the custom field of the PCIe configuration space to 1.

[0114] S7: The RAID controller polls the store data complete flag of the custom field in the PCIe configuration space. If it is 1, the capacitor switch is turned off. The RAID controller polls the store data complete flag status bit of the target hard disk in the PCIe configuration space. This flag is actively set by the hard disk after completing the NAND flash memory persistence operation, and is used to synchronize the data backup completion status to the RAID controller. The RAID controller continuously detects this flag at a preset period. If it detects that its value is logical 1, it determines that the data has been safely written to the non-volatile storage medium, and then sends a shutdown command to the capacitor switch control module to cut off the capacitor discharge path to prevent residual charge from causing hardware damage or data tampering, and at the same time trigger the system power management module to enter a low-power standby state.

[0115] The present disclosure also provides a power-off data protection device, such as Figure 6 As shown, the device is applied to a redundant array of independent disks RAID controller, and the device includes:

[0116] The hard disk screening module 601 is used to read the high-speed serial bus PCIe configuration space of all connected hard disks during the initialization phase and screen at least one target hard disk that meets the preset whitelist.

[0117] In this example, during the initialization phase, when the RAID controller boots up, it needs to identify and configure connected hardware devices. During this phase, the controller actively scans all devices on the PCIe bus and simultaneously reads the high-speed serial bus PCIe configuration space of all connected hard drives. The PCIe configuration space contains a standardized register set for PCIe devices, along with key parameters such as the device's vendor ID, device ID, and base address register mapping information, as shown in Table 1. The preset whitelist is a predefined list of authorized hard drives, typically stored in the RAID controller's firmware or non-volatile memory. Target hard drives that meet the preset whitelist must be certified storage devices that support the persistent memory area function.

[0118] The base address acquisition module 602 is configured to acquire the base address register space mapped to the persistent memory region PMR of the target hard disk.

[0119] In this example, the PMR (Persistent Memory Region) is a standardized non-volatile storage area on an NVMe solid-state drive whose data is retained even after the device loses power. The Base Address Register Space (BAR space) is the physical address range used by PCIe devices to expose their hardware resources (such as memory or I / O ports) to the host system. According to the NVMe protocol specification, the PMR is defined by registers in the PCIe configuration space and mapped to the BAR space, allowing the host system to directly access this area through the PCIe bus.

[0120] The verification module 603 is used to verify whether the total base address register space corresponding to all target hard disks meets the total cache data volume.

[0121] In this example, the base address register space capacity mapped to the persistent memory area of ​​all target hard disks is accumulated and calculated to obtain the total available storage space. This total capacity needs to be compared and verified with the total amount of volatile cache data to be protected in the RAID controller. Specifically, the total available storage space is the sum of the BAR space capacity mapped to the PMR area of ​​each target hard disk. For example, when the PMRs of two target hard disks are mapped to BAR1 (4GB) and BAR2 (4GB) respectively, their total capacity is 8GB; and the total amount of volatile cache data to be backed up (such as 6GB of user data temporarily stored in DRAM) is used as the verification threshold.

[0122] The enabling module 604 is configured to set the backup enable flag in the PCIe configuration space of the target hard disk to an enabled state and enable the power-off backup solution if the total base address register space satisfies the total cache data volume.

[0123] In this example, after the capacity check passes, the RAID controller sets the target hard drive's offload enable flag (specifically corresponding to bit 2 in Table 1) to a logic high level (1) through a PCIe configuration space write transaction. This operation triggers the target hard drive's firmware layer logic, activates the backup function of its persistent memory region (PMR), and puts the system into power-off data protection mode. The specific implementation mechanism is: sending a configuration write request to the target hard drive via the PCIe bus, directly modifying the hardware register state of its BAR space mapping, and sending a ready instruction (Ready-for-Offload) to the target hard drive to notify it to start the pre-allocation and initialization process of the PMR region.

[0124] The data writing module 605 is used to concurrently write the cache data into the base address register space of the target hard disk when the RAID controller is in a power-off state, and back it up to the PMR, so that the hard disk controller stores the cache data of the PMR into the flash memory.

[0125] In this example, when the RAID controller detects a main power anomaly, it immediately activates the backup power supply mechanism to maintain system operation and triggers the power-off backup plan: the data to be protected in the volatile cache is divided into multiple independent data blocks, which are then written in parallel to the persistent memory area mapped to the base address register space of each target hard drive using a concurrent transmission mechanism. After receiving the data, the target hard drive's firmware further persists the temporary data blocks received in the PMR area to the NAND flash media through the flash translation layer scheduling mechanism, completing the complete data protection chain from volatile storage to non-volatile storage.

[0126] In one example, the hard disk screening module 601 is specifically configured to: read a magic number field in the PCIe configuration space of the hard disk; compare the magic number field with a preset whitelist, and screen out at least one matching target hard disk.

[0127] In this example, the RAID controller sends a configuration space read request to the target hard drive via the PCIe bus, reading a 32-bit register value from the manufacturer-agreed offset 0x5C. According to the protocol specification jointly defined by the device manufacturer and the RAID controller, the magic number (MagicNumber) is extracted from bits 31:19 of this register value using a bit mask (e.g., 0xFFF80000). This field uniquely identifies the drive model and determines whether it supports the Persistent Memory Region (PMR) feature. Its encoding rules and bit width (13 bits in this example) are clearly stated in the device manufacturer's technical documentation. The RAID controller then compares the extracted magic number against a preset whitelist of pre-stored identifiers. This whitelist, stored in the controller's non-volatile storage medium as a firmware image or configurable parameter file, contains the magic number identifiers for all valid drive models supporting the Persistent Memory Region (PMR) feature. If the comparison result is an exact match, the hard drive is marked as the PMR backup target device and included in the subsequent PMR data persistence process; if there is no match, the PMR initialization process for the hard drive is skipped and a miss log is recorded, which contains the PCIe device identifier of the unmatched hard drive.

[0128] In an example, the base address acquisition module 602 is specifically configured to: read the base indication register field of the PMR capability register of the target hard disk; and acquire the base address register space mapped by the PMR according to the base indication register field.

[0129] The Persistent Memory Region Capability Register (PMRCAP) is a standardized register defined in the NVMe specification. It's located in the hard drive's PCIe extended configuration space (typically at offset 0x100) and is used to describe the configuration parameters and functional characteristics of the SSD's persistent memory region (PMR). The Base Indicator Register (BIR) field is a hardware register field defined in the NVMe specification. It's located within the hard drive's PMR capability register (bits 7 to 5) and is used to indicate which base address register space on the PCIe device the persistent memory region (PMR) is mapped to. The RAID controller sends a configuration space read request to the target hard drive via the PCIe bus to access the persistent memory region capability register defined in the NVMe specification. The RAID controller extracts the Base Indicator Register field value from the bits 7:5 of the PMRCAP register.

[0130] The RAID controller locates the target BAR space in the base address register area of ​​the PCIe configuration space based on the base indicator register field value extracted in step 301: first, the target BAR number is determined based on the BIR field value, and the register corresponding to the BAR in the PCIe configuration space is accessed. The length of the mappable area of ​​the BAR space is calculated, thereby completing the base address and space resolution of the PMR mapping. If the read 32-bit BAR register value is 0x000000A0, the base indicator register field value is 0x02, indicating that the PMR is mapped to BAR2 of the PCIe configuration space. At this time, the BAR2 register value is 0x80000000. After calculation, it can be obtained that the length of the mappable area of ​​the BAR space is 1GB.

[0131] In an example, the data writing module 605 is specifically configured to: divide the cache data into multiple data blocks via direct memory access transmission; and write the data blocks in parallel into the base address register space mapped by the PMR of the target hard disk.

[0132] In this example, Direct Memory Access (DMA) is a technology in which dedicated hardware (DMA controller) directly manages data transfer in a computer system, allowing external devices (such as hard disks, network cards, and RAID controllers) to directly read and write data with system memory or other device memory without relying on the intervention of the central processing unit. Specifically, the RAID controller uses a built-in direct memory access engine and a hardware-level data transfer mechanism to bypass the intervention of the CPU and operating system, and divide the data in the cache memory into preset block sizes: first, based on the independent hardware characteristics of the DMA controller, it allows external devices to directly access system memory or device memory through the PCIe bus, realizing data reading and writing without CPU participation; then, the RAID controller configures the segmentation parameters through the DMA engine, and each data block is encapsulated as a PCIe transaction layer packet (TLP) before transmission, and is transferred at high speed through the PCIe physical layer link, thereby completing the conversion and transmission of cached data into fixed-size data blocks.

[0133] The RAID controller writes the segmented data blocks in parallel to the PMR-mapped base address register space of the target hard drives via a multi-channel PCIe interface. First, based on the BAR base address information obtained in step 302, the controller leverages the concurrent transmission capabilities of the multi-channel PCIe interface to distribute the data blocks simultaneously to the BAR spaces of multiple target hard drives. Subsequently, the RAID controller dynamically allocates the data block transmission timing for each channel using a pipeline scheduling strategy to ensure sequential data writing and avoid multi-channel conflicts. It also enables an end-to-end CRC checksum mechanism to verify the integrity of the transmitted data, thereby achieving multi-drive parallel acceleration while ensuring data reliability. For example, four hard drives can receive data simultaneously, each processing 2GB of data, reducing the total transmission time to one-quarter that of a single drive.

[0134] In one example, the device also includes: a processing module 606, which is used to set the storage data to PMR flag in the PCIe configuration space to a completion state and trigger the target hard disk to start data persistence; the target hard disk polls the storage data to PMR flag, and if it is detected that the storage data to PMR flag is in a completion state, the PMR data is written to the flash memory through the ONFI interface.

[0135] In this example, during the data backup process, after the RAID controller completes concurrent writes of cached data to the target hard drive's PMR-mapped BAR space, it sets the Store Data to PMR flag in the PCIe configuration space (bit 1 at offset 0x5C, as shown in Table 1) to 1 through a PCIe Memory Write TLP transaction. This flag update directly triggers the hard drive controller to initiate the data persistence process: the hard drive firmware polls this flag. Once it detects the set state, it immediately writes the PMR data to the physical block at the NAND flash page granularity through the parallel channel of the ONFI interface. During this process, the ONFI controller prioritizes PMR data transmission to ensure that the flash write operation is initiated during the temporary storage period in the hard drive's internal cache. At the same time, an end-to-end CRC check mechanism is combined to ensure data integrity, ultimately achieving reliable transmission from the PMR buffer to the NAND flash memory particles.

[0136] In one example, the processing module 606 is also used to: after the target hard disk completes the persistent storage of data, set the storage completion flag in the PCIe configuration space to a completion state; the RAID controller polls the storage completion flag, and if it is detected that the storage completion flag is in a completion state, close the capacitor switch.

[0137] In this example, after the hard disk controller completes the persistent storage of PMR data in the NAND flash memory, it sets the storage completion flag in the PCIe configuration space (bit 0 at offset 0x5C, as shown in Table 1) to 1 through a PCIe Memory Write TLP transaction. This flag update uses atomic operations to ensure system state consistency. Subsequently, the RAID controller continuously checks this flag in a polling cycle. Once the set state is confirmed, it immediately triggers the capacitor switch shutdown command, terminating the temporary power supply to the cache and hard disk. At this time, the capacitor discharge circuit immediately cuts off the power output after receiving the shutdown command. By eliminating the residual current path, the risk of data tampering is effectively avoided, ultimately achieving a secure closed loop from data persistence to power management.

[0138] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0139] Figure 6A schematic block diagram of an example electronic device 800 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are provided as examples only and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0140] like Figure 6 As shown, the device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. Various programs and data required for the operation of the device 800 can also be stored in the RAM 803. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0141] Various components in device 800 are connected to I / O interface 805, including an input unit 806, such as a keyboard, mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, optical disk, etc.; and a communication unit 809, such as a network card, modem, wireless communication transceiver, etc. The communication unit 809 allows device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0142] The computing unit 801 can be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as the power-failure data protection method. For example, in some embodiments, the power-failure data protection method can be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed onto the device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the power-failure data protection method described above can be performed. Alternatively, in other embodiments, the computing unit 801 can be configured to perform the power-failure data protection method by any other suitable means (e.g., via firmware).

[0143] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0144] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0145] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0146] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0147] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0148] A computer system may include a client and a server. The client and server are generally remote from each other and typically interact through a communication network. The client-server relationship arises through computer programs running on the respective computers and having a client-server relationship with each other. The server may be a cloud server, a server in a distributed system, or a server integrated with a blockchain.

[0149] The present disclosure also provides a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the many-core cache coherence method described above in the present disclosure.

[0150] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved. This is not a limitation herein.

[0151] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. Throughout the present disclosure, "plurality" means two or more, unless otherwise specifically defined.

[0152] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A power-off data protection method, characterized in that: Applied to a redundant array of independent disks (RAID) controller, the method includes: During the initialization phase, the high-speed serial bus PCIe configuration space of all connected hard disks is read, and at least one target hard disk that meets the preset whitelist is selected; Obtaining the base address register space mapped to the persistent memory region PMR of the target hard disk; Verify whether the total base address register space corresponding to all target hard disks meets the total cache data capacity; If the conditions are met, the backup enable flag in the PCIe configuration space of the target hard disk is set to enabled, and the power-off backup solution is enabled; When the RAID controller is in a power-off state, the cache data is concurrently written into the base address register space of the target hard disk and backed up to the PMR, so that the hard disk controller stores the cache data of the PMR into the flash memory.

2. The method according to claim 1, characterized in that The step of reading the PCIe configuration space of all connected hard disks and screening at least one target hard disk that meets a preset whitelist includes: Read the magic number field in the PCIe configuration space of the hard disk; The magic number field is compared with a preset whitelist to filter out at least one matching target hard disk.

3. The method according to claim 1, characterized in that The obtaining of the base address register space mapped by the PMR of the target hard disk includes: Reading the base indication register field of the PMR capability register of the target hard disk; The base address register space mapped by the PMR is obtained according to the base indication register field.

4. The method according to claim 1, wherein The concurrently writing the cache data into the base address register space of the target hard disk includes: Splitting the cache data into a plurality of data blocks by direct memory access transmission; The data blocks are written in parallel into the base address register space mapped by the PMR of the target hard disk.

5. The method according to claim 1, wherein The method further comprises: Setting the storage data to PMR flag in the PCIe configuration space to a completion state, and triggering the target hard disk to start data persistence; The target hard disk polls the store data to PMR flag, and if it is detected that the store data to PMR flag is in a completion state, writes the PMR data into the flash memory through the ONFI interface.

6. The power-off data protection method for a RAID system according to claim 5, wherein: The method further comprises: After the target hard disk completes the persistent storage of the data, setting the storage completion flag in the PCIe configuration space to a completion state; The RAID controller polls the storage completion flag, and if it is detected that the storage completion flag is in a completion state, turns off the capacitor switch.

7. A power-off data protection device, characterized in that: Applied to a redundant array of independent disks (RAID) controller, the device comprises: A hard disk screening module is used to read the high-speed serial bus PCIe configuration space of all connected hard disks during the initialization phase and screen at least one target hard disk that meets the preset whitelist; A base address acquisition module is used to obtain the base address register space mapped by the persistent memory area PMR of the target hard disk; A verification module, used to verify whether the total base address register space corresponding to all target hard disks meets the total cache data capacity; an enabling module, configured to set a backup enable flag in the PCIe configuration space of the target hard disk to an enabled state and enable a power-off backup solution if the total base address register space satisfies the total cache data volume; A data writing module is used to concurrently write cache data into the base address register space of the target hard disk when the RAID controller is in a power-off state, and back it up to the PMR, so that the hard disk controller stores the cache data of the PMR into the flash memory.

8. The device according to claim 7, characterized in that The hard disk screening module is specifically used to: Read the magic number field in the PCIe configuration space of the hard disk; The magic number field is compared with a preset whitelist to filter out at least one matching target hard disk.

9. The device according to claim 7, characterized in that The base address acquisition module is specifically used to: Reading the base indication register field of the PMR capability register of the target hard disk; The base address register space mapped by the PMR is obtained according to the base indication register field.

10. The device according to claim 7, characterized in that The data writing module is specifically used to: Splitting the cache data into a plurality of data blocks by direct memory access transmission; The data blocks are written in parallel into the base address register space mapped by the PMR of the target hard disk.

11. The device according to claim 7, characterized in that The device further includes a processing module configured to: Setting the storage data to PMR flag in the PCIe configuration space to a completion state, and triggering the target hard disk to start data persistence; The target hard disk polls the store data to PMR flag, and if it is detected that the store data to PMR flag is in a completion state, writes the PMR data into the flash memory through the ONFI interface.

12. The device according to claim 11, characterized in that The processing module is further configured to: After the target hard disk completes the persistent storage of the data, setting the storage completion flag in the PCIe configuration space to a completion state; The RAID controller polls the storage completion flag, and if it is detected that the storage completion flag is in a completion state, turns off the capacitor switch.

13. An electronic device, characterized in that: include: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 6.

14. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 6.

15. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

Images