Digital down-conversion and anti-mirror interference method for Internet of Things

Abstract

The invention discloses a digital down-conversion and anti-mirror-interference method for the Internet of Things, and the method comprises the following steps: S1, constructing a receiving path, carrying out the down-conversion of a radio-frequency signal, and carrying out the analog-to-digital conversion of the radio-frequency signal into a low-intermediate-frequency I / Q orthogonal digital signal; s2, inputting the I / Q signal into a notch filter, suppressing harmonic interference of a crystal oscillator, and outputting an interference weakening signal; s3, looking up the table to generate an orthogonal local oscillator signal; s4, performing compound frequency mixing on the filtered I / Q signal and a local oscillator signal; s5, inputting the frequency mixing signal into a mirror image rejection module, and executing weighting operation to filter mirror image interference; s6, inputting the signal into a low-pass filter, suppressing sideband and mirror image residue, and outputting a target baseband signal; s7, performing normalization and compression processing on the signals; and S8, inputting into a post-stage processing module, and dynamically adjusting parameters according to feedback to enhance the anti-interference capability. According to the method, a low-power-consumption digital down-conversion link is constructed, image rejection and a self-adaptive mechanism are fused, and robust receiving processing of interference is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing and wireless communication systems, and in particular to a method for digital down-conversion and anti-mirror interference of the Internet of Things. Background Art

[0002] With the widespread deployment of IoT technology, terminal devices are placing higher demands on the stability and anti-interference capabilities of received signals in complex electromagnetic environments. In IoT systems, the receiving chain typically employs a superheterodyne structure or its digital variant, downconverting high-frequency RF signals to an intermediate frequency (IF) or even baseband for subsequent digital demodulation and data processing. However, traditional digital downconversion systems often face two prominent issues: first, the non-ideal operating frequency of the crystal oscillator introduces fixed-frequency harmonic interference into the IF signal; second, the lack of an effective image interference suppression mechanism during digital complex mixing results in strong image frequency interference in the mixing result, seriously affecting the signal-to-noise ratio (SNR) and demodulation accuracy of the received signal.

[0003] While existing Weaver structures and IQ demodulation systems can theoretically suppress image components to a certain extent, they still face numerous limitations in practical applications. For one thing, traditional solutions often employ a dual-mixer structure coupled with high-order analog filters for bandpass or lowpass filtering. This results in high hardware complexity and high resource consumption, making it particularly impractical in low-power, miniaturized IoT devices. Furthermore, in digital implementation, existing systems often employ static local oscillator configurations and fixed-structure image suppression methods, lacking adaptability to dynamic interference environments and unable to address issues such as spectrum leakage and enhanced image residuals caused by environmental changes.

[0004] Furthermore, current common digital down-conversion designs rely heavily on multipliers for mixing and filtering calculations. Multipliers are resource-intensive modules in hardware, occupying large chip areas, consuming high power, and exhibiting significant latency, making them unsuitable for deployment in resource-constrained embedded platforms or IoT devices. Therefore, reducing circuit complexity, minimizing resource overhead, and achieving structural adjustability and dynamic adaptability while maintaining anti-interference performance have become key areas of focus for optimizing digital down-conversion systems.

[0005] The IoT digital down-conversion and anti-image interference method proposed in the present invention addresses the defects of the above-mentioned existing technologies and constructs a complete processing chain from harmonic notching, table lookup of local oscillator, complex mixing, image filtering to low-pass filtering, amplitude normalization and feedback optimization, achieving a balance between signal quality, system flexibility and implementation cost, and significantly improving the practicality and stability of the digital receiving system in the complex environment of the IoT.

[0006] Therefore, how to provide a method for digital down-conversion and anti-mirror interference in the Internet of Things is an urgent problem that needs to be solved by those skilled in the art. Summary of the Invention

[0007] One objective of the present invention is to provide a method for digital down-conversion and image interference resistance in the Internet of Things. The present invention constructs a low-power digital down-conversion processing link for Internet of Things terminals, integrating notch filtering, table lookup local oscillator, image suppression, low-pass filtering and amplitude normalization modules to replace the traditional multiplier structure, reduce hardware resource overhead, and introduce a parameter adaptation mechanism to enhance the system's spectrum restoration capability and reception robustness in a multi-source interference environment, thereby achieving stable conversion of intermediate frequency signals to baseband signals and dynamic interference suppression.

[0008] According to an embodiment of the present invention, a method for digital down-conversion and anti-image interference in the Internet of Things includes the following steps:

[0009] S1. Build a digital receiving path for IoT terminals, perform analog down-conversion and analog-to-digital conversion on RF signals, and obtain low-IF I- and Q-channel orthogonal digital signals with a predetermined frequency range and sampling accuracy as input for subsequent digital processing.

[0010] S2. Input the I-channel and Q-channel orthogonal signals into the digital notch filter module respectively, perform band-stop attenuation operation on the interference frequency introduced by the crystal oscillator harmonics, and output the first intermediate frequency orthogonal signal after the interference is weakened;

[0011] S3. Generate a digital local oscillator signal in a memory using a table lookup method, including discrete cosine waves and sine waves sampled at equal intervals, and set the output frequency to the target down-conversion frequency point to form a local orthogonal mixing reference signal;

[0012] S4, respectively performing digital complex mixing processing on the filtered I-channel and Q-channel signals and the local oscillator sine and cosine signals generated by the lookup table to achieve frequency shifting of the low intermediate frequency signal to the baseband frequency band, thereby obtaining an orthogonal mixing signal after preliminary down-conversion;

[0013] S5. Inputting the mixing result into an image interference suppression module, which is composed of multiple sets of parallel multiplication and addition structures, performs weighted operations on the input signal based on preset image interference characteristics and structural parameters, and outputs a baseband candidate signal that has been subjected to image term suppression processing;

[0014] S6. Inputting the image suppression signal into an anti-aliasing low-pass filter module, wherein the filter has a limited bandwidth and order design, suppresses sideband interference and spectrum image residues in the mixing process, and outputs a target baseband signal within the limited bandwidth;

[0015] S7. Performing amplitude normalization, polarity correction, and dynamic range compression on the orthogonal signal output by the low-pass filter to ensure that the output signal meets the amplitude and phase input requirements of the digital modulation and demodulation module, thereby obtaining a stable digital baseband signal;

[0016] S8. Input the obtained baseband signal into the subsequent communication protocol processing unit, cache and evaluate the intermediate data in the image suppression path, and dynamically adjust the filter parameters, mixing reference phase and weight configuration according to system feedback, thereby enhancing the spectrum demodulation robustness of the IoT terminal in a multi-source interference environment.

[0017] Optionally, the S1 specifically includes:

[0018] S11, receiving a high-frequency wireless signal output by a radio frequency receiving unit in an IoT terminal, and sending the signal to an analog down-conversion module after suppressing adjacent channel interference through a bandpass filter;

[0019] S12, in the analog down-conversion module, mixing the first local oscillator signal with the high-frequency signal to convert the signal frequency to a set intermediate frequency band, and output an analog intermediate frequency signal;

[0020] S13, inputting the analog intermediate frequency signals into the orthogonal demodulators respectively, and demodulating to obtain orthogonal I-channel and Q-channel analog signals;

[0021] S14, inputting the I-channel and Q-channel analog signals into an analog-to-digital conversion module, performing synchronous sampling using a unified sampling clock, and converting them into digital low-intermediate-frequency I-channel and Q-channel signals;

[0022] S15 , performing amplitude normalization and code amplitude limitation on the I-channel and Q-channel digital signals to ensure that their amplitudes are within a preset dynamic range, and outputting standardized orthogonal digital signals as inputs for subsequent digital down-conversion.

[0023] Optionally, the S2 specifically includes:

[0024] S21, inputting the analog-to-digital converted I and Q digital intermediate frequency signals into a first channel notch filter and a second channel notch filter, respectively, wherein the notch filter channels correspond to the I and Q signal paths, respectively, and have independent data input interfaces and clock control logic;

[0025] S22, setting a preset notch frequency parameter and a bandwidth adjustment factor in the notch filter, and constructing a corresponding filter coefficient group based on the parameter configuration to generate a filter window for suppressing interference at a specific frequency point, wherein the notch frequency parameter can be set according to the crystal oscillator harmonic frequency;

[0026] S23, constructing a finite impulse response filter unit using a symmetrical tap structure, and performing odd-even tap optimization and multiplication-addition calculation process streamlining on the structure to meet the computing resource limitation requirements of a low-power embedded platform;

[0027] S24. Synchronously controlling the input and output timings of the two channel filters by configuring a channel controller to ensure phase consistency and delay alignment of the I-channel and Q-channel signals after being processed by the independent notch channels, thereby ensuring that the orthogonal relationship remains stable after filtering.

[0028] S25. Buffer the I-channel and Q-channel signals that have passed the notch processing into the data input cache area of ​​the complex mixing module respectively, and mark them as the orthogonal intermediate frequency signal input ports after image interference preprocessing, so as to provide the input data stream with reduced interference for the local oscillator mixing operation in the next stage.

[0029] Optionally, the S3 specifically includes:

[0030] S31, constructing a local oscillator signal generation module, configuring a read-only memory for storing a table of sine and cosine sampling values ​​within a cycle, wherein the sampling values ​​are pre-calculated according to a fixed frequency and written into a table lookup storage unit;

[0031] S32, setting the local oscillator output frequency parameter and the system main sampling clock frequency, determining the table lookup step control logic based on the ratio between the two, and mapping it to the address counter control module for sequencing the output of sine and cosine signals;

[0032] S33, sequentially reading the sine and cosine sampling values ​​at corresponding positions in the read-only memory through a synchronous address generator, and outputting them as digital local oscillator orthogonal signals, respectively, wherein the orthogonal signals have phase difference and frequency stability characteristics;

[0033] S34. Utilizing the periodicity of the lookup table, the address range is mapped in half, and a symmetrical storage optimization mechanism is adopted to retain only half-cycle sample data. Complete sine and cosine wave reconstruction is achieved through logic inversion and amplitude compensation, thereby reducing the storage capacity of the local oscillator lookup table.

[0034] S35. Output the generated orthogonal local oscillator signal to the input port of the complex mixing module while maintaining its clock synchronization characteristics and period continuity, and use it as a local oscillator reference input signal for the frequency shifting operation in the digital down-conversion process.

[0035] Optionally, the S4 specifically includes:

[0036] S41, inputting the I-channel signal and the Q-channel signal output by the notch filter module into the first input channel and the second input channel of the complex frequency mixing module respectively, and inputting the sine signal and the cosine signal output by the local oscillator module into the local oscillator channel of the module;

[0037] S42. In the complex mixing module, the I-channel signal is paired with the cosine local oscillator signal, and the Q-channel signal is paired with the sine local oscillator signal, and the signals are transmitted to two multiplication structure paths respectively to form an orthogonal mixing input pair.

[0038] S43, constructing a table lookup multiplication and addition unit for multiplication operation, performing a time-series weighted multiplication operation on each pair of input data based on the synchronization index relationship between the input signal and the table lookup local oscillator signal, to generate a mixed intermediate signal;

[0039] S44. Coordinate the calculation rhythm and data synchronization of the two multiplication paths using a sampling clock controller to ensure that the I / Q channel mixing operation maintains phase consistency within the cycle and avoid phase drift caused by delay or asynchrony.

[0040] S45. Send the two mixed signals output by the multiplication path to the buffer interface uniformly, and output them as primary baseband orthogonal signals that have completed the first stage of frequency conversion to the input port of the image interference suppression module.

[0041] Optionally, the S5 specifically includes:

[0042] S51, connecting the first orthogonal signal channel and the second orthogonal signal channel output by the complex mixing module to the input channel of the image interference suppression module respectively, wherein the module includes multiple parallel multiplication and addition processing units, each unit having an independent data path and coefficient control path;

[0043] S52, setting a plurality of table lookup coefficient storage units inside the image interference suppression module, preloading filter weight parameters matching the image frequency band characteristics, and distributing them to operation channels of corresponding multiplication-addition structures according to preset instructions;

[0044] S53, inputting the orthogonal mixing signal into each multiplication-addition channel respectively, performing multiplication operation with the image suppression weight coefficient according to the synchronous clock sequence, and accumulating the output results cycle by cycle through the addition-accumulation unit to form a weighted sum signal sequence;

[0045] S54, setting a normalizer and a delay compensation module at the end of the multiplication-addition path to perform amplitude compression and timing synchronization processing on each weighted result to ensure that the output signal amplitude is stable and the phase between channels is consistent;

[0046] S55 , integrating and merging the image interference suppression signals output by all the multiplication-addition paths, outputting an orthogonal baseband signal with suppressed image interference, and transmitting the signal to the input interface of the low-pass filter module.

[0047] Optionally, the S6 specifically includes:

[0048] S61, inputting the orthogonal baseband signals output by the image interference suppression module into a first low-pass filter channel and a second low-pass filter channel, respectively, where the two channels correspond to the I and Q signal paths, respectively, and maintaining input synchronization;

[0049] S62: setting the passband range, cutoff frequency, and order parameters in the low-pass filter module, generating a filter coefficient group based on a window function design method, writing the coefficients into the tap register of the filter structure, and performing a sliding window convolution operation;

[0050] S63, using a multi-tap finite impulse response filter structure to process the input signal in real time, retaining the main frequency component of the baseband signal within the set bandwidth range, and suppressing the high-frequency interference, sideband noise and sampling aliasing signal components left after mixing;

[0051] S64: The delay alignment control logic embedded in the filter channel monitors the operational delay difference between the two channels in real time and dynamically compensates the output signals to ensure that the I and Q signals maintain orthogonality and phase consistency after filtering.

[0052] S65. Cache the I and Q baseband signals output by the low-pass filter as input sources for subsequent amplitude normalization and digital demodulation. At the same time, write the filter control parameters into the register interface to support subsequent adaptive adjustment.

[0053] Optionally, the S7 specifically includes:

[0054] S71, inputting the I-channel and Q-channel baseband signals output by the low-pass filtering module into the amplitude normalization processing module respectively, which has amplitude detection, amplitude adjustment, polarity processing and dynamic range mapping function channels;

[0055] S72. Extracting the amplitude envelope information of each input signal in the amplitude detection unit, calculating the current signal strength based on the detection result, and generating a normalized adjustment coefficient for controlling the subsequent adjustment process;

[0056] S73. In the amplitude adjustment unit, perform an amplitude scaling operation on the input signal according to the normalization adjustment coefficient to compress its peak amplitude to below the upper limit of the preset dynamic range, while ensuring that the amplitude change ratios of the two signals are consistent;

[0057] S74. Monitoring the positive and negative sign states of the signals in the polarity processing module, performing sign correction operations on signals with amplitude inversion, unifying polarity directions, and eliminating mismatch errors caused by path asymmetry or system bias;

[0058] S75. Perform dynamic amplitude linear compression processing on the normalized signal in the dynamic range mapping unit, and map the original amplitude space to a set low dynamic range to ensure that the signal has a stable amplitude characteristic when input into the subsequent digital demodulation module.

[0059] Optionally, the S8 specifically includes:

[0060] S81, inputting the amplitude-normalized I and Q baseband signals into a digital demodulation module, performing modulation recognition, symbol decision or data restoration operations, and completing information extraction of the received signal;

[0061] S82. Setting an intermediate data monitoring channel inside the image interference suppression module and the low-pass filter module to sample the operation results of key processing nodes in real time and cache them in the system log buffer according to the processing rounds;

[0062] S83, extracting features from the intermediate data in the cache, interference-related parameters including channel output stability index, image suppression residual amplitude, and filter sideband leakage, and forming a feedback data set;

[0063] S84. Based on the feedback data set result, the system control unit triggers a configuration update mechanism to adjust the weight coefficient, local oscillator frequency control word, and filter passband boundary parameters in the image suppression module online.

[0064] S85. Write the updated configuration parameters into the register interface of the corresponding module, overwriting the old values ​​and taking effect immediately, thereby realizing adaptive adjustment of the processing structure of the IoT terminal in a dynamic interference environment and closed-loop enhancement of system performance.

[0065] The beneficial effects of the present invention are:

[0066] The IoT digital down-conversion and anti-image interference method provided by the present invention has many advantages, such as compact structure, efficient processing, strong interference suppression capability, and excellent adaptability. It significantly improves the reception stability and system robustness of IoT terminal devices in complex electromagnetic environments.

[0067] First, the present invention introduces a dedicated notch filter module into the digital signal input path to perform targeted suppression of the crystal oscillator harmonic frequency points, which can effectively eliminate the crystal oscillator parasitic interference that is difficult to avoid in traditional systems, improve the purity of the intermediate frequency signal, and provide a higher quality raw data foundation for subsequent mixing and filtering links.

[0068] Secondly, the present invention uses a table lookup to generate orthogonal local oscillator signals. By optimizing the periodic reconstruction of sine and cosine waveforms, it significantly reduces storage resource usage, maintaining local oscillator frequency stability and phase accuracy while reducing reliance on computing devices. Furthermore, by performing complex mixing operations with I / Q intermediate frequency signals, efficient spectrum shifting is achieved. The multi-channel multiplication-addition structure constructed with the image interference suppression module accurately filters out the image frequency components generated during the mixing process, resolving the difficulty of removing residual images in traditional methods.

[0069] Furthermore, the present invention introduces an anti-aliasing low-pass filter structure after the mixing output. Combined with a delay compensation mechanism, it ensures the consistency and phase balance of the orthogonal channels, effectively filtering out the sidebands and high-frequency artifacts generated by the mixing superposition, making the output baseband signal more focused and clear. Amplitude normalization, polarity correction, and dynamic compression are then performed to ensure that the baseband signal meets the amplitude dynamic characteristics required by the digital demodulation module, enhancing the stability and distortion resistance of the demodulation decoding.

[0070] In addition, the present invention also constructs a parameter adaptive adjustment mechanism by caching and feedback analysis of the intermediate calculation results of the image suppression and filtering modules, which can update the filtering parameters, mixing configuration and weight distribution in real time according to changes in the interference environment, thereby enabling the system to have dynamic response capabilities and improve robustness and long-term stability in non-ideal environments.

[0071] Ultimately, the present invention not only realizes the complete digital down-conversion function of the intermediate frequency to baseband signal of the IoT terminal, but also achieves the unity of high performance, low power consumption and high reliability through modularization, parameterization and feedback adjustable design without relying on complex hardware multipliers. It is suitable for various wireless reception application scenarios with limited resources and complex interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0073] Figure 1 This is an overall flow chart of a method for digital down-conversion and anti-image interference in the Internet of Things proposed by the present invention;

[0074] Figure 2 This is a structural diagram of the I / Q signal receiving and notch filtering processing module proposed in the present invention;

[0075] Figure 3 This is a schematic diagram of the multiplication and addition structure of the image interference suppression module proposed in the present invention. DETAILED DESCRIPTION

[0076] The present invention will now be described in further detail with reference to the accompanying drawings, which are simplified schematic diagrams that illustrate the basic structure of the present invention in a schematic manner.

[0077] refer to Figure 1-3 , a method for digital down-conversion and anti-image interference of the Internet of Things, comprising the following steps:

[0078] S1. Build a digital receiving path for IoT terminals, perform analog down-conversion and analog-to-digital conversion on RF signals, and obtain low-IF I- and Q-channel orthogonal digital signals with a predetermined frequency range and sampling accuracy as input for subsequent digital processing.

[0079] S2. Input the I-channel and Q-channel orthogonal signals into the digital notch filter module respectively, perform band-stop attenuation operation on the interference frequency introduced by the crystal oscillator harmonics, and output the first intermediate frequency orthogonal signal after the interference is weakened;

[0080] S3. Generate a digital local oscillator signal in a memory using a table lookup method, including discrete cosine waves and sine waves sampled at equal intervals, and set the output frequency to the target down-conversion frequency point to form a local orthogonal mixing reference signal;

[0081] S4, respectively performing digital complex mixing processing on the filtered I-channel and Q-channel signals and the local oscillator sine and cosine signals generated by the lookup table to achieve frequency shifting of the low intermediate frequency signal to the baseband frequency band, thereby obtaining an orthogonal mixing signal after preliminary down-conversion;

[0082] S5. Inputting the mixing result into an image interference suppression module, which is composed of multiple sets of parallel multiplication and addition structures, performs weighted operations on the input signal based on preset image interference characteristics and structural parameters, and outputs a baseband candidate signal that has been subjected to image term suppression processing;

[0083] S6. Inputting the image suppression signal into an anti-aliasing low-pass filter module, wherein the filter has a limited bandwidth and order design, suppresses sideband interference and spectrum image residues in the mixing process, and outputs a target baseband signal within the limited bandwidth;

[0084] S7. Performing amplitude normalization, polarity correction, and dynamic range compression on the orthogonal signal output by the low-pass filter to ensure that the output signal meets the amplitude and phase input requirements of the digital modulation and demodulation module, thereby obtaining a stable digital baseband signal;

[0085] S8. Input the obtained baseband signal into the subsequent communication protocol processing unit, cache and evaluate the intermediate data in the image suppression path, and dynamically adjust the filter parameters, mixing reference phase and weight configuration according to system feedback, thereby enhancing the spectrum demodulation robustness of the IoT terminal in a multi-source interference environment.

[0086] The present invention constructs a top-down modular digital down-conversion link to completely cover the entire process of signal acquisition, interference suppression, frequency shifting, image filtering and feedback control. Without relying on traditional analog mixing and hardware multipliers, it integrates digital processing and structural adaptation functions, taking into account both receiving performance and hardware feasibility. It is suitable for IoT receiving scenarios in resource-constrained environments and has the advantages of high robustness, high integration and low power consumption.

[0087] In this embodiment, S1 specifically includes:

[0088] S11, receiving a high-frequency wireless signal output by a radio frequency receiving unit in an IoT terminal, and sending the signal to an analog down-conversion module after suppressing adjacent channel interference through a bandpass filter;

[0089] S12, in the analog down-conversion module, mixing the first local oscillator signal with the high-frequency signal to convert the signal frequency to a set intermediate frequency band, and output an analog intermediate frequency signal;

[0090] S13, inputting the analog intermediate frequency signals into the orthogonal demodulators respectively, and demodulating to obtain orthogonal I-channel and Q-channel analog signals;

[0091] S14, inputting the I-channel and Q-channel analog signals into an analog-to-digital conversion module, performing synchronous sampling using a unified sampling clock, and converting them into digital low-intermediate-frequency I-channel and Q-channel signals;

[0092] S15 , performing amplitude normalization and code amplitude limitation on the I-channel and Q-channel digital signals to ensure that their amplitudes are within a preset dynamic range, and outputting standardized orthogonal digital signals as inputs for subsequent digital down-conversion.

[0093] By down-converting the RF signal into a low-IF orthogonal analog signal and performing high-precision synchronous analog-to-digital conversion, a stable digital I / Q input channel is effectively established, providing a digital basic signal source with structural matching, phase consistency, and amplitude control for subsequent modules at all levels. This enhances the overall interface standardization and input signal consistency of the digital down-conversion system, while reducing demodulation errors caused by uneven front-end sampling or signal imbalance.

[0094] In this embodiment, S2 specifically includes:

[0095] S21, inputting the analog-to-digital converted I and Q digital intermediate frequency signals into a first channel notch filter and a second channel notch filter, respectively, wherein the notch filter channels correspond to the I and Q signal paths, respectively, and have independent data input interfaces and clock control logic;

[0096] S22, setting a preset notch frequency parameter and a bandwidth adjustment factor in the notch filter, and constructing a corresponding filter coefficient group based on the parameter configuration to generate a filter window for suppressing interference at a specific frequency point, wherein the notch frequency parameter can be set according to the crystal oscillator harmonic frequency;

[0097] S23, constructing a finite impulse response filter unit using a symmetrical tap structure, and performing odd-even tap optimization and multiplication-addition calculation process streamlining on the structure to meet the computing resource limitation requirements of a low-power embedded platform;

[0098] S24. Synchronously controlling the input and output timings of the two channel filters by configuring a channel controller to ensure phase consistency and delay alignment of the I-channel and Q-channel signals after being processed by the independent notch channels, thereby ensuring that the orthogonal relationship remains stable after filtering.

[0099] S25. Buffer the I-channel and Q-channel signals that have passed the notch processing into the data input cache area of ​​the complex mixing module respectively, and mark them as the orthogonal intermediate frequency signal input ports after image interference preprocessing, so as to provide the input data stream with reduced interference for the local oscillator mixing operation in the next stage.

[0100] A dual-channel digital notch filter is set up to suppress the crystal oscillator harmonics and their integer multiples in a targeted manner, significantly improving the cleanliness of the intermediate frequency signal. This overcomes the problem of difficult-to-eradicate image interference caused by long-term accumulation of in-band interference in traditional intermediate frequency channels. At the same time, a symmetrical tap structure is used to improve filtering accuracy and resource utilization, ensuring that the filtering effect and the channel orthogonality relationship are stable and not mismatched.

[0101] In this embodiment, S3 specifically includes:

[0102] S31, constructing a local oscillator signal generation module, configuring a read-only memory for storing a table of sine and cosine sampling values ​​within a cycle, wherein the sampling values ​​are pre-calculated according to a fixed frequency and written into a table lookup storage unit;

[0103] S32, setting the local oscillator output frequency parameter and the system main sampling clock frequency, determining the table lookup step control logic based on the ratio between the two, and mapping it to the address counter control module for sequencing the output of sine and cosine signals;

[0104] S33, sequentially reading the sine and cosine sampling values ​​at corresponding positions in the read-only memory through a synchronous address generator, and outputting them as digital local oscillator orthogonal signals, respectively, wherein the orthogonal signals have phase difference and frequency stability characteristics;

[0105] S34. Utilizing the periodicity of the lookup table, the address range is mapped in half, and a symmetrical storage optimization mechanism is adopted to retain only half-cycle sample data. Complete sine and cosine wave reconstruction is achieved through logic inversion and amplitude compensation, thereby reducing the storage capacity of the local oscillator lookup table.

[0106] S35. Output the generated orthogonal local oscillator signal to the input port of the complex mixing module while maintaining its clock synchronization characteristics and period continuity, and use it as a local oscillator reference input signal for the frequency shifting operation in the digital down-conversion process.

[0107] The lookup table local oscillator signal generation structure is designed based on equal sampling intervals and periodic symmetry. While maintaining output orthogonal stability, it can compress the ROM lookup table storage capacity to half of the original structure, greatly reducing on-chip storage resource overhead. At the same time, combined with the stepper controller and synchronous address counting mechanism, a high-precision, low-power, and low-occupancy local oscillator output system is realized, with excellent frequency controllability and clock synchronization characteristics.

[0108] In this embodiment, the S4 specifically includes:

[0109] S41, inputting the I-channel signal and the Q-channel signal output by the notch filter module into the first input channel and the second input channel of the complex frequency mixing module respectively, and inputting the sine signal and the cosine signal output by the local oscillator module into the local oscillator channel of the module;

[0110] S42. In the complex mixing module, the I-channel signal is paired with the cosine local oscillator signal, and the Q-channel signal is paired with the sine local oscillator signal, and the signals are transmitted to two multiplication structure paths respectively to form an orthogonal mixing input pair.

[0111] S43, constructing a table lookup multiplication and addition unit for multiplication operation, performing a time-series weighted multiplication operation on each pair of input data based on the synchronization index relationship between the input signal and the table lookup local oscillator signal, to generate a mixed intermediate signal;

[0112] S44. Coordinate the calculation rhythm and data synchronization of the two multiplication paths using a sampling clock controller to ensure that the I / Q channel mixing operation maintains phase consistency within the cycle and avoid phase drift caused by delay or asynchrony.

[0113] S45. Send the two mixed signals output by the multiplication path to the buffer interface uniformly, and output them as primary baseband orthogonal signals that have completed the first stage of frequency conversion to the input port of the image interference suppression module.

[0114] By adopting a digital complex mixing structure combined with a lookup table for local oscillator signals, through branch multiplication and synchronous control, the frequency shift of the low-IF signal to the baseband band is achieved without introducing a hardware multiplier array, and the phase consistency and amplitude symmetry of the I / Q path are ensured, thus overcoming the problems of high resource usage and difficult synchronous control in the traditional mixer structure, and significantly improving the signal spectrum conversion accuracy and path matching.

[0115] In this embodiment, the S5 specifically includes:

[0116] S51, connecting the first orthogonal signal channel and the second orthogonal signal channel output by the complex mixing module to the input channel of the image interference suppression module respectively, wherein the module includes multiple parallel multiplication and addition processing units, each unit having an independent data path and coefficient control path;

[0117] S52, setting a plurality of table lookup coefficient storage units inside the image interference suppression module, preloading filter weight parameters matching the image frequency band characteristics, and distributing them to operation channels of corresponding multiplication-addition structures according to preset instructions;

[0118] S53, inputting the orthogonal mixing signal into each multiplication-addition channel respectively, performing multiplication operation with the image suppression weight coefficient according to the synchronous clock sequence, and accumulating the output results cycle by cycle through the addition-accumulation unit to form a weighted sum signal sequence;

[0119] S54, setting a normalizer and a delay compensation module at the end of the multiplication-addition path to perform amplitude compression and timing synchronization processing on each weighted result to ensure that the output signal amplitude is stable and the phase between channels is consistent;

[0120] S55 , integrating and merging the image interference suppression signals output by all the multiplication-addition paths, outputting an orthogonal baseband signal with suppressed image interference, and transmitting the signal to the input interface of the low-pass filter module.

[0121] The image interference suppression module constructs a multipath filtering network through a parallel multiplication-addition structure, and combines table lookup weights with a multiplication-addition accumulation mechanism to achieve selective suppression of the image frequency band. This effectively overcomes the problems of image energy leakage and sideband superposition after frequency shifting, ensuring the purity of the main frequency domain of the output signal while maintaining high sensitivity, helping to improve the signal-to-noise ratio, anti-mismatch capability and measurable frequency band integrity of the receiving system.

[0122] In this embodiment, S6 specifically includes:

[0123] S61, inputting the orthogonal baseband signals output by the image interference suppression module into a first low-pass filter channel and a second low-pass filter channel, respectively, where the two channels correspond to the I and Q signal paths, respectively, and maintaining input synchronization;

[0124] S62: setting the passband range, cutoff frequency, and order parameters in the low-pass filter module, generating a filter coefficient group based on a window function design method, writing the coefficients into the tap register of the filter structure, and performing a sliding window convolution operation;

[0125] S63, using a multi-tap finite impulse response filter structure to process the input signal in real time, retaining the main frequency component of the baseband signal within the set bandwidth range, and suppressing the high-frequency interference, sideband noise and sampling aliasing signal components left after mixing;

[0126] S64: The delay alignment control logic embedded in the filter channel monitors the operational delay difference between the two channels in real time and dynamically compensates the output signals to ensure that the I and Q signals maintain orthogonality and phase consistency after filtering.

[0127] S65. Cache the I and Q baseband signals output by the low-pass filter as input sources for subsequent amplitude normalization and digital demodulation. At the same time, write the filter control parameters into the register interface to support subsequent adaptive adjustment.

[0128] By introducing a dual-channel anti-aliasing low-pass filter structure, adopting a parameter-configurable window function design method, and coordinating delay compensation logic to synchronously correct phase drift between channels, the system can stably filter out mixing high-frequency residues and sideband interference, while maintaining consistent signal output within the band, enhancing demodulation reliability and the error tolerance capability of the post-processing module, making it suitable for precise reception applications in bandwidth-controlled scenarios.

[0129] In this embodiment, the S7 specifically includes:

[0130] S71, inputting the I-channel and Q-channel baseband signals output by the low-pass filtering module into the amplitude normalization processing module respectively, which has amplitude detection, amplitude adjustment, polarity processing and dynamic range mapping function channels;

[0131] S72. Extracting the amplitude envelope information of each input signal in the amplitude detection unit, calculating the current signal strength based on the detection result, and generating a normalized adjustment coefficient for controlling the subsequent adjustment process;

[0132] S73. In the amplitude adjustment unit, perform an amplitude scaling operation on the input signal according to the normalization adjustment coefficient to compress its peak amplitude to below the upper limit of the preset dynamic range, while ensuring that the amplitude change ratios of the two signals are consistent;

[0133] S74. Monitoring the positive and negative sign states of the signals in the polarity processing module, performing sign correction operations on signals with amplitude inversion, unifying polarity directions, and eliminating mismatch errors caused by path asymmetry or system bias;

[0134] S75. Perform dynamic amplitude linear compression processing on the normalized signal in the dynamic range mapping unit, and map the original amplitude space to a set low dynamic range to ensure that the signal has a stable amplitude characteristic when input into the subsequent digital demodulation module.

[0135] The normalization processing module performs amplitude standardization processing at three levels: amplitude compression, polarity correction, and dynamic interval mapping. This ensures that the baseband I / Q signals meet the input characteristic requirements of the demodulation module. Especially in the case of multipath interference or pre-amplification mismatch, it can effectively suppress the risks of amplitude drift and symbol flipping, improve modulation recognition stability and decoding accuracy, and provide standardized and predictable digital signal input for the link backend.

[0136] In this embodiment, S8 specifically includes:

[0137] S81, inputting the amplitude-normalized I and Q baseband signals into a digital demodulation module, performing modulation recognition, symbol decision or data restoration operations, and completing information extraction of the received signal;

[0138] S82. Setting an intermediate data monitoring channel inside the image interference suppression module and the low-pass filter module to sample the operation results of key processing nodes in real time and cache them in the system log buffer according to the processing rounds;

[0139] S83, extracting features from the intermediate data in the cache, interference-related parameters including channel output stability index, image suppression residual amplitude, and filter sideband leakage, and forming a feedback data set;

[0140] S84. Based on the feedback data set result, the system control unit triggers a configuration update mechanism to adjust the weight coefficient, local oscillator frequency control word, and filter passband boundary parameters in the image suppression module online.

[0141] S85. Write the updated configuration parameters into the register interface of the corresponding module, overwriting the old values ​​and taking effect immediately, thereby realizing adaptive adjustment of the processing structure of the IoT terminal in a dynamic interference environment and closed-loop enhancement of system performance.

[0142] By building a feedback adjustment mechanism that combines intermediate data caching, feature extraction and parameter reconstruction, online adjustment of image suppression and filter configuration can be achieved, improving the system's adaptive processing capabilities in dynamic interference environments, and driving the overall signal processing path parameter change response through a configuration update closed loop, thereby significantly enhancing the long-term stability, spectrum tracking capability and environmental adaptability of the receiving system.

[0143] Example 1:

[0144] In order to verify the feasibility of the present invention in implementation, the present invention is applied to an IoT environmental monitoring system deployed in an industrial park. The main goal is to monitor the diffusion concentration of industrial pollutants and the changing trend of environmental gases. The system includes 120 terminal nodes and 1 central gateway. The terminals use wireless sensors to send low-power data in the 433MHz ISM frequency band.

[0145] In the traditional solution previously used, terminal devices implemented wireless reception processing using analog downconversion combined with low-precision digital demodulation. This architecture, which relies on high-order analog filters and a fixed-frequency local oscillator signal source, presents the following issues: First, fixed-frequency interference often occurs in the intermediate frequency signal due to the second harmonic of the on-chip crystal oscillator, affecting the stability of the downconverted output; second, image interference cannot be effectively distinguished during spectrum aliasing, resulting in high bit error rates; third, the complex mixing structure composed of multipliers is inefficient in terminals with limited MCU resources, resulting in long operating cycles and high power consumption; and fourth, the overall link lacks adaptability, making it difficult to cope with interference scenarios in rapidly changing spectrum environments.

[0146] To address these issues, this embodiment employs the "IoT Digital Down-Conversion and Image Interference Reduction Method" proposed in this invention for receiver replacement deployment. In this new solution, each terminal is equipped with a low-power DSP module (TIMSP430FR5994), internally loaded with a lookup table digital local oscillator generation structure, a dual-channel notch filter, a complex mixing module, an image interference suppression module, an anti-aliasing FIR low-pass filter, and an amplitude normalization structure. The overall solution has an execution cycle of approximately 36μs, and average power consumption is reduced to 1.1mW, significantly outperforming the traditional architecture (execution cycle of 74μs, average power consumption of 3.4mW).

[0147] In specific applications, after the terminal receives RF data via a 433MHz antenna, it is first down-converted to a 1.25MHz intermediate frequency band. The analog-to-digital conversion module samples the data with a 5MHz clock to generate I / Q digital signals. The system effectively suppresses interference from the crystal oscillator's double frequency by setting a notch filter with a 100kHz bandwidth and a center notch frequency of 2.5MHz. A 2MHz quadrature local oscillator signal is then generated using a ROM lookup table and mixed with the I / Q signals to obtain the primary baseband signal. In the image suppression module, the system's six-channel multiply-add structure performs weighted image interference cancellation on the mixed signal. The result is then fed into an FIR low-pass filter with a passband set to 750kHz to remove sidebands and aliasing components.

[0148] In the amplitude normalization processing unit, the system uses signal envelope detection and dynamic range compression to stabilize the maximum amplitude of the input signal within 1.0±0.02, ensuring positive and negative polarity consistency. The signal then enters the QPSK modulation identification module. Simultaneously, all intermediate node data, such as the filter output power spectrum density and the image residual signal amplitude, are cached in on-chip Flash via DMA and transmitted back to the central gateway on a 16-hour cycle for parameter feedback and structural reconstruction.

[0149] Comparative testing showed that a terminal using the processing structure of the present invention achieved a bit error rate of 0.0082 under conditions of an 18dB signal-to-noise ratio, approximately 60 meters from the base station, and multiple mirror channel interference (frequency deviations of ±1.8MHz and ±2.0MHz). Compared to the bit error rate of 0.0357 using the traditional structure, the image leakage power decreased by 12.4dB, and the sideband energy decreased by 9.7dB. The long-term operational stability of the system has also been significantly improved. The feedback reconstruction cycle is triggered an average of once every three hours, and it can automatically adjust the local oscillator phase and filter passband based on daytime device switching noise and nighttime temperature drift and frequency deviation, maintaining the dynamic consistency of the overall spectrum processing.

[0150] Furthermore, the table-lookup multiplication structure occupies only 256 bytes of ROM, and after compression, only 128 bytes, reducing logic resource usage by approximately 82% compared to a traditional 16×16-bit multiplier array. The image suppression module consists of six groups of multiplication-add paths, each using only two adders and a constant lookup table entry, eliminating the need for a multiplication operator. This significantly reduces hardware complexity and power consumption.

[0151] This example fully demonstrates the feasibility and technical advantages of this invention in low-power IoT terminals. It successfully addresses key issues such as intermediate frequency interference, image aliasing, high computational complexity, and poor system rigidity, achieving a high-precision, low-cost, and highly stable IoT receive link optimization processing structure. This method has high practical value and is suitable for upgrading receiving systems in wide-area, low-power wireless communication scenarios such as industrial monitoring, smart agriculture, urban security, and energy meter reading.

[0152] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any technician familiar with the technical field, within the technical scope disclosed by the present invention, who makes equivalent replacements or changes based on the technical solution and inventive concept of the present invention, should be covered by the scope of protection of the present invention.

Claims

1. A method for digital down-conversion and anti-image interference of the Internet of Things, characterized in that: The steps include: S1. Build a digital receiving path for IoT terminals, perform analog down-conversion and analog-to-digital conversion on RF signals, and obtain low-IF I- and Q-channel orthogonal digital signals with a predetermined frequency range and sampling accuracy. S2. Input the I-channel and Q-channel orthogonal signals into the digital notch filter module respectively, perform band-stop attenuation operation on the interference frequency introduced by the crystal oscillator harmonics, and output the first intermediate frequency orthogonal signal after the interference is weakened; S3. Generate a digital local oscillator signal in a memory using a table lookup method, including discrete cosine waves and sine waves sampled at equal intervals, and set the output frequency to the target down-conversion frequency point to form a local orthogonal mixing reference signal; S4, respectively performing digital complex frequency mixing processing on the filtered I-channel and Q-channel signals and the local oscillator sine and cosine signals generated by the lookup table; S5. Inputting the mixing result into an image interference suppression module, which is composed of multiple sets of parallel multiplication and addition structures, performs weighted operations on the input signal based on preset image interference characteristics and structural parameters, and outputs a baseband candidate signal that has been subjected to image term suppression processing; S6. Inputting the image suppression signal into an anti-aliasing low-pass filter module, wherein the filter has a limited bandwidth and order design, suppresses sideband interference and spectrum image residues in the mixing process, and outputs a target baseband signal within the limited bandwidth; S7, performing amplitude normalization, polarity correction and dynamic range compression on the orthogonal signal output by the low-pass filter; S8. Input the obtained baseband signal into the communication protocol processing unit, cache and evaluate the intermediate data in the image suppression path, and dynamically adjust the filter parameters, mixing reference phase and weight configuration according to system feedback.

2. The method for digital down-conversion and anti-image interference of the Internet of Things according to claim 1, wherein: Said S1 specifically includes: S11, receiving a high-frequency wireless signal output by a radio frequency receiving unit in an IoT terminal, and sending the signal to an analog down-conversion module after suppressing adjacent channel interference through a bandpass filter; S12, in the analog down-conversion module, mixing the first local oscillator signal with the high-frequency signal to convert the signal frequency to a set intermediate frequency band, and output an analog intermediate frequency signal; S13, inputting the analog intermediate frequency signals into the orthogonal demodulators respectively, and demodulating to obtain orthogonal I-channel and Q-channel analog signals; S14, inputting the I-channel and Q-channel analog signals into an analog-to-digital conversion module, performing synchronous sampling using a unified sampling clock, and converting them into digital low-intermediate-frequency I-channel and Q-channel signals; S15 , performing amplitude normalization and code amplitude limitation on the I-channel and Q-channel digital signals, and outputting standardized orthogonal digital signals.

3. The method for digital down-conversion and anti-image interference of the Internet of Things according to claim 1, wherein: The S2 specifically includes: S21, inputting the analog-to-digital converted I and Q digital intermediate frequency signals into a first channel notch filter and a second channel notch filter, respectively, wherein the notch filter channels correspond to the I and Q signal paths, respectively, and have independent data input interfaces and clock control logic; S22, setting a preset notch frequency parameter and a bandwidth adjustment factor in the notch filter, and constructing a corresponding filter coefficient group based on the parameter configuration to generate a filter window for suppressing interference at a specific frequency point, wherein the notch frequency parameter can be set according to the crystal oscillator harmonic frequency; S23, constructing a finite impulse response filter unit using a symmetrical tap structure, and performing odd-even tap optimization and multiplication-addition calculation process streamlining processing on the structure; S24, synchronously controlling the input and output timings of the two channel filters by configuring the channel controller; S25 , buffering the I-channel and Q-channel signals that have undergone the notch processing to the data input buffer area of ​​the complex mixing module respectively, and marking them as the orthogonal intermediate frequency signal input ports after image interference preprocessing.

4. The method for digital down-conversion and anti-image interference of the Internet of Things according to claim 1, wherein: The S3 specifically includes: S31, constructing a local oscillator signal generation module, configuring a read-only memory for storing a table of sine and cosine sampling values ​​within a cycle, wherein the sampling values ​​are pre-calculated according to a fixed frequency and written into a table lookup storage unit; S32, setting the local oscillator output frequency parameter and the system main sampling clock frequency, determining the table lookup step control logic according to the ratio between the two, and mapping it to the address counter control module; S33, sequentially reading the sine and cosine sampling values ​​at corresponding positions in the read-only memory through a synchronous address generator, and outputting them as digital local oscillator orthogonal signals, respectively, wherein the orthogonal signals have phase difference and frequency stability characteristics; S34. Utilize the periodicity of the lookup table to perform a halved mapping of the address range, adopt a symmetrical storage optimization mechanism, retain only half-cycle sample data, and achieve complete sine and cosine wave reconstruction through logic inversion and amplitude compensation; S35 , outputting the generated orthogonal local oscillator signal to the input port of the complex frequency mixing module while maintaining its clock synchronization characteristics and period continuity.

5. The method for digital down-conversion and anti-image interference of the Internet of Things according to claim 1, wherein: The S4 specifically includes: S41, inputting the I-path signal and the Q-path signal outputted by the notch filter module into the first input channel and the second input channel of the complex frequency mixing module respectively, and inputting the sine signal and the cosine signal outputted by the local oscillator module into the local oscillator channel of the module at the same time; S42. In the complex mixing module, pair the I-channel signal with the cosine local oscillator signal, and pair the Q-channel signal with the sine local oscillator signal, and transmit them to two multiplication structure paths respectively to form an orthogonal mixing input pair; S43, constructing a table lookup multiplication and addition unit for multiplication operation, performing a time-series weighted multiplication operation on each pair of input data based on the synchronization index relationship between the input signal and the table lookup local oscillator signal, to generate a mixed intermediate signal; S44, using a sampling clock controller to coordinate the calculation rhythm and data synchronization of the two multiplication paths; S45 , sending the two mixed signals output by the multiplication path to the buffer interface and outputting them to the input port of the image interference suppression module.

6. The method for digital down-conversion and anti-image interference of the Internet of Things according to claim 1, wherein: The S5 specifically includes: S51, connecting the first orthogonal signal channel and the second orthogonal signal channel output by the complex mixing module to the input channel of the image interference suppression module respectively, wherein the module includes multiple parallel multiplication and addition processing units, each unit having an independent data path and coefficient control path; S52, setting a plurality of table lookup coefficient storage units inside the image interference suppression module, preloading filter weight parameters matching the characteristics of the image frequency band, and distributing them to the operation channels of the corresponding multiplication-addition structures according to preset instructions; S53, inputting the orthogonal mixing signal into each multiplication-addition channel respectively, performing multiplication operation with the image suppression weight coefficient according to the synchronous clock sequence, and accumulating the output results cycle by cycle through the addition-accumulation unit to form a weighted sum signal sequence; S54, setting a normalizer and a delay compensation module at the end of the multiplication-addition path to perform amplitude compression and timing synchronization processing on each weighted result; S55 , integrating and merging the image interference suppression signals output by all the multiplication-addition paths, outputting an orthogonal baseband signal with suppressed image interference, and transmitting the signal to the input interface of the low-pass filter module.

7. The method for digital down-conversion and anti-image interference of the Internet of Things according to claim 1, wherein: The S6 specifically includes: S61, inputting the orthogonal baseband signals output by the image interference suppression module into a first low-pass filter channel and a second low-pass filter channel, respectively, where the two channels correspond to the I and Q signal paths, respectively, and maintaining input synchronization; S62: setting the passband range, cutoff frequency, and order parameters in the low-pass filter module, generating a filter coefficient group based on a window function design method, writing the coefficients into the tap register of the filter structure, and performing a sliding window convolution operation; S63, using a multi-tap finite impulse response filter structure to process the input signal in real time, retaining the main frequency component of the baseband signal within the set bandwidth range, and suppressing the high-frequency interference, sideband noise and sampling aliasing signal components left after mixing; S64, using the delay alignment control logic embedded in the filter channel, monitors the difference in operation delay between the two channels in real time and dynamically compensates the output signal; S65 , buffering the I-path and Q-path baseband signals output by the low-pass filter, and writing the filter control parameters into the register interface.

8. The method for digital down-conversion and anti-image interference of the Internet of Things according to claim 1, wherein: The S7 specifically includes: S71, inputting the I-channel and Q-channel baseband signals output by the low-pass filtering module into the amplitude normalization processing module respectively, which has amplitude detection, amplitude adjustment, polarity processing and dynamic range mapping function channels; S72, extracting the amplitude envelope information of each input signal in the amplitude detection unit, calculating the current signal strength based on the detection result, and generating a normalized adjustment coefficient; S73. In the amplitude adjustment unit, perform an amplitude scaling operation on the input signal according to the normalized adjustment coefficient; S74. Monitoring the positive and negative sign states of the signals in the polarity processing module, performing sign correction operations on signals with amplitude inversion, unifying polarity directions, and eliminating mismatch errors caused by path asymmetry or system bias; S75 . Perform dynamic amplitude linear compression processing on the normalized signal in the dynamic range mapping unit to map the original amplitude space to a set low dynamic range.

9. The method for digital down-conversion and anti-image interference of the Internet of Things according to claim 1, wherein: The S8 specifically includes: S81, inputting the amplitude-normalized I and Q baseband signals into a digital demodulation module, performing modulation recognition, symbol decision or data restoration operations, and completing information extraction of the received signal; S82. Setting an intermediate data monitoring channel inside the image interference suppression module and the low-pass filter module to sample the operation results of key processing nodes in real time and cache them in the system log buffer according to the processing rounds; S83, extracting features from the intermediate data in the cache, interference-related parameters including channel output stability index, image suppression residual amplitude, and filter sideband leakage, and forming a feedback data set; S84. Based on the feedback data set result, the system control unit triggers a configuration update mechanism to adjust the weight coefficient, local oscillator frequency control word, and filter passband boundary parameters in the image suppression module online. S85. Write the updated configuration parameters into the register interface of the corresponding module, overwriting the old values.

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