Current driving circuit for brain nerve stimulation

Abstract

The invention discloses a current driving circuit for brain nerve stimulation. The current driving circuit comprises a positive-phase current pulse output circuit and a negative-phase current pulse output circuit, the normal-phase current pulse output circuit comprises a first low-voltage cascode current mirror module and a first auxiliary circuit module; the negative-phase current pulse output circuit comprises a second low-voltage cascode current mirror module and a second auxiliary circuit module; the first low-voltage cascode current mirror module and the second low-voltage cascode current mirror module are used for copying the current of the current source and then outputting positive-phase stimulation current or negative-phase stimulation current; the first auxiliary circuit module and the second auxiliary circuit module are used for expanding the feasible range of the bias voltage of the low-voltage cascode current mirror in the current driving circuit; a current monitoring circuit is additionally arranged to monitor the stimulation current, and it is ensured that the stimulation current is at a normal level; according to the invention, the output voltage range of the nerve stimulator is expanded, correct current copying in a full-swing range is realized, and the application scene of the nerve stimulator is wider.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a current driving circuit for brain nerve stimulation. Background Art

[0002] A major new study published in The Lancet Neurology reveals that in 2021, more than one-third of the world's population was affected by neurological diseases, making them one of the leading causes of illness and disability. With the advancement of neuromodulation technology, electrical nerve stimulation is widely used in the treatment of neuropsychiatric disorders such as epilepsy, Parkinson's disease, and essential tremor, demonstrating unique advantages such as minimal side effects, minimally invasive surgery, fewer complications, and controllable therapeutic effects.

[0003] Generally, a neurostimulator needs to output biphasic current pulses to reduce the body's irreversible reactions by balancing the charge. From a circuit design perspective, researchers prefer to use a bipolar stimulation structure to better balance the charge. However, bipolar neurostimulators consume a relatively large area, which is not conducive to large-scale integration. To address this problem, researchers have proposed many neurostimulators with unipolar stimulation structures, in which the current output drive circuit changes the current direction through a current mirror to output biphasic current pulses.

[0004] For example, a current driving circuit of a neurostimulator with a monopolar stimulation structure in the prior art is as follows: Figure 3 As shown in FIG, the current driving circuit includes a PMOS current mirror and an NMOS current mirror. Among them, the PMOS current mirror is a common cascode current mirror composed of PMOS transistors M6, PMOS transistors M7, PMOS transistors M11 and PMOS transistors M12. For the PMOS current mirror, that is, a common cascode current mirror, ignoring the bias effect and assuming that the transistors therein are the same, the voltage margin consumed by the common cascode current mirror is V GS7 +V GS6 -V TH =(V GS7 -V TH )+(V GS6 -V TH )+V TH , which is two overdrive voltages plus a threshold voltage; where V GS7 is the gate-source voltage of PMOS tube M7, V GS6 is the gate-source voltage of PMOS tube M6, V THis the threshold voltage of the MOS tube. Under the condition that the output voltage does not affect the saturation state of the current mirror, the ordinary cascode current mirror can achieve the correct replication of the full-swing stimulation current. However, the MOS tube M7 connected in a diode connection causes the voltage margin of the ordinary cascode current mirror to "waste" a threshold voltage. Similarly, the voltage margin of the NMOS current mirror in the current drive circuit also "wastes" a threshold voltage. Since the PMOS current mirror and the NMOS current mirror are directly connected to the output end of the neurostimulator, this causes the output voltage range of the neurostimulator to be reduced by two threshold voltages, which limits the stimulation amplitude and stimulation time of the neurostimulator, the electrode impedance range applicable to the neurostimulator is small, and the stimulation current is not constant. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a current driving circuit for brain nerve stimulation. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a current driving circuit for brain nerve stimulation, comprising: a positive phase current pulse output circuit and a negative phase current pulse output circuit;

[0007] The positive phase current pulse output circuit includes a first low-voltage cascode current mirror module and a first auxiliary circuit module; the first low-voltage cascode current mirror module is used to replicate the current of the current source and output the positive phase stimulation current; the first auxiliary circuit module is used to expand the feasible range of the bias voltage of the low-voltage cascode current mirror in the first low-voltage cascode current mirror module;

[0008] The negative phase current pulse output circuit includes a second low-voltage cascode current mirror module and a second auxiliary circuit module; the second low-voltage cascode current mirror module is used to replicate the current of the current source and output a negative phase stimulation current; the second auxiliary circuit module is used to increase the upper limit of the feasible range of the bias voltage of the low-voltage cascode current mirror in the second low-voltage cascode current mirror module;

[0009] The feasible range of the bias voltage of the low-voltage cascode current mirror is as follows: when the input current of the low-voltage cascode current mirror changes from minimum to maximum, the transistors of the low-voltage cascode current mirror can all operate in the saturation region.

[0010] Optionally, the first low-voltage cascode current mirror module includes a first low-voltage cascode current mirror and a third low-voltage cascode current mirror; the first auxiliary circuit module includes a first auxiliary circuit and a third auxiliary circuit;

[0011] The first low-voltage cascode current mirror is used to copy the current of the current source and output the copied current;

[0012] The third low-voltage cascode current mirror is used to replicate the replicated current and output the positive-phase stimulation current;

[0013] The first auxiliary circuit is used to increase the upper limit of a feasible range of the bias voltage of the first low-voltage cascode current mirror;

[0014] The third auxiliary circuit is used to reduce a lower limit of a feasible range of a bias voltage of the third low-voltage cascode current mirror.

[0015] Optionally, the first low-voltage cascode current mirror includes: a MOS transistor M3, a MOS transistor M5, a MOS transistor M11, and a MOS transistor M13; the MOS transistor M3, the MOS transistor M5, the MOS transistor M11, and the MOS transistor M13 are all NMOS transistors;

[0016] The drain of the MOS transistor M3 is connected to the current source, the source is connected to the drain of the MOS transistor M5, and the gate of the MOS transistor M5 is connected to the gate of the MOS transistor M11;

[0017] The gate of the MOS transistor M3 and the gate of the MOS transistor M13 are both connected to the first bias voltage, and the source of the MOS transistor M5 and the source of the MOS transistor M11 are both connected to the negative phase excitation voltage;

[0018] The source of the MOS transistor M13 is connected to the drain of the MOS transistor M11 , and the drain of the MOS transistor M13 serves as the output end of the first low-voltage cascode current mirror.

[0019] Optionally, the first auxiliary circuit includes: a MOS transistor M7 and a MOS transistor M9; both the MOS transistor M7 and the MOS transistor M9 are NMOS transistors;

[0020] The gate of the MOS transistor M7 is connected to the second bias voltage, the source is connected to the negative phase excitation voltage, and the drain is connected to the gate of the MOS transistor M5 and the source of the MOS transistor M9;

[0021] The gate of the MOS transistor M9 is connected to the drain of the MOS transistor M3 , and the drain of the MOS transistor M9 is connected to a negative internal voltage; the negative internal voltage is a voltage obtained by boosting the negative excitation voltage.

[0022] Optionally, the third low-voltage cascode current mirror includes: a MOS transistor M15, a MOS transistor M16, a MOS transistor M17, and a MOS transistor M18; the MOS transistor M15, the MOS transistor M16, the MOS transistor M17, and the MOS transistor M18 are all PMOS transistors;

[0023] The drain of the MOS transistor M15 is connected to the output end of the first low-voltage cascode current mirror, the source is connected to the drain of the MOS transistor M17, and the gate of the MOS transistor M17 is connected to the gate of the MOS transistor M18;

[0024] The gate of the MOS transistor M15 and the gate of the MOS transistor M16 are both connected to a third bias voltage, and the source of the MOS transistor M17 and the source of the MOS transistor M18 are both connected to a positive phase excitation voltage;

[0025] The source of the MOS transistor M16 is connected to the drain of the MOS transistor M18. The drain of the MOS transistor M16 is the output end of the positive phase current pulse output circuit, which is used to output the positive phase stimulation current.

[0026] Optionally, the third auxiliary circuit includes: a MOS transistor M19 and a MOS transistor M20; both the MOS transistor M19 and the MOS transistor M20 are PMOS transistors;

[0027] The gate of the MOS transistor M19 is connected to the fourth bias voltage, the source is connected to the positive phase excitation voltage, and the drain is connected to the gate of the MOS transistor M17 and the source of the MOS transistor M20;

[0028] The gate of the MOS transistor M20 is connected to the drain of the MOS transistor M15 , and the drain of the MOS transistor M20 is connected to a positive-phase internal voltage; the positive-phase internal voltage is a voltage obtained by stepping down the positive-phase excitation voltage.

[0029] Optionally, the second low-voltage cascode current mirror module includes: a MOS transistor M4, a MOS transistor M6, a MOS transistor M12, and a MOS transistor M14; the MOS transistor M4, the MOS transistor M6, the MOS transistor M12, and the MOS transistor M14 are all NMOS transistors;

[0030] The drain of the MOS transistor M4 is connected to the current source, the source is connected to the drain of the MOS transistor M6, and the gate of the MOS transistor M6 is connected to the gate of the MOS transistor M12;

[0031] The gate of the MOS transistor M4 and the gate of the MOS transistor M14 are both connected to the first bias voltage, and the source of the MOS transistor M6 and the source of the MOS transistor M12 are both connected to the negative phase excitation voltage;

[0032] The source of the MOS transistor M14 is connected to the drain of the MOS transistor M12 . The drain of the MOS transistor M14 is the output end of the negative phase current pulse output circuit, and is used to output the negative phase stimulation current.

[0033] Optionally, the second auxiliary circuit module includes: a MOS transistor M8 and a MOS transistor M10; both the MOS transistor M8 and the MOS transistor M10 are NMOS transistors;

[0034] The gate of the MOS transistor M8 is connected to the second bias voltage, the source is connected to the negative phase excitation voltage, and the drain is connected to the gate of the MOS transistor M6 and the source of the MOS transistor M10;

[0035] The gate of the MOS transistor M10 is connected to the drain of the MOS transistor M4 , and the drain of the MOS transistor M10 is connected to the negative phase internal voltage.

[0036] Optionally, the circuit further comprises: a current monitoring circuit;

[0037] The current monitoring circuit is used to monitor the working status of the positive phase current pulse output circuit and the negative phase current pulse output circuit, and output the monitoring result of whether the positive phase stimulation current or the negative phase stimulation current deviates from the set value.

[0038] Optionally, the current monitoring circuit includes: a MOS transistor M21, a MOS transistor M22, a MOS transistor M23, a MOS transistor M24, a MOS transistor M25, a MOS transistor M26, a MOS transistor M27, a MOS transistor M28, a MOS transistor M29, a MOS transistor M30, a MOS transistor M31, a MOS transistor M32, a MOS transistor M33, a MOS transistor M34, a resistor R1, a resistor R2, a resistor R3, a resistor R4, an inverter INV1, an inverter INV2, an inverter INV3, and a NAND gate NAND; the MOS transistors M21, M22, M23, M24, M28, M33, and M34 are all NMOS transistors; the MOS transistors M25, M26, M27, M29, M30, M31, and M32 are all PMOS transistors;

[0039] The source of the MOS transistor M21, the source of the MOS transistor M22, and the gate of the MOS transistor M27 are all connected to the positive phase internal voltage, the drain of the MOS transistor M21 is respectively connected to its gate and one end of the resistor R1, and the other end of the resistor R1 is connected to the positive phase excitation voltage;

[0040] The drain of the MOS transistor M22 is connected to the source of the MOS transistor M23 and the source of the MOS transistor M24, and the gate is connected to the gate of the MOS transistor M21.

[0041] The gate of the MOS transistor M23 is connected to the drain of the MOS transistor M17, and the drain of the MOS transistor M23, the source of the MOS transistor M25, and the source of the MOS transistor M26 are all connected to the positive phase excitation voltage;

[0042] The gate of the MOS transistor M25 is connected to its drain and the gate of the MOS transistor M26 respectively, the drain is connected to the drain of the MOS transistor M24, and the gate of the MOS transistor M24 is connected to the drain of the MOS transistor M18;

[0043] The source of the MOS transistor M27 is connected to the drain of the MOS transistor M26, the drain of the MOS transistor M27 is respectively connected to one end of the resistor R2 and the input end of the inverter INV1, the other end of the resistor R2 is connected to the ground end, and the output end of the inverter INV1 is connected to the first input end of the NAND gate NAND;

[0044] The resistor R3, the drain of the MOS transistor M31, the source of the MOS transistor M33, and the source of the MOS transistor M34 are all connected to the negative phase excitation voltage;

[0045] The gate of the MOS transistor M31 is connected to the source of the MOS transistor M4, and the source of the MOS transistor M31 is connected to the drain of the MOS transistor M30;

[0046] The drain of the MOS transistor M32 is connected to the drain of the MOS transistor M33, the source is connected to the drain of the MOS transistor M30, and the gate of the MOS transistor M32 is connected to the source of the MOS transistor M14;

[0047] The gate of the MOS transistor M33 is connected to its drain and the gate of the MOS transistor M34 respectively;

[0048] The source of the MOS transistor M29, the source of the MOS transistor M30, and the gate of the MOS transistor M28 are all connected to the negative internal voltage. The drain of the MOS transistor M29 is respectively connected to its gate and one end of the resistor R3, and the gate is connected to the gate of the MOS transistor M30.

[0049] The source of the MOS transistor M28 is connected to the drain of the MOS transistor M34, the drain is respectively connected to one end of the resistor R4 and the input end of the inverter INV2, and the other end of the resistor R4 is connected to a voltage source;

[0050] The output end of the inverter INV2 is connected to the input end of the inverter INV3, and the output end of the inverter INV3 is connected to the second input end of the NAND gate NAND;

[0051] The NAND gate NAND outputs the monitoring result.

[0052] The current driving circuit for brain nerve stimulation provided by the present invention utilizes a positive phase current pulse output circuit and a negative phase current pulse output circuit to output a positive phase stimulation current and a negative phase stimulation current respectively. The positive phase current pulse output circuit and the negative phase current pulse output circuit contain a low voltage cascode current mirror. The low voltage cascode current mirror reduces the voltage margin consumed by the current mirror by introducing a bias voltage, thereby improving the output voltage range of the current mirror. In addition, the present invention expands the feasible range of the bias voltage of the low voltage cascode current mirror by adding an auxiliary circuit, thereby overcoming the problem that the low voltage cascode current mirror cannot achieve correct current replication within the full swing range under a fixed bias voltage. Therefore, the current driving circuit improves the output voltage range of the neurostimulator, achieves correct current replication within the full swing range, obtains better stimulation amplitude and stimulation time, and makes the application scenario of the current driving circuit more extensive.

[0053] In addition, a current monitoring circuit can be added to the current driving circuit, through which the positive phase stimulation current and the negative phase stimulation current can be monitored in real time to see whether they deviate from the set value. When the stimulation current deviates from the set value, the operator can adjust the stimulation current level in time to ensure the normal implementation of the brain nerve stimulation treatment plan, which is conducive to the quantitative evaluation of brain nerve stimulation treatment. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 is a circuit diagram of a current driving circuit for brain nerve stimulation provided by an embodiment of the present invention;

[0055] Figure 2 This is a structural diagram of a low-voltage cascode current mirror provided by an embodiment of the present invention;

[0056] Figure 3 This is a circuit diagram of a current driving circuit of a neurostimulator with a traditional monopolar stimulation structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0057] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0058] In order to improve the output voltage range of the neurostimulator and achieve correct current replication within the full swing range, so that the application scenarios of the current driving circuit are more extensive, the embodiment of the present invention provides a current driving circuit for brain nerve stimulation, see Figure 1 , a current driving circuit for brain nerve stimulation provided by an embodiment of the present invention is described.

[0059] The current driving circuit for brain nerve stimulation provided by an embodiment of the present invention includes: a positive phase current pulse output circuit and a negative phase current pulse output circuit.

[0060] Among them, the positive phase current pulse output circuit includes a first low-voltage cascode current mirror module and a first auxiliary circuit module; the first low-voltage cascode current mirror module is used to replicate the current of the current source and output a positive phase stimulation current; the first auxiliary circuit module is used to expand the feasible range of the bias voltage of the low-voltage cascode current mirror in the first low-voltage cascode current mirror module.

[0061] A negative phase current pulse output circuit includes a second low-voltage cascode current mirror module and a second auxiliary circuit module; the second low-voltage cascode current mirror module is used to replicate the current of the current source and output a negative phase stimulation current; the second auxiliary circuit module is used to increase the upper limit of the feasible range of the bias voltage of the low-voltage cascode current mirror in the second low-voltage cascode current mirror module.

[0062] The feasible range of the bias voltage of the low-voltage cascode current mirror is as follows: when the input current of the low-voltage cascode current mirror changes from minimum to maximum, the transistors of the low-voltage cascode current mirror can all operate in the saturation region.

[0063] Specifically, the first low-voltage cascode current mirror module includes a first low-voltage cascode current mirror and a third low-voltage cascode current mirror; the first auxiliary circuit module includes a first auxiliary circuit and a third auxiliary circuit. The first low-voltage cascode current mirror is used to copy the current of the current source and output the copied current. The third low-voltage cascode current mirror is used to copy the copied current and output a positive-phase stimulation current. The first auxiliary circuit is used to increase the upper limit of the feasible range of the bias voltage of the first low-voltage cascode current mirror. The third auxiliary circuit is used to lower the lower limit of the feasible range of the bias voltage of the third low-voltage cascode current mirror.

[0064] In this embodiment, the current source is a programmable N-bit current output digital-to-analog converter (DAC), which provides a reference current I DAC To adapt to different stimulation situations, the reference current I DAC The step length I LSB Adjustable, current range is 0~(2 N -1)I LSB .

[0065] In one implementation, a PMOS transistor with a grounded gate can be added between the current source and the positive phase current pulse output circuit and the input of the positive phase current pulse output circuit to isolate the low voltage circuit from the high voltage circuit. Figure 1 In the figure, the PMOS tube M0 is such a low-voltage-high-voltage isolation tube.

[0066] In this embodiment, the current drive circuit includes multiple voltage domains, namely the low-voltage domain GND to VDD, the anode voltage domain, i.e., the positive-phase voltage domain VINTP(-) to VSTIMP(+), and the cathode voltage domain, i.e., the negative-phase voltage domain VSTIMN(-) to VINTN(+), wherein VSTIMP and VSTIMN, VINTP and VINTN are completely symmetrical about GND. VSTIMP represents the positive-phase excitation voltage, VINTP is the positive-phase internal voltage, VSTIMN is the negative-phase excitation voltage, and VINTN is the negative-phase internal voltage. Here, the positive-phase internal voltage VINTP is the voltage obtained by stepping down the positive-phase excitation voltage VSTIMP, and the negative-phase internal voltage VINTN is the voltage obtained by stepping up the negative-phase excitation voltage VSTIMN.

[0067] like Figure 1 As shown, the first low-voltage cascode current mirror includes: MOS transistor M3, MOS transistor M5, MOS transistor M11, and MOS transistor M13. Here, MOS transistor M3, MOS transistor M5, MOS transistor M11, and MOS transistor M13 are all NMOS transistors. Specifically, MOS transistor M3 and MOS transistor M13 are high-voltage NMOS transistors.

[0068] The drain of the MOS transistor M3 is connected to the current source, the source is connected to the drain of the MOS transistor M5, the gate of the MOS transistor M5 is connected to the gate of the MOS transistor M11; the gate of the MOS transistor M3 and the gate of the MOS transistor M13 are both connected to the first bias voltage V bn1 The source of the MOS transistor M5 and the source of the MOS transistor M11 are both connected to the negative phase excitation voltage VSTIMN; the source of the MOS transistor M13 is connected to the drain of the MOS transistor M11, and the drain of the MOS transistor M13 serves as the output end of the first low-voltage cascode current mirror.

[0069] like Figure 1 As shown, in this embodiment, the first auxiliary circuit is used to increase the first bias voltage V bn1 The upper limit of the feasible range enables the first low-voltage cascode current mirror to achieve correct current replication within the full swing range. The first auxiliary circuit includes: MOS transistor M7 and MOS transistor M9. Here, MOS transistor M7 and MOS transistor M9 are both NMOS transistors.

[0070] The gate of the MOS tube M7 is connected to the second bias voltage V bn2 The source is connected to the negative phase excitation voltage VSTIMN, the drain is connected to the gate of the MOS tube M5 and the source of the MOS tube M9; the gate of the MOS tube M9 is connected to the drain of the MOS tube M3, and the drain of the MOS tube M9 is connected to the negative phase internal voltage VINTN.

[0071] like Figure 1 As shown, in this embodiment, the third low-voltage cascode current mirror includes: MOS transistor M15, MOS transistor M16, MOS transistor M17, and MOS transistor M18. Here, MOS transistor M15, MOS transistor M16, MOS transistor M17, and MOS transistor M18 are all PMOS transistors. Specifically, MOS transistor M15 and MOS transistor M16 are high-voltage PMOS transistors.

[0072] The drain of the MOS transistor M15 is connected to the output end of the first low-voltage cascode current mirror, that is, the drain of the MOS transistor M13, the source is connected to the drain of the MOS transistor M17, and the gate of the MOS transistor M17 is connected to the gate of the MOS transistor M18; the gate of the MOS transistor M15 and the gate of the MOS transistor M16 are both connected to the third bias voltage V bp1 The source of the MOS tube M17 and the source of the MOS tube M18 are both connected to the positive phase excitation voltage VSTIMP; the source of the MOS tube M16 is connected to the drain of the MOS tube M18, and the drain of the MOS tube M16 is the output end of the positive phase current pulse output circuit, which is used to output the positive phase stimulation current I OUT-A .

[0073] like Figure 1 As shown, in this embodiment, the third auxiliary circuit is used to reduce the third bias voltage V of the third low-voltage cascode current mirror. bp1 The lower limit of the feasible range enables the third low-voltage cascode current mirror to achieve correct current replication within the full swing range. The third auxiliary circuit includes: MOS transistor M19 and MOS transistor M20. Here, MOS transistor M19 and MOS transistor M20 are both PMOS transistors.

[0074] The gate of the MOS tube M19 is connected to the fourth bias voltage V bp2 The source is connected to the positive phase excitation voltage VSTIMP, the drain is connected to the gate of the MOS tube M17 and the source of the MOS tube M20; the gate of the MOS tube M20 is connected to the drain of the MOS tube M15, and the drain of the MOS tube M20 is connected to the positive phase internal voltage VINTP.

[0075] like Figure 1 As shown, in this embodiment, the second low-voltage cascode current mirror module includes a second low-voltage cascode current mirror, which is used to copy the current I DAC , output negative stimulation current I OUT-C The second low-voltage cascode current mirror module includes: MOS transistor M4, MOS transistor M6, MOS transistor M12, and MOS transistor M14. Here, MOS transistor M4, MOS transistor M6, MOS transistor M12, and MOS transistor M14 are all NMOS transistors. Specifically, MOS transistor M4 and MOS transistor M14 are high-voltage NMOS transistors.

[0076] The drain of the MOS transistor M4 is connected to the current source, the source is connected to the drain of the MOS transistor M6, the gate of the MOS transistor M6 is connected to the gate of the MOS transistor M12; the gate of the MOS transistor M4 and the gate of the MOS transistor M14 are both connected to the first bias voltage V bn1 The source of the MOS tube M6 and the source of the MOS tube M12 are both connected to the negative phase excitation voltage VSTIMN; the source of the MOS tube M14 is connected to the drain of the MOS tube M12, and the drain of the MOS tube M14 is the output end of the negative phase current pulse output circuit, which is used to output the negative phase stimulation current I OUT-C .

[0077] like Figure 1 As shown, in this embodiment, the second auxiliary circuit module includes: a MOS transistor M8 and a MOS transistor M10. Here, the MOS transistor M8 and the MOS transistor M10 are both NMOS transistors.

[0078] The gate of the MOS tube M8 is connected to the second bias voltage V bn2 The source is connected to the negative phase excitation voltage VSTIMN, the drain is connected to the gate of the MOS tube M6 and the source of the MOS tube M10; the gate of the MOS tube M10 is connected to the drain of the MOS tube M4, and the drain of the MOS tube M10 is connected to the negative phase internal voltage VINTN.

[0079] In this embodiment, the second auxiliary circuit module is used to increase the first bias voltage V of the second low-voltage cascode current mirror. bn1 The upper limit of the feasible range of the second low-voltage cascode current mirror can achieve correct current replication within the full swing range.

[0080] In practice, the output end of the positive phase current pulse output circuit and the output end of the negative phase current pulse output circuit are both connected to the electrodes of the neurostimulator to apply brain nerve stimulation to the patient through the electrodes. Therefore, by controlling the switch tube M1 and the switch tube M2, it is possible to select the current path as the positive phase current pulse output circuit or the negative phase current pulse output circuit, and output the positive phase stimulation current I accordingly. OUT-A Or the negative stimulation current I OUT-C , thereby outputting the positive phase stimulation current I alternately OUT-A and negative stimulation current I OUT-C Generates biphasic pulse current.

[0081] Furthermore, taking the second low-voltage cascode current mirror module as an example, the principle of expanding the feasible range of the bias voltage of the low-voltage cascode current mirror by the auxiliary circuit is explained, so that the first low-voltage cascode current mirror, the second low-voltage cascode current mirror and the third low-voltage cascode current mirror can achieve correct current replication within the full swing range.

[0082] Here, the problem of applying the second low-voltage cascode current mirror in a wide current range is first analyzed.

[0083] Depend on Figure 2 It can be seen that the conditions for MOS tube M6 to work in the saturation region are:

[0084] V bn1 -V GS4 ≥V GS6 -V TH6 ;(1)

[0085] Among them, V bn1 is the first bias voltage, V GS4 is the gate-source voltage of MOS tube M4, V GS6 is the gate-source voltage of MOS tube M6, V TH6 is the threshold voltage of the MOS tube M6.

[0086] The conditions for MOS tube M4 to work in the saturation region are:

[0087] V bn1 -V TH4 ≤V GS6 ;(2)

[0088] Among them, V TH4 is the threshold voltage of the MOS tube M4.

[0089] From formula (1) and formula (2), it can be obtained that when MOS tube M4 and MOS tube M6 work in the saturation region, V bn1 The conditions that need to be met are:

[0090] V GS4 +V GS6 -V TH6 ≤V bn1 ≤V GS6 +V TH4 (3)

[0091] Since the reference current I DAC The step length is I LSB , the current range is 0~(2 N -1)I LSB , without considering the current is 0, the current I DAC The minimum value is I LSB , the maximum value is (2 N -1)I LSB Therefore, the gate-source voltage of the corresponding MOS tube M6 reaches the minimum value V GS6,min and maximum value V GS6,max .

[0092] In order to make 0~(2 N-1)I LSB The current within the range can be correctly copied, V GS6,max Determines V in formula (3) bn1 The lower limit of the range, V GS6,min Decided V bn1 The upper limit of the range, that is, V bn1 Need to meet:

[0093] V GS4 +V GS6,max -V TH6 ≤V bn1 ≤V GS6,min +V TH4 ;(4)

[0094] Among them, V GS6,min is the minimum value that the gate-source voltage of MOS tube M6 can reach, V GS6,max It is the maximum value that the gate-source voltage of MOS tube M6 can reach.

[0095] According to the MOS tube saturation current formula, we can get:

[0096]

[0097] Among them, μ n is the electron mobility of MOS tube M6, C ox is the gate oxide capacitance per unit area of ​​the MOS transistor M6, and (W / L)6 is the ratio of the channel width to the length of the MOS transistor M6.

[0098] From formula (5) and formula (6), we can see that V GS6,min and V GS6,max difference Overdrive voltage. In general, N in the current source is ≥ 6. Therefore, when N takes the minimum value, that is, N = 6, V GS6,min and V GS6,max The difference is 7 overdrive voltages, that is, V GS6,min and V GS6,max The difference is at least 7 overdrive voltages.

[0099] By adjusting the size of MOS tube M4, the following can be achieved:

[0100] V GS4 -V TH4 ≤V TH6 ;(7)

[0101] However, even this cannot offset V GS6,min and V GS6,max The gap between them, that is, V in formula (4) bn1 The upper limit voltage is less than the lower limit voltage, and there is no V bn1Make 0~(2 N -1)I LSB Currents within the range can be reproduced correctly.

[0102] In order to solve the above problem, the present invention increases the first bias voltage V by adding a second auxiliary circuit module. bn1 The upper limit of the feasible range. Figure 1 As shown, the second auxiliary circuit module is composed of NMOS transistor M8 and NMOS transistor M10. The gate of MOS transistor M6, the gate of MOS transistor M12 and the drain of MOS transistor M4 are connected through the source follower MOS transistor M10 and are subjected to the second bias voltage V bn2 The biased MOS tube M8 provides a current path for the MOS tube M10. At this time, the V bn1 Need to meet:

[0103] V GS4 +V GS6,max -V TH6 ≤V bn1 ≤V GS6,min +V TH4 +V GS10 ;(8)

[0104] Comparing equations (4) and (8), we can see that the addition of source follower MOS tube M10 increases V bn1 The upper limit of the feasible range increases the gate-source voltage V of a MOS tube M10 GS10 Therefore, by adjusting the second bias voltage V bn2 The size of MOS tube M10 is V GS10 By setting, equation (8) can have a feasible solution in the full swing current range. bn1 .

[0105] Similarly, since the third low-voltage cascode current mirror is a PMOS current mirror, the second low-voltage cascode current mirror is an NMOS current mirror, and the third low-voltage cascode current mirror and the second low-voltage cascode current mirror are completely symmetrical in structure, the lower limit of the feasible range of the bias voltage of the third low-voltage cascode current mirror is reduced by the third auxiliary circuit, thereby achieving correct current replication within the full swing range.

[0106] Furthermore, in order to minimize the voltage margin consumed by the second low-voltage cascode current mirror, V bn1 Take the lower limit of its range, that is, V bn1,min =V GS4 +V GS6,max -V TH6 At this time, the voltage margin consumed by the second low-voltage cascode current mirror is V bn1,min -V TH4 =V GS4-V TH4 +V GS6,max -V TH6 .

[0107] It can be seen that the voltage margin consumed by the second low-voltage cascode current mirror is two overdrive voltages. That is to say, by adding the second auxiliary circuit module, the voltage margin consumed by the second low-voltage cascode current mirror is reduced by one threshold voltage while ensuring that the full swing current range is correctly replicated. In other words, the output voltage range of the negative phase current pulse output circuit is increased by one threshold voltage. Similarly, since the auxiliary circuit design is also used in the positive phase current pulse output circuit, the output voltage range of the positive phase current pulse output circuit is also increased by one threshold voltage. Therefore, Figure 3 Compared with the current driving circuit of the traditional monopolar stimulation structure of the neurostimulator shown in FIG, the current driving circuit proposed in the present invention can increase the output voltage range of the neurostimulator by two threshold voltages and realize the correct replication of the current under the full swing range.

[0108] In practice, the current driving circuit passes through the output terminal V E It is connected to the electrode of the neurostimulator. As the stimulation current is continuously injected into the electrode, when the electrode voltage rises to a level that cannot meet the voltage margin of the cascode current mirror, the cascode tube in the current mirror enters the linear region, causing the cascode current mirror to be unable to correctly copy the current, thereby causing the stimulation current to deviate from the set value, making the stimulation current smaller than the set value, and the stimulation effect is also weakened, affecting the nerve stimulation effect.

[0109] To address the aforementioned issues, the present invention incorporates a current monitoring circuit into the current drive circuit to monitor the operating status of the positive-phase current pulse output circuit and the negative-phase current pulse output circuit. This circuit then outputs a monitoring result indicating whether the positive-phase stimulation current or the negative-phase stimulation current deviates from a set value. This current monitoring circuit then monitors and evaluates the neurostimulation treatment process. This allows the operator to be promptly notified if the stimulation current in the current drive circuit deviates from the set value, allowing them to adjust the stimulation current level promptly, ensuring the proper implementation of the brain neurostimulation treatment plan.

[0110] Specifically, such as Figure 1 As shown, the current monitoring circuit includes: a MOS transistor M21, a MOS transistor M22, a MOS transistor M23, a MOS transistor M24, a MOS transistor M25, a MOS transistor M26, a MOS transistor M27, a MOS transistor M28, a MOS transistor M29, a MOS transistor M30, a MOS transistor M31, a MOS transistor M32, a MOS transistor M33, a MOS transistor M34, a resistor R1, a resistor R2, a resistor R3, a resistor R4, an inverter INV1, an inverter INV2, an inverter INV3, and a NAND gate NAND.

[0111] Here, MOS transistors M21, M22, M23, M24, M28, M33, and M34 are all NMOS transistors; MOS transistors M25, M26, M27, M29, M30, M31, and M32 are all PMOS transistors. MOS transistor M27 is a high-voltage PMOS transistor, and MOS transistor M28 is a high-voltage NMOS transistor.

[0112] The source of the MOS transistor M21, the source of the MOS transistor M22, and the gate of the MOS transistor M27 are all connected to the positive internal voltage VINTP. The drain of the MOS transistor M21 is respectively connected to its gate and one end of the resistor R1, and the other end of the resistor R1 is connected to the positive excitation voltage VSTIMP. The drain of the MOS transistor M22 is respectively connected to the source of the MOS transistor M23 and the source of the MOS transistor M24, and the gate is connected to the gate of the MOS transistor M21. The gate of the MOS transistor M23 is connected to the drain of the MOS transistor M17, and the drain of the MOS transistor M23 and the source of the MOS transistor M25 are connected to the positive excitation voltage VSTIMP. The gate of the MOS transistor M25 is connected to its drain and the gate of the MOS transistor M26 respectively, the drain is connected to the drain of the MOS transistor M24, and the gate of the MOS transistor M24 is connected to the drain of the MOS transistor M18; the source of the MOS transistor M27 is connected to the drain of the MOS transistor M26, and the drain of the MOS transistor M27 is respectively connected to one end of the resistor R2 and the input end of the inverter INV1, the other end of the resistor R2 is connected to the ground end, and the output end of the inverter INV1 is connected to the first input end of the NAND gate NAND.

[0113] The resistor R3, the drain of the MOS transistor M31, the source of the MOS transistor M33, and the source of the MOS transistor M34 are all connected to the negative phase excitation voltage VSTIMN; the gate of the MOS transistor M31 is connected to the source of the MOS transistor M4, and the source of the MOS transistor M31 is connected to the drain of the MOS transistor M30; the drain of the MOS transistor M32 is connected to the drain of the MOS transistor M33, and the source is connected to the drain of the MOS transistor M30; the gate of the MOS transistor M32 is connected to the source of the MOS transistor M14; the gate of the MOS transistor M33 is respectively connected to its drain and the gate of the MOS transistor M34; the source of the MOS transistor M29, the MOS transistor M31 and the gate of the MOS transistor M30 are connected. The source of the MOS transistor M30 and the gate of the MOS transistor M28 are both connected to the negative internal voltage VINTN. The drain of the MOS transistor M29 is respectively connected to its gate and one end of the resistor R3, and the gate is connected to the gate of the MOS transistor M30. The source of the MOS transistor M28 is connected to the drain of the MOS transistor M34, and the drain is respectively connected to one end of the resistor R4 and the input end of the inverter INV2. The other end of the resistor R4 is connected to the voltage source. The output end of the inverter INV2 is connected to the input end of the inverter INV3. The output end of the inverter INV3 is connected to the second input end of the NAND gate NAND. The NAND gate NAND outputs the monitoring result.

[0114] Specifically, when the NAND gate NAND outputs a low level, it indicates that the positive phase stimulation current I OUT-A or negative stimulation current I OUT-C It is at a normal level and does not deviate from the set value; when the NAND gate NAND outputs a high level, it means the positive phase stimulation current I OUT-A or negative stimulation current I OUT-C Deviation from the set value. Therefore, in practice, the output of the NAND gate can be connected to a host computer or an alarm module, so that the monitoring results can be notified to the operator through the host computer or the alarm module. In addition, the above-mentioned set value refers to the range of the stimulation current output by the neurostimulator set by the operator during brain nerve stimulation treatment. In practice, the operator can set the stimulation current by controlling the current output by the current source.

[0115] The following describes the working principle of the current monitoring circuit for monitoring the positive phase stimulation current and the negative phase stimulation current and outputting the monitoring results.

[0116] like Figure 1 As shown, the current monitoring circuit includes two parts, namely the positive phase current monitoring circuit and the negative phase current monitoring circuit. In the positive phase current monitoring circuit, the current mirror composed of the resistor R1, the MOS tube M21 and the MOS tube M22 generates the tail current I d1 MOS transistor M23 and MOS transistor M24 convert the voltages at points A and B of the third low-voltage cascode current mirror into currents I1 and I2 respectively, and I1+I2=I d1 .

[0117] Similarly, the negative phase current monitoring circuit is completely symmetrical with the positive phase current monitoring circuit. The current mirror composed of resistor R3, MOS tube M29 and MOS tube M30 generates tail current I d2 MOS transistor M31 and MOS transistor M32 convert the voltages at points C and D of the second low-voltage cascode current mirror into currents I3 and I4, respectively, and I3+I4=I d2 .

[0118] When the positive phase stimulation current is applied, the third low voltage cascode current mirror outputs the positive phase stimulation current I OUT-A , the electrode voltage shifts toward the positive phase voltage domain. Under normal circumstances, the voltage at point A is close to the voltage at point B, and the gate-source voltages of MOS tube M23 and MOS tube M24 are equal. When both work in the saturation region, the tail current I d1 The current is split according to the width-to-length ratio of the MOS tube M23 and the MOS tube M24, which is K:1. Therefore, the current flowing through the MOS tube M24 is

[0119] At this point, current I2 is copied to resistor R2 via the PMOS current mirror formed by MOS transistors M25 and M26. When the voltage drop I2R2 across resistor R2 is less than the threshold voltage of inverter INV1, inverter INV1 outputs a high level. Simultaneously, no current flows through the second low-voltage cascode current mirror, and the voltage at point D remains higher than the voltage at point C, causing I4R4 to be significantly lower than the inverter's threshold voltage. After passing through inverters INV2 and INV3, the current outputs a high level. Ultimately, the current monitoring circuit outputs a low level, indicating that the stimulus current is at a normal level and has not deviated from the set value.

[0120] During the positive current stimulation process, when the electrode voltage of the neurostimulator exceeds the output voltage range of the neurostimulator, the common-gate transistor MOS tube M16 of the third low-voltage common-source common-gate current mirror enters the linear region, and the stimulation current decreases compared to the set value. It begins to compress the voltage at point B to approach the positive-phase excitation voltage VSTIMP, causing the gate-source voltage of the MOS tube M24 to increase, and the current flowing through the MOS tube M24 increases. The voltage drop across the resistor R2 increases, and when the current I2 increases to a point where the voltage drop across R2 is greater than the threshold voltage of the inverter INV1, the inverter INV1 outputs a low level. At this point, the second low-voltage common-source common-gate current mirror and the negative-phase current monitoring circuit are in normal working order, so the inverter INV3 outputs a high level. Finally, the current monitoring circuit outputs a high level, indicating that the stimulation current deviates from the set value.

[0121] Similarly, when the negative current is stimulated, the second low-voltage cascode current mirror module outputs the negative stimulation current I OUT-C, no current flows through the third low-voltage cascode current mirror, and the electrode voltage of the neurostimulator shifts to the negative phase voltage domain. At this time, if the negative phase stimulation current I OUT-C If the negative stimulus current I OUT-C When the current is at a normal level and does not deviate from the set value, the inverter INV3 outputs a high level and the current monitoring circuit outputs a low level.

[0122] In the present invention, the current monitoring circuit can be used to monitor in real time whether the positive phase stimulation current and the negative phase stimulation current deviate from the set value. When the stimulation current deviates from the set value, the operator can adjust the stimulation current level in time to ensure the normal implementation of the brain nerve stimulation treatment plan, which is conducive to the quantitative evaluation of the brain nerve stimulation treatment.

[0123] The current driving circuit for brain nerve stimulation provided by the present invention utilizes a positive phase current pulse output circuit and a negative phase current pulse output circuit to output a positive phase stimulation current and a negative phase stimulation current respectively. The positive phase current pulse output circuit and the negative phase current pulse output circuit contain a low voltage cascode current mirror. The low voltage cascode current mirror reduces the voltage margin consumed by the current mirror by introducing a bias voltage, thereby improving the output voltage range of the current mirror. In addition, the present invention expands the feasible range of the bias voltage of the low voltage cascode current mirror by adding an auxiliary circuit, thereby overcoming the problem that the low voltage cascode current mirror cannot achieve correct current replication within the full swing range under a fixed bias voltage. Therefore, the current driving circuit improves the output voltage range of the neurostimulator, achieves correct current replication within the full swing range, obtains better stimulation amplitude and stimulation time, and makes the application scenario of the current driving circuit more extensive.

[0124] In addition, a current monitoring circuit can be added to the current driving circuit, through which the positive phase stimulation current and the negative phase stimulation current can be monitored in real time to see whether they deviate from the set value. When the stimulation current deviates from the set value, the operator can adjust the stimulation current level in time to ensure the normal implementation of the brain nerve stimulation treatment plan, which is conducive to the quantitative evaluation of brain nerve stimulation treatment.

[0125] It should be noted that the terms "first," "second," and the like are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in sequences other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention.

[0126] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0127] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the word "comprising" does not exclude other components or steps, "one" or "a" does not exclude multiple situations, and "multiple" means two or more, unless otherwise clearly and specifically defined. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0128] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A current driving circuit for brain nerve stimulation, characterized in that: include: Positive phase current pulse output circuit and negative phase current pulse output circuit; The positive phase current pulse output circuit includes a first low voltage cascode current mirror module and a first auxiliary circuit module; The first low-voltage cascode current mirror module is used to replicate the current of the current source and output a positive-phase stimulation current; the first auxiliary circuit module is used to expand the feasible range of the bias voltage of the low-voltage cascode current mirror in the first low-voltage cascode current mirror module; The negative phase current pulse output circuit includes a second low-voltage cascode current mirror module and a second auxiliary circuit module; The second low-voltage cascode current mirror module is used to replicate the current of the current source and output a negative-phase stimulation current; the second auxiliary circuit module is used to increase the upper limit of the feasible range of the bias voltage of the low-voltage cascode current mirror in the second low-voltage cascode current mirror module; The feasible range of the bias voltage of the low-voltage cascode current mirror is as follows: when the input current of the low-voltage cascode current mirror changes from minimum to maximum, the transistors of the low-voltage cascode current mirror can all operate in the saturation region.

2. The current driving circuit for brain nerve stimulation according to claim 1, characterized in that: The first low-voltage cascode current mirror module includes a first low-voltage cascode current mirror and a third low-voltage cascode current mirror; the first auxiliary circuit module includes a first auxiliary circuit and a third auxiliary circuit; The first low-voltage cascode current mirror is used to copy the current of the current source and output the copied current; The third low-voltage cascode current mirror is used to replicate the replicated current and output the positive-phase stimulation current; The first auxiliary circuit is used to increase the upper limit of a feasible range of the bias voltage of the first low-voltage cascode current mirror; The third auxiliary circuit is used to reduce a lower limit of a feasible range of a bias voltage of the third low-voltage cascode current mirror.

3. The current driving circuit for brain nerve stimulation according to claim 2, characterized in that: The first low-voltage cascode current mirror includes: a MOS transistor M3, a MOS transistor M5, a MOS transistor M11, and a MOS transistor M13; the MOS transistor M3, the MOS transistor M5, the MOS transistor M11, and the MOS transistor M13 are all NMOS transistors; The drain of the MOS transistor M3 is connected to the current source, the source is connected to the drain of the MOS transistor M5, and the gate of the MOS transistor M5 is connected to the gate of the MOS transistor M11; The gate of the MOS transistor M3 and the gate of the MOS transistor M13 are both connected to the first bias voltage, and the source of the MOS transistor M5 and the source of the MOS transistor M11 are both connected to the negative phase excitation voltage; The source of the MOS transistor M13 is connected to the drain of the MOS transistor M11 , and the drain of the MOS transistor M13 serves as the output end of the first low-voltage cascode current mirror.

4. The current driving circuit for brain nerve stimulation according to claim 3, characterized in that: The first auxiliary circuit includes: a MOS transistor M7 and a MOS transistor M9; both the MOS transistor M7 and the MOS transistor M9 are NMOS transistors; The gate of the MOS transistor M7 is connected to the second bias voltage, the source is connected to the negative phase excitation voltage, and the drain is connected to the gate of the MOS transistor M5 and the source of the MOS transistor M9; The gate of the MOS transistor M9 is connected to the drain of the MOS transistor M3 , and the drain of the MOS transistor M9 is connected to a negative internal voltage; the negative internal voltage is a voltage obtained by boosting the negative excitation voltage.

5. The current driving circuit for brain nerve stimulation according to claim 4, characterized in that: The third low-voltage cascode current mirror includes: a MOS transistor M15, a MOS transistor M16, a MOS transistor M17, and a MOS transistor M18; the MOS transistor M15, the MOS transistor M16, the MOS transistor M17, and the MOS transistor M18 are all PMOS transistors; The drain of the MOS transistor M15 is connected to the output end of the first low-voltage cascode current mirror, the source is connected to the drain of the MOS transistor M17, and the gate of the MOS transistor M17 is connected to the gate of the MOS transistor M18; The gate of the MOS transistor M15 and the gate of the MOS transistor M16 are both connected to a third bias voltage, and the source of the MOS transistor M17 and the source of the MOS transistor M18 are both connected to a positive phase excitation voltage; The source of the MOS transistor M16 is connected to the drain of the MOS transistor M18. The drain of the MOS transistor M16 is the output end of the positive phase current pulse output circuit, which is used to output the positive phase stimulation current.

6. The current driving circuit for brain nerve stimulation according to claim 5, characterized in that: The third auxiliary circuit includes: a MOS transistor M19 and a MOS transistor M20; both the MOS transistor M19 and the MOS transistor M20 are PMOS transistors; The gate of the MOS transistor M19 is connected to the fourth bias voltage, the source is connected to the positive phase excitation voltage, and the drain is connected to the gate of the MOS transistor M17 and the source of the MOS transistor M20; The gate of the MOS transistor M20 is connected to the drain of the MOS transistor M15 , and the drain of the MOS transistor M20 is connected to a positive-phase internal voltage; the positive-phase internal voltage is a voltage obtained by stepping down the positive-phase excitation voltage.

7. The current driving circuit for brain nerve stimulation according to claim 6, characterized in that: The second low-voltage cascode current mirror module includes: a MOS transistor M4, a MOS transistor M6, a MOS transistor M12, and a MOS transistor M14; the MOS transistor M4, the MOS transistor M6, the MOS transistor M12, and the MOS transistor M14 are all NMOS transistors; The drain of the MOS transistor M4 is connected to the current source, the source is connected to the drain of the MOS transistor M6, and the gate of the MOS transistor M6 is connected to the gate of the MOS transistor M12; The gate of the MOS transistor M4 and the gate of the MOS transistor M14 are both connected to the first bias voltage, and the source of the MOS transistor M6 and the source of the MOS transistor M12 are both connected to the negative phase excitation voltage; The source of the MOS transistor M14 is connected to the drain of the MOS transistor M12 . The drain of the MOS transistor M14 is the output end of the negative phase current pulse output circuit, and is used to output the negative phase stimulation current.

8. The current driving circuit for brain nerve stimulation according to claim 7, characterized in that: The second auxiliary circuit module includes: a MOS transistor M8 and a MOS transistor M10; both the MOS transistor M8 and the MOS transistor M10 are NMOS transistors; The gate of the MOS transistor M8 is connected to the second bias voltage, the source is connected to the negative phase excitation voltage, and the drain is connected to the gate of the MOS transistor M6 and the source of the MOS transistor M10; The gate of the MOS transistor M10 is connected to the drain of the MOS transistor M4 , and the drain of the MOS transistor M10 is connected to the negative phase internal voltage.

9. The current driving circuit for brain nerve stimulation according to claim 8, characterized in that: The circuit further comprises: a current monitoring circuit; The current monitoring circuit is used to monitor the working status of the positive phase current pulse output circuit and the negative phase current pulse output circuit, and output the monitoring result of whether the positive phase stimulation current or the negative phase stimulation current deviates from the set value.

10. The current driving circuit for brain nerve stimulation according to claim 9, characterized in that: The current monitoring circuit includes: a MOS transistor M21, a MOS transistor M22, a MOS transistor M23, a MOS transistor M24, a MOS transistor M25, a MOS transistor M26, a MOS transistor M27, a MOS transistor M28, a MOS transistor M29, a MOS transistor M30, a MOS transistor M31, a MOS transistor M32, a MOS transistor M33, a MOS transistor M34, a resistor R1, a resistor R2, a resistor R3, a resistor R4, an inverter INV1, an inverter INV2, an inverter INV3, and a NAND gate NAND; the MOS transistors M21, M22, M23, M24, M28, M33, and M34 are all NMOS transistors; the MOS transistors M25, M26, M27, M29, M30, M31, and M32 are all PMOS transistors; The source of the MOS transistor M21, the source of the MOS transistor M22, and the gate of the MOS transistor M27 are all connected to the positive phase internal voltage, the drain of the MOS transistor M21 is respectively connected to its gate and one end of the resistor R1, and the other end of the resistor R1 is connected to the positive phase excitation voltage; The drain of the MOS transistor M22 is connected to the source of the MOS transistor M23 and the source of the MOS transistor M24, and the gate is connected to the gate of the MOS transistor M21. The gate of the MOS transistor M23 is connected to the drain of the MOS transistor M17, and the drain of the MOS transistor M23, the source of the MOS transistor M25, and the source of the MOS transistor M26 are all connected to the positive phase excitation voltage; The gate of the MOS transistor M25 is connected to its drain and the gate of the MOS transistor M26 respectively, the drain is connected to the drain of the MOS transistor M24, and the gate of the MOS transistor M24 is connected to the drain of the MOS transistor M18; The source of the MOS transistor M27 is connected to the drain of the MOS transistor M26, the drain of the MOS transistor M27 is respectively connected to one end of the resistor R2 and the input end of the inverter INV1, the other end of the resistor R2 is connected to the ground end, and the output end of the inverter INV1 is connected to the first input end of the NAND gate NAND; The resistor R3, the drain of the MOS transistor M31, the source of the MOS transistor M33, and the source of the MOS transistor M34 are all connected to the negative phase excitation voltage; The gate of the MOS transistor M31 is connected to the source of the MOS transistor M4, and the source of the MOS transistor M31 is connected to the drain of the MOS transistor M30; The drain of the MOS transistor M32 is connected to the drain of the MOS transistor M33, the source is connected to the drain of the MOS transistor M30, and the gate of the MOS transistor M32 is connected to the source of the MOS transistor M14; The gate of the MOS transistor M33 is connected to its drain and the gate of the MOS transistor M34 respectively; The source of the MOS transistor M29, the source of the MOS transistor M30, and the gate of the MOS transistor M28 are all connected to the negative internal voltage. The drain of the MOS transistor M29 is respectively connected to its gate and one end of the resistor R3, and the gate is connected to the gate of the MOS transistor M30. The source of the MOS transistor M28 is connected to the drain of the MOS transistor M34, the drain is respectively connected to one end of the resistor R4 and the input end of the inverter INV2, and the other end of the resistor R4 is connected to a voltage source; The output end of the inverter INV2 is connected to the input end of the inverter INV3, and the output end of the inverter INV3 is connected to the second input end of the NAND gate NAND; The NAND gate NAND outputs the monitoring result.

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