Widely controllable intrinsic MOSFET cascode current mirror

Abstract

Methods and apparatus for a cascode current mirror with a large modulation range, low headroom voltage, and high output impedance are presented. An input branch of the current mirror comprises a compound transistor in series with an intrinsic transistor. The compound transistor comprises two regular transistors connected in series, each with dimensions twice that of the intrinsic transistor. An output branch of the current mirror comprises a regular transistor in series with an intrinsic transistor. A gate voltage of the compound transistor, provided at a node common to the gates of the two series-connected regular transistors, self-adjusts when a reference current flows through the input branch. This self-adjusted gate voltage is used to bias the regular transistor of the output branch.Preloads for the gates of the intrinsic transistors are provided by an intermediate node, which provides the series connection of the regular transistors of the compound transistor.

Description

CROSS-REFERENCE TO RELATED REGISTRATIONS

[0001] The present application claims the priority and benefit of the concurrently pending US application No. 18 / 160,536 entitled “Wide-Swing Intrinsic MOSFET Cascode Current Mirror”, which was filed on January 27, 2023, and the disclosure of which is hereby incorporated in its entirety by reference. TECHNICAL AREA

[0002] The present disclosure relates to electronic circuits, in particular cascode current mirrors with low headroom voltage and high output impedance, to enable an output voltage with a large modulation range. BACKGROUND

[0003] With the advent of nanometer-scale technologies (i.e., < 90 nm), electronic circuits may need to operate at low voltages (e.g., < 1.2 volts) due to the lower breakdown voltages of transistors manufactured using such nanometer technologies. Consequently, analog signal processing may benefit from current-mode rather than voltage-mode operation due to the reduced voltage headroom available at these lower operating voltages. Therefore, current mirrors are expected to play a more significant role in current-mode signal processing.

[0004] However, transistors manufactured using nanometer technologies can suffer from short-channel effects at lower output resistances. When used in (an output branch of) a current mirror, a transistor with a lower output resistance can impair the current mirror's performance and deviate from operating as an ideal current source (e.g., a current source with infinite output / internal resistance).

[0005] The aforementioned shortcomings of the prior art form the basis for the teaching of the present disclosure, including a practical and scalable cascode current mirror with reduced headroom voltage for a large output voltage range. SUMMARY

[0006] According to a first aspect of the present disclosure, a cascode current mirror circuit is presented comprising: an input string comprising a common-source transistor in series with a first intrinsic common-gate transistor; and an output string comprising a first common-source transistor in series with a second intrinsic common-gate transistor, the compound transistor comprising two series-connected transistors with gates connected to a gate node of the common-source compound transistor, and an intermediate node connecting the two series-connected transistors to the gates of the first and second intrinsic common-gate transistors.

[0007] According to a second aspect of the present disclosure, a method for operating a cascode current mirror with low headroom voltage is presented, the method comprising: realizing an input branch of the cascode current mirror by connecting a common-source compound transistor in series with a first intrinsic common-gate transistor; realizing an output branch of the cascode current mirror by connecting a first common-source transistor in series with a second intrinsic common-gate transistor;and biasing the gates of the first and second common-gate transistors with a voltage at an intermediate node connecting two series-connected transistors of the common-source compound transistor, wherein a ratio between a width and a length of each of the two series-connected transistors is twice a ratio between a width and a length of any first common-source transistor, the first intrinsic common-gate transistor, or the second intrinsic common-gate transistor.

[0008] Further aspects of the disclosure are contained in the description, drawings and claims of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which form part of this description, illustrate one or more embodiments of the present disclosure and, together with the description of the embodiments, serve to explain the principles and implementations of the disclosure. Fig. Figure 1A shows a simplified schematic representation of a cascode current mirror in which the gate voltages for transistors of the output string are generated by the input string. Fig. Figure 1B shows a simplified schematic representation of another cascode current mirror in which the gate voltages for transistors of the output string are generated by the input string. Fig. Figure 2 shows a simplified schematic representation of a cascode current mirror according to an embodiment of the present disclosure. Fig. Figure 3 shows a simplified schematic representation of a cascode current mirror according to an embodiment of the present disclosure, wherein the cascode current mirror comprises several output strands. Fig. Figure 4 shows a simplified schematic representation of a cascode current mirror according to a further embodiment of the present disclosure, wherein the cascode current mirror is configured for a higher output voltage on the output string. Fig. Figure 5 is a process diagram showing various steps of a method according to an embodiment of the present disclosure for operating a cascode current mirror with low headroom voltage.

[0010] The same reference numbers and designations in the different drawings refer to the same elements. DETAILED DESCRIPTION

[0011] In this disclosure, embodiments and variants are described to illustrate the use and implementation of the inventive concepts of different embodiments. The descriptions are to be understood as examples of the inventive concept and not as limiting the scope of the concept disclosed herein.

[0012] A cascode current mirror can increase its output resistance by inserting a cascode stack on one of the current mirror's output strings. Since the cascode stack includes at least one common-gate transistor (cascode transistor) in series (e.g., stacked) with a common-source transistor (input transistor), the output string may require a voltage headroom equal to the sum of the gate-source (Vgs) voltage of the common-source transistor and the common-gate transistor's overdrive voltage. This headroom may therefore be too large for operation with low-voltage supplies (e.g., 1.2 volts and below) and / or too limiting with respect to the dynamic range (e.g., fluctuation) of a voltage coupled to the current mirror's output string.

[0013] One possible design technique to overcome the aforementioned disadvantage of a cascode current mirror involves using one or more dedicated transistor branches (separate from the input branch) to generate one or more gate voltages for biasing one or more common-gate transistors (cascode transistors) of the current mirror's output branch. In this case, the operation of the output branch may require a voltage headroom approximately equal to the sum of the common-source and common-gate transistor overdrive voltages, and therefore sufficiently low for operation with some low-voltage supplies (e.g., 1.2 volts and below).However, this potential solution comes at a cost, requiring at least one additional / dedicated transistor branch, including a larger chip area and higher power consumption, with costs increasing with the number of common-gate transistors (cascode circuit).

[0014] Fig. Figure 1A shows a simplified schematic representation of a cascode current mirror (100a) with one input string (M1X). 11 , e.g. reference branch), which includes a common-source transistor (FET) M1X 11 includes, and an output strand (M1X 21 , MiX 22 , e.g. output branch), which contains a common-source transistor (FET), M1X 21 , in series with a common-gate (cascode) MiX 22 includes a (reference) current source, I B , is connected to the input string (M1X 11 ) coupled. During operation, a current I is carried out. B , which is powered by the current source I Bthrough the input line (M1X 11 ) flows from the output strand (M1X 21 , MiX 22 ) mirrored and used as output current (sinks) current I OUT issued.

[0015] With further reference to Fig. 1A is the transistor M1X 11 of the input string (M1X 11 ) arranged in a diode circuit configuration so that it self-biases to supply the input current I B to conduct through this transistor. In other words, since the drain and gate of transistor M1X 11 When connected to each other, the gate voltage VG1 adjusts itself automatically to control the input current I B through transistor M1X 11 to guide, for example, based on the current-voltage characteristics (e.g., IV curves) of the M1X transistor. 11 The gate voltage VG1 is in turn used to apply gate bias voltages to the transistors M1X. 21 and MiX 22of the output string (M1X 21 , MiX 22 ) for the transmission of the output current I OUT to determine.

[0016] The use of a common gate voltage (e.g. VG1) to bias both transistors, M1X 21 and MiX 22 , of the output string (M1X 21 , MiX 22 ) is made possible by selecting transistors that are similar to a "regular" transistor (e.g., M1X). 21 ) with a size W / L, which results from the ratio of its width (W) to its length (L), and an “intrinsic” or “native” transistor (e.g. M1X 22 ) of the same size. As used in the present disclosure, a regular transistor is a transistor with a (regular) positive threshold voltage (V). th ), and an intrinsic transistor is a transistor with a (strictly) negative and non-zero V th -voltage, where the V thThe gate-source voltage is a voltage that brings the transistor to a boundary between conductivity and non-conductivity. th The voltage of a regular NMOS-FET transistor can be approximately (positively) 500 millivolts or more, and the V th The voltage of an intrinsic NMOS-FET transistor can be approximately negative 200 millivolts or less (i.e., more negative). In some embodiments according to the present disclosure, the voltage can be even lower. th the intrinsic NMOS-FET transistors are in a range of negative 200 millivolts to negative 250 millivolts.

[0017] Accordingly, a regular transistor (e.g., M1X) can 21 ) operate in a corresponding saturation range for a gate-source voltage Vgs of approximately 600 millivolts, which is equal to the sum of the (positive) voltage V th of the transistor (e.g., about 500 millivolts) and an overdrive voltage V OVof the transistor (e.g., up to about 100 millivolts). On the other hand, an intrinsic transistor (e.g., M1X) can 22 ) in a corresponding saturation region for a gate-source voltage V gs work equal to the sum of the (negative) V th -Voltage of the transistor (e.g., approximately negative 200 millivolts or less) and an overdrive voltage V OV of the transistor (e.g., only about 100 millivolts). Accordingly, such an intrinsic transistor can operate in its saturation region for a gate-source voltage V. gs operating voltages that are significantly smaller than 600 millivolts, for example less than 150 millivolts, and may extend into a negative voltage range (depending on the negative value of the voltage V). thIt should be noted that a necessary condition for the operation of a FET transistor in its saturation region (and thus for providing a high output impedance of the transistor) is a drain-source voltage V. ds is, which is greater than the overdrive voltage V OV of the transistor (i.e. V ds > V gs - V th In other words, a FET transistor, whether regular or intrinsic, can operate in its saturation region at a V ds -operated at a voltage of only about 100 millivolts.

[0018] With further reference to Fig. 1A sets the gate voltage VG1 the V gs and the drain-source voltage (V ds ) of the transistor M1X 11 as well as the V gs of the transistor M1X 21 on the other hand, the V ds of the transistor M1X 21 through the difference between the gate voltage VG1, which the V gsof the regular transistor M1X 11 is, and the V gs of the intrinsic transistor M1X 22 depicted. Assuming that M1X 11 and M1X 22 with similar or closely spaced values ​​of the corresponding overdrive voltages V OV can work the V ds of the transistor M1X 21 through the difference between the (positive) V th of the (regular) transistor M1X 11 and the (negative) V th of the (intrinsic) transistor M1X 11 be represented. In other words, although the (regular) M1X transistors 11 and M1X 21 the same V gs They can have different voltages. ds -Voltages, and therefore for a given gate voltage VG1 a current I can B , which passes through the input strand (M1X 11 ) flows, from a current I OUT , which is through the output strand (M1X 21 , MiX22 ) flows, (slightly) deviating. Such a difference between the currents can in turn cause an undesirable systematic offset of the cascode current mirror (100a).

[0019] Since also the V ds of the intrinsic transistor MiX 22 can be at least 100-150 millivolts and the V ds of the transistor M1X 21 can be larger than its V th , can provide a headroom voltage for the operation of the output string (M1X) 21 , MiX 22 ), i.e., the sum of the V ds -Voltage of transistors M1X 21 and MiX 22 , greater than approximately 600 to 650 millivolts. Such a relatively large headroom voltage, which is necessary for the operation of the output string (M1X) 21 , MiX 22 ) is required, the available voltage fluctuation range (dynamic range) for one with the output string (M1X) can be used. 21 , MiX 22 ) reduce coupled circuitry.

[0020] Fig. Figure 1B shows a simplified schematic representation of another cascode current mirror (100b) with an input string (M1X). 11 , R1), which incorporates a common-source transistor (FET) M1X 11 includes, which is connected in series with a resistor R1, and an output string (M1X 21 , M1X 22 ), which uses a common-source (FET) transistor M1X 21 includes, in series with a common-gate (cascode) M1X 22 is switched. A (reference) current source I B is connected to the input string (M1X 11 ) coupled. During operation, a current I is carried out. B , which is powered by the current source I B through the input line (M1X 11 , R1) flows from the output strand (M1X 21 , M1X 22 ) mirrored and used as output current (sink current) I OUT issued.

[0021] In contrast to the above regarding Fig. The configuration described in 1A (100a) includes the output string (M1X). 21 , M1X 22 ) of the configuration (100b) from Fig. 1B has no intrinsic transistor, since both transistors are M1X 21 and M1X 22 These are regular transistors (i.e., as opposed to intrinsic transistors). Similar to configuration (100a), the gate voltage VG1, which here is the bias voltage of the common-source transistor M1X, is... 22 of the output string (M1X 21 , M1X 22 ) is used, the line of the input current I B through transistor M1X 11 of the input string (M1X 11 , R1) itself. In addition, a voltage drop forms on the input current I line. B through the resistor R1, a gate voltage VG2, which is used to bias the common-gate (cascode) transistor M1X 22 of the output string (M1X 21 , M1X 22 ) is used.

[0022] With further reference to Fig. 1B The resistor R1 can be chosen so that it generates a gate voltage VG2 which is approximately an overdrive voltage V OV is greater than the gate voltage VG1. In other words, the resistor R1 can be chosen such that VG2 = V th +2V OV is. Since the V gs of the transistor M1X 22 approximately V th + V OV is, can the V ds , of the transistor M1X 21 approximately V OV In other words, configuration (100b) can reduce the power required for the operation of the output string (e.g., M1X). 21 , M1X 22 ) required headroom voltage compared to the configuration (100a) in Fig. 1A is possible. Similar to configuration (100a), configuration (100b) operates the common-source transistors M1X. 11 and M1X 21 with different V ds-tensions, which can lead to a systematic offset.

[0023] Furthermore, the voltage drop across resistor R1 has a linear dependence on the value of the current I. B and the voltage VG1 (e.g. V OV of the transistor M1X 11 ) a quadratic relationship with the value of the current I B , a change in current I B This can lead to a shift in the operating points of the M1X transistors. 21 and M1X 22 lead to, for example, the V ds -Voltage of the common-source transistors M1X 11 and M1X 21They no longer track each other. Furthermore, process-, voltage-, and temperature-related (PVT) fluctuations can affect the properties (e.g., the resistance) of resistor R1 differently than the properties (e.g., the current-voltage characteristic) of the transistors used in the cascode current mirror (100b), resulting in similar shifts in the operating points of transistors M1X. 21 and M1X 22 , with similar effects. Finally, the presence of a resistor (e.g., R1) in a cascode current mirror may be undesirable due to its larger footprint on the chip, especially in low-current applications where larger resistors may be required to produce a desired voltage drop across the resistor.

[0024] The teachings according to the present revelation deal with the design compromises described above, with reference to configurations (100a) and (100b). In particular, it shows Fig. 2 A simplified schematic representation of a cascode current mirror (200) according to an embodiment of the present disclosure. The cascode current mirror (200) comprises an input strand (210, MiX) 13 , e.g. a reference branch), which has M2X transistors connected in series. 11 , M2X 12 and MiX 13 includes a (reference) current source I B is connected to the input string (210, MiX) 13 ) coupled. During operation, a current I is carried out. B , which is powered by the current source I B through the input line (210, MiX 13 ) flows from the output strand (M1X 21 , MiX 22 ) mirrored and used as output current (sink current) I OUT issued.

[0025] With further reference to Fig. 2 are, according to some embodiments of the present disclosure, the transistor MiX 13 of the input string (210, MiX 13 ) and the MiX transistor 22 of the output string (M1X 21 , MiX 22 ) intrinsic transistors. On the other hand, the transistors M2X are 11 and M2X 12 , which is the element (210) of the input string (210, MiX 13 ) form, and the M1X transistor 21 of the output string (M1X 21 , MiX 22 ) regular transistors. Furthermore, the size (e.g., 2X) of the transistors is M2X. 11 and M2X 12 twice the size (e.g. 1X) of the MiX transistors 13 , M1X 21 and MiX 22 .

[0026] As in Fig. Shown in section 2 are the gates of the M2X transistors. 11 and M2X 12 connected to each other, and a drain of the transistor M2X 11 is with a source of the transistor M2X 12connected. Accordingly, element (210) can be considered a compound transistor (210) having a source that is connected to a source of transistor M2X. 11 is provided, a drain which is supplied by a drain of the transistor M2X 12 is provided, and a gate that is provided by the common gates (e.g. the node carrying the voltage VG1) of the transistors M2X 11 and M2X 12 is provided. Since the compound transistor (210) also has a width W 210 can exhibit a width W2 equal to that of each of the transistors M2X 11 and M2X 12 , and a length L 210 , which is the sum of the lengths L2 + L2 of the transistors M2X 11 and M2X 12 If this corresponds to the size W, then the size W can be determined. 210 / L 210 of the composite transistor (210) be equal to W2 / (L2 + L2), or in other words equal to half the size (2X) of each of the transistors M2X 11 and M2X 12, which corresponds to the size (1X) of each of the transistors MiX 13 , M1X 21 and MiX 22 corresponds.

[0027] With further reference to Fig. 2 is the compound transistor (210) in series with the (cascode) intrinsic transistor MiX 13 switched. Similar to the above with reference to Fig. In the configurations described in 1A / 1B (100a, 100b), the gate voltage VG1 adjusts itself to the input current I. B to conduct through the compound transistor (210), for example based on the current-voltage characteristics (e.g. IV curves) of the transistors M2X 11 and M2X 21 The gate voltage VG1 is in turn used to control the transistor M1X. 21 of the output string (M1X 21 , MiX 22 ) for the transmission of the output current I OUT to pre-tension. In other words, the V gs-Voltage of the common-source compound transistor (210) of the input string (210, MiX) 13 ) (e.g. exactly or almost exactly) equal to V gs -Voltage of the common source transistor M1X 21 of the output string (M1X 21 , MiX 22 Since the transistors (210) and M1X 21 They may be matched to each other (e.g., with the same current-voltage characteristics and size), but with the same V ds -Voltages of these transistors (e.g. VS) 13 = VS 22 ) the current I OUT through transistor M1X 21 (e.g., exactly or almost exactly) equal to the current I B through the transistor (210).

[0028] As in Fig. As shown in Figure 2, a voltage VG2 is applied to an intermediate node between the two transistors M2X connected in series. 11 and M2X 12 , or in other words, a node that connects a drain of transistor M2X 11 with a source of the transistor M2X12 connects / couples, used as gate voltage to control the intrinsic transistors MiX 13 and MiX 22 of the input string (210, M2X 11 ) and the output strand (M1X 21 , MiX 22 ) to bias. Since the transistors MiX 13 and MiX 22 Even if the transistors are matched to each other (e.g., with the same current-voltage characteristics and size), the following applies to an equal current flow through these transistors (e.g., I). B = I OUT ) flows, with the same voltage for both transistors. gs -voltage, and therefore the voltage VS 13 equal to the voltage VS 22 (e.g. VS) 13 = VS 22 In other words, the voltage VG2 represents an equal value to V ds -voltages of the transistors (210) and M1X 21 , and therefore, as described above, the current I OUT through transistor M1X 21 (e.g., exactly or almost exactly) equal to the current IB through the transistor (210).

[0029] Since the transistor M1X 21 is intrinsic and therefore has a negative V th exhibits the voltage VS 13 and thus the V ds of transistor (210) be greater than the voltage VG2, which is a sufficiently large and positive V ds -Voltage for operating the M2X transistors 11 and M2X 12 This represents the voltage VG2. Assume that the voltage is approximately positive 20-30 millivolts and the V th If the intrinsic transistor has a voltage of approximately negative 220 millivolts, then the voltage VS 13 and thus the V ds of the transistor (210) for an overdrive voltage V OV of approximately +100 millivolts, approximately positive 140-150 millivolts. Accordingly, the V ds of the transistor M1X 21 of the output strand, which is equal to V dsThe transistor (210) of the input string is also approximately positive 140-150 millivolts.

[0030] It follows that the configuration (200) in Fig. 2 a lower headroom voltage of the output string operation (M1X) 21 , MiX 22 ) enables, for example, the configuration (100b) mentioned above. Fig. The headroom voltage described in 1B is comparable, but without mismatch of the V. ds -Voltage of the common-source transistors of the input / output strings. In addition, the input string (210, M2X) exhibits 11 ) of configuration (200) exhibits a similarly low headroom voltage, which allows operation with a supply voltage V dd made possible by only 1.2 volts or less.

[0031] It should be noted that the use of intrinsic transistors (MiX) 13 , MiX 22 ) as cascode transistors in the cascode current mirror (200) of Fig. 2 can be used for the operation of the current mirror, which in turn allows the use of a (low) voltage VG2 at the intermediate node between the two series-connected transistors M2X 11 and M2X 12 can be used to bias the cascode transistors, which in turn allows each of the input and output strings to operate at low headroom voltages, which are about twice as high as the overdrive voltage of the transistors (e.g., headroom voltages in the range of 200 to 250 millivolts).

[0032] According to some embodiments of the present disclosure and as detailed in A in Fig. As shown in section 2, the common-source transistor M1X can 21 of the output string (M1X 21 , MiX 22 ) a compound transistor, which consists of M2X transistors connected in series 21a and M2X 21b includes each of the series-connected transistors M2X 11 and M2X 12are adapted (e.g. with regard to their current-voltage characteristics and their size) that connect the compound transistor (210) of the input string (210, MiX) 13 ). This in turn can result in a better overall match between the two common-source (compound) transistors (210) and M1X. 21 make possible

[0033] With further reference to Fig. 2 can be in Fig. The two transistors shown are designed for operation according to desired / specific parameter values, including, for example, currents (e.g., I). B and I OUT ) and threshold / overdrive voltages. Such parameter values ​​may also exist with regard to the required operation of the common-source transistors in their respective saturation regions. The relationships between the (drain) current (I) D ), the threshold voltage (V th ), the gate-source voltage (V gsThe overdrive voltage (Δ), transistor width (W) and transistor length (L) of a FET transistor are given by the following (general) equations (1) and (2): ID=K'2WLΔ2 Δ=Vgs−Vth=2IDK'WL where K and K' are well-established FET process parameters.

[0034] By applying the above equations to the nodes that are in Fig. 2 voltages shown VG1, VG2, VS 13 and VS 22 By carrying this out, we obtain the following equations (3), (4) and (5): VG1=Vth+2IBK'WL VG2=Vth+2IBK'WL−(Vth+2IBK'WL)=(1−12)Δ VS13=VS22=VG2−Vgsi=VG2−(Vthi+2IBKi'WL)=VG2−(Vthi+Δi) where: Vth denotes the threshold voltage of regular transistors, Δ denotes the overdrive voltage of the regular transistors, Vthi denotes the threshold voltage of the intrinsic transistors and Vgsi denotes the gate-source voltage of the intrinsic transistors.

[0035] As previously described in the present application, some advantageous arrangements for keeping a FET transistor in its saturation region can be provided by the following conditions: V ds > V gs - V th Since V ds = VS 13 and V gs If VG1 is equal to the above equations (1) to (5), the following inequality (6) results: (1−12)Δ−Vthi−Δi>Δ⇒−2(Vthi+Δi)>Δ the one relationship between the overdrive voltage (Δ) of the regular transistors (e.g. M2X) 11 , M2X 12 , M1X 21 ) and the overdrive voltage (Δ i ) and the threshold voltage (V thi) ) of the intrinsic transistors (e.g. MiX) 13 , MiX 22 ) for the operation of the cascode current mirror (200) from Fig. 2. In other words, by manufacturing / designing the regular transistors (e.g., M2X) 11 , M2X 12 , M1X 21 ) and the intrinsic transistors (e.g., MiX) 13 , MiX 22 ) according to the threshold / overdrive voltages according to inequality (6), operation of each of the transistors (210, MiX) 13 , M1X 21 , MiX 22 ) in their respective saturation ranges. On the other hand, as can be clearly seen from equation (4), the voltage VG2, which is equal to V ds of the M2X transistor 11 is smaller than the overdrive voltage of such a transistor. In other words, during the operation of the cascode current mirror (200) of Fig. 2. The transistor M2X works 11in its triode region, while all other transistors operate in their saturation region. It should be noted that although the equations above are written in terms of the width W and length L of the transistors (e.g., 1X / 2X prefixes indicating the ratio of W to L), the equations can also be written in terms of ratios and generalized for different transistor sizes (e.g., scaling).

[0036] The above with reference to Fig. The configuration described in section 2 (200) can be extended for higher stack sizes, for example to withstand higher voltages on the output string and / or to increase the output string impedance. An example configuration of this type is shown in Fig. 3 shown.

[0037] Fig. Figure 3 shows a simplified schematic representation of a cascode current mirror (300) according to an embodiment of the present disclosure, wherein the cascode current mirror has a plurality of (parallel) output strands for outputting mirrored currents I OUT , I' OUT and I'' OUT includes. As in Fig. 3 shown, includes a first output strand (M1X 21 , MiX 22 , MiX 22 ), which carries the current I OUT outputs a stacked cascode array with a stack height of three, a second output strand (M1X 31 , MiX 32 ), which carries the current I' OUT outputs and comprises a stacked cascode arrangement with a stack height of two, and a third output strand (M1X 41 ), which carries the current I'' OUToutputs and comprises a single transistor. It should be noted that the three output strands of the cascode current mirror (300) can operate independently of each other, since their operation is based solely on gate bias voltages (e.g., VG1, VG2, VG3) supplied by the input strand (210, MiX). 13 , MiX 14 ) are generated. Furthermore, configurations are possible that are based on configuration (300) from Fig. 3 are based, but do not have one or more of the output strands shown (e.g. according to Fig. 4, which will be described later).

[0038] With further reference to Fig. 3 is the operating principle of the cascode flow mirror (300) similar to the one above with reference to Fig. 2 described, including the use of the compound transistor (210), the transistors (M2X 11 , M2X 21 ) includes transistors that are twice the size of the other transistors. Likewise, those in Fig. 3 shown voltages at nodes VG1, VG2, VG3, VS 13 , VS 14 , VS 22 and VS 23 can be obtained via equations (1) and (2) described above. In particular, the above can be compared with respect to the in Fig. The equations (3)-(5) and inequality (6) described for the two nodes shown apply equally to the same nodes in Fig. 3 will be applied. In other words, similar to configuration (200) in Fig. 2. All transistors of configuration (300) except transistor M2X can be used. 11 operate within their respective saturation ranges. Due to the different stack heights of the three output strands (e.g., I OUT , I' OUT , I'' OUT ) in Fig. 3. Different output impedances, voltage fluctuations and voltage ratings can be provided at the output strings.

[0039] According to some embodiments of the present disclosure, an increased dielectric strength at an output strand (e.g. I) can be achieved. OUT in Fig. 3) provided by one or more transistors connected in series, configured to self-bias. This is in Fig. 4 shown where a self-biased stack (420) of intrinsic transistors connected in series (MiX) 24 ,..., MiX 27 ,...) with the output string (M1X 21 , MiX 22 , MiX 23 ) coupled. Accordingly, an (aggregated V) ds, e.g. 100-150 millivolts per transistor) voltage drop across the self-biased stack (420) couples a higher voltage to the output string, including a voltage higher than a technological rating (e.g. breakdown voltage) of the transistors on the output string. Since the stack (420) is self-biased, the input string (210, MiX) can couple a higher voltage to the output string. 13 , MiX 14 ) no additional prestresses are generated.

[0040] As in Fig. As shown in Figure 4, the self-bias of a transistor can be determined by the series-connected intrinsic transistors (MiX). 24 , ..., MiX 27 ...) are provided by coupling a gate of the transistor to a source of an adjacent transistor whose drain is connected to a source of the transistor (e.g., directly coupled). Consider, for example, the intrinsic transistor MiX. 25, whose source is connected to the drain of the adjacent (intrinsic) transistor MiX 24 If connected, then the self-bias of the intrinsic transistor MiX 25 by connecting its gate to the source of the adjacent (intrinsic) transistor MiX 24 The self-bias is provided by coupling the gates of the transistors to voltages that are smaller than the voltages at the respective sources of the transistors, so the use of intrinsic transistors can be advantageous in some embodiments.

[0041] According to an exemplary embodiment of the present disclosure, the intrinsic transistors connected in series (MiX) can 24 , ..., MiX 27,...) of the self-biasing stack (420) advantageously comprise source-body-bound transistor devices, which include bodies connected to the respective sources. Some advantages obtained by such source-body-bound transistor devices may include increased stability of the threshold voltage (V). th ) of the device and thus ensure a more stable self-preloading scheme.

[0042] It should be noted that the teachings according to the present revelation do not apply to a cascode current mirror (e.g. Fig. 3-4) are limited to devices whose input / output strings are configured to sink input / output currents through n-type FET transistor devices, but the present teachings apply equally to a cascode current mirror whose input / output strings are configured to feed input / output currents through p-type FET transistor devices. Such a p-type configuration can be considered a dual or complementary configuration to the n-type configuration described above.

[0043] Fig.Figure 5 is a process diagram (500) showing various steps of a method for operating a cascode current mirror with a low headroom voltage. As can be seen from the process diagram (500), the method comprises: realizing an input branch of the cascode current mirror by connecting a common-source compound transistor in series with a first intrinsic common-gate transistor according to step (510); realizing an output branch of the cascode current mirror by connecting a first common-source transistor in series with a second intrinsic common-gate transistor, in each step (520); and biasing the gates of the first and second common-gate transistors with a voltage at an intermediate node connecting two series-connected transistors of the common-source compound transistor, in each step (530).where the ratio between the width and length of each transistor of the two series-connected transistors is twice the ratio between the width and length of any first common-source transistor, first intrinsic common-gate transistor, or second intrinsic common-gate transistor.

[0044] Applications that may include the novel devices and systems of various embodiments encompass electronic circuits used in high-speed computers, communication and signal processing circuits, modems, single or multi-processor modules, single or multiple embedded processors, data switches, and application-specific modules, including multilayer multi-chip modules. Such devices and systems may also be included as subcomponents in a variety of electronic systems, such as televisions, mobile phones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 players), vehicles, medical devices (e.g., cardiac monitors, blood pressure monitors, etc.), and others. Some embodiments may include a number of methods.

[0045] The term "MOSFET" technically refers to a metal-oxide-semiconductor field-effect transistor; another synonym for MOSFET is "MISFET," for metal-insulator-semiconductor FET. However, "MOSFET" has become a common term for most types of insulated-gate FETs ("IGFETs"). Nevertheless, the term "metal" in the names MOSFET and MISFET is now often misleading, as the formerly metallic gate material is now frequently a layer of polysilicon (polycrystalline silicon). Similarly, the term "oxide" in the name MOSFET can be misleading, as various dielectric materials are used to achieve strong channels at lower applied voltages. Accordingly, the term "MOSFET" in this context should not be understood literally as being limited to metal-oxide-semiconductor FETs, but rather encompasses IGFETs in general.

[0046] As is readily apparent to a person skilled in the art, various embodiments of the invention can be implemented to meet a wide range of specifications. Unless otherwise stated above, the selection of suitable component values ​​is a matter of design choice, and various embodiments of the invention can be implemented in any suitable IC technology (including, but not limited to, MOSFET and IGFET structures) or in hybrid or discrete circuit configurations. Integrated circuit embodiments can be fabricated using any suitable substrates and methods, including, but not limited to, standard bulk silicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), GaN HEMT, GaAs pHEMT, and MESFET technologies.The inventive concepts described above are particularly useful in SOI-based fabrication processes (including SOS) and in fabrication processes with similar characteristics. Fabrication in CMOS on SOI or SOS enables low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (above approximately 10 GHz and especially above approximately 20 GHz). Monolithic IC implementation is particularly advantageous because parasitic capacitances can generally be kept low through careful design (or at least uniformly across all units so that they can be compensated).

[0047] The voltage levels can be adjusted depending on the specific specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS, as well as transistors in enhancement or depletion mode), or the polarities of the voltage and / or logic signals can be reversed. The voltage, current, and power handling capabilities of the components can be adapted as needed, for example, by adjusting component sizes, serially stacking components (especially FETs) to withstand higher voltages, and / or by using multiple components in parallel to handle higher currents. Additional circuit components can be added to enhance the capabilities of the disclosed circuits and / or provide additional functionality without substantially altering the functionality of the disclosed circuits.

[0048] The examples mentioned above are intended to provide those skilled in the art with a complete disclosure and description of the manufacture and use of the embodiments of the gate drivers for stacked transistor amplifiers disclosed in the disclosure, and are not intended to limit the scope of what the applicant considers to be the invention. Such embodiments may be used, for example, in mobile devices for current communication systems (e.g., WCDMA, LTE, WiFi, etc.) where amplification of signals with frequency components above 100 MHz and at power levels above 50 mW may be required. Those skilled in the art may find other suitable implementations of the embodiments presented.

[0049] Modifications of the modes described above for carrying out the methods and systems disclosed herein, which are obvious to those skilled in the art, shall be within the scope of the following claims. All patents and publications mentioned in the description are to be understood as references to the prior art to which the disclosure relates. All references cited in this disclosure are incorporated by reference to the same extent as if each reference had been incorporated individually in its entirety by reference.

[0050] It is understood that the disclosure is not limited to specific processes or systems, which may of course vary. It is also understood that the terminology used herein serves only to describe specific embodiments and is not intended to be restrictive. As used in this description and the accompanying claims, the singular forms "a," "an," and "the" include multiple references unless the context clearly requires otherwise. The term "plural" includes two or more references unless the context clearly requires otherwise. Unless otherwise defined, all technical and scientific terms used herein have the same meanings as they are generally understood by a person skilled in the art in the field of the disclosure.

[0051] Several embodiments of the disclosure have been described. It is understood, however, that various modifications can be made without deviating from the core and scope of the present disclosure. Accordingly, other embodiments fall within the scope of the following claims. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 18 / 160,536

[0001]

Claims

[1] A cascode current mirror circuit comprising: an input string comprising a common-source compound transistor in series with a first intrinsic common-gate transistor, and an output string comprising a first common-source transistor in series with a second intrinsic common-gate transistor, where The compound transistor comprises two transistors connected in series, whose gates are connected to a gate node of the common-source compound transistor, and an intermediate node that connects the two transistors connected in series, which is connected to the gates of the first and second intrinsic common-gate transistors. [2] The cascode current mirror circuit according to claim 1, wherein the ratio between a width and a length of each transistor of the two series-connected transistors is twice as large as the ratio between a width and a length of the first common-source transistor. [3] The cascode current mirror circuit according to claim 1, wherein a ratio between a width and a length of each transistor of the first common-source transistor, the first intrinsic common-gate transistor and the second intrinsic common-gate transistor is equal to S, and a ratio between the width and length of each transistor of the two transistors connected in series is equal to twice S. [4] The cascode current mirror circuit according to claim 1, wherein the gate node of the common-source compound transistor is connected to a gate of the first common-source transistor and to a drain of the first intrinsic common-gate transistor. [5] The cascode current mirror circuit according to claim 4, wherein a source of the first intrinsic common-gate transistor is connected to a drain node of the common-source compound transistor and a source of the second intrinsic common-gate transistor is connected to a drain node of the first common-source transistor. [6] The cascode current mirror circuit according to claim 4, which further comprises a current source coupled to the drain of the first intrinsic common-gate transistor. [7] The cascode current mirror circuit according to claim 1, wherein the two series-connected transistors of the common-source compound transistor include a second common-source transistor in series with a first common-gate transistor, and a drain of the second common-source transistor and a source of the first common-gate transistor are connected to the intermediate node. [8] The cascode current mirror circuit according to claim 7, wherein during operation of the cascode current mirror circuit a voltage at the intermediate node is smaller than an overdrive voltage of the second common-source transistor, so that the second common-source transistor is operated in a triode region. [9] The cascode current mirror circuit according to claim 7, wherein during operation of the cascode current mirror circuit a difference between a voltage at a drain of the first common-gate transistor and a voltage at the intermediate node is greater than an overdrive voltage of the first common-gate transistor, such that the first common-gate transistor is operated in a saturation region. [10] The cascode current mirror circuit according to claim 1, wherein the first intrinsic common-gate transistor and the second intrinsic common-gate transistor each exhibit negative threshold voltages, and Each transistor of the two series-connected transistors and the first common-source transistor each have positive threshold voltages. [11] The cascode current mirror circuit according to claim 10, wherein the respective negative threshold voltages are in a range of negative 200 millivolts to negative 250 millivolts. [12] The cascode current mirror circuit according to claim 1, wherein the first common-source transistor is a compound transistor comprising two transistors connected in series, the gates of which are connected to each other. [13] The cascode current mirror circuit according to claim 1, wherein The input string further comprises a third intrinsic common-gate transistor in series with the first intrinsic common-gate transistor, and The output string further comprises a fourth intrinsic common-gate transistor in series with the second intrinsic common-gate transistor. [14] The cascode current mirror circuit according to claim 13, wherein the gate node of the common-source compound transistor is connected to a gate of the first common-source transistor and to a drain of the third intrinsic common-gate transistor, and a drain node of the common-source compound transistor is connected to a gate of the third intrinsic common-gate transistor and to a gate of the fourth intrinsic common-gate transistor. [15] The cascode current mirror circuit according to claim 13, which further comprises an additional output string comprising a third common-source transistor, wherein a gate of the third common-source transistor is connected to the gate node of the common-source compound transistor. [16] The cascode current mirror circuit according to claim 15, wherein the additional output string further comprises a fifth intrinsic common-gate transistor connected in series with the third common-source transistor, wherein a gate of the fifth intrinsic common-gate transistor is connected to the intermediate node. [17] The cascode current mirror circuit according to claim 1, wherein the output string further comprises a self-biasing stack of several intrinsic transistors connected in series, wherein the self-biasing stack is connected in series with the second intrinsic common-gate transistor, where for each transistor of the several series-connected intrinsic transistors of the self-biased stack, a source node of each transistor is connected to a drain node of an adjacent intrinsic transistor, wherein the adjacent intrinsic transistor is one of the several series-connected intrinsic transistors of the self-biased stack or the second intrinsic common-gate transistor, and a gate node of each transistor is connected to a source node of the adjacent intrinsic transistor. [18] The cascode current mirror circuit according to claim 7, wherein each transistor of the multiple series-connected intrinsic transistors of the self-biased stack comprises a source-body bonded transistor. [19] A method for operating a low headroom voltage cascode current mirror, comprising: Implementing an input string of the cascode current mirror by connecting a common-source transistor in series with a first intrinsic common-gate transistor; Implementing an output stage of the cascode current mirror by connecting a first common-source transistor in series with a second intrinsic common-gate transistor; and Preloading the gates of the first and second common-gate transistors with a voltage at an intermediate node connecting two series-connected transistors of the common-source compound transistor, where a ratio between a width and a length of each transistor of the two series-connected transistors is twice as large as a ratio between a width and a length of any first common-source transistor, the first intrinsic common-gate transistor, or the second intrinsic common-gate transistor. [20] The method according to claim 19, wherein the first intrinsic common-gate transistor and the second intrinsic common-gate transistor each exhibit negative threshold voltages, and Each transistor of the two series-connected transistors and the first common-source transistor each have positive threshold voltages.

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