High-precision BJT current mirror circuit based on CMOS technology

Abstract

The invention discloses a high-precision BJT (Bipolar Junction Transistor) current mirror circuit based on a CMOS (Complementary Metal Oxide Semiconductor) process, which belongs to the field of integrated circuits and comprises a current source bias module, a current mirror core module and a current discharge module. The current source bias module is composed of a PMOS current source, an NMOS current mirror and a cascode current mirror. The current mirror core module is composed of a BJT triode. The current discharge module is composed of a PMOS tube, a resistor path, an NMOS tube connected with a capacitor, and a capacitor. Base bias current is provided for a BJT triode through the current source bias module, the inherent defect that a traditional BJT current mirror structure cannot accurately copy reference current is overcome, and meanwhile the current self-adaptability of the current source bias module is improved by adding the current discharge module. According to the invention, the BJT current mirror can be adopted to accurately copy the reference current under the CMOS technology, the precision is high, the matching performance is good, the flicker noise is low, and the performance of the current mirror can be obviously improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a high-precision BJT current mirror circuit based on CMOS technology. Background Technology

[0002] In analog and mixed-signal integrated circuit design, the current mirror serves as a core unit for current copying, bias generation, and signal processing, and its performance directly determines the accuracy, stability, and reliability of the entire system. Commonly used MOSFET current mirrors suffer from low matching accuracy and high flicker noise, while BJT current mirrors offer high accuracy, good matching, and low flicker noise, significantly improving the performance of the current mirror.

[0003] Traditional BJT current mirror circuit structure, such as Figure 2 As shown, it consists of two transistors, where Q1 is connected in a diode configuration, and Q2 replicates the current of Q1 by connecting to the base of Q1. The base current I of the two BJTs is... B Provided by the reference branch, I B =I C / β. Traditional BJT current mirrors produce systematic errors caused by base current. The essence is that as a current-controlled device, the base port of a BJT device requires a non-zero input drive current. This current does not participate in the mirror transmission of the output current, thus destroying the current transmission accuracy of an ideal current source.

[0004] Since Q1 and Q2 have exactly the same characteristics, λ and β (process parameters) are the same. The V value is achieved through circuit connection. BE I B I C same.

[0005] The base and collector of Q1 are shorted, causing V CE =V BE The NPN transistor operates in the amplification region (VA). CE ≥V BE ), so I C =βI B .Depend on Figure 2 It can be known that:

[0006]

[0007] Therefore, it can be seen that Figure 2 The current mirror shown cannot be accurately replicated due to errors:

[0008] Even if β matches, I OUT It is also slightly smaller than I REF.

[0009] For the improved emitter follower buffer structure (β multiplier): an emitter follower Q3 is inserted between the reference branch and the base of the mirror transistor. See the schematic diagram below. Figure 3 .

[0010] It can be seen that I C2 with I C1 The base current Ib3 of Q3 remains equal, and is taken from I. REF The emitter current is used to drive the bases of the image transistors Q1 and Q2. By introducing transistor Q3, the error-causing current (base current) can be controlled to decrease. Calculation and analysis show that its transmission error is reduced from... The magnitude was reduced to Quantity:

[0011]

[0012]

[0013]

[0014] As you can see, Figure 3 The structure shown reduces image error to some extent. However, in CMOS processes, the transistors available are typically parasitic or vertical, with very low β values, usually on the order of 1 to 10. When β decreases below 10, the error of this current source structure is comparable to that of a current source using a diode connection.

[0015] In summary, traditional BJT current mirrors, due to their inherent defect of large current mirror deviation caused by base current shunting, can no longer meet the high precision requirements of circuits. Summary of the Invention

[0016] The purpose of this invention is to provide a high-precision BJT current mirror circuit based on CMOS technology to solve the problems in the background art.

[0017] To address the aforementioned technical problems, this invention provides a high-precision BJT current mirror circuit based on CMOS technology, comprising: The current source bias module consists of a PMOS current source, an NMOS current mirror, and a common source cascode current mirror, providing base bias current to the core module of the current mirror. The core module of the current mirror is composed of BJT transistors; The current discharge module consists of a PMOS transistor, an NMOS transistor with a resistor path and a capacitor connection, and a capacitor. The increased current discharge path improves the current adaptability of the current source bias module.

[0018] In one embodiment, the current source biasing module includes PMOS transistors P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, NMOS transistor N2, NMOS transistor N3, and NMOS transistor N4. The source of PMOS transistor P1 is connected to the power supply VDD, and the gate is connected to an external bias voltage V. bias The drain of PMOS transistor P2 is connected to the drain of NMOS transistor N2; the source of PMOS transistor P2 is connected to the power supply VDD, and its gate is connected to the gates of PMOS transistors P3, P4, and P5. The drain of PMOS transistor P2 is connected to the source of PMOS transistor P3; the drain of PMOS transistor P3 is connected to both its own gate and the drain of NMOS transistor N3; the source of PMOS transistor P4 is connected to the power supply VDD, and its drain is connected to PMOS transistor P5; the drain of PMOS transistor P5 is connected to the source of PMOS transistor P6; the gate of PMOS transistor P6 is connected to its own drain, and its drain is connected to the drain of NMOS transistor N4; the gate of NMOS transistor N2 is connected to its own drain, and also to the gates of NMOS transistors N3 and N4. The sources of NMOS transistors N2, N3, and N4 are all connected to GND.

[0019] In one embodiment, the current mirror core module includes NPN transistors Q1 and Q2; the collector of NPN transistor Q1 is connected to an external reference current I. REF The base of transistor Q1 is connected to the base of NPN transistor Q2, and the emitter is connected to GND; the collector of NPN transistor Q1 is connected to an external output current I. OUT The emitter is connected to GND.

[0020] In one embodiment, the current discharge module comprises an NMOS transistor N1, a PMOS transistor P7, a capacitor C1, and a resistor R1. The gate of the NMOS transistor N1 is connected to the gate of the PMOS transistor P7 and the collector of the NPN transistor Q1, and its source and drain are both connected to GND. The source of the PMOS transistor P7 is connected to the drain of the PMOS transistor P5 and the source of the PMOS transistor P6, and its drain is connected to the first end of the resistor R1, while the second end of the resistor R1 is connected to GND. The first end of the capacitor C1 is connected to the gate of the NMOS transistor N1, the gate of the PMOS transistor P7, and the collector of the NPN transistor Q1, while its second end is connected to GND.

[0021] In one embodiment, the PMOS transistor P6 and the PMOS transistor P7 are the same PMOS transistor.

[0022] The present invention provides a high-precision BJT current mirror circuit based on CMOS technology, which has the following advantages: (1) By using an auxiliary active device with high output impedance to provide drive current specifically for the base node of the mirror transistor, the base current path is decoupled from the main reference current path; (2) In order to make the transistor work normally in the amplification region, the present invention introduces a diode-connected MOS transistor path so that the base voltage and collector voltage of the transistor are approximately equal; (3) The stability of the current source bias module is increased by using a common source cascode current mirror; (4) Increase the current discharge path to improve the current adaptability of the current source bias module.

[0023] This invention enables precise replication of reference current using a BJT current mirror in CMOS technology, exhibiting high precision and good matching, as well as low flicker noise, which can significantly improve the performance of the current mirror. Attached Figure Description

[0024] Figure 1 This is a circuit logic diagram of a high-precision BJT current mirror based on CMOS technology. Figure 2 This is a schematic diagram of a BJT current mirror structure using a diode connection. Figure 3 This is a schematic diagram of a BJT current mirror structure employing an emitter follower buffer structure; Figure 4 A schematic diagram of a BJT current mirror structure using current source biasing; Figure 5 This is a schematic diagram of the current path relationship in a current source bias circuit. Figure 6 The transistor's ID versus VDS characteristic curves; Figure 7 A schematic diagram of current mirroring for multiple transistors connected in parallel. Detailed Implementation

[0025] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of the high-precision BJT current mirror circuit based on CMOS technology proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0026] This invention provides a high-precision BJT current mirror circuit based on CMOS technology, comprising: a current source bias module, a current mirror core module, and a current discharge module. The current source bias module consists of a PMOS current source, an NMOS current mirror, and a common-source, common-gate current mirror, providing base bias current to the current mirror core module. The current mirror core module is composed of BJT transistors. The current discharge module consists of a PMOS transistor, an NMOS transistor with a resistor path and capacitor connection, and a capacitor, increasing the current discharge path to improve the current adaptability of the current source bias module.

[0027] The current source bias module includes PMOS transistors P1, P2, P3, P4, P5, P6, NMOS transistors N2, N3, and N4; the source of PMOS transistor P1 is connected to the power supply VDD, and its gate is connected to an external bias voltage V. bias The drain of PMOS transistor P2 is connected to the drain of NMOS transistor N2; the source of PMOS transistor P2 is connected to the power supply VDD, and its gate is connected to the gates of PMOS transistors P3, P4, and P5. The drain of PMOS transistor P2 is connected to the source of PMOS transistor P3; the drain of PMOS transistor P3 is connected to both its own gate and the drain of NMOS transistor N3; the source of PMOS transistor P4 is connected to the power supply VDD, and its drain is connected to PMOS transistor P5; the drain of PMOS transistor P5 is connected to the source of PMOS transistor P6; the gate of PMOS transistor P6 is connected to its own drain, and its drain is connected to the drain of NMOS transistor N4; the gate of NMOS transistor N2 is connected to its own drain, and also to the gates of NMOS transistors N3 and N4. The sources of NMOS transistors N2, N3, and N4 are all connected to GND.

[0028] The core module of the current mirror includes NPN transistors Q1 and Q2; the collector of NPN transistor Q1 is connected to a reference current I. REF The base of transistor Q1 is connected to the base of NPN transistor Q2, and the emitter is connected to GND; the collector of NPN transistor Q1 is connected to an external output current I. OUT The emitter is connected to GND.

[0029] The current discharge module consists of an NMOS transistor N1, a PMOS transistor P7, a capacitor C1, and a resistor R1. The gate of the NMOS transistor N1 is connected to the gate of the PMOS transistor P7 and the collector of the NPN transistor Q1, while its source and drain are both connected to GND. The source of the PMOS transistor P7 is connected to the drain of the PMOS transistor P5 and the source of the PMOS transistor P6, while its drain is connected to the first end of the resistor R1, and the second end of the resistor R1 is connected to GND. The first end of the capacitor C1 is connected to the gate of the NMOS transistor N1, the gate of the PMOS transistor P7, and the collector of the NPN transistor Q1, while its second end is connected to GND.

[0030] The specific working principle of this invention is analyzed as follows: The improved current mirror will strictly replicate the reference current I according to the set ratio. REF Furthermore, a current mirror current source is used to provide circuit bias, ensuring that the transistor base current remains within the normal operating range. The circuit of this invention has the following characteristics: This invention decouples the base current path from the main reference current path by using an auxiliary current source bias module with high output impedance to specifically provide drive current for the base node of the mirror transistor. A schematic diagram is shown below. Figure 4 The total base drive current required by transistors Q1 and Q2 is changed to the bias current source i. bias Provides bias current source i bias It is V bias This is generated through P1. At this time, the current flowing through the collector of Q2 will be equal to the collector current of Q1:

[0031] The bias current source i is provided by the current source bias module. bias Physically separating the base current supply path from the precision current mirror path is an effective way to eliminate the system error of traditional BJT current mirror systems. It is suitable for analog integrated circuits that have high requirements for absolute accuracy and do not have extremely demanding output impedance requirements.

[0032] like Figure 1 As shown, the current source bias module, composed of PMOS transistors P1, P2, P3, P4, P5, P6 and NMOS transistors N2, N3, N4, works as follows: A bias voltage V is provided to PMOS transistor P1. bias Constructing a current source I1, when the PMOS transistor P1 is in the saturation region, the current remains approximately constant, and we can obtain:

[0033] Current source I1 is mirrored through NMOS transistors N2 and N3 to obtain current source I2 in the branch, and through NMOS transistors N2 and N4 to obtain current source I4 in the branch; current source I2 is mirrored through a common-source cascode current mirror to obtain current source I3. The final current relationship injected into the base of the BJT current mirror transistor is as follows:

[0034] See the schematic diagram of the current path relationship of the current source bias module. Figure 5 .

[0035] To ensure that transistor Q1 operates normally in the amplification region, this invention introduces a diode-connected path between PMOS transistors P6 and P7, making the base and collector voltages of transistor Q1 approximately equal. Since P6 and P7 use the same PMOS transistor, the base-collector voltage of transistor Q1 can be calculated as follows:

[0036] This makes V CE =V BE V CE V is the emitter-collector voltage of the transistor. BE This is the base-emitter voltage. The NPN transistor operates in the amplification region (V...). CE ≥V BE ), so I C =βI B , where I C For collector current, I B This is the base current.

[0037] Furthermore, this invention enhances the stability of the current source biasing module by employing a common-source, common-gate current mirror composed of PMOS transistors P2, P3, P4, and P5. When current fluctuations occur, PMOS transistors P4 and P5 and NMOS transistor N4 may operate in the non-saturation region: for example, when the drain current I of NMOS transistor N5... D_N5 If the current decreases, the current in the branches of PMOS transistors P4 and P5 will also decrease accordingly. When the current decreases, the drain-source voltage V... DS It will also decrease, potentially causing the transistor to move from the saturation region into the linear region.

[0038] (Considering channel length modulation effect) By employing a common-source cascode current mirror for P2, P3, P4, and P5, the output impedance is significantly increased, which can reduce the occurrence of this situation to some extent. Increasing the impedance would affect... Figure 6 The drain current I of the transistor shown D With drain-source voltage V DSIn terms of the characteristic curve, it is represented by its slope g m The reduction in voltage fluctuation caused by current decreases, providing a certain degree of stability for P4, P5, and N4 to work together in the saturation region.

[0039] Considering the current mirroring of multiple transistors connected in parallel, such as Figure 7 As shown, the base current of the transistor needs to be precisely set, but the current source circuit used has a fixed proportional adjustment, and the maximum current is already fixed. Therefore, this invention adds a current discharge path to improve the current adaptability of the bias circuit.

[0040] like Figure 7 As shown, the bias current should be:

[0041] To obtain the bias current i calculated above bias1 And the i provided by the current source calculated above bias0 Complete equality is obviously impossible. Therefore, we adopt... R 1. The current discharge structure composed of P7, through the design of the current discharge path, allows the current source bias module to provide a base current i greater than required. bias1 Larger current i bias0 In addition to providing the base current, the current Δ i It can be done by R 1. The circuit composed of P7 discharges.

[0042]

[0043] The current discharge path employed in this invention enables precise matching between the base drive current required by the mirror current mirror and the current provided by the bias current source. This design method effectively eliminates the limitations imposed by the finite current source. β The resulting system-level current error ensures the high replication accuracy and stability of the current mirror. This characteristic is particularly useful when multiple outputs are required or low-power applications are used. β This is especially important in applications involving transistors.

[0044] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A high-precision BJT current mirror circuit based on CMOS technology, characterized in that, include: Current source bias module, current mirror core module, current discharge module; The current source bias module consists of a PMOS current source, an NMOS current mirror, and a common source cascode current mirror, providing base bias current to the core module of the current mirror. The core module of the current mirror is composed of BJT transistors; The current discharge module consists of a PMOS transistor, an NMOS transistor with a resistor path and a capacitor connection, and a capacitor. The increased current discharge path improves the current adaptability of the current source bias module.

2. The high-precision BJT current mirror circuit based on CMOS technology as described in claim 1, characterized in that, The current source bias module includes PMOS transistors P1, PMOS transistor P2, PMOS transistor P3, PMOS transistor P4, PMOS transistor P5, PMOS transistor P6, NMOS transistor N2, NMOS transistor N3, and NMOS transistor N4. The source of PMOS transistor P1 is connected to the power supply VDD, and the gate is connected to an external bias voltage V. bias The drain of PMOS transistor P2 is connected to the drain of NMOS transistor N2; the source of PMOS transistor P2 is connected to the power supply VDD, and its gate is connected to the gates of PMOS transistors P3, P4, and P5. The drain of PMOS transistor P2 is connected to the source of PMOS transistor P3; the drain of PMOS transistor P3 is connected to both its own gate and the drain of NMOS transistor N3; the source of PMOS transistor P4 is connected to the power supply VDD, and its drain is connected to PMOS transistor P5; the drain of PMOS transistor P5 is connected to the source of PMOS transistor P6; the gate of PMOS transistor P6 is connected to its own drain, and its drain is connected to the drain of NMOS transistor N4; the gate of NMOS transistor N2 is connected to its own drain, and also to the gates of NMOS transistors N3 and N4. The sources of NMOS transistors N2, N3, and N4 are all connected to GND.

3. The high-precision BJT current mirror circuit based on CMOS technology as described in claim 2, characterized in that, The core module of the current mirror includes NPN transistors Q1 and Q2; the collector of NPN transistor Q1 is connected to a reference current I. REF The base of transistor Q1 is connected to the base of NPN transistor Q2, and the emitter is connected to GND; the collector of NPN transistor Q1 is connected to an external output current I. OUT The emitter is connected to GND.

4. The high-precision BJT current mirror circuit based on CMOS technology as described in claim 3, characterized in that, The current discharge module consists of an NMOS transistor N1, a PMOS transistor P7, a capacitor C1, and a resistor R1. The gate of the NMOS transistor N1 is connected to the gate of the PMOS transistor P7 and the collector of the NPN transistor Q1, while its source and drain are both connected to GND. The source of the PMOS transistor P7 is connected to the drain of the PMOS transistor P5 and the source of the PMOS transistor P6, while its drain is connected to the first end of the resistor R1, and the second end of the resistor R1 is connected to GND. The first end of the capacitor C1 is connected to the gate of the NMOS transistor N1, the gate of the PMOS transistor P7, and the collector of the NPN transistor Q1, while its second end is connected to GND.

5. The high-precision BJT current mirror circuit based on CMOS technology as described in claim 4, characterized in that, The PMOS transistor P6 and the PMOS transistor P7 are the same PMOS transistors.

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