Desktop card issuing device

Abstract

The utility model relates to the technical field of card issuing devices, aims to solve the technical problems of unstable radio frequency signal emission, low communication rate and poor system adaptability of the existing card issuing device, and discloses a desktop card issuing device, which is characterized in that a radio frequency transceiving circuit comprises double emission channels and a single receiving channel, the antenna ports are connected through matching circuits respectively; the matching circuit comprises an inductor L3 and an inductor L4, the TX1 end of the double transmitting channel is connected with the antenna port ANT1 through the inductor L3 and a capacitor C34 in sequence, the TX1 end of the transmitting channel is grounded through the inductor L3, the capacitor C34 and a capacitor C14 in sequence, the TX2 end of the transmitting channel is connected with the second end of the inductor L3 through the inductor L4, a capacitor C13 and a capacitor C11 in sequence, the TX2 end of the transmitting channel is connected with the antenna port ANT1 through the inductor L4, a capacitor C35, a capacitor C15 and a capacitor C14 in sequence, and the TX2 end of the transmitting channel is grounded. And the TX2 end of the transmitting channel is grounded through an inductor L4 and a capacitor C13 in sequence, so that effective synthesis and impedance matching of double-path signals are realized, harmonic and spurious signals are suppressed, and the quality of radio-frequency signals is improved.

Description

Technical Field

[0001] This utility model relates to the field of card issuer technology, and in particular to a desktop card issuer. Background Technology

[0002] With the rapid development of IoT technology, Radio Frequency Identification (RFID) technology has been widely applied in many fields such as logistics management, access control, and asset tracking. In practical applications, RFID readers (also known as card issuers) are core devices, and their performance directly affects the system's identification efficiency and stability.

[0003] Most existing RFID card issuers adopt a single-end transmission design. The radio frequency signal is susceptible to harmonic interference and poor antenna port matching along the transmission path, resulting in shortened identification distance, reduced identification accuracy, and even decreased system stability. In addition, some devices neglect noise filtering and front-end matching in the receiving path during signal processing, resulting in weak system response to tags and insufficient anti-interference capability.

[0004] In terms of radio frequency circuit design, achieving efficient synthesis, harmonic suppression, and antenna matching of dual-channel radio frequency signals has always been key to improving the performance of card issuers. Meanwhile, the data communication method between the main controller and the RFID module also affects the overall communication efficiency and system response speed. Traditional interfaces such as I2C often have rate bottlenecks in high-frequency scenarios, making it difficult to meet the demands of high-performance applications.

[0005] Therefore, there is an urgent need for a desktop RFID card issuer with a compact structure, high signal integrity, and stable communication to optimize the design of the radio frequency transceiver path, improve communication efficiency and overall system performance, and meet the actual needs of next-generation RFID applications. Utility Model Content

[0006] The purpose of this invention is to provide a desktop card issuer to solve the technical problems of unstable radio frequency signal transmission, low communication rate and poor system adaptability of existing card issuers.

[0007] To achieve the above objectives, this utility model provides a desktop card issuer, including a microcontroller, an RFID module, and an RF transceiver circuit. The RF transceiver circuit includes dual transmit channels and a single receive channel, which are respectively connected to a matching circuit, antenna port ANT1, and antenna port ANT2. The matching circuit includes inductor L3 and inductor L4. The TX1 terminal of the dual transmit channels is connected to antenna port ANT1 via inductor L3 and capacitor C34 in sequence. The TX1 terminal of the transmit channels is grounded via inductor L3, capacitor C34, and capacitor C14 in sequence. The TX2 terminal of the transmit channels is connected to the second terminal of inductor L3 via inductor L4, capacitor C13, and capacitor C11 in sequence. The TX2 terminal of the transmit channels is connected to antenna port ANT1 via inductor L4, capacitor C35, capacitor C15, and capacitor C14 in sequence. The TX2 terminal of the transmit channels is grounded via inductor L4 and capacitor C13 in sequence. Inductor L3, inductor L4, capacitor C34, capacitor C11, capacitor C13, capacitor C14, and capacitor C15 form a π-type filter circuit.

[0008] This invention achieves effective synthesis and impedance matching of dual signals by setting up dual transmission channels connected to the antenna port ANT1 via a π-type filter circuit composed of inductors L3 and L4 and multiple capacitors. This significantly suppresses harmonics and spurious signals, improving the transmission efficiency and transmission quality of radio frequency signals. At the same time, the receiving channel is connected to ANT2 through front-end matching, enhancing the receiving sensitivity. The overall structure improves radio frequency performance and system stability, thereby achieving the beneficial effects of longer identification distance, higher identification accuracy, and more reliable communication.

[0009] Furthermore, the RX terminal of the receiving channel is connected to the antenna port ANT2 via resistor R18 and capacitor C36, and the TX2 terminal of the transmitting channel is connected to the antenna port ANT2 via inductor L4 and capacitor C35. Through this reasonable front-end matching and coupling design, the receiving channel's response to echo or tag-reflected signals is improved, the noise suppression effect of the signal path is optimized, and the receiving sensitivity and system anti-interference performance are enhanced.

[0010] Furthermore, the XTAL1 and XTAL2 ports of the RFID module are connected to a crystal oscillator, with grounded capacitors on both sides to provide a clock signal. This provides a stable and reliable clock source for the RFID module, ensuring the normal operation of the internal logic circuits and contributing to improved system stability and data processing accuracy.

[0011] Furthermore, the microcontroller and RFID module are connected via an SPI bus. The SPI interface features high speed, full-duplex operation, and strong anti-interference capabilities, enabling fast and stable data exchange, improving the overall communication efficiency and response speed of the card issuer, and making it suitable for high-performance RFID applications.

[0012] The desktop card issuer provided by this utility model has the following advantages:

[0013] Compared with the prior art, this utility model introduces a π-type filter circuit composed of inductors L3 and L4 and multiple capacitors between the dual transmission channels TX1 and TX2, which effectively realizes the synthesis, filtering and impedance matching of radio frequency signals, significantly improves the integrity and stability of radio frequency signals, suppresses harmonic interference and spurious signals, enhances the transmission efficiency and receiving sensitivity of the antenna, thereby improving the distance and accuracy of RFID identification, ensuring the communication reliability and anti-interference capability of the system, and has the advantage of stable performance. Attached Figure Description

[0014] Figure 1 The RFID module and its peripheral circuit structure diagram provided by this utility model;

[0015] Figure 2 The filter circuit structure diagram provided by this utility model;

[0016] Figure 3 The microcontroller and its peripheral circuit structure provided by this utility model. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this utility model and are not intended to limit this utility model.

[0018] See Figures 1 to 3 This utility model provides a desktop card issuer, including a microcontroller U2, an RFID module U1, and a radio frequency transceiver circuit. The radio frequency transceiver circuit is connected to a transceiver antenna. The microcontroller U2 and the RFID module U1 are connected via an SPI bus.

[0019] The XTAL1 and XTAL2 of the RFID module U1 are connected to the crystal oscillator Y1, and the two sides are connected to the ground via capacitors to provide clock signals.

[0020] See Figure 2The radio frequency transceiver circuit is connected to a π-type filter. The front-end matching circuit of the RFID radio frequency transmitter / receiver is mainly used for the matching network between the TX1 / TX2 dual transmitter ports and the antenna ANT1, as well as the matching path between the RX receiver and the antenna ANT2.

[0021] Among them, the specifications of inductors L3 and L4 are 2.2μH (L-type matching).

[0022] The signal flow in the transmitting section is: TX1, TX2 → ANT1

[0023] 1. TX1 path

[0024] TX1 → Inductor L3

[0025] Pin 2 of inductor L3 → Inductor C34 → Antenna terminal ANT1

[0026] The first end of inductor L3 is connected to the TX1 port of RFID module U1, and the second end of inductor L3 is connected to the antenna ANT1 through capacitor C34. The second end of inductor L3 is grounded through capacitor C34 and capacitor C14 in sequence, and the second end of inductor L3 is grounded through capacitor C11 in sequence.

[0027] 2. TX2 path

[0028] TX2 → Inductor L4

[0029] Inductor L4 pin 2 → Capacitor C35 → Capacitor C15 → Capacitor C14 → Antenna terminal ANT1

[0030] The first terminal of inductor L4 is connected to the TX2 port of RFID module U1. The second terminal of inductor L4 is connected to the second terminal of inductor L3 in sequence through capacitor C13 and capacitor C11. The second terminal of inductor L4 is grounded through capacitor C13.

[0031] 3. RX path

[0032] RFID module U1's RX port → Resistor R18 → Capacitor C36 → Antenna ANT2

[0033] The RX port of RFID module U1 is connected to the antenna terminal ANT2 via resistor R18 and capacitor C36 in sequence.

[0034] Common-mode network description

[0035] TX1 and TX2 are output through L3 and L4 respectively. After passing through multiple cross-coupled capacitors C11, C13, C35, C14 and C15, a π-type structure is constructed to achieve dual-end signal synthesis and output to ANT1.

[0036] This circuit implements the provided RFID transceiver function, and its working principle is as follows:

[0037] Regarding power supply: The module is powered by an external power supply VCC, and each voltage is regulated by a filter capacitor to ensure operational stability.

[0038] In terms of communication: RFID module U1 communicates with microcontroller U2 through the SPI interface. Microcontroller U2 controls the working status of the module by reading / writing registers and receives identification information.

[0039] In terms of clock driving: Crystal oscillator Y1 provides the basic operating frequency for the chip and drives the internal logic of RFID module U1.

[0040] Radio frequency signal transmission:

[0041] The modulated radio frequency signals output by TX1 and TX2 of RFID module U1 are filtered and matched by a π-type network and then sent to an external antenna to realize RFID signal transmission.

[0042] Radio frequency signal reception:

[0043] The antenna receives echo or tag reflection signals, which are then transmitted to the RX pin via internal circuitry for amplification and processing. The microcontroller U2 ultimately reads the identification data.

[0044] The desktop card issuer provided by this utility model has the following advantages:

[0045] This invention combines dual transmission channels with a π-type filter circuit to effectively improve the synthesis efficiency and transmission quality of radio frequency signals, suppress harmonic interference and spurious signals, ensure signal integrity, and significantly improve identification distance and accuracy. The receiving channel adopts a front-end matching design to enhance receiving sensitivity and anti-interference capability. The RFID module obtains a stable clock through a crystal oscillator to ensure stable system operation. The microcontroller and RFID module communicate via an SPI bus, providing high-speed and reliable data transmission capabilities. The circuit structure is easy to integrate and can be easily integrated into various desktop or embedded RFID application scenarios, offering advantages such as stable communication, accurate identification, and compact structure.

[0046] The above description is only a preferred embodiment of the present utility model and is not intended to limit the present utility model. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included within the protection scope of the present utility model.

Claims

1. A desktop card issuer, characterized in that, The system includes a microcontroller (U2), an RFID module (U1), and an RF transceiver circuit. The RF transceiver circuit includes dual transmit channels and a single receive channel, which are connected to antenna ports ANT1 and ANT2 respectively through a matching circuit. The matching circuit includes inductors L3 and L4. The TX1 terminal of the dual transmit channels is connected to antenna port ANT1 via inductor L3 and capacitor C34 in sequence. The TX1 terminal of the transmit channels is grounded via inductor L3, capacitor C34, and capacitor C14 in sequence. The TX2 terminal of the transmit channels is connected to the second terminal of inductor L3 via inductor L4, capacitor C13, and capacitor C11 in sequence. The TX2 terminal of the transmit channels is connected to antenna port ANT1 via inductor L4, capacitor C35, capacitor C15, and capacitor C14 in sequence. The TX2 terminal of the transmit channels is grounded via inductor L4 and capacitor C13 in sequence. The inductors L3, L4, C34, C11, C13, C14, and C15 form a π-type filter circuit.

2. The desktop card issuer according to claim 1, characterized in that, The RX terminal of the receiving channel is connected to the antenna port ANT2 via resistor R18 and capacitor C36 in sequence, and the TX2 terminal of the transmitting channel is connected to the antenna port ANT2 via inductor L4 and capacitor C35 in sequence.

3. The desktop card issuer according to claim 2, characterized in that, The XTAL1 and XTAL2 ports of the RFID module (U1) are connected to a crystal oscillator (Y1), with grounded capacitors on both sides to provide a clock signal.

4. The desktop card issuer according to claim 3, characterized in that, The microcontroller (U2) and the RFID module (U1) are connected via an SPI bus.

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