Frequency-locked loop circuit driven by high power supply rejection ratio and low swing and control method thereof

Abstract

The invention relates to the field of integrated circuit design, and particularly discloses a high power supply rejection ratio and low swing driving frequency-locked loop circuit and a control method thereof, a low dropout regulator is adopted to provide independent power supply lower than a main power supply voltage for a voltage-controlled oscillator, and double optimization effects are achieved. The clean power supply provided by the low dropout linear regulator effectively isolates the interference of the main power supply noise to the voltage-controlled oscillator, so that the power supply noise suppression capability of the circuit is remarkably enhanced, and the jitter of an output clock signal is greatly reduced; and on the other hand, the working voltage of the voltage-controlled oscillator is allowed and dynamically regulated and controlled to be optimized in a low range meeting the performance according to the real-time load of the voltage-controlled oscillator, so that on-demand power supply is realized, the dynamic power consumption of the voltage-controlled oscillator is reduced to the maximum extent while the output quality is not reduced, and the energy efficiency of the whole circuit under different load conditions is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a frequency locked loop circuit with high power supply rejection ratio and low swing drive and a control method thereof. Background Art

[0002] Frequency-locked loops (FLLs) and phase-locked loops (PLLs) are core modules in clock generation circuits. However, the performance of these circuits, particularly their internal voltage-controlled oscillators (VCOs), is susceptible to power supply noise. In some traditional designs, the VCO is powered directly from the system's main power supply (VDD). This approach causes power supply noise to couple directly to the VCO's output frequency, causing clock signal jitter and impacting system stability.

[0003] To improve the impact of power supply noise on VCO performance, several solutions have been proposed in the prior art: The first solution is to use a global low-dropout linear regulator to provide a low-noise power supply for the entire frequency-locked loop (FLL) or phase-locked loop (PLL). While this approach can suppress some power supply noise to a certain extent, it does not address the VCO's need to operate within the full VDD swing, resulting in still high VCO driving power consumption. Furthermore, a global low-dropout linear regulator cannot completely isolate the VCO from the coupling effects of local power supply noise generated by the digital modules in the loop.

[0004] Another solution is to add an RC filter to the VCO's power supply path for isolation. While this approach can suppress some high-frequency noise, the resistors in the RC filter introduce additional voltage drop. To compensate for this voltage drop and maintain the required VCO frequency tuning range, the VCO's operating voltage may need to be increased, which can increase power consumption. Furthermore, the RC filter's ability to suppress low-frequency power supply noise is generally limited.

[0005] Another solution is to use a differential VCO. The common-mode rejection of differential signals can theoretically offset some of the effects of power supply noise, improving noise rejection. However, differential VCOs typically require more complex frequency tuning circuits, such as large capacitor arrays, which significantly increases the chip area. Furthermore, component mismatch in the differential structure can introduce new nonlinear errors, affecting VCO performance.

[0006] In addition to the effects of power supply noise on the VCO, the techniques used to generate the feedback current in the feedback loop can also be inadequate. For example, a switched-capacitor charge pump can introduce charge injection errors when generating the feedback current if there is overlap in the control clock signal, which can limit the ultimate locking accuracy of the loop. Summary of the Invention

[0007] The purpose of the present invention is to provide a frequency locked loop circuit with high power supply rejection ratio and low swing drive and a control method thereof, which solves the defects of voltage controlled oscillators that they have high power consumption and are susceptible to power supply noise coupling interference.

[0008] The present invention discloses a frequency-locked loop circuit with high power supply rejection ratio and low swing drive, comprising: a current comparator for comparing a reference current with a feedback current and generating an error current signal according to the comparison result; a loop filter for generating a control voltage based on the error current signal; A low-dropout linear regulator, configured to dynamically adjust an operating voltage of the voltage-controlled oscillator according to a load current of the voltage-controlled oscillator; wherein the operating voltage is lower than a main power supply voltage received by the low-dropout linear regulator; A voltage-controlled oscillator, comprising: a bias voltage providing unit, an odd number of delay cascade units and an output buffer; The bias voltage providing unit provides a bias voltage for each of the delay cascade units based on the control voltage; The plurality of delay cascade units are sequentially connected end to end in series, and the output end of the last delay cascade unit outputs a first voltage signal; wherein the delay cascade unit is used to logically invert the voltage inside the voltage-controlled oscillator and apply a transmission delay adjusted by the control voltage; The first voltage signal is buffered by the output buffer to generate the output clock signal.

[0009] Furthermore, the current comparator includes: a first operational amplifier, a second operational amplifier, a first resistor, a first capacitor, a first PMOS transistor, a second PMOS transistor and a first NMOS transistor; The non-inverting input terminal of the first operational amplifier is connected to a first reference voltage; The gate of the first PMOS transistor is connected to the output terminal of the first operational amplifier, the source is connected to the main power supply voltage, the drain is connected to the inverting input terminal of the first operational amplifier, and the drain of the first PMOS transistor is also grounded through a first resistor; The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the source is connected to the reference current, and the drain forms a comparison node; The non-inverting input terminal of the second operational amplifier is connected to a second reference voltage; The gate of the first NMOS transistor is connected to the output terminal of the second operational amplifier, the drain is connected to the comparison node, the source is connected to the inverting input terminal of the second operational amplifier, and the source of the first NMOS transistor is also grounded through a first capacitor.

[0010] Furthermore, it also includes a feedback circuit, which is used to generate the feedback current based on the output clock signal.

[0011] Furthermore, the feedback circuit includes: A frequency divider, dividing the output clock signal to generate a divided clock signal; a first level converter, performing voltage domain conversion on the frequency-divided clock signal; a non-overlapping clock generating circuit for generating a non-overlapping clock signal based on the divided clock signal converted in the voltage domain; A switch network generates the feedback current based on the non-overlapping clock signal and the second reference voltage.

[0012] Furthermore, the switch network includes: a second capacitor, a third capacitor, a first switch, a second switch, a third switch and a fourth switch; One end of the first switch and the second switch are connected to the source of the first NMOS transistor, and the other ends are connected to one end of the second capacitor and one end of the third capacitor respectively, and the other ends of the second capacitor and the third capacitor are both connected to ground; the first switch and the second switch are controlled by a first clock signal and a second clock signal respectively; The third switch is connected between one end of the second capacitor and the ground and is controlled by the second clock signal; The fourth switch is connected between one end of the third capacitor and the ground, and is controlled by the first clock signal.

[0013] Furthermore, the loop filter includes: a fourth capacitor and a second resistor; One end of the fourth capacitor is connected to the comparison node, and the other end is grounded through the second resistor.

[0014] Furthermore, the bias voltage providing unit includes: a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor and a third NMOS transistor; The gate of the third PMOS transistor is connected to a low-level enable signal, and the gate of the second NMOS transistor is connected to a high-level enable signal; The source and drain of the third PMOS transistor are respectively connected to the drain and source of the second NMOS transistor to form a first connection node and a second connection node; The source of the fourth PMOS transistor is connected to the operating voltage, the drain is connected to the first connection node, and the gate is connected to the bias voltage input terminal of the delay cascade unit and the drain of the fourth PMOS transistor; The source of the third NMOS transistor is grounded, the gate is connected to the control voltage, and the drain is connected to the second connection node.

[0015] Furthermore, the delay cascade unit includes: a fifth PMOS transistor, a sixth PMOS transistor, a fourth NMOS transistor and a fifth NMOS transistor; The source of the fifth PMOS transistor is connected to the operating voltage, the gate is connected to the output end of the bias voltage providing unit and is used to receive the bias voltage, and the drain is connected to the source of the sixth PMOS transistor; A node where the gate of the sixth PMOS transistor and the gate of the fourth NMOS transistor are connected is connected to an output end of another delay cascade unit; A node where the drain of the sixth PMOS tube is connected to the drain of the fourth NMOS tube is connected to an input end of another delay cascade unit; The source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the control voltage, and the source of the fifth NMOS transistor is grounded.

[0016] Furthermore, the output buffer includes: an even number of inverters connected in series, and the last inverter outputs the output clock signal.

[0017] Furthermore, the low voltage difference linear regulator includes: a seventh PMOS transistor, an eighth PMOS transistor, a sixth NMOS transistor, a fifth capacitor and a sixth capacitor; The source of the eighth PMOS transistor is connected to the drain of the seventh PMOS transistor, the drain of the eighth PMOS transistor is grounded via a second current source, and the gate of the eighth PMOS transistor is connected to a fourth reference voltage; the source of the seventh PMOS transistor is connected to a power supply voltage, and the gate of the seventh PMOS transistor is connected between the first current source and the drain of the sixth NMOS transistor; a third connection node connecting the source of the eighth PMOS transistor and the drain of the seventh PMOS transistor outputs the operating voltage; The drain of the sixth NMOS transistor is connected to the first current source; the gate is connected to the third reference voltage, the source is connected to one end of the fifth capacitor, one end of the fifth capacitor is also connected to the first current source; the other end of the fifth capacitor is connected to the third connection node; One end of the sixth capacitor is connected to the third connection node, and the other end is grounded.

[0018] Furthermore, the system further includes: a second level converter, which converts the output clock signal into a system clock output signal.

[0019] On the other hand, the present invention further discloses a frequency locked loop method with high power supply rejection ratio and low swing drive, the method comprising: comparing the reference current with the feedback current and generating an error current signal based on the comparison result; generating a control voltage based on the error current signal; generating an operating voltage lower than the main power voltage based on the main power voltage; Under the operating voltage, an output clock signal is generated based on the control voltage.

[0020] Compared with the prior art, the present invention has at least the following technical effects: The present invention introduces a dedicated low-voltage dropout linear regulator for independent power supply to the internal voltage-controlled oscillator under a closed-loop architecture composed of a current comparator and a loop filter, thereby achieving all-round optimization from power supply to signal chain. The clean power provided by the low-voltage dropout linear regulator and the high power supply rejection ratio of the voltage-controlled oscillator itself work together to significantly reduce clock jitter. At the same time, its characteristic of dynamically adjusting the voltage according to the load greatly optimizes power consumption. In addition, the bias voltage providing unit inside the voltage-controlled oscillator converts the main control voltage into a precise bias for an odd number of delay cascade units, so that the transmission delay of each inverting stage can be finely adjusted to achieve high-precision frequency control, generate a stable clock with strong driving capability, and effectively isolate the interference of back-end load changes on the oscillator core frequency. This helps the circuit ultimately generate a stable clock signal with high quality, low power consumption and low jitter characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 This is a schematic block diagram of the structure of a frequency-locked loop circuit with high power supply rejection ratio and low swing drive in the first embodiment of the present invention; Figure 2 Schematic diagram of the structure of the current comparator, loop filter and switch network in the first embodiment of the present invention; Figure 3 Schematic diagram of the structure of the voltage-controlled oscillator in the first embodiment of the present invention; Figure 4 Schematic diagram of the structure of a low-dropout linear regulator in Embodiment 1 of the present invention; Figure 5 This is a simplified flowchart of a method for controlling a frequency-locked loop circuit with high power supply rejection ratio and low swing drive in the second embodiment of the present invention. DETAILED DESCRIPTION

[0022] The high power supply rejection ratio and low swing driven frequency locked loop circuit and its control method of the present invention will be described in detail below with reference to the schematic diagram, in which the preferred embodiment of the present invention is shown. It should be noted that the following description is intended to enable those skilled in the art to understand and implement the present invention, and is for the purpose of illustrating rather than limiting the scope of the present invention. Those skilled in the art should understand that, based on the teachings of this specification, various forms of modification, equivalent replacement or improvement can be made to the specific embodiments described without departing from the core spirit and principles of the present invention, such as cross-combining the technical features in different embodiments to form a new technical solution. As long as no technical contradictions arise, these variations and combinations should fall within the scope of protection claimed by the present invention.

[0023] The following paragraphs describe the present invention in more detail by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are greatly simplified and not to exact scale, and are provided solely for the purpose of assisting in the description of the embodiments of the present invention.

[0024] Example 1 Please refer to Figures 1-4 The present invention discloses a frequency-locked loop circuit with high power supply rejection ratio and low swing drive, comprising: A current comparator is configured to compare a reference current IREF with a feedback current IDN and generate an error current signal based on the comparison result. A loop filter is configured to generate a control voltage Vctrl based on the error current signal. A low-dropout linear regulator is configured to dynamically adjust an operating voltage VDD_VCO of the voltage-controlled oscillator based on the load current of the voltage-controlled oscillator; wherein the operating voltage VDD_VCO is lower than the main power supply voltage VDD received by the low-dropout linear regulator. The voltage-controlled oscillator is configured to generate the output clock signal CLK_VCO based on the control voltage Vctrl. A voltage-controlled oscillator, comprising: a bias voltage providing unit, an odd number of delay cascade units, and an output buffer; the bias voltage providing unit provides a bias voltage to each delay cascade unit based on the control voltage Vctrl; multiple delay cascade units are connected in series end to end, with the output end of the last delay cascade unit outputting a first voltage signal; wherein the delay cascade units are used to logically invert the voltage inside the voltage-controlled oscillator and apply a transmission delay adjusted by the control voltage; the first voltage signal is buffered by the output buffer to generate an output clock signal CLK_VCO.

[0025] In this embodiment, a dedicated low-dropout linear regulator is introduced to independently power the internal voltage-controlled oscillator within a closed-loop architecture consisting of a current comparator and a loop filter, thereby achieving all-round optimization from power supply to signal chain. The clean power provided by the low-dropout linear regulator works synergistically with the high power supply rejection ratio of the voltage-controlled oscillator itself to significantly reduce clock jitter. At the same time, its ability to dynamically adjust voltage according to the load greatly optimizes power consumption. In addition, the bias voltage supply unit within the voltage-controlled oscillator converts the main control voltage into a precise bias for an odd number of delay cascade units, thereby enabling fine adjustment of the transmission delay of each inverting stage to achieve high-precision frequency control, generate a stable clock with strong driving capability, and effectively isolate the interference of back-end load changes on the oscillator core frequency. This helps the circuit ultimately generate a stable clock signal with high quality, low power consumption, and low jitter.

[0026] Specifically, under 100mVpp power supply ripple injection, the frequency jitter amplitude of the voltage-controlled oscillator (VCO) using the above-mentioned high power supply rejection ratio and low swing drive frequency-locked loop circuit is suppressed to 16.1% of the traditional direct supply architecture (i.e., an improvement of 6.2 times); the operating voltage VDD_VCO of the VCO is reduced from the original main power supply voltage VDD of 2.8V to 2.2V, the swing drive power consumption is reduced, and the measured total power consumption is saved by 35%.

[0027] Furthermore, the current comparator includes: a first operational amplifier U1, a second operational amplifier U2, a first resistor R1, a first capacitor C1, a first PMOS transistor MP1, a second PMOS transistor MP2 and a first NMOS transistor MN1.

[0028] The non-inverting input terminal of the first operational amplifier U1 is connected to the first reference voltage VREF1.

[0029] The gate of the first PMOS transistor MP1 is connected to the output terminal of the first operational amplifier U1, the source is connected to the main power supply voltage, the drain is connected to the inverting input terminal of the first operational amplifier U1, and the drain of the first PMOS transistor MP1 is also grounded through the first resistor R1.

[0030] The gate of the second PMOS transistor MP2 is connected to the gate of the first PMOS transistor MP1 , the source is connected to the reference current, and the drain forms a comparison node.

[0031] The non-inverting input terminal of the second operational amplifier U2 is connected to the second reference voltage VREF2.

[0032] The gate of the first NMOS transistor MN1 is connected to the output terminal of the second operational amplifier U2, the drain is connected to the comparison node, and the source is connected to the inverting input terminal of the second operational amplifier U2. The source of the first NMOS transistor MN1 is also grounded through the first capacitor C1.

[0033] In this embodiment, the current comparator can linearly map the first reference voltage VREF1 to the reference current IREF.

[0034] in, , VREF1 is the value of the first reference voltage, IREF is the reference current value, and R1 is the resistance value of the first resistor R1.

[0035] Next, based on the aspect ratio coefficient of the first PMOS transistor MP1 and the second PMOS transistor MP2 Implement current mirroring, so that the second PMOS tube MP2 branch generates a ratio of Reference current .

[0036] in, ; is the width-to-length ratio of the second PMOS transistor MP2, is the width-to-length ratio of the first PMOS transistor MP1, is the proportional coefficient.

[0037] The feedback current IDN is generated by the periodic charging and discharging of the first capacitor C1 driven by the non-overlapping clocks CLKN and CLKP, and satisfies .

[0038] Wherein, C1 is the capacitance of the first capacitor C1, VREF2 is the magnitude of the second reference voltage, and fb is the feedback frequency (fb=fout / N, N is the frequency division ratio, and fout is the output frequency).

[0039] When the system is in steady state, the current balance condition is forced to be satisfied =IDN, the output frequency expression is derived by combining the frequency relationship: ,in , which shows that fout is only proportional to the coefficient The output frequency fout is related to the process constants of the first capacitor C1, the frequency division ratio N, and the first capacitor C1, while being decoupled from the power supply voltage VDD and the reference voltage VREF1. This feature makes the output frequency fout highly robust to process variations, power supply fluctuations, and temperature variations (PVT).

[0040] Furthermore, in this embodiment, a feedback circuit is further included, wherein the feedback circuit is configured to generate the feedback current IDN based on the output clock signal CLK_VCO, thereby completing closed-loop detection and compensation of frequency error.

[0041] Specifically, the feedback circuit includes: The frequency divider divides the output clock signal CLK_VCO to generate a divided clock signal CLK_DIV.

[0042] The first level converter performs voltage domain conversion on the divided clock signal CLK_DIV.

[0043] The non-overlapping clock generating circuit generates a non-overlapping clock signal based on the divided clock signal CLK_DIV converted into the voltage domain.

[0044] The switch network generates the feedback current IDN based on the non-overlapping clock signals CLKN and CLKP and the second reference voltage VREF2.

[0045] Specifically, the voltage-controlled oscillator generates an output clock signal CLK_VCO. CLK_VCO synchronously drives a frequency divider to generate a divided clock signal CLK_DIV. The divided clock signal CLK_DIV undergoes level conversion via a first electrical converter and is then fed into a non-overlapping clock generation circuit. Ultimately, the non-overlapping clock generation circuit generates phase-complementary non-overlapping clock signals, namely the first clock signal CLKN and the second clock signal CLKP (frequency fb = fout / N, where N is the division ratio). The first and second clock signals CLKN and CLKP control a switched capacitor network in a non-overlapping manner, generating a feedback current IDN through the charge pump effect to achieve closed-loop detection and compensation of frequency error.

[0046] In this embodiment, the switch network includes: a second capacitor C2, a third capacitor C3, a first switch S1, a second switch S2, a third switch S3, and a fourth switch S4.

[0047] Specifically, one end of the first switch S1 and the second switch S2 are connected to the source of the first NMOS transistor MN1, and the other ends are connected to one end of the second capacitor C2 and one end of the third capacitor C3, respectively. The other ends of the second capacitor C2 and the third capacitor C3 are both connected to ground. The first switch S1 and the second switch S2 are controlled by the first clock signal CLKN and the second clock signal CLKP, respectively.

[0048] The third switch S3 is connected between one end of the second capacitor C2 and ground, and is controlled by the second clock signal CLKP.

[0049] The fourth switch S4 is connected between one end of the third capacitor C3 and ground, and is controlled by the first clock signal CLKN.

[0050] In this embodiment, the switch network uses two complementary, non-overlapping clock signals (a first clock signal CLKN and a second clock signal CLKP) to control the switches, alternatingly operating the two capacitors (the second capacitor C2 and the third capacitor C3). The purpose is to extract a certain average current from the input end (the point connected to the first switch S1 and the second switch S2, i.e., the source of the NMOS transistor, with a voltage of approximately VREF2). This average current is the feedback current IDN.

[0051] Furthermore, the loop filter includes: a fourth capacitor C4 and a second resistor R2.

[0052] Specifically, one end of the fourth capacitor C4 is connected to the comparison node, and the other end is grounded via the second resistor R2.

[0053] In this embodiment, after receiving the error current signal from the current comparator, the loop filter removes high-frequency noise and pulses through low-pass filtering, and converts the error current into a relatively smooth control voltage Vctrl by integrating the error current. The control voltage Vctrl is then used to adjust the output frequency of the voltage-controlled oscillator to obtain a high-performance phase-locked loop.

[0054] In this embodiment, the bias voltage providing unit includes: a third PMOS transistor MP3, a fourth PMOS transistor MP4, a second NMOS transistor MN2, and a third NMOS transistor MN3.

[0055] Specifically, the gate of the third PMOS transistor MP3 is connected to a low-level enable signal ENB, and the gate of the second NMOS transistor MN2 is connected to a high-level enable signal ENI. The source and drain of the third PMOS transistor MP3 are respectively connected to the drain and source of the second NMOS transistor MN2, forming a first connection node and a second connection node, respectively. The source of the fourth PMOS transistor MP4 is connected to the operating voltage VDD_VCO, the drain is connected to the first connection node, and the gate is connected to the bias voltage input terminal and the drain of the delay cascade unit. The source of the third NMOS transistor MN3 is grounded, the gate is connected to the control voltage Vctrl, and the drain is connected to the second connection node.

[0056] In this embodiment, the third NMOS transistor MN3 is used to set the current flowing through the bias branch. When the circuit is enabled, the transmission switch, formed by the third PMOS transistor MP3 and the second NMOS transistor MN2 in parallel, is turned on. At this point, the current set by the third NMOS transistor MN3 can flow through the turned-on switch and reach the fourth PMOS transistor MP4, establishing a stable bias voltage on the gate of the fourth PMOS transistor MP4. This voltage is then provided as a bias voltage to the delay cascade unit. When the enable signal is deactivated, the transmission switch is turned off, cutting off the bias current path, thereby preventing the generation of the bias voltage and disabling the oscillator.

[0057] Furthermore, in this embodiment, the delay cascade unit includes: a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a fourth NMOS transistor MN4 and a fifth NMOS transistor MN5.

[0058] Specifically, the source of the fifth PMOS transistor MP5 is connected to the operating voltage VDD_VCO, the gate is connected to the output of the bias voltage providing unit for receiving the bias voltage, and the drain is connected to the source of the sixth PMOS transistor MP6. The node where the gate of the sixth PMOS transistor MP6 is connected to the gate of the fourth NMOS transistor MN4 is connected to the output of another delay cascade unit. The node where the drain of the sixth PMOS transistor MP6 is connected to the drain of the fourth NMOS transistor MN4 is connected to the input of another delay cascade unit. The source of the fourth NMOS transistor MN4 is connected to the drain of the fifth NMOS transistor MN5. The gate of the fifth NMOS transistor MN5 is connected to the control voltage Vctrl, and the source of the fifth NMOS transistor MN5 is grounded.

[0059] In a specific embodiment, the number of delay cascade units is 3. Of course, those skilled in the art can select the number of delay cascade units based on design decisions such as target frequency, phase noise requirements, power budget, area constraints, and matching with other loop parameters. For example, the number may be 5 or 7, and no specific limitation is imposed herein.

[0060] In this embodiment, by controlling the voltage Vctrl's effect on the transconductance characteristics of the fifth NMOS transistor MN5 within the voltage-controlled oscillator, voltage variations are effectively converted into control over the magnitude of the current flowing through the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5. This controlled current, in turn, affects the discharge rate of the output node of each delay cascade unit, adjusting the transmission delay time of the signal through each delay cascade unit (higher current means shorter delay, and vice versa). Because the frequency of the entire oscillator is inversely proportional to the total delay time of the signal traveling around the loop, adjusting the unit delay by controlling the voltage Vctrl ultimately achieves precise modulation of the oscillator's output frequency.

[0061] Furthermore, the output buffer includes: an even number of inverters NG connected in series, and the last inverter NG outputs the output clock signal CLK_VCO.

[0062] In a specific embodiment, the number of inverters NG is two, meeting the requirements of a common-mode buffer. Those skilled in the art may weigh the ratio of the load to be driven to the output capability of the previous stage, in combination with factors such as delay, power consumption, and area, and may also use four or six inverters, for example, without specific limitation herein.

[0063] In this embodiment, the output buffer can effectively shape the original signal from the oscillator core, and output the output clock signal CLK_VCO with a steeper edge and a waveform closer to an ideal square wave, thereby enabling the subsequent system to operate stably, reliably and at high speed.

[0064] The low voltage difference linear regulator includes: a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, a sixth NMOS transistor MN6, a fifth capacitor C5 and a sixth capacitor C6.

[0065] Specifically, the source of the eighth PMOS transistor MP8 is connected to the drain of the seventh PMOS transistor MP7, the drain of the eighth PMOS transistor MP8 is grounded via the second current source I2, and the gate of the eighth PMOS transistor MP8 is connected to the third reference voltage VB2; the source of the seventh PMOS transistor MP7 is connected to the main power supply voltage VDD, and the gate of the seventh PMOS transistor MP7 is connected between the first current source I1 and the drain of the sixth NMOS transistor MN6; and a third connection node at which the source of the eighth PMOS transistor MP8 and the drain of the seventh PMOS transistor MP7 are connected outputs the operating voltage VDD_VCO.

[0066] The drain of the sixth NMOS transistor MN6 is connected to the first current source I1; the gate is connected to the fourth reference voltage VB1, the source is connected to one end of the fifth capacitor C5, and one end of the fifth capacitor C5 is also connected to the first current source I1; the other end of the fifth capacitor C5 is connected to the third connection node.

[0067] One end of the sixth capacitor C6 is connected to the third connection node, and the other end is grounded.

[0068] Please refer to Figure 4In this embodiment, the low-dropout linear regulator utilizes Miller compensation. Through the dynamic response of the seventh PMOS transistor MP7 and the pole-splitting design of the fifth capacitor C5, the main pole is placed at the internal node Y, while simultaneously pushing the poles of the X and Z nodes (the third connection node) outside the unity-gain bandwidth. The sixth capacitor C6, acting as an output stabilizing capacitor, effectively absorbs ripple, thereby improving the phase stability of the low-dropout linear regulator. Furthermore, by using a separate low-dropout linear regulator to power the voltage-controlled oscillator, this embodiment decouples the operating voltage VDD_VCO from the main power supply voltage VDD, effectively suppressing power supply noise from jittering the gate voltage of the MOS transistors in the voltage-controlled oscillator and, consequently, suppressing output frequency jitter.

[0069] Furthermore, this embodiment further includes: a second level converter, which is used to convert the output clock signal CLK_VCO into a system clock output signal, and the system clock output signal can be used as the clock output provided by the frequency-locked loop circuit to the outside.

[0070] Example 2 Please refer to Figure 5 This embodiment discloses a frequency-locked loop method with high power supply rejection ratio and low swing drive, which is implemented using the frequency-locked loop circuit with high power supply rejection ratio and low swing drive disclosed in Example 1. The method includes the following steps: S1. Compare the reference current IREF with the feedback current IDN and generate an error current signal based on the comparison result; S2. Generates a control voltage Vctrl based on the error current signal; S3. Generating an operating voltage VDD_VCO lower than the main power supply voltage VDD based on the main power supply voltage VDD; S4. Under the operating voltage VDD_VCO, generate an output clock signal CLK_VCO based on the control voltage Vctrl.

[0071] It can be understood that the technical effect achievable by the high power supply rejection ratio and low swing drive frequency locked loop method disclosed in this embodiment is the same as the technical effect achievable by the high power supply rejection ratio and low swing drive frequency locked loop circuit disclosed in Example 1, and will not be repeated here.

[0072] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A frequency-locked loop circuit with high power supply rejection ratio and low swing drive, characterized in that: include: a current comparator for comparing a reference current with a feedback current and generating an error current signal based on the comparison result; a loop filter for generating a control voltage based on the error current signal; A low-dropout linear regulator, configured to dynamically adjust an operating voltage of the voltage-controlled oscillator according to a load current of the voltage-controlled oscillator; wherein the operating voltage is lower than a main power supply voltage received by the low-dropout linear regulator; A voltage-controlled oscillator, comprising: a bias voltage providing unit, an odd number of delay cascade units and an output buffer; The bias voltage providing unit provides a bias voltage for each of the delay cascade units based on the control voltage; The plurality of delay cascade units are sequentially connected end to end in series, and the output end of the last delay cascade unit outputs a first voltage signal; wherein the delay cascade unit is used to logically invert the voltage inside the voltage-controlled oscillator and apply a transmission delay adjusted by the control voltage; The first voltage signal is buffered by the output buffer to generate an output clock signal.

2. The frequency-locked loop circuit with high power supply rejection ratio and low swing drive according to claim 1, wherein: The current comparator includes: a first operational amplifier, a second operational amplifier, a first resistor, a first capacitor, a first PMOS transistor, a second PMOS transistor and a first NMOS transistor; The non-inverting input terminal of the first operational amplifier is connected to a first reference voltage; The gate of the first PMOS transistor is connected to the output terminal of the first operational amplifier, the source is connected to the main power supply voltage, the drain is connected to the inverting input terminal of the first operational amplifier, and the drain of the first PMOS transistor is also grounded through a first resistor; The gate of the second PMOS transistor is connected to the gate of the first PMOS transistor, the source is connected to the reference current, and the drain forms a comparison node; The non-inverting input terminal of the second operational amplifier is connected to a second reference voltage; The gate of the first NMOS transistor is connected to the output terminal of the second operational amplifier, the drain is connected to the comparison node, the source is connected to the inverting input terminal of the second operational amplifier, and the source of the first NMOS transistor is also grounded through a first capacitor.

3. The frequency locked loop circuit with high power supply rejection ratio and low swing drive according to claim 2, wherein: Also included is a feedback circuit configured to generate a feedback current based on the output clock signal.

4. The frequency locked loop circuit with high power supply rejection ratio and low swing drive according to claim 3, wherein: The feedback circuit comprises: A frequency divider, dividing the output clock signal to generate a divided clock signal; a first level converter, performing voltage domain conversion on the frequency-divided clock signal; a non-overlapping clock generating circuit for generating a non-overlapping clock signal based on the divided clock signal converted in the voltage domain; A switch network generates the feedback current based on the non-overlapping clock signal and the second reference voltage.

5. The frequency locked loop circuit with high power supply rejection ratio and low swing drive according to claim 4, wherein: The switch network includes: a second capacitor, a third capacitor, a first switch, a second switch, a third switch and a fourth switch; One end of the first switch and the second switch are connected to the source of the first NMOS transistor, and the other ends are connected to one end of the second capacitor and one end of the third capacitor respectively, and the other ends of the second capacitor and the third capacitor are both connected to ground; the first switch and the second switch are controlled by a first clock signal and a second clock signal respectively; The third switch is connected between one end of the second capacitor and the ground and is controlled by the second clock signal; The fourth switch is connected between one end of the third capacitor and the ground, and is controlled by the first clock signal.

6. The frequency locked loop circuit with high power supply rejection ratio and low swing drive according to claim 2, wherein: The loop filter includes: a fourth capacitor and a second resistor; One end of the fourth capacitor is connected to the comparison node, and the other end is grounded through the second resistor.

7. The frequency locked loop circuit with high power supply rejection ratio and low swing drive according to claim 1, wherein: The bias voltage providing unit includes: a third PMOS transistor, a fourth PMOS transistor, a second NMOS transistor and a third NMOS transistor; The gate of the third PMOS transistor is connected to a low-level enable signal, and the gate of the second NMOS transistor is connected to a high-level enable signal; The source and drain of the third PMOS transistor are respectively connected to the drain and source of the second NMOS transistor to form a first connection node and a second connection node; The source of the fourth PMOS transistor is connected to the operating voltage, the drain is connected to the first connection node, and the gate is connected to the bias voltage input terminal of the delay cascade unit and the drain of the fourth PMOS transistor; The source of the third NMOS transistor is grounded, the gate is connected to the control voltage, and the drain is connected to the second connection node.

8. The frequency locked loop circuit with high power supply rejection ratio and low swing drive according to claim 1, wherein: The delay cascade unit includes: a fifth PMOS tube, a sixth PMOS tube, a fourth NMOS tube and a fifth NMOS tube; The source of the fifth PMOS transistor is connected to the operating voltage, the gate is connected to the output end of the bias voltage providing unit and is used to receive the bias voltage, and the drain is connected to the source of the sixth PMOS transistor; A node where the gate of the sixth PMOS transistor and the gate of the fourth NMOS transistor are connected is connected to an output end of another delay cascade unit; A node where the drain of the sixth PMOS tube is connected to the drain of the fourth NMOS tube is connected to an input end of another delay cascade unit; The source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor, the gate of the fifth NMOS transistor is connected to the control voltage, and the source of the fifth NMOS transistor is grounded.

9. The frequency locked loop circuit with high power supply rejection ratio and low swing drive according to claim 1, wherein: The output buffer includes an even number of inverters connected in series, and the last inverter outputs the output clock signal.

10. The frequency locked loop circuit with high power supply rejection ratio and low swing drive according to claim 1, wherein: The low voltage difference linear regulator includes: a seventh PMOS transistor, an eighth PMOS transistor, a sixth NMOS transistor, a fifth capacitor and a sixth capacitor; The source of the eighth PMOS transistor is connected to the drain of the seventh PMOS transistor, the drain of the eighth PMOS transistor is grounded via a second current source, and the gate of the eighth PMOS transistor is connected to a fourth reference voltage; the source of the seventh PMOS transistor is connected to a power supply voltage, and the gate of the seventh PMOS transistor is connected between the first current source and the drain of the sixth NMOS transistor; a third connection node connecting the source of the eighth PMOS transistor and the drain of the seventh PMOS transistor outputs the operating voltage; The drain of the sixth NMOS transistor is connected to the first current source; the gate is connected to the third reference voltage, the source is connected to one end of the fifth capacitor, one end of the fifth capacitor is also connected to the first current source; the other end of the fifth capacitor is connected to the third connection node; One end of the sixth capacitor is connected to the third connection node, and the other end is grounded.

11. The frequency locked loop circuit with high power supply rejection ratio and low swing drive according to claim 1, wherein: Also includes: The second level converter converts the output clock signal into a system clock output signal.

12. A frequency locked loop control method with high power supply rejection ratio and low swing drive, characterized in that: The method comprises: comparing the reference current with the feedback current and generating an error current signal based on the comparison result; generating a control voltage based on the error current signal; generating an operating voltage lower than the main power voltage based on the main power voltage; Under the operating voltage, an output clock signal is generated based on the control voltage.

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