Process method for improving pixel performance of CMOS image sensor
By optimizing the epitaxial layer design of the CMOS image sensor, the linearly increased N-type epitaxial layer doping concentration and intrinsic epitaxial layer are used to solve the problems of impurity diffusion and hole electron pair recombination, improve pixel performance and production stability, and reduce hysteresis effect and concentration inhomogeneity.
Patent Information
- Application Number
- CN202510703404.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-28
- Publication Date
- 2025-08-29
AI Technical Summary
When the prior art improves the full well capacity of CMOS image sensors and reduces the hysteresis effect, there are uneven concentration distribution caused by diffusion of impurity atoms and cross-contamination caused by hole electron pair recombination in P-type or N-type epitaxial layers, which affects pixel performance and production stability.
By growing the first epitaxial layer on the P-type substrate and gradually increasing the doping concentration along the growth direction of the N-type epitaxial layer thereon, the design of the epitaxial layer is optimized, and impurity atom diffusion and hole electron pair recombination are avoided, a linear potential distribution is formed, and hysteresis effect and concentration inhomogeneity are reduced.
It effectively improves the pixel performance of CMOS image sensor, reduces image afterimage, increases the window of process technology, and improves production stability and pixel performance.
Smart Images
Figure CN120568876A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of image sensors, and in particular to a process method for improving pixel performance of CMOS image sensors. Background Art
[0002] CMOS image sensors (CIS), as optical sensor devices, play a vital role in modern electronic devices. Currently, domestic CIS development is primarily based on a mature boron-doped epitaxial growth process (P-EPI). This process, with an expansion coefficient close to that of silicon, effectively reduces interfacial stress and prevents package cracking, providing a reliable foundation for stable CIS production.
[0003] Among CIS performance parameters, full well capacity (FWC) is a key indicator for measuring pixel performance. It represents the number of electrons in the photodiode after photoelectric conversion. A higher FWC value means that the CIS can carry more electrons during the photoelectric conversion process, resulting in better performance. Hysteresis, another important parameter, is used to represent the number of electrons remaining in the pixel after the photodiode readout. The fewer electrons remaining in the pixel, the higher the full well capacity (FWC). Excessive electrons remaining in the pixel can directly lead to image sticking.
[0004] The industry generally uses N-type semiconductors as CIS photodiodes. This is because the majority carriers in N-type semiconductors are electrons with high mobility, resulting in less recombination losses and a longer lifetime, which can enhance the effective separation of photogenerated carriers. N-type semiconductors are generally prepared by doping P-EPI with N-type impurities (such as As or P).
[0005] In order to increase the full well capacity, researchers have made many attempts, such as increasing the N-type injection area. At present, the more common method to increase the full well capacity is to inject N-type impurities (such as As or P) with higher energy and dose into the pixel area, but this method has obvious disadvantages. Higher energy ion implantation not only has a greater impact on production capacity, but also puts higher requirements on the thickness of the photoresist, and even affects the silicon surface, thereby damaging pixel performance. In order to solve the above disadvantages, researchers have introduced an N-type epitaxial layer into PEPI, but the impurity atoms in the N-type epitaxial layer will diffuse, resulting in uneven concentration distribution, and the N-type epitaxial layer and the P-type epitaxial layer are doped with elements of different properties. The hole-electron pairs will recombine, causing cross-contamination, thereby affecting the performance and production stability of the CIS.
[0006] The statements herein merely provide background information related to the present invention and do not necessarily constitute prior art. Summary of the Invention
[0007] The purpose of the present invention is to provide a process method for improving the pixel performance of CMOS image sensors. By optimizing the design of the epitaxial layer, the hysteresis effect is reduced, the uneven concentration distribution caused by the diffusion of impurity atoms in the N-type epitaxial layer is effectively improved, and cross contamination caused by the recombination of hole-electron pairs in the P-type or N-type epitaxial layer is avoided, thereby improving pixel performance and increasing the process window.
[0008] To achieve the above objectives, the present invention provides a process for improving pixel performance of a CMOS image sensor, comprising at least the following steps:
[0009] Step S1, providing a P-type substrate, and growing a first epitaxial layer on the P-type substrate;
[0010] Step S2, growing an N-type epitaxial layer on the first epitaxial layer;
[0011] Starting from the first epitaxial layer and along the growth direction of the N-type epitaxial layer, the doping concentration of the N-type epitaxial layer increases.
[0012] Optionally, the first epitaxial layer is any one of an intrinsic epitaxial layer and a P-type epitaxial layer.
[0013] Optionally, a process temperature for growing the first epitaxial layer is greater than a process temperature for growing the N-type epitaxial layer.
[0014] Optionally, after step S2, the method further includes: growing a second epitaxial layer on the N-type epitaxial layer.
[0015] Optionally, the second epitaxial layer is any one of an intrinsic epitaxial layer and a P-type epitaxial layer.
[0016] Optionally, a process temperature for growing the second epitaxial layer is lower than a process temperature for growing the N-type epitaxial layer.
[0017] Optionally, the first epitaxial layer and the second epitaxial layer are intrinsic epitaxial layers.
[0018] Optionally, the thickness of the first epitaxial layer is 1 μm to 2 μm, the thickness of the N-type epitaxial layer is 1.5 μm to 2.9 μm, and the thickness of the second epitaxial layer is 0.5 μm to 1 μm.
[0019] Optionally, the doping concentration of the N-type epitaxial layer increases linearly.
[0020] Optionally, the doping concentration of the N-type epitaxial layer is 2.5E15 atom / cm 3 ~4E16 atoms / cm 3 .
[0021] Optionally, the doping concentration of the P-type substrate is 4E18 atom / cm 3 ~6E18 atoms / cm 3 .
[0022] Optionally, after step S2, the method further includes: removing the P-type substrate and the first epitaxial layer, and performing deep P-well ion implantation to form an N-type metal oxide semiconductor device substrate.
[0023] Optionally, after step S2, the method further includes: performing deep N-well ion implantation to form a P-type metal oxide semiconductor device substrate.
[0024] Compared with the prior art, the technical solution of the present invention has at least the following beneficial effects:
[0025] 1) The present invention optimizes the design of the epitaxial layer. A first epitaxial layer is grown on a P-type substrate, and an N-type epitaxial layer is grown on top of the first epitaxial layer. Starting from the first epitaxial layer and along the growth direction of the N-type epitaxial layer, the doping concentration of the N-type epitaxial layer is linearly increased by adjusting process parameters (such as gas flow rate). On the one hand, the linear increase in the doping concentration of the N-type epitaxial layer causes a linear change in carrier concentration and electric field strength, thereby resulting in a linear increase in the potential distribution, eliminating the need for extensive simulation to optimize ion implantation parameters. A controllable doping concentration gradient is then formed through ion implantation and annealing processes to achieve the desired potential distribution. This linear increase in potential distribution facilitates the transmission of electrons generated by the photoelectron effect in the photodiode to a higher potential, thereby reducing hysteresis and image sticking. On the other hand, the linear increase in the doping concentration of the N-type epitaxial layer can effectively improve the uneven concentration distribution caused by the diffusion of impurity atoms in the N-type epitaxial layer, thereby improving pixel performance and increasing the process window.
[0026] 2) Furthermore, the first epitaxial layer includes an intrinsic epitaxial layer. Inserting the intrinsic epitaxial layer between the P-type substrate and the N-type epitaxial layer can avoid cross contamination caused by recombination of hole-electron pairs in the P-type substrate and the N-type epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 This is a flow chart of the process method for improving pixel performance of a CMOS image sensor according to the present invention.
[0028] Figure 2 It is a schematic structural diagram of growing a first epitaxial layer and an N-type epitaxial layer on a P-type substrate according to the present invention.
[0029] Figure 3 It is a schematic structural diagram of growing a second epitaxial layer on an N-type epitaxial layer according to the present invention.
[0030] Figure ID:
[0031] P-type substrate 10
[0032] First epitaxial layer 20
[0033] N-type epitaxial layer 30
[0034] The second epitaxial layer 40 . DETAILED DESCRIPTION
[0035] The following is a further detailed description of the process method for improving the pixel performance of CMOS image sensors proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will become clearer. It should be noted that the drawings are in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In order to make the purposes, features and advantages of the present invention more obvious and easy to understand, please refer to the drawings. It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the conditions for the implementation of the present invention, so they have no technical substantive significance. Any structural modification, change in proportional relationship or adjustment of size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention.
[0036] The “intrinsic epitaxial layer” described herein refers to a pure semiconductor thin film layer that does not contain impurities.
[0037] As described in the background technology, in order to increase the full well capacity, researchers introduced an N-type epitaxial layer into PEPI. However, the impurity atoms in the N-type epitaxial layer will diffuse, resulting in uneven concentration distribution. In addition, the N-type epitaxial layer and the P-type epitaxial layer are doped with elements of different properties, and the impurity atoms will recombine, causing cross-contamination and affecting the performance of CIS.
[0038] In order to solve the above problems, the present invention provides a new process method, which optimizes the design of the epitaxial layer. First, a P-type substrate is provided, and a first epitaxial layer is grown on the P-type substrate; then an N-type epitaxial layer is grown on the first epitaxial layer; starting from the first epitaxial layer, along the growth direction of the N-type epitaxial layer, the doping concentration of the N-type epitaxial layer tends to increase. The use of this process method can avoid cross-contamination caused by the recombination of hole-electron pairs in the P-type or N-type epitaxial layer, reduce the hysteresis effect, and effectively improve the problem of uneven concentration distribution caused by the diffusion of impurity atoms, thereby improving pixel performance. Specifically, if Figure 1 As shown, the present invention provides a process method for improving pixel performance of a CMOS image sensor, which at least comprises the following steps:
[0039] Step S1: providing a P-type substrate and growing a first epitaxial layer on the P-type substrate.
[0040] In some embodiments, the doping concentration of the P-type substrate is 4E18 atoms / cm 3 ~6E18 atoms / cm 3 The first epitaxial layer is any one of an intrinsic epitaxial layer and a P-type epitaxial layer.
[0041] like Figure 2 As shown, in this embodiment, the first epitaxial layer 20 is an intrinsic epitaxial layer that does not contain impurities and is located between the P-type substrate 10 and the subsequently grown N-type epitaxial layer 30, effectively preventing cross-contamination caused by the recombination of hole-electron pairs in the P-type substrate 10 and the N-type epitaxial layer 30. In other embodiments, when the first epitaxial layer 20 is a P-type epitaxial layer, the doping concentration of the P-type epitaxial layer needs to be lower than the doping concentration of the P-type substrate 10. The reduction in the doping concentration of the P-type epitaxial layer can, to a certain extent, reduce cross-contamination caused by the recombination of hole-electron pairs in the P-type or N-type epitaxial layers.
[0042] Step S2 : growing an N-type epitaxial layer on the first epitaxial layer, wherein the doping concentration of the N-type epitaxial layer increases from the first epitaxial layer along the growth direction of the N-type epitaxial layer.
[0043] In this embodiment, the doping concentration of the N-type epitaxial layer 30 is increased linearly by adjusting process parameters (such as gas flow rate, etc.).
[0044] In some embodiments, the doping concentration of the N-type epitaxial layer 30 is 2.5E15 atom / cm 3 ~4E16atom / cm 3 .
[0045] The term "linear" as used herein refers to a gradual increase in the doping concentration, rather than a strict conformance to a linear formula. The doping concentration of the N-type epitaxial layer 30 increases linearly, resulting in a uniform increase in the number of ionized free electrons, a linear increase in carrier concentration, and a uniform increase in electric field strength. This results in a linear increase in the potential distribution, which is beneficial for the electrons generated by the photogenerated electron effect in the photodiode to be transferred to a high potential, thereby reducing hysteresis and image sticking. In the prior art, ion implantation parameters are often optimized through extensive simulations, and then a controllable doping concentration gradient is formed through ion implantation and annealing processes to form the desired potential distribution. However, in the present invention, a linearly increasing potential distribution can be formed simply by naturally growing an N-type epitaxial layer 30 with a linearly increasing doping concentration, greatly simplifying the manufacturing process. Furthermore, the linear increase in the doping concentration of the N-type epitaxial layer 30 can effectively improve the uneven concentration distribution problem caused by the diffusion of impurity atoms in the N-type epitaxial layer 30, thereby improving pixel performance and increasing the manufacturing process window.
[0046] In some embodiments, the process temperature for growing the first epitaxial layer 20 is greater than the process temperature for growing the N-type epitaxial layer 30. During the atomic diffusion process, the diffusion coefficient and temperature follow the formula D=D0·exp(-E a / kT), where T represents temperature and D0 represents the initial diffusion coefficient, which is proportional to temperature. When the process temperature is low, the diffusion coefficient is small, and the diffusion ability of the impurity atoms in the N-type epitaxial layer 30 is greatly reduced. At the same time, the impurity atoms in the first epitaxial layer 20, which was previously processed at a higher process temperature, will basically not diffuse at the lower process temperature, thereby greatly reducing the recombination of hole-electron pairs in the first epitaxial layer 20 and the N-type epitaxial layer 30.
[0047] like Figure 3 As shown, after step S2, the process further includes: growing a second epitaxial layer 40 on the N-type epitaxial layer 30. If the second epitaxial layer 40 is not grown, on the one hand, without the barrier effect of the second epitaxial layer 40, the impurity atoms in the N-type epitaxial layer 30 will diffuse upward, resulting in an uneven concentration distribution; on the other hand, when forming an N-type metal oxide semiconductor (NMOS) device, more P-type dopant ions (high doping concentration) need to be implanted into the N-type epitaxial layer 30 to overcompensate to form a P-well, but the high doping concentration will increase the channel resistance, ultimately slowing down the device.
[0048] In some embodiments, the second epitaxial layer 40 is either an intrinsic epitaxial layer or a P-type epitaxial layer. In this embodiment, the second epitaxial layer 40 is an intrinsic epitaxial layer, which acts as a barrier layer and can effectively prevent impurity atoms in the N-type epitaxial layer 30 from diffusing into other layers grown above it, thereby improving concentration uniformity. In other embodiments, the second epitaxial layer 40 is a P-type epitaxial layer. The doping concentration of the P-type epitaxial layer needs to be lower than the doping concentration of the N-type epitaxial layer 30. The reduction in the doping concentration of the P-type epitaxial layer can, to a certain extent, reduce cross-contamination caused by hole-electron pair recombination in the P-type or N-type epitaxial layers.
[0049] In some embodiments, the process temperature for growing the second epitaxial layer 40 is lower than the process temperature for growing the N-type epitaxial layer 30. When the process temperature is lower, the diffusion coefficient is lower, and the diffusion capacity of the impurity atoms in the second epitaxial layer 40 is significantly reduced. At the same time, the impurity atoms in the N-type epitaxial layer 30, which was previously grown at a higher process temperature, will essentially not diffuse at the lower process temperature, thereby significantly reducing the recombination of hole-electron pairs in the second epitaxial layer 40 and the N-type epitaxial layer 30.
[0050] In some embodiments, the thickness of the first epitaxial layer 20 is 1 μm to 2 μm, the thickness of the N-type epitaxial layer 30 is 1.5 μm to 2.9 μm, and the thickness of the second epitaxial layer 40 is 0.5 μm to 1 μm. The thicknesses of the first epitaxial layer 20, the N-type epitaxial layer 30, and the second epitaxial layer 40 are set according to process requirements. The thicknesses described here are only examples and should not be considered as limitations.
[0051] After the second epitaxial layer 40 is grown, if an N-type metal oxide semiconductor (NMOS) device is to be formed, a deep P-well ion implantation is further performed to form an N-type metal oxide semiconductor device substrate. If a P-type metal oxide semiconductor (PMOS) device is to be formed, a deep N-well ion implantation is further performed to form a P-type metal oxide semiconductor device substrate. In subsequent processes, different types of ion implantation are performed to achieve the performance of NMOS and PMOS devices.
[0052] In summary, the process method for improving the pixel performance of CMOS image sensors provided by the present invention can avoid cross-contamination caused by the recombination of hole-electron pairs in P-type or N-type epitaxial layers, reduce hysteresis effects and image sticking, and effectively improve the problem of uneven concentration distribution caused by the diffusion of impurity atoms, thereby improving pixel performance and increasing the process window.
[0053] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.
[0054] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.
[0055] Although the present invention has been described in detail through the above preferred embodiments, it should be understood that the above description is not intended to limit the present invention. After reading the above description, various modifications and substitutions of the present invention will become apparent to those skilled in the art. Therefore, the scope of protection of the present invention should be defined by the appended claims.
Claims
1. A process for improving pixel performance of a CMOS image sensor, characterized in that: At least the following steps are included: Step S1, providing a P-type substrate, and growing a first epitaxial layer on the P-type substrate; Step S2, growing an N-type epitaxial layer on the first epitaxial layer; Starting from the first epitaxial layer and along the growth direction of the N-type epitaxial layer, the doping concentration of the N-type epitaxial layer increases.
2. The method according to claim 1, wherein The first epitaxial layer is any one of an intrinsic epitaxial layer and a P-type epitaxial layer.
3. The method according to claim 1, wherein The process temperature for growing the first epitaxial layer is greater than the process temperature for growing the N-type epitaxial layer.
4. The method according to any one of claims 1 to 3, wherein: After step S2, the method further includes: growing a second epitaxial layer on the N-type epitaxial layer.
5. The method according to claim 4, wherein The second epitaxial layer is any one of an intrinsic epitaxial layer and a P-type epitaxial layer.
6. The method according to claim 4, wherein The process temperature for growing the second epitaxial layer is lower than the process temperature for growing the N-type epitaxial layer.
7. The method according to claim 4, wherein The first epitaxial layer and the second epitaxial layer are intrinsic epitaxial layers.
8. The method according to claim 4, wherein The thickness of the first epitaxial layer is 1 μm to 2 μm, the thickness of the N-type epitaxial layer is 1.5 μm to 2.9 μm, and the thickness of the second epitaxial layer is 0.5 μm to 1 μm.
9. The method according to claim 1, wherein The doping concentration of the N-type epitaxial layer increases linearly.
10. The method according to claim 1, wherein The doping concentration of the N-type epitaxial layer is 2.5E15 atom / cm 3 ~4E16 atoms / cm 3 .
11. The method according to claim 1, wherein The doping concentration of the P-type substrate is 4E18 atom / cm 3 ~6E18 atoms / cm 3 .
12. The method according to claim 1, wherein After step S2, the method further includes: removing the P-type substrate and the first epitaxial layer, and performing deep P-well ion implantation to form an N-type metal oxide semiconductor device substrate.
13. The method according to claim 1, wherein After step S2, the method further includes: performing deep N-well ion implantation to form a P-type metal oxide semiconductor device substrate.