TOPCon battery with domain surface structure and preparation method of TOPCon battery

Abstract

The invention relates to the technical field of solar cells, and particularly discloses a TOPCon cell with a domain surface structure and a preparation method of the TOPCon cell. The TOPCon battery comprises an N-type silicon substrate, the front surface of the N-type silicon substrate is divided into an emitter region and a non-emitter region, the emitter region is of a planar structure, the non-emitter region is of a pyramid textured structure, and the boron doping concentration of the emitter region is higher than that of the non-emitter region. According to the invention, the silicon oxide layer is generated in the emitter region through the laser oxidation process, so that local planarization is realized; in combination with selective boron diffusion doping, the contradiction between the contact resistance and the light absorption efficiency of the traditional TOPCon cell is solved; the specific process comprises the steps of alkali polishing, laser oxidation, texturing, doping, passivation, electrode printing and the like. And the process is stable, is compatible with the existing production line, and has remarkable industrial application value.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a TOPCon cell with a domain-divided surface structure and a preparation method thereof. Background Art

[0002] TOPCon cells have become a research hotspot for high-efficiency photovoltaic cells due to their excellent passivation effect and high open circuit voltage (Voc). However, their front structure design faces a contradiction between contact resistance and light absorption:

[0003] Traditional full velvet structure: The pyramid velvet is formed by alkali velveting, and the surface is rough. Although it reduces the reflectivity, the actual contact area between the metal electrode and the silicon surface per unit area is reduced, resulting in increased contact resistance and a decrease in the fill factor (FF). In addition, the unevenness of the velvet surface can easily cause local electric field concentration, aggravating carrier recombination and affecting battery efficiency.

[0004] Traditional fully planar structure: Although it can reduce contact resistance and interface recombination, the high surface reflectivity limits the light absorption capacity and restricts the improvement of short-circuit current (Isc).

[0005] In the existing technology, a single-structure planar or velvet design is difficult to take into account both light absorption and electrical performance at the same time; therefore, there is an urgent need for a partitioned optimized cell structure, which adopts a planar structure in the emitter area to improve contact performance, and retains a velvet structure in the non-emitter area to enhance light capture capability and improve the efficiency of the TOPCon cell. Summary of the Invention

[0006] This application aims to solve the above-mentioned problems, make up for the deficiencies of the existing technology, and provide a TOPCon battery with a domain-specific surface structure and a preparation method thereof.

[0007] This application is implemented through the following technical solutions:

[0008] In the first aspect, the present application provides a TOPCon battery with a domain-divided surface structure, including an N-type silicon substrate, characterized in that the front side of the N-type silicon substrate is divided into an emitter region and a non-emitter region; the emitter region is a planar structure, the non-emitter region is a pyramid velvet structure, and the boron doping concentration of the emitter region is higher than that of the non-emitter region.

[0009] Furthermore, the reflectivity of the emitter is 20%~40%, and the reflectivity of the non-emitter is 6%~9%; the tower height of the pyramid velvet structure is 0.5~1.5μm, the tower width is 0.5~1.5μm, and the surface height of the planar structure is 4~6μm lower than the tower top of the pyramid velvet structure.

[0010] Furthermore, the surface of the emitter region is covered with a heavily doped P++ layer with a square resistance of 100~200Ω and a concentration of 1*10^19~3*10^19 atoms / cm³; the surface of the non-emitter region is covered with a lightly doped P+ layer with a square resistance of 400-600Ω and a concentration of 1*10^18~6*10^18 atoms / cm³.

[0011] In a second aspect, the present application provides a method for preparing a TOPCon battery having the above-mentioned domain-divided surface structure, characterized in that it comprises the following steps:

[0012] S1: Alkaline polishing is performed on the N-type silicon wafer to form the front and back polished surfaces;

[0013] S2: Generate a silicon oxide layer on the emitter region on the front side of the silicon wafer through a laser oxidation process;

[0014] S3: Texturing the silicon wafer to form a velvet structure in the non-emitter region and retain a planar structure in the emitter region;

[0015] S4: Boron diffusion doping is performed on the front side of the silicon wafer to form a heavily doped P++ layer in the emitter region and a lightly doped P+ layer in the non-emitter region.

[0016] Furthermore, in S2, the parameters of the laser oxidation process are:

[0017] Laser wavelength 200~600nm, power density 0.5~2.0J / cm², scanning speed 100~500mm / s;

[0018] Oxygen flow rate is 1000~3000sccm, spot size is 30~50μm, and spot overlap rate is 20%~50%.

[0019] Furthermore, in S2, the laser pulse frequency is 20-100 kHz.

[0020] Furthermore, in the S2, the thickness of the silicon oxide layer is 20-50 nm, the refractive index is 1.4-1.8, and the porosity is <0.5%.

[0021] Furthermore, the S3 also reports that: the silicon oxide layer in the emitter region is removed by acid pickling, and the textured structure in the non-emitter region is retained.

[0022] Furthermore, in the step S4 , the conditions for boron diffusion doping are: temperature 800-950° C., boron source flow rate 100-400 sccm, and deposition pressure 100-500 mbar.

[0023] Furthermore, it also includes:

[0024] S5: acid washing and alkaline washing and polishing the back of the silicon wafer;

[0025] S6: depositing a tunnel oxide layer and an N+ polysilicon layer on the back side of the silicon wafer;

[0026] S7: Chemically clean the front side of the silicon wafer and plate N+ polysilicon;

[0027] S8: depositing an aluminum oxide passivation layer on the silicon wafer surface;

[0028] S9: Deposition of anti-reflection layer on the front and back sides of silicon wafer;

[0029] S10: Electrodes are printed on the front and back of the silicon wafer and sintered.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] This application adopts a domain-specific surface structure design, using a flat polished structure in the emitter area to reduce contact resistance (improve carrier collection efficiency), and a pyramid velvet structure with lower reflectivity (enhance light absorption) in the non-emitter area; combined with a laser oxidation process to achieve local protection, it avoids the limitations of doping concentration and velvet size adjustment in traditional processes, and breaks through the difficult problem of balancing contact loss and light absorption.

[0032] The laser oxidation in this application is a non-contact process that does not require additional laser re-doping equipment, avoiding the damage to the suede surface caused by traditional wet oxidation. At the same time, selective doping is achieved through structural differences, adapting to existing production lines, simplifying the process and improving electrical performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions of the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] Figure 1 Schematic diagram of the TOPCon battery structure with a domained surface structure provided in Examples 1-3 of the present invention;

[0035] Figure 2 Schematic diagram of the TOPCon battery structure in which the entire front surface of the polished sheet provided in Comparative Example 1 of the present invention has a pyramid velvet structure;

[0036] Figure 3 Schematic diagram of the TOPCon battery structure in which the entire front surface of the polishing sheet provided in Comparative Example 2 of the present invention is a planar structure.

[0037] Explanation of reference numerals: 1. electrode; 2. heavily doped P++ layer; 3. lightly doped P+ layer; 4. aluminum oxide passivation layer; 5. front anti-reflection layer; 6. tunneling oxide layer; 7. N+ polysilicon layer; 8. back anti-reflection layer DETAILED DESCRIPTION

[0038] In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that these specific details are not necessarily required to practice the present invention. In other embodiments, well-known materials or methods are not specifically described to avoid obscuring the present invention.

[0039] Throughout this specification, references to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the present invention. Thus, appearances of the phrases "one embodiment," "an embodiment," "an example," or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combinations and / or subcombinations in one or more embodiments or examples. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] First, as Figure 1 As shown, the present application provides a TOPCon cell with a domain-divided surface structure, comprising an N-type silicon substrate, wherein the front surface of the N-type silicon substrate is divided into an emitter region and a non-emitter region; the emitter region is a planar structure, the non-emitter region is a pyramid velvet structure, and the reflectivity of the non-emitter region is lower than that of the emitter region;

[0041] The emitter area of ​​the TOPCon battery of this application adopts a flat polishing structure to improve the contact performance, and retains the pyramid velvet structure in the non-emitter area to enhance the light capture ability. Because the emitter and non-emitter of conventional batteries are both consistent pyramid velvet structures, in order to ensure the contact of the emitter, the emitter reflectivity should not be too low, which will result in a large surface area and reduce the metal contact ability per unit area. The present invention can differentiate the emitter and non-emitter structures, and the non-emitter can have a lower reflectivity, while the emitter is not affected. Because the emitter of a conventional battery will be printed with slurry, resulting in no light absorption effect in this area, the emitter planar structure of this application has a high reflectivity, but the degree of no light absorption effect after printing the slurry is consistent with the conventional one. In this way, a selective optical structure is obtained to improve the efficiency of the TOPCon battery.

[0042] At the same time, the differentiated textured structure on the front side allows for heavy doping of the emitter's planar structure and light doping of the pyramidal structure in the non-emitter region during the doping process, resulting in a selective electrical structure. Because conventional solar cell emitters are inherently printed with slurry, resulting in no light absorption in this area, the emitter's planar structure, while having high reflectivity, exhibits the same lack of light absorption after printing as conventional cells.

[0043] In a specific embodiment, the reflectivity of the emitter is 20%~40%, and the reflectivity of the non-emitter is 6%~9%; the tower height of the pyramid velvet structure is 0.5~1.5μm, the tower width is 0.5~1.5μm, and the surface height of the planar structure is 4~6μm lower than the tower top of the pyramid velvet structure.

[0044] The conventional pyramid velvet structure of a battery has a tower height of 1~2.5um, a tower width of 1~2.5um, and a reflectivity of 9%~11%, which is higher than the reflectivity of the TOPCon battery of the present application, but has a poor light trapping effect.

[0045] In a specific embodiment, the surface of the emitter region is covered with a heavily doped P++ layer with a sheet resistance of 100~200Ω and a concentration of 1*10^19~3*10^19 atoms / cm³; the surface of the non-emitter region is covered with a lightly doped P+ layer with a sheet resistance of 400-600Ω and a concentration of 1*10^18~6*10^18 atoms / cm³.

[0046] In a second aspect, the present application provides a method for preparing a TOPCon battery having the above-mentioned domain-divided surface structure, characterized in that it comprises the following steps:

[0047] S1: Alkaline polishing is performed on the N-type silicon wafer to form the front and back polished surfaces;

[0048] S2: A silicon oxide layer is generated in the emitter region on the front side of the silicon wafer through a laser oxidation process. When a laser is used to irradiate the silicon surface according to the emitter pattern on the polished side of the silicon wafer, the high energy density triggers a plasma effect on the surface of the silicon material. This plasma wave model promotes the rapid combination of silicon and surrounding oxygen elements to form a silicon oxide layer. This process achieves localized precise oxidation at the micron / nanometer scale, avoiding the damage to the planar structure caused by traditional high-temperature processes. Among them: the oxygen flow rate is 1000-3000sccm, the laser power density is 0.5~2.0 J / cm², the laser wavelength is 200-600nm (for example, ultraviolet laser can achieve higher precision oxidation and reduce heat diffusion), the laser scanning speed is 100-500mm / s, the pulse frequency is 20~100kHz, and the laser spot size is controlled at 30~50 μm, with a spot overlap of 20% to 50%. Smaller spots and higher overlap help form a continuous and dense oxide film. The light source is a square flat-top light. The resulting silicon oxide film has a thickness of 20 to 50 nm, a refractive index of 1.4-1.8, and high density (porosity <0.5%). The generated silicon oxide layer is dense and chemically stable, effectively blocking the penetration of acid / alkali corrosive solutions in subsequent processes and preventing deformation of planar structures due to chemical erosion. At the same time, the silicon oxide layer can reduce the density of dangling bonds on the surface and reduce carrier recombination losses. The non-contact processing characteristics of the laser enable it to achieve uniform oxide layer coverage on flat or velvet surfaces, overcoming the problem of insufficient coverage of microscopic recessed areas in traditional wet oxidation processes.

[0049] S3: The silicon wafer is textured to form a pyramid texture structure in the non-laser area, and the laser area retains a planar structure; specifically, the silicon wafer after laser oxidation is textured to form a nano-scale texture in the non-laser oxidation area on the front surface of the silicon wafer. In the positive laser emitter graphic area, due to the protection of the oxide layer, the planar structure can still be retained in the texture forming pyramid step. Finally, the silicon oxide of the emitter is removed after the pickling step of the texture making step, and finally the front domain surface structure is obtained, the emitter is flat, and the non-emitter is a pyramid texture; because the front domain texture can achieve optical and contact differentiation, the non-laser area can achieve a low-reflection structure with a smaller texture, so an emitter is obtained with a planar structure to improve contact, with a reflectivity of 20-40%; the non-emitter reflectivity is 6-9%, the pyramid size is 0.5-1.5um high and 0.5-1.5um wide; the surface height of the planar structure in the emitter area is 4~6μm lower than the top of the pyramid texture structure in the non-emitter area;

[0050] S4: Boron diffusion doping is performed on the front side of the silicon wafer to form a heavily doped P++ layer 2 in the emitter region and a lightly doped P+ layer 3 in the non-emitter region. Specifically, a P+ layer is normally doped on the velvet surface in different regions on the front side of the silicon wafer. Since the emitter region is a planar structure and has a smaller surface area than the pyramid structure in the non-emitter region, the doping concentration is higher than that in the non-emitter region under the same source atmosphere. Therefore, this structure can achieve a selective structure in which the emitter contact region is heavily doped and the non-emitter region is lightly doped by the traditional CVD method. The doping temperature is 800-950°C, the boron source is 100-400sccm, and the deposition pressure is 100-500mbar. The square resistance of the heavily doped region is 100-200Ω, and the concentration is 1*10^19--3*10^19atoms / cm³. The square resistance of the non-emitter region is 1*10^18--6*10^18atoms / cm³, and the square resistance is 400-600Ω.

[0051] S5: Pickling the back of the silicon wafer, followed by alkaline cleaning and polishing;

[0052] S6: depositing a tunnel oxide layer 6 on the back of the silicon wafer at a high temperature, and then depositing an N+ polysilicon layer 7;

[0053] S7: Perform acid and alkaline washing on the front and back sides of the silicon wafer to remove the N+ polysilicon that has been plated on the front side;

[0054] S8: depositing an aluminum oxide passivation layer 4 on the silicon wafer surface; depositing an Al2O3 thin film on the silicon wafer surface using ALD;

[0055] S9: Depositing anti-reflection layers on the front and back sides of the silicon wafer; specifically, depositing a SixNy or SiONy thin film on the front side of the silicon wafer using PECVD to form a front anti-reflection layer 5; Depositing anti-reflection layers on the back side of the silicon wafer: depositing a SixNy or SiONy thin film on the back side of the silicon wafer using PECVD to form a back anti-reflection layer 8;

[0056] S10: Electrodes 1 are printed on the front and back of the silicon wafer and sintered.

[0057] The following will clearly and completely describe the technical solutions of the present invention in conjunction with specific embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0058] Example 1

[0059] This embodiment provides a method for preparing a TOPCon battery with a domain-specific surface structure, comprising the following steps:

[0060] S1 Alkali Polishing: N-type silicon wafers are roughly polished with alkali to form a uniform polished surface on the front and back surfaces of the silicon wafer;

[0061] S2 Laser Oxidation: On the polished surface, a silicon oxide layer is formed by irradiating the silicon substrate with a laser according to the emitter pattern. The oxygen flow rate is 3000 sccm, the laser power density is 2 J / cm², the laser wavelength is 200 nm, the laser scanning speed is 100 mm / s, the pulse frequency is 20 kHz, the laser spot size is controlled at 30 μm, and the spot overlap is 20%. The resulting silicon oxide layer is 50 nm thick and has a refractive index of 1.40%.

[0062] S3 domain texturing: Texturing is performed on laser-oxidized silicon wafers to form a nano-scale pyramid texture in the non-laser area of ​​the silicon wafer surface. The laser emitter pattern area is protected by the silicon oxide layer, so the planar structure can still be retained during the texturing step. The emitter reflectivity is 20%; the non-emitter reflectivity is 6%. The pyramid size is 0.5um high and 0.5um wide. The emitter plane platform is 4um lower than the non-emitter pyramid top.

[0063] S4 regional doping: Boron diffusion doping is performed on the textured surface of the front side of the silicon wafer in different regions after texturing; the deposition temperature is 950°C, the boron source flow rate is 400sccm, and the deposition pressure is 500mbar; the emitter region is a heavily doped P++ layer with a square resistance of 200Ω and a concentration of 1*10^19atoms / cm³; the non-emitter region is a lightly doped layer with a square resistance of 600Ω and a concentration of 1*10^18atoms / cm³;

[0064] S5 alkali polishing: pickling the back side, then alkali cleaning and polishing the back side;

[0065] S6 N+ layer poly silicon: SiO layer is formed first at high temperature on the back side and then N+ polysilicon layer is grown;

[0066] S7 Rca: Acid and alkaline washing on the front and back sides to remove the N+ polysilicon plated on the front side;

[0067] Al2O3 thin film was deposited on the S8 surface using ALD;

[0068] S9 silicon nitride: PECVD deposition of Si on the front surface x N y or SiON y film;

[0069] The back surface of S10 silicon nitride is deposited by PECVD x N y or SiON y film;

[0070] S11 performs electrode printing and sintering on both sides to obtain Figure 1 The front emitter region shown is a flat structure, and the non-emitter is a velvet structure cell;

[0071] S12 light injection is performed for processing, followed by testing and sorting.

[0072] Example 2

[0073] This embodiment provides a method for preparing a TOPCon battery with a domain-specific surface structure, comprising the following steps:

[0074] S1 Alkali Polishing: N-type silicon wafers are roughly polished with alkali to form a uniform polished surface on the front and back surfaces of the silicon wafer;

[0075] S2 laser oxidation: On the polished surface, a silicon oxide layer is formed by irradiating the silicon substrate with a laser according to the emitter pattern. The oxygen flow rate is 2000 sccm, the laser power density is 1.5 J / cm², the laser wavelength is 400 nm, the laser scanning speed is 300 mm / s, the pulse frequency is 60 kHz, the laser spot size is controlled at 40 μm, and the spot overlap is 35%. The resulting silicon oxide layer has a thickness of 35 nm and a refractive index of 1.6%.

[0076] S3 domain texturing: Texturing is performed on laser-oxidized silicon wafers, forming a nano-scale pyramid texture in the non-laser area of ​​the silicon wafer surface. The laser emitter pattern area, protected by a silicon oxide film, retains its planar structure during the texturing step. The emitter reflectivity is 30%, while the non-emitter reflectivity is 7.5%. The pyramid size is 1um high and 1um wide. The emitter plane platform is 5um lower than the non-emitter pyramid top.

[0077] S4 regional doping: Boron diffusion doping is performed on the textured surface of the front side of the silicon wafer after texturing; the deposition temperature is 870℃, the boron source flow rate is 250sccm, and the deposition pressure is 300mbar; the emitter area is a heavily doped P++ layer with a square resistance of 150Ω and a concentration of 2*10^19atoms / cm³; the non-emitter area is a lightly doped layer with a square resistance of 500Ω and a concentration of 3.5*10^18atoms / cm³.

[0078] S5 alkali polishing: pickling the back side, then alkali cleaning and polishing the back side;

[0079] S6 N+ layer poly silicon: SiO layer is formed first at high temperature on the back side and then N+ polysilicon layer is grown;

[0080] S7 Rca: Acid and alkaline washing on the front and back sides to remove the N+ polysilicon plated on the front side;

[0081] Al2O3 thin film was deposited on the S8 surface using ALD;

[0082] S9 silicon nitride: PECVD deposition of Si on the front surface x N y or SiON y film;

[0083] The back surface of S10 silicon nitride is deposited by PECVD x N y or SiON y film;

[0084] S11 performs electrode printing and sintering on both sides to obtain Figure 1 The front emitter region shown is a flat structure, and the non-emitter is a velvet structure cell;

[0085] S12 light injection is performed for processing, followed by testing and sorting.

[0086] Example 3

[0087] This embodiment provides a method for preparing a TOPCon battery with a domain-specific surface structure, comprising the following steps:

[0088] S1 Alkali Polishing: N-type silicon wafers are roughly polished with alkali to form a uniform polished surface on the front and back surfaces of the silicon wafer;

[0089] S2 Laser Oxidation: On the positive polished surface, a silicon oxide layer is formed when a laser is irradiated on the silicon substrate according to the emitter pattern; wherein: the oxygen flow rate is 1000sccm, the laser power density is 0.5J / cm², the laser wavelength is 600nm, the laser scanning speed is 500mm / s, the pulse frequency is 100kHz, the laser spot size is controlled at 50μm, and the spot overlap rate is 50%; the resulting silicon oxide layer is 20nm thick and has a refractive index of 1.8%.

[0090] S3 domain texturing: Texturing is performed on laser-oxidized silicon wafers to form a nano-scale pyramid texture in the non-laser area of ​​the silicon wafer surface. The laser emitter pattern area is protected by a silicon oxide film layer, and its planar structure can still be retained during the texturing step. The emitter reflectivity is 40%; the non-emitter reflectivity is 9%. The pyramid size is 1.5um high and 1.5um wide. The emitter plane platform is 6um lower than the non-emitter pyramid top.

[0091] S4 regional doping: Boron diffusion doping is performed on the textured surface of the front side of the silicon wafer in different regions after texturing; the deposition temperature is 800℃, the boron source flow rate is 100sccm, and the deposition pressure is 100mbar; the emitter area is a heavily doped P++ layer with a square resistance of 100Ω and a concentration of 3*10^19atoms / cm³; the non-emitter area is a lightly doped layer with a square resistance of 400Ω and a concentration of 6*10^18atoms / cm³;

[0092] S5 alkali polishing: pickling the back side, then alkali cleaning and polishing the back side;

[0093] S6 N+ layer poly silicon: SiO layer is formed first at high temperature on the back side and then N+ polysilicon layer is grown;

[0094] S7 Rca: Acid and alkaline washing on the front and back sides to remove the N+ polysilicon plated on the front side;

[0095] Al2O3 thin film was deposited on the S8 surface using ALD;

[0096] S9 silicon nitride: PECVD deposition of Si on the front surface x N y or SiON y film;

[0097] The back surface of S10 silicon nitride is deposited by PECVD x N y or SiON y film;

[0098] S11 performs electrode printing and sintering on both sides to obtain Figure 1 The front emitter region shown is a flat structure, and the non-emitter is a velvet structure cell;

[0099] S12 light injection is performed for processing, followed by testing and sorting.

[0100] Comparative Example 1

[0101] This comparative example provides a method for preparing a TOPCon battery with a domain-specific surface structure. This comparative example adopts a traditional process to prepare a TOPCon battery, and the entire front surface of the polished sheet thereof has a pyramid velvet structure; the method comprises the following steps:

[0102] S1 Texturing: Texturing of N-type silicon wafers, forming a nano-scale texture on the surface of the silicon wafer; the entire texture surface remains consistent in the wet process tank, with a reflectivity of 10% and a pyramid size of 1.7um high and 1.7um wide;

[0103] S2 Boron diffusion doping: A P+ layer is doped on the front surface of the silicon wafer to obtain a uniform sheet resistance of 300Ω across the entire surface.

[0104] S3 alkali polishing: pickling the back side, then alkali cleaning and polishing the back side;

[0105] S4 N+ layer poly silicon: SiO layer is formed first at high temperature on the back side and then N+ polysilicon layer is grown;

[0106] S5 Rca: Acid and alkaline washing on the front and back sides to remove the N+ polysilicon on the front side;

[0107] Al2O3 thin film was deposited on the S6 surface using ALD;

[0108] S7 silicon nitride: Si is deposited on the front surface using PECVD x N y or SiON y film;

[0109] The back surface of S8 silicon nitride is deposited by PECVD x N y or SiON y film;

[0110] S9 performs electrode printing and sintering on the front and back sides; Figure 2 The battery structure shown;

[0111] S10 light injection is performed for processing, followed by test sorting.

[0112] Comparative Example 2

[0113] This comparative example provides a method for preparing a TOPCon battery with a domain-divided surface structure. This comparative example adopts a traditional process to prepare a TOPCon battery, and the front surface of the polished sheet thereof is a flat structure. The method comprises the following steps:

[0114] S1 alkali polishing: N-type silicon wafers are roughly polished with alkali, and the front and back surfaces of the silicon wafers are alkali polished to a full plane (reflectivity 30%).

[0115] S2 Boron diffusion doping: A P+ layer is doped on the front surface of the silicon wafer to obtain a uniform sheet resistance of 300Ω across the entire surface;

[0116] S3 alkali polishing: pickling the back side, then alkali cleaning and polishing the back side;

[0117] S4 N+ layer poly silicon: SiO layer is formed first at high temperature on the back side and then N+ polysilicon layer is grown;

[0118] S5 Rca: Acid and alkaline washing on the front and back sides to remove the N+ polysilicon on the front side;

[0119] Al2O3 thin film was deposited on the S6 surface using ALD;

[0120] S7 silicon nitride: Si is deposited on the front surface using PECVD x N y or SiON y film;

[0121] The back surface of S8 silicon nitride is deposited by PECVD x N y or SiON y film;

[0122] S9 performs electrode printing and sintering on the front and back sides; Figure 3 The battery structure shown;

[0123] S10 light injection is performed for processing, followed by test sorting.

[0124] Performance Testing

[0125] The electrical performance of the TBC batteries prepared in Examples 1-3 and Comparative Examples 1-2 was tested, and the data are shown in Table 1:

[0126] Table 1 Test results of batteries of Examples and Comparative Examples

[0127] category Opening voltage Voc (mV) Short current Isc (mA) Filling FF (%) Conversion efficiency Eta (%) Series resistance Rs (mΩ) Parallel resistance Rsh (Ω) Leakage current Irev2 (A) Comparative Example 1 729.6 14.070 85.40 26.191 1.26 2413 0.051 Comparative Example 2 718.6 11.270 85.60 20.711 1.24 2555 0.054 Example 1 731.8 14.119 85.55 26.408 1.22 3765 0.042 Example 2 731.9 14.110 85.60 26.410 1.19 3777 0.022 Example 3 731.8 14.102 85.65 26.407 1.16 3870 0.033

[0128] Performance test data conclusion analysis:

[0129] Compared with the full velvet surface ratio 1, the conversion efficiency of the embodiment of the present application is improved by more than 0.2%, which is mainly due to the optoelectronic synergistic optimization of the domain structure;

[0130] The emitter planar design of the embodiment of the present application significantly reduces the contact square resistance, reduces the string resistance, and improves the fill factor by 0.15% to 0.25%, indicating that the domain structure effectively reduces carrier recombination; the domain structure reduces the risk of edge recombination and leakage, increases the parallel resistance by 1352 to 1457Ω, and reduces the leakage by 0.018 to 0.029A; the non-emitter suede reflectivity is reduced to 6% to 9%, and the short-circuit current is increased by more than 30mA; the non-emitter high square resistance design reduces recombination and increases the open-circuit voltage by more than 2mV;

[0131] Compared with Comparative Example 2 (entire planar structure), Comparative Example 2 has a significantly lower efficiency due to a decrease in current due to excessive reflectivity; the short-circuit current of the embodiment of the present application is increased by more than 30 mA, and the conversion efficiency is increased by more than 0.2%, which significantly compensates for the light absorption defects of the planar structure.

[0132] Therefore, the domain-divided surface structure of the present application breaks through the bottleneck of the traditional single structure by synergistically optimizing the contact performance and light absorption efficiency, verifying the significant advancement of the present invention.

[0133] The present application forms an emitter planar contact structure and a non-emitter low-reflectivity and low-doping structure by regionalizing the front velvet surface. Compared with conventional processes, the non-emitter low-doping recombination is significantly reduced and the opening voltage is significantly improved; the non-emitter velvet surface becomes smaller, the reflectivity is significantly reduced, the optical absorption is significantly increased, and the current is significantly improved; the emitter contact area is planar and highly doped, the contact is significantly improved, and the filling ff is significantly improved; therefore, the above structure significantly improves the battery efficiency.

[0134] The present invention is further described above with the aid of specific embodiments. However, it should be understood that the specific description herein should not be construed as limiting the essence and scope of the present invention. Various modifications made to the above embodiments by ordinary technicians in this field after reading this specification are all within the scope of protection of the present invention.

Claims

1. A TOPCon cell with a domain-specific surface structure, comprising an N-type silicon substrate, characterized in that: The front side of the N-type silicon substrate is divided into an emitter region and a non-emitter region; the emitter region is a planar structure, the non-emitter region is a pyramid velvet structure, and the boron doping concentration of the emitter region is higher than that of the non-emitter region.

2. The TOPCon battery with a domain surface structure according to claim 1, characterized in that: The reflectivity of the emitter is 20%~40%, and the reflectivity of the non-emitter is 6%~9%; the tower height of the pyramid velvet structure is 0.5~1.5μm, the tower width is 0.5~1.5μm, and the surface height of the planar structure is 4~6μm lower than the tower top of the pyramid velvet structure.

3. The TOPCon battery with a domain surface structure according to claim 1, characterized in that: The surface of the emitter region is covered with a heavily doped P++ layer with a square resistance of 100~200Ω and a concentration of 1*10^19~3*10^19 atoms / cm³; the surface of the non-emitter region is covered with a lightly doped P+ layer with a square resistance of 400-600Ω and a concentration of 1*10^18~6*10^18 atoms / cm³.

4. A method for preparing a TOPCon battery having a domain surface structure according to any one of claims 1 to 3, characterized in that: The steps include: S1: Alkaline polishing of N-type silicon wafer to form front and back polished surfaces; S2: Generate a silicon oxide layer on the emitter region on the front side of the silicon wafer through a laser oxidation process; S3: Texturing the silicon wafer to form a velvet structure in the non-emitter region and retain a planar structure in the emitter region; S4: Boron diffusion doping is performed on the front side of the silicon wafer to form a heavily doped P++ layer in the emitter region and a lightly doped P+ layer in the non-emitter region.

5. The preparation method according to claim 4, characterized in that In S2, the parameters of the laser oxidation process are: Laser wavelength 200~600nm, power density 0.5~2.0J / cm², scanning speed 100~500mm / s; Oxygen flow rate is 1000~3000sccm, spot size is 30~50μm, and spot overlap rate is 20%~50%.

6. The preparation method according to claim 4, characterized in that In the S2, the laser pulse frequency is 20-100 kHz.

7. The preparation method according to claim 4, characterized in that In the S2, the thickness of the silicon oxide layer is 20-50 nm, the refractive index is 1.4-1.8, and the porosity is less than 0.5%.

8. The preparation method according to claim 4, characterized in that After S3, the method further includes: removing the silicon oxide layer in the emitter region by pickling, and retaining the textured structure in the non-emitter region.

9. The preparation method according to claim 4, characterized in that In the above-mentioned S4, the conditions for boron diffusion doping are: temperature 800-950° C., boron source flow rate 100-400 sccm, and deposition pressure 100-500 mbar.

10. The preparation method according to claim 4, characterized in that Also includes: S5: acid washing and alkaline washing and polishing the back of the silicon wafer; S6: depositing a tunnel oxide layer and an N+ polysilicon layer on the back side of the silicon wafer; S7: Chemically clean the front side of the silicon wafer and plate N+ polysilicon; S8: depositing an aluminum oxide passivation layer on the silicon wafer surface; S9: Deposition of anti-reflection layer on the front and back sides of silicon wafer; S10: Electrodes are printed on the front and back of the silicon wafer and sintered.

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