Multi-threshold 16T anti-radiation SRAM (Static Random Access Memory) storage unit circuit and storage

Abstract

The invention relates to a multi-threshold 16T anti-radiation SRAM (Static Random Access Memory) storage unit circuit and a memory, a storage module in the circuit is of a bistable structure formed by two cross-coupled phase inverters formed by PMOS (P-channel Metal Oxide Semiconductor) transistors, and two storage nodes are formed; the redundant storage module adopts NMOS (N-channel metal oxide semiconductor) transistors to form a bistable structure, and two redundant nodes are formed to serve as redundant backups of the storage module; when the read-write operation control module reads or writes data, a word line is activated, and the data is read from the storage node and the redundant node or written into the storage node and the redundant node through the switched-on transistor; and the bit line driving module is used for driving the bit lines during reading and writing operations. According to the circuit, by introducing redundant nodes and a feedback mechanism, efficient resistance and recovery of single-particle and multi-node upset are achieved, the anti-radiation capacity is improved, the static noise margin, the read-write speed and the power consumption performance are optimized, and the circuit is suitable for the reliable data storage requirement in the high-radiation environment.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits and relates to a multi-threshold 16T radiation-resistant SRAM storage unit circuit and a memory. Background Art

[0002] With the rapid advancement of semiconductor technology, demand for electronic devices operating in extreme environments continues to grow, encompassing diverse fields such as space exploration, nuclear power facilities, and high-radiation medical environments. Under these demanding conditions, electronic devices embedded in system-on-chip (SoC) chips must not only meet high performance and high integration requirements but also possess excellent radiation resistance to ensure system reliability and stability. Radiation-induced electromagnetic interference, bit flips, and memory cell errors pose significant challenges to SoC memory devices, particularly static random access memory (SRAM).

[0003] As a core component in SoC systems, SRAM plays a vital role in system performance and stability. However, in radiation environments, SRAM is susceptible to the effects of ionizing radiation. When high-energy particles pass through the silicon substrate, they generate minority carriers, which can be diffused and collected by the source or drain electrodes. When the transistors surrounding the storage node collect these carriers, they may cause changes in the storage node data, a phenomenon known as single event upset. If these changes are not corrected in a timely manner, they may cause the data of the entire storage cell to flip, affecting the data integrity and reliability of the storage cell, resulting in temporary or permanent failure.

[0004] To meet the radiation-hardening requirements of integrated circuits (ICs) in spacecraft and other applications, several existing solutions have been proposed. However, most of these solutions have limitations. While some solutions can fully recover from data upsets at a single node caused by a single-event effect, their ability to recover data at two or more nodes simultaneously is significantly reduced, or even impossible. Summary of the Invention

[0005] To address the problems existing in the above-mentioned traditional methods, the present invention proposes a multi-threshold 16T radiation-hardened SRAM memory cell circuit and a memory, which overcome the defects of existing radiation-hardened SRAM memory cells such as insufficient recovery capability when dealing with simultaneous multi-node flips, low static noise margin (SNM), limited read and write speeds, and high power consumption. It can effectively deal with single-event effects and can still maintain data integrity in the case of multi-node flips.

[0006] To achieve the above objectives, the embodiments of the present invention adopt the following technical solutions: On the one hand, a multi-threshold 16T radiation-resistant SRAM memory cell circuit is provided, which includes: a memory module, a redundant memory module, a read / write operation control module, and a bit line driver module; The storage module is used to form a bistable structure with two cross-coupled inverters composed of PMOS transistors to form two storage nodes.

[0007] The redundant storage module is used to form a bistable structure using NMOS transistors to form two redundant nodes as a redundant backup of the storage module. When a storage node in the storage module is disturbed and an error occurs, the redundant storage module helps restore the correct data through a specific circuit mechanism.

[0008] The read and write operation control module is used to activate the word line when reading or writing data, and read data from the storage node and the redundant node or write data into the storage node and the redundant node through the turned-on transistor.

[0009] The bit line driver module is used to drive the bit line during read and write operations to ensure that the bit line can correctly interact with the storage node and the redundant node for data.

[0010] On the other hand, a memory is further provided, comprising at least one of any of the above-mentioned multi-threshold 16T radiation-resistant SRAM memory cell circuits.

[0011] One of the above technical solutions has the following advantages and beneficial effects: The multi-threshold 16T radiation-resistant SRAM memory cell circuit and memory described above feature a storage module that uses two cross-coupled inverters composed of PMOS transistors to form a bistable structure, creating two storage nodes. A redundant storage module uses NMOS transistors to form a bistable structure, creating two redundant nodes that serve as redundant backups for the storage module. A read / write operation control module activates the word line when reading or writing data, allowing the transistors to turn on and read or write data from or to the storage and redundant nodes. A bitline driver module drives the bitline during read and write operations. By introducing redundant nodes and a feedback mechanism, this circuit achieves efficient resistance and recovery from single-particle and multi-node upsets, improving radiation resistance while also optimizing static noise margin, read / write speed, and power consumption. It is suitable for reliable data storage in high-radiation environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 11 is a principle block diagram of a multi-threshold 16T radiation-hardened SRAM memory cell circuit according to one embodiment; Figure 2 16T radiation-resistant SRAM memory cell circuit in a multi-threshold value according to an embodiment of the present invention; Figure 3 1 is a transient recovery waveform simulation diagram of a multi-threshold 16T radiation-hardened SRAM memory cell circuit under single event upset (SEU) injection in one embodiment. DETAILED DESCRIPTION

[0014] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0015] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0016] It should be noted that, when referred to in this document as an "embodiment", it means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presentation of this phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It will be understood by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or" used in this document refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0017] The following describes the implementation of the present invention in detail with reference to the accompanying drawings in the embodiments of the present invention.

[0018] In one embodiment, Figure 1 As shown, a multi-threshold 16T radiation-resistant SRAM memory cell circuit is provided, which includes: a memory module, a redundant memory module, a read-write operation control module, and a bit line driver module.

[0019] The storage module is used to form a bistable structure with two cross-coupled inverters composed of PMOS transistors to form two storage nodes.

[0020] The redundant storage module is used to form a bistable structure using NMOS transistors to form two redundant nodes as a redundant backup of the storage module. When a storage node in the storage module is disturbed and an error occurs, the redundant storage module helps restore the correct data through a specific circuit mechanism.

[0021] Specifically, by utilizing the states of the first redundant node S1 and the second redundant node S0, through a cross-coupling feedback path, not only can certain SEUs of the first redundant node S1 and the second redundant node S0 themselves be immune, but single-node flips occurring in the first storage node Q and the second storage node QB, as well as double-node flips occurring simultaneously in the first storage node Q and the second storage node QB, can also be effectively recovered.

[0022] The read and write operation control module is used to activate the word line when reading or writing data, and read data from the storage node and the redundant node or write data into the storage node and the redundant node through the turned-on transistor.

[0023] The bit line driver module is used to drive the bit line during read and write operations to ensure that the bit line can correctly interact with the storage node and the redundant node for data.

[0024] This circuit utilizes source isolation reinforcement technology, introducing key peripheral feedback nodes—the first redundant node S1 and the second redundant node S0—through redundant node and feedback design. Source isolation reinforcement involves stacking PMOS transistors in a source-drain series configuration. When a high-energy particle strikes the drain of a PMOS transistor near a storage node in the stack, the generated charge must simultaneously flip the gate voltages of both series-connected PMOS transistors in the stack to cause the storage node to flip, significantly increasing the difficulty of the flip and effectively suppressing single-event upsets (0→1) in the storage nodes. The first and second redundant nodes S1 and S0 are driven by the states of the first and second storage nodes Q and QB, and control the recovery of the first and second storage nodes Q and QB through feedback paths. Furthermore, the first and second redundant nodes S1 and S0 isolate the complex reinforcement logic from the core storage nodes Q and QB, reducing direct leakage paths on the first and second storage nodes Q and QB, lowering the risk of leakage during data retention, and enhancing long-term stability. At the same time, the data feedback of the first redundant node S1 and the second redundant node S0 ensures that the first storage node Q and the second storage node QB can be restored to their initial states after a flip, thereby enabling the unit to achieve improved radiation resistance while ensuring tolerance performance, and can achieve recovery even when SEU occurs in some dual nodes.

[0025] The multi-threshold 16T radiation-resistant SRAM memory cell circuit described above features a storage module that uses two cross-coupled inverters composed of PMOS transistors to form a bistable structure, creating two storage nodes. A redundant storage module uses NMOS transistors to form a bistable structure, creating two redundant nodes that serve as redundant backups for the storage module. A read / write operation control module activates the word line when reading or writing data, allowing the transistors to turn on and read or write data from or to the storage and redundant nodes. A bitline driver module drives the bitline during read and write operations. By introducing redundant nodes and a feedback mechanism, this circuit achieves efficient resistance and recovery from single-particle and multi-node upsets. This not only improves radiation resistance but also optimizes static noise margin, read / write speed, and power consumption, making it suitable for reliable data storage in high-radiation environments.

[0026] In one embodiment, the storage module has four PMOS transistors, which are denoted as: P1, P2, P5, and P6 in sequence; the first storage node is connected to the drain of P1, the gate of P2, the source of P5, and the gate of P6, and the second storage node is connected to the gate of P1, the drain of P2, the gate of P5, and the source of P6; the sources of P1 and P2 are connected to the power supply voltage VDD, the drain of P5 is connected to the second redundant node, and the drain of P6 is connected to the first redundant node.

[0027] In one embodiment, P1 and P5, P2 and P6 form source isolation reinforcement, and the PMOS transistors are stacked and connected in a source-drain series manner.

[0028] In one embodiment, the redundant memory module includes four NMOS transistors, which are sequentially denoted as: N1L, N2L, N3L, and N4L.

[0029] The first redundant node is connected to the drain of P5, the drain of N1L, the gate of N2L and the gate of N4L; the first redundant node is connected to the first storage node through a conductive NMOS transistor in the read operation control module, and the first redundant node is connected to the BL line through a conductive NMOS transistor in the bit line driver module.

[0030] The second redundant node is connected to the drain of P6, the gate of N1L, the drain of N2L and the gate of N3L; the second redundant node is connected to the second storage node through another conductive NMOS transistor in the read operation control module, and the second redundant node is connected to the BLB line through another conductive NMOS transistor in the bit line driver module.

[0031] The drain of N4L is connected to the second storage node, the drain of N3L is connected to the first storage node, and the sources of N1L, N2L, N3L, and N4L are all connected to the ground potential GND.

[0032] In one embodiment, N1L, N2L, N3L, and N4L utilize large dimensions and low threshold voltages to provide strong pull-down capability and high read current. The key pull-down NMOS transistors (N1L-N4L) utilize low threshold voltage (LVT), significantly increasing read current and improving read speed.

[0033] In one embodiment, the read and write operation control module includes: two NMOS transistors and two high-threshold PMOS transistors; denoted as: N5, N6, P3H and P4H in sequence; the drain, source and gate of P3H are respectively connected to the drain of N5, the power supply voltage VDD and the first storage node; the drain, source and gate of P4H are respectively connected to the drain of N6, the power supply voltage VDD and the second storage node; the gate and source of N5 are respectively connected to the second storage node and the second redundant node; the gate and source of N6 are respectively connected to the first storage node and the first redundant node.

[0034] Specifically, a multi-threshold voltage design is adopted, and the key PMOS transistors (P3H, P4H) use a high threshold voltage (HVT) to suppress radiation leakage current, reduce power consumption, and enhance node stability.

[0035] In one embodiment, P3H and P4H are used for write assist or stability enhancement, using a high threshold voltage.

[0036] In one embodiment, the bit line driver module includes four NMOS transistors, which are sequentially denoted as: N7, N8, N9, and N10.

[0037] The drains of N7, N8, N9 and N10 are all connected to the word lines, the sources of N7 and N9 are all connected to the first bit line BL, the sources of N8 and N10 are all connected to the second bit line BLB, the gate of N7 is connected to the first storage node, the gate of N8 is connected to the second storage node, the gate of N9 is connected to the first redundant node, and the gate of N10 is connected to the second redundant node.

[0038] In one embodiment, N7, N8, N9, and N10 are large in size to reduce the bit line discharge equivalent resistance during a read operation.

[0039] In a specific embodiment, a multi-threshold 16T radiation-hardened SRAM memory cell circuit is provided, comprising: six PMOS transistors, two of which are high-threshold PMOS transistors (P3H and P4H); and ten NMOS transistors, four of which are low-threshold NMOS transistors (N1L-N4L). The six PMOS transistors are sequentially designated P1, P2, P3H, P4H, P5, and P6, and the ten NMOS transistors are sequentially designated N1L-N4L and N5-N10. The specific connection relationship is as follows: The first storage node Q is connected to the drain of the PMOS transistor P1 , the gate of the PMOS transistor P2 , the gate of the PMOS transistor P3H, the source of the PMOS transistor P5 , the gate of the PMOS transistor P6 , the drain of the NMOS transistor N3L, the gate of the NMOS transistor N6 , and the drain of the NMOS transistor N7 .

[0040] The second storage node QB is connected to the gate of the PMOS transistor P1, the drain of the PMOS transistor P2, the gate of the PMOS transistor P4H, the gate of the PMOS transistor P5, the source of the PMOS transistor P6, the drain of the NMOS transistor N4L, the gate of the NMOS transistor N5, and the drain of the NMOS transistor N8.

[0041] The first redundancy node S1 is connected to the drain of the PMOS transistor P5 , the drain of the NMOS transistor N1L, the gate of the NMOS transistor N2L, the gate of the NMOS transistor N4L, the source of the NMOS transistor N6 , and the drain of the NMOS transistor N9 .

[0042] The second redundancy node S0 is connected to the drain of the PMOS transistor P6 , the gate of the NMOS transistor N1L, the drain of the NMOS transistor N2L, the gate of the NMOS transistor N3L, the source of the NMOS transistor N5 , and the drain of the NMOS transistor N10 .

[0043] The drain of the PMOS transistor P3H is connected to the drain of the NMOS transistor N5 ; the drain of the PMOS transistor P4H is connected to the drain of the NMOS transistor N6 .

[0044] The power supply voltage VDD is connected to the source of the PMOS transistor P1, the source of the PMOS transistor P2, the source of the PMOS transistor P3H, and the source of the PMOS transistor P4H; the ground potential GND is connected to the source of the NMOS transistor N1L, the source of the NMOS transistor N2L, the source of the NMOS transistor N3L, and the source of the NMOS transistor N4L.

[0045] The word line WL connects the gates of the NMOS transistors N7, N8, N9, and N10; the first bit line BL connects the source of the NMOS transistors N7 and N9; and the second bit line BLB connects the source of the NMOS transistors N8 and N10.

[0046] The gate of the PMOS transistor P1 is electrically connected to the drain of the PMOS transistor P2, and the drain of the PMOS transistor P1 is electrically connected to the gate of the PMOS transistor P2, forming a cross-coupling structure that significantly enhances resistance to data flipping at a single node; the gate of the NMOS transistor N1L is electrically connected to the drain of the NMOS transistor N2L, and the drain of the NMOS transistor N1L is electrically connected to the gate of the NMOS transistor N2L, forming a cross-coupling structure to resist data flipping at a single node.

[0047] The key pull-up PMOS transistors (P1, P2, P5, P6) use a smaller size to balance area and drive capability; the PMOS transistors (P3H, P4H) used for write assist or stability enhancement use a high threshold voltage; the key pull-down NMOS transistors (N1L-N4L) use a larger size and a low threshold voltage to provide strong pull-down capability and high read current; the pass transistors (N7-N10) use a larger size to reduce the bit line discharge equivalent resistance during read operations.

[0048] The multi-threshold 16T radiation-resistant SRAM memory cell circuit proposed in this application uses multiple cross-couplings to form positive feedback to maintain the logic state. The PMOS transistors P3H and P4H use high-threshold transistors to suppress radiation-induced leakage current, reduce charge injection into sensitive nodes, and reduce power consumption. The NMOS transistors N1L, N2L, N3L, and N4L use low-threshold voltage NMOS transistors, with the core purpose of increasing the on-state current and significantly improving the speed of read operations. Four pass transistors are used to reduce the equivalent resistance of bitline discharge and accelerate voltage difference establishment. The present invention also uses a transistor stacking method to significantly reduce leakage current. All data branches are powered by a power supply, increasing data drive capability.

[0049] The working principle of the multi-threshold 16T radiation-hardened SRAM memory cell circuit is as follows: In the data writing phase: the word line WL is at a high level, and the NMOS transistors N7-N10 are turned on; If the first bit line BL is at a high level and the second bit line BLB is at a low level, then "1" is written to the first storage node Q through the NMOS transistor N7, "1" is written to the first redundant node S1 through the NMOS transistor N9, "0" is written to the second storage node QB through the NMOS transistor N8, and "0" is written to the second redundant node S0 through the NMOS transistor N10; On the contrary, if the first bit line BL is at a low level and the second bit line BLB is at a high level, then "0" is written to the first storage node Q through the NMOS transistor N7, "0" is written to the first redundant node S1 through the NMOS transistor N9, "1" is written to the second storage node QB through the NMOS transistor N8, and "1" is written to the second redundant node S0 through the NMOS transistor N10.

[0050] In the data holding stage: the first bit line BL and the second bit line BLB of the word are precharged to a high level, the word line WL is at a low level, and the inside of the cell maintains an initial state and does not operate.

[0051] In the data reading phase: the first bit line BL and the second bit line BLB are both precharged to a high level, the word line WL is at a high level, and the NMOS transistors N7-N10 are turned on; If the data stored in the cell circuit is "0," then Q = S1 = 0, QB = S0 = 1. The first bit line BL then flows through discharge path 1: first bit line BL -> N7 (on, WL high) -> Q (low) -> N3L (on, because S0 = 1) -> GND; and discharge path 2: first bit line BL -> N9 (on, WL high) -> S1 (low) -> N1L (on, because S0 = 1) -> GND. The voltage on the second bit line BLB remains unchanged, creating a voltage difference between the first and second bit lines. The data is then read out via a sense amplifier.

[0052] If the data stored in the unit circuit is "1" at this time, then "Q=S1=1, QB=S0=0", then the second bit line BLB is connected to discharge path 1: second bit line BLB ->N10 (on, WL high) ->S0 (low level) ->N2L (on, because S1=1) ->GND, and discharge path 2: second bit line BLB ->N8 (on, WL high) ->QB (low level) ->N4L (on, because S1=1) ->GND. A voltage difference is generated between the first bit line BL and the second bit line BLB, and then the data is read out through the sense amplifier.

[0053] like Figure 2 As shown in FIG, the timing waveform diagram of the multi-threshold 16T radiation-resistant SRAM memory cell circuit proposed in this application, the specific simulation conditions are: process corner (Corner): TT, temperature (Temperature): 25°C, power supply voltage VDD: 1.2V. Figure 2 It can be seen that the data "0" is written in 10-20ns, the data "0" is read out in 30-40ns, the data "1" is written in 50-60ns, and the data "1" is read out in 70-80ns. It can be seen that the multi-threshold 16T radiation-resistant SRAM storage cell circuit provided by the present invention can realize the operations of writing "0", reading "0", writing "1", and reading "1" on the storage node.

[0054] like Figure 3 As shown in FIG, it is a transient waveform simulation diagram of a multi-threshold 16T radiation-resistant SRAM memory cell circuit when different nodes are injected with a double exponential current pulse at different times. Figure 3As can be seen, at 22ns, the second redundant node S0 was struck by a single event, causing the data to flip from "1" to "0". Through the circuit feedback structure, the data was restored in a short time. At 27ns, the first storage node Q was struck by a single event, causing the data to flip from "0" to "1". Through the circuit feedback structure, the data was restored in a short time. At 450ns, the second storage node QB was struck by a single event, causing the data to flip from "1" to "0". Through the circuit feedback structure, the data was restored in a short time. At 62ns, the first storage node Q was struck by a single event, causing the data to flip from "1" to "0". The second storage node QB was struck by a single event, causing the data to flip from "0" to "1". Through the circuit feedback structure, the data was restored in a short time. At 68ns, the first redundant node S1 was struck by a single event, causing the data to flip from "1" to "0". Through the circuit feedback structure, the data was restored in a short time.

[0055] Let's take the storage state of "1" (i.e., Q="1", QB="0", S1="1", S0="0") as an example. When the first storage node Q undergoes a data flip, from state "1" to state "0," the PMOS transistors P2, P3H, and P6 turn on, while the NMOS transistor N6 turns off. The unaffected first redundant node S1 remains high. At this point, due to the conduction of PMOS transistors P2 and P3H, the second storage node QB and the second redundant node S0 attempt to charge via the pull-up path. However, the NMOS transistors N2L and N4L in the pull-down path remain on due to the high level of the first redundant node S1, creating a competition between the pull-up and pull-down currents. This causes the second storage node QB and the second redundant node S0 to only briefly display a weak "0" state, preventing a significant increase in potential. Crucially, because the second storage node QB maintains its initial low level, PMOS transistor P1 remains continuously on, providing a stable pull-up charging path for the first storage node Q, allowing its potential to gradually return to a high level. As the potential of the first storage node Q recovers, PMOS transistors P2, P3H, and P6 turn off one after another, and the circuit eventually fully returns to its initial stable state.

[0056] When the data of the second storage node QB is flipped, that is, from state "0" to state "1". When the data of the second storage node QB is flipped from "1" to "0", the PMOS transistors P1, P4H, and P5 are turned off, and the NMOS transistor N5 is turned on. The unaffected first redundant node S1 still maintains its original high level state, and the second redundant node S0 still maintains its original low level state. The NMOS transistors N1L and N3L remain turned off, while the NMOS transistors N2L and N4L continue to be turned on due to the high level of the first redundant node S1. It is worth noting that the potential of the first storage node Q is completely unaffected by this flip and remains at a stable high level. As the potential of the second storage node QB increases, the pull-down transistor N4H is activated and turned on, and the potential of the second storage node QB gradually decreases through the discharge path, and eventually completely recovers to the initial low level state, so that the entire storage unit reaches a stable working state again.

[0057] When the data of the first redundant node S1 flips from state "1" to state "0," the NMOS transistors N2L and N4L turn off, turning off the pull-down circuits of the memory cells. Since the first storage node Q and the second storage node QB of the pull-up circuits are not affected, the PMOS transistors P4H and P5 remain on, and the potential of the first redundant node S1 is pulled high, restoring to the potential of "1."

[0058] When the first storage node Q and the second storage node QB are simultaneously flipped due to a single event effect, that is, the potential of the first storage node Q flips from "1" to "0", and the potential of the second storage node QB flips from "0" to "1", the PMOS transistors P2, P3H, and P6 are turned on, the PMOS transistors P1, P4H, and P5 are turned off, the NMOS transistor N5 is turned on, and the NMOS transistor N6 is turned off. The first redundant node S1 and the second redundant node S0 are not affected, and the pull-down circuit of the storage unit remains in the initial state. Because the size of the cell pull-down transistor N2L is larger than that of transistor P3H, the potential of the second redundant node S0 is not pulled high, but remains at a weak "0" potential. Therefore, the pull-down circuit maintains its original state. As NMOS transistor N4L turns on, the potential of the second storage node QB gradually discharges to a low level through the path from NMOS transistor N4L to ground. PMOS transistors P1, P4H, and P5 turn on, while NMOS transistor N3L turns off. The potential of the first storage node Q is charged to a high level by the conductive VDD to PMOS transistor P1, and then PMOS transistors P2, P3H, and P6 turn off, thus restoring the potential state of the storage cell to its initial state. This process proves that after the first storage node Q and the second storage node QB flip simultaneously, the circuit can achieve autonomous recovery through the state and feedback mechanism of the first redundant node S1 and the second redundant node.

[0059] It should be noted that when the storage state is "0", the principle of combating SEU is similar and will not be repeated here.

[0060] In one embodiment, a memory is further provided, comprising at least one of any of the above-mentioned multi-threshold 16T radiation-resistant SRAM memory cell circuits.

[0061] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0062] The above embodiments merely illustrate several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person skilled in the art would be able to make numerous modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of the present application.

Claims

1. A multi-threshold 16T radiation-hardened SRAM memory cell circuit, characterized in that: The circuit includes: a storage module, a redundant storage module, a read and write operation control module and a bit line driver module; The storage module is configured to form a bistable structure with two cross-coupled inverters composed of PMOS transistors to form two storage nodes; The redundant storage module is configured to use NMOS transistors to form a bistable structure, forming two redundant nodes as a redundant backup of the storage module. When a storage node in the storage module is disturbed and an error occurs, the redundant storage module helps restore the correct data through a specific circuit mechanism. The read / write operation control module is configured to activate the word line when reading or writing data, and read data from the storage node and the redundant node or write data to the storage node and the redundant node through the turned-on transistor; The bit line driving module is used to drive the bit line during read and write operations to ensure that the bit line can correctly exchange data with the storage node and the redundant node.

2. The multi-threshold 16T radiation-hardened SRAM memory cell circuit according to claim 1, characterized in that: The four PMOS transistors in the storage module are denoted as: P1, P2, P5, and P6; The first storage node is connected to the drain of P1, the gate of P2, the source of P5, and the gate of P6, and the second storage node is connected to the gate of P1, the drain of P2, the gate of P5, and the source of P6; The sources of P1 and P2 are connected to the power supply voltage VDD, the drain of P5 is connected to the second redundancy node, and the drain of P6 is connected to the first redundancy node.

3. The multi-threshold 16T radiation-hardened SRAM memory cell circuit according to claim 2, characterized in that: P1 and P5, P2 and P6 form source isolation reinforcement, and the PMOS transistors are stacked and connected in a source-drain series manner.

4. The multi-threshold 16T radiation-hardened SRAM memory cell circuit according to claim 2, characterized in that: The redundant memory module includes four NMOS transistors, which are sequentially denoted as: N1L, N2L, N3L and N4L; The first redundant node is connected to the drain of P5, the drain of N1L, the gate of N2L, and the gate of N4L; the first redundant node is connected to the first storage node through a conductive NMOS transistor in the read operation control module, and the first redundant node is connected to the BL line through a conductive NMOS transistor in the bit line driver module; The second redundant node is connected to the drain of P6, the gate of N1L, the drain of N2L, and the gate of N3L; the second redundant node is connected to the second storage node through another conductive NMOS transistor in the read operation control module, and the second redundant node is connected to the BLB line through another conductive NMOS transistor in the bit line driver module; The drain of N4L is connected to the second storage node, the drain of N3L is connected to the first storage node, and the sources of N1L, N2L, N3L, and N4L are all connected to the ground potential GND.

5. The multi-threshold 16T radiation-hardened SRAM memory cell circuit according to claim 4, characterized in that: N1L, N2L, N3L, and N4L use large sizes and low threshold voltages to provide strong pull-down capability and high read current.

6. The multi-threshold 16T radiation-hardened SRAM memory cell circuit according to claim 1, characterized in that: The read and write operation control module includes: two NMOS transistors and two high-threshold PMOS transistors; denoted as: N5, N6, P3H and P4H; The drain, source and gate of P3H are connected to the drain of N5, the power supply voltage VDD and the first storage node respectively; The drain, source and gate of P4H are connected to the drain of N6, the power supply voltage VDD and the second storage node respectively; The gate and source of N5 are connected to the second storage node and the second redundancy node respectively; The gate and source of N6 are connected to the first storage node and the first redundancy node respectively.

7. The multi-threshold 16T radiation-hardened SRAM memory cell circuit according to claim 6, characterized in that: P3H and P4H are used for write assist or stability enhancement and adopt high threshold voltage.

8. The multi-threshold 16T radiation-hardened SRAM memory cell circuit according to claim 1, characterized in that: The bit line driver module includes four NMOS transistors, which are sequentially denoted as: N7, N8, N9, and N10; The drains of N7, N8, N9 and N10 are all connected to the word lines, the sources of N7 and N9 are all connected to the first bit line BL, the sources of N8 and N10 are all connected to the second bit line BLB, the gate of N7 is connected to the first storage node, the gate of N8 is connected to the second storage node, the gate of N9 is connected to the first redundant node, and the gate of N10 is connected to the second redundant node.

9. The multi-threshold 16T radiation-hardened SRAM memory cell circuit according to claim 8, characterized in that: N7, N8, N9, and N10 are large in size to reduce the bit line discharge equivalent resistance during the read operation.

10. A memory, characterized in that: The memory comprises at least one multi-threshold 16T radiation-hardened SRAM memory cell circuit according to any one of claims 1 to 9.

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