Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention provides a semiconductor device with good reliability and a method for manufacturing the semiconductor device. A semiconductor device including a transistor, the transistor including: a first insulator; a second insulator; a first oxide; a second oxide; a third oxide; a first conductor and a second conductor; a third insulator; a third conductor; a fourth insulator; and a fifth insulator. The fourth insulator and the fifth insulator are provided with openings that reach the second oxide, and a third oxide, a third insulator, and a third conductor are provided in this order from the inner wall side of the openings so as to be embedded in the openings. In a channel length direction of the transistor, at least a portion of the fourth insulator in a region where the fourth insulator and the second oxide do not overlap is in contact with the first insulator. In a channel width direction of the transistor, at least a portion of the third oxide in a region where the third oxide and the second oxide do not overlap is in contact with the first insulator.

Description

This invention application is a divisional application of the invention patent application with international application number PCT / IB2019 / 051397, international application date February 21, 2019, application number 201980016079.8 entering the Chinese national phase, and name “Semiconductor device and method for manufacturing a semiconductor device”. Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

[0002] Note that in this specification and other documents, a semiconductor device refers to any device that can operate by utilizing semiconductor properties. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, and storage devices are also examples of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, and electronic devices may also include semiconductor devices.

[0003] Note that one embodiment of the present invention is not limited to the aforementioned technical fields. An embodiment of the invention disclosed in this specification and other aspects relates to an object, method, or manufacturing method. Furthermore, one embodiment of the present invention relates to a process, machine, product, or composition of matter. Background Art

[0004] Silicon-based semiconductor materials are well-known as semiconductor thin films that can be used in transistors. Oxide semiconductors are also attracting attention as other materials. For example, in addition to single-metal oxides such as indium oxide and zinc oxide, multinary metal oxides are also known as oxide semiconductors. Among multinary metal oxides, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) is particularly intense.

[0005] Research on IGZO has led to the discovery of CAAC (c-axis aligned crystalline) and nc (nanocrystalline) structures in oxide semiconductors, which are neither single crystal nor amorphous (see Non-Patent Documents 1 to 3). Non-Patent Documents 1 and 2 disclose a technique for manufacturing transistors using oxide semiconductors having a CAAC structure. Non-Patent Documents 4 and 5 disclose a method for producing even microcrystalline oxide semiconductors with lower crystallinity than the CAAC and nc structures.

[0006] Transistors using IGZO for their active layers have extremely low off-state current (see Non-Patent Document 6), and LSIs and displays utilizing this characteristic are known (see Non-Patent Documents 7 and 8). [Prior technical literature] [Non-patent literature]

[0007] [Non-Patent Document 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, pp. 183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, number 4S, pp. 04ED18-1-04ED18-10 [Non-Patent Document 3] S. Ito et al., “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, pp. 151-154 [Non-patent document 4] S. Yamazaki et al., “ECS Journal of Solid State Science and Technology”, 2014, volume 3, issue 9, pp. Q3012-Q3022 [Non-patent document 5] S. Yamazaki, “ECS Transactions”, 2014, volume 64, issue 10, pp. 155-164 [Non-patent document 6] K. Kato et al., “Japanese Journal of Applied Physics”, 2012, volume 51, p. 021201-1-021201-7 [Non-Patent Document 7] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, pp. T216-T217 [Non-Patent Document 8] S.Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, pp. 626-629 Summary of the Invention Technical problem to be solved by the invention

[0008] One object of one embodiment of the present invention is to provide a semiconductor device with a large on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with high frequency characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with good reliability. Another object of one embodiment of the present invention is to provide a semiconductor device that can achieve miniaturization or high integration. Another object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity.

[0009] One object of one embodiment of the present invention is to provide a semiconductor device capable of retaining data for a long period of time. Another object of one embodiment of the present invention is to provide a semiconductor device with a high information writing speed. Another object of one embodiment of the present invention is to provide a semiconductor device with a high degree of design freedom. Another object of one embodiment of the present invention is to provide a semiconductor device capable of suppressing power consumption. Another object of one embodiment of the present invention is to provide a novel semiconductor device.

[0010] Note that the inclusion of the above-mentioned objectives does not preclude the existence of other objectives. Furthermore, one embodiment of the present invention does not necessarily achieve all of the above-mentioned objectives. Furthermore, objectives other than these objectives are naturally apparent from the description, drawings, claims, etc., and can be inferred from the description, drawings, claims, etc. Means of solving technical problems

[0011] One embodiment of the present invention is a semiconductor device including a transistor. The transistor includes: a first insulator; a second insulator on the first insulator; a first oxide on the second insulator; a second oxide on the first oxide; a third oxide on the second oxide; a first conductor and a second conductor on the second oxide; a third insulator on the third oxide; a third conductor on the third insulator; a fourth insulator on the first and second conductors; and a fifth insulator on the fourth insulator. The fourth and fifth insulators have openings that reach the second oxide. The third oxide is provided to cover the inner walls of the openings. The third insulator is provided to cover the inner walls of the openings via the third oxide. The third conductor is provided to be embedded in the openings via the third oxide and the third insulator. In the channel length direction of the transistor, at least a portion of the fourth insulator in a region where the fourth insulator does not overlap with the second oxide contacts the first insulator. The bottom of the third conductor in a region where the third conductor does not overlap with the second oxide is lower than the bottom of the second oxide, based on the bottom height of the first insulator in the channel width direction of the transistor. At least a portion of the third oxide in a region where the third oxide does not overlap with the second oxide in a channel width direction of the transistor is in contact with the first insulator.

[0012] In the above semiconductor device, the third oxide preferably has a stacked structure including a first layer and a second layer, wherein the first layer is in contact with the second oxide and the fifth insulator, and the second layer is provided between the first layer and the third insulator. Furthermore, the crystallinity of the second layer is preferably higher than that of the first layer. Furthermore, preferably, both the first and second layers contain In, an element M (M is Al, Ga, Y, or Sn), and Zn, and the atomic ratio of In among the constituent elements in the second layer is smaller than the atomic ratio of In among the constituent elements in the first layer.

[0013] Another embodiment of the present invention is a semiconductor device including a transistor, wherein the transistor includes: a first insulator; a second insulator on the first insulator; a first oxide on the second insulator; a second oxide on the first oxide; a third oxide on the second oxide; a third insulator on the third oxide; a conductor on the third insulator; a fourth insulator in contact with at least a portion of the third oxide, at least a portion of the top surface of the second oxide, at least a portion of the side surface of the second oxide, at least a portion of the side surface of the first oxide, at least a portion of the side surface of the second insulator, and at least a portion of the first insulator; a fifth insulator on the fourth insulator; and a sixth insulator in contact with at least a portion of the top surface of the third oxide, at least a portion of the top surface of the third insulator, at least a portion of the top surface of the conductor, and at least a portion of the top surface of the fifth insulator. The second oxide includes a first region, a second region, and a third region located between the first and second regions. The first and second regions have lower resistance than the third region. The conductor is provided above the third region so as to overlap with the third region. A portion of the third oxide and a portion of the third insulator are provided between the side surface of the conductor and the side surface of the fifth insulator. The fourth insulator has a region in contact with the first and second regions. In the channel width direction of the transistor, the bottom surface height of the conductor in a region where the conductor does not overlap with the second oxide is lower than the bottom surface height of the second oxide, with reference to the bottom surface height of the first insulator. In the channel width direction of the transistor, at least a portion of the third oxide in a region where the third oxide does not overlap with the second oxide is in contact with the first insulator.

[0014] In the above semiconductor device, the first region and the second region preferably contain phosphorus or boron.

[0015] Furthermore, in the above-mentioned semiconductor device, the first region and the second region preferably contain more oxygen vacancies than the third region.

[0016] In the semiconductor device, the fourth insulator preferably has a stacked structure including a third layer and a fourth layer, the third layer preferably contacts the first insulator, and the fourth layer preferably contacts the fifth insulator. Furthermore, the third layer preferably contains silicon oxide, and the fourth layer preferably contains aluminum oxide.

[0017] In the above semiconductor device, the third oxide preferably has a stacked structure including a first layer and a second layer, wherein the first layer is in contact with the second oxide and the fifth insulator, and the second layer is provided between the first layer and the third insulator. Furthermore, it is preferred that both the first layer and the second layer contain In, an element M (M is Al, Ga, Y, or Sn), and Zn, and the atomic ratio of In to the element M in the second layer is preferably smaller than the atomic ratio of In to the element M in the first layer. Effects of the Invention

[0018] According to one embodiment of the present invention, a semiconductor device with a large on-state current can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with excellent reliability can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with excellent electrical characteristics can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0019] Furthermore, a semiconductor device capable of retaining data for a long period of time can be provided. Furthermore, a semiconductor device with a high data write speed can be provided. Furthermore, a semiconductor device with a high degree of design freedom can be provided. Furthermore, a semiconductor device capable of suppressing power consumption can be provided. Furthermore, a novel semiconductor device can be provided.

[0020] Note that the description of these effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the aforementioned effects. Furthermore, effects other than these effects are naturally apparent from the description of the specification, drawings, claims, and the like, and effects other than these effects can be inferred from the description of the specification, drawings, claims, and the like. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG. 1 is a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. [ Figure 2 ] is a three-dimensional diagram of a semiconductor device according to one embodiment of the present invention. FIG3 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 4 is a plan view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 5 is a plan view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG6 is a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 7 is a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG8 is a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 9 is a plan view and a cross-sectional view illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 10 is a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 11 is a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 12 is a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 13 is a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 14 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 15 is a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 16 is a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 17 is a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 18 is a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 19 is a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 20 is a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 21 is a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 22 is a plan view and a cross-sectional view showing a method for manufacturing a semiconductor device according to one embodiment of the present invention. [ Figure 23 ] is a cross-sectional view showing the structure of a storage device according to one embodiment of the present invention. [ Figure 24 ] is a cross-sectional view showing the structure of a storage device according to one embodiment of the present invention. [ Figure 25 ] is a cross-sectional view showing the structure of a storage device according to one embodiment of the present invention. [ Figure 26 ] is a cross-sectional view showing the structure of a storage device according to one embodiment of the present invention. [Figure 27] is a block diagram showing a structural example of a storage device according to one embodiment of the present invention. FIG. 28 is a circuit diagram showing a structural example of a storage device according to one embodiment of the present invention. FIG29 is a schematic diagram of a semiconductor device according to one embodiment of the present invention. [Figure 30] is a schematic diagram of a storage device according to one embodiment of the present invention. [Figure 31] is a diagram showing an electronic device according to one embodiment of the present invention. Modes for Carrying Out the Invention

[0022] The following describes the embodiments with reference to the accompanying drawings. However, those skilled in the art will readily appreciate that the embodiments may be implemented in a variety of different forms, and their methods and details may be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited solely to the following embodiments.

[0023] In the drawings, the size, thickness of a layer or an area are sometimes exaggerated for the sake of clarity. Therefore, the present invention is not necessarily limited to the above-mentioned dimensions. In addition, in the drawings, ideal examples are schematically shown, so the present invention is not limited to the shapes or numerical values ​​shown in the drawings. For example, in an actual manufacturing process, a layer or a resist mask is sometimes unintentionally thinned due to treatments such as etching, but this is sometimes omitted and not reflected in the drawings for ease of understanding. In addition, in the drawings, the same reference numerals are sometimes used in common between different drawings to represent the same parts or parts with the same function, and their repeated descriptions are omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without specifically adding a reference numeral.

[0024] Furthermore, in particular, in top views (also referred to as plan views) or perspective views, some components may be omitted to facilitate understanding of the invention. In addition, some hidden lines may be omitted.

[0025] In addition, in this specification and other documents, ordinal numbers such as "first" and "second" are used for convenience, but these numbers do not indicate the order of the steps or the order of stacking. Therefore, for example, "first" can be appropriately replaced with "second" or "third" to provide a more detailed description. Furthermore, the ordinal numbers used in this specification and other documents may not match the ordinal numbers used to designate one embodiment of the present invention.

[0026] For convenience, terms such as "upper" and "lower" are used in this specification and other descriptions to describe the positional relationships of components with reference to the accompanying drawings. Furthermore, the positional relationships of the components may vary depending on the orientation in which the components are described. Therefore, the terms and phrases described in this specification are not limited and may be substituted as appropriate.

[0027] For example, in this specification, when it is explicitly stated that "X is connected to Y," this means that: X is electrically connected to Y; X is functionally connected to Y; or X is directly connected to Y. Therefore, the disclosure is not limited to specified connection relationships (e.g., those shown in the drawings or text), and connection relationships other than those shown in the drawings or text are also included in the disclosure.

[0028] Here, X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films and layers, etc.).

[0029] In this specification, etc., a transistor refers to an element that includes at least three terminals: a gate, a drain, and a source. A transistor has a region (hereinafter also referred to as a channel formation region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) where a channel is formed. Current can flow between the source and drain through the channel formation region. Note that in this specification, etc., the channel formation region refers to the region where current primarily flows.

[0030] In addition, when transistors with different polarities are used or when the direction of current changes during circuit operation, the functions of the source and drain may be interchanged. Therefore, in this specification, etc., the source and drain may be interchanged.

[0031] Note that the channel length refers to, for example, the area where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on state) and the gate electrode overlap each other in a top view of the transistor, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. In addition, in a transistor, the channel length is not necessarily the same in all regions. In other words, the channel length of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel length is any value, maximum value, minimum value, or average value in the channel formation region.

[0032] The channel width refers to, for example, the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in an on-state) and the gate electrode overlap in a top view of the transistor, or the length of the channel formation region in a direction perpendicular to the channel length direction in the channel formation region. In addition, in a transistor, the channel width is not necessarily the same in all regions. In other words, the channel width of a transistor is sometimes not limited to a single value. Therefore, in this specification, the channel width is any value, maximum value, minimum value, or average value in the channel formation region.

[0033] In this specification, etc., depending on the structure of the transistor, the actual channel width in the region where the channel is formed (hereinafter also referred to as the "effective channel width") and the channel width shown in the top view of the transistor (hereinafter also referred to as the "apparent channel width") may differ. For example, when the gate electrode covers the side of the semiconductor, the effective channel width may be larger than the apparent channel width, and its influence cannot be ignored. For example, in a miniature transistor with a gate electrode covering the side of the semiconductor, the proportion of the channel formation region formed on the side of the semiconductor may increase. In this case, the effective channel width is larger than the apparent channel width.

[0034] In this case, it is sometimes difficult to estimate the effective channel width through actual measurement. For example, estimating the effective channel width from the design value requires assuming the semiconductor shape is known. Therefore, when the semiconductor shape is unknown, it is difficult to accurately measure the effective channel width.

[0035] In this specification, when simply referring to "channel width," this may refer to the apparent channel width. Alternatively, when simply referring to "channel width," this may refer to the effective channel width. Note that the values ​​of channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing cross-sectional TEM images, etc.

[0036] Note that the impurities of a semiconductor refer to, for example, elements other than the main components of the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity. When impurities are contained, for example, the defect state density of the semiconductor may increase or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. For example, there are hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen, etc. When the semiconductor is an oxide semiconductor, water sometimes also acts as an impurity. In addition, when the semiconductor is an oxide semiconductor, oxygen defects may sometimes be generated due to the entry of impurities. In addition, when the semiconductor is silicon, impurities that change the characteristics of the semiconductor include, for example, oxygen, Group 1 elements other than hydrogen, Group 2 elements, Group 13 elements, Group 15 elements, etc.

[0037] Note that in this specification and other documents, silicon oxynitride refers to a substance containing more oxygen than nitrogen. Also, silicon nitride oxide refers to a substance containing more nitrogen than oxygen.

[0038] In this specification and other documents, the term "insulator" may be referred to as an "insulating film" or "insulating layer." The term "conductor" may be referred to as a "conductive film" or "conductive layer." The term "semiconductor" may be referred to as a "semiconductor film" or "semiconductor layer."

[0039] In this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, a state where the angle is greater than -5° and less than 5° is also included. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, a state where the angle is greater than 85° and less than 95° is also included. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0040] Note that in this specification, a barrier film refers to a film having a function of suppressing the permeation of impurities such as water and hydrogen, and oxygen. When the barrier film has conductivity, it may be referred to as a conductive barrier film.

[0041] In this specification, metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (also referred to as OS). For example, when a metal oxide is used in a semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor can be referred to as a transistor containing an oxide or an oxide semiconductor.

[0042] Note that in this specification and other documents, normally off means that when no potential is applied to the gate or when a ground potential is applied to the gate, the current flowing through the transistor per channel width of 1 μm is 1×10 -20 Below A, at 85℃, it is 1×10 -18 A or less, or 1×10 -16 A or below.

[0043] (Implementation Method 1) An example of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described below.

[0044] <Structural Example 1 of Semiconductor Device> Figures 1A to 1C 1 and 2 are a top view and a cross-sectional view of a transistor 200 and its surroundings according to one embodiment of the present invention.

[0045] Figure 1A2 is a top view of a semiconductor device including a transistor 200. Figure 1B and Figure 1C is a cross-sectional view of the semiconductor device. Figure 1B It is along Figure 1A The cross-sectional view of the portion indicated by the dot-dash line A1-A2 is also a cross-sectional view along the channel length direction of the transistor 200. Figure 1C It is along Figure 1A The cross-sectional view of the portion indicated by the dot-dash line A3-A4 is also a cross-sectional view along the channel width direction of the transistor 200. Note that Figure 1A Some components are omitted in the top view for clarity.

[0046] in addition, Figure 2 : is a perspective view of a transistor 200 according to one embodiment of the present invention. Note that Figure 2 The three-dimensional diagram omits some components for the sake of clarity.

[0047] A semiconductor device according to one embodiment of the present invention includes a transistor 200, an insulator 214 serving as an interlayer film, an insulator 280, an insulator 274, and an insulator 281. The semiconductor device also includes a conductor 240 (conductor 240a and conductor 240b) electrically connected to the transistor 200 and serving as a plug. Furthermore, an insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surfaces of the conductor 240 serving as the plug.

[0048] In addition, an insulator 241 is provided in contact with the side walls of the openings of insulators 254, 280, 274, and 281, and a first conductor of conductor 240 is provided in contact with the side surfaces thereof, and a second conductor of conductor 240 is provided inside the first conductor. Here, the height of the top surface of conductor 240 and the height of the top surface of insulator 281 may be substantially the same. In addition, a structure in which the first conductor of conductor 240 and the second conductor of conductor 240 are stacked is shown in transistor 200, but the present invention is not limited to this. For example, conductor 240 may also have a single-layer structure or a stacked structure of three or more layers. In addition, when a structure has a stacked structure, an ordinal number is sometimes given according to the order of formation to distinguish them.

[0049] [Transistor 200] As shown in FIG1 , the transistor 200 includes an insulator 216 disposed on a substrate (not shown), a conductor 205 disposed in an embedded manner in the insulator 216, an insulator 222 disposed on the insulator 216 and the conductor 205, an insulator 224 disposed on the insulator 222, an oxide 230 (oxide 230a, oxide 230b, and oxide 230c) disposed on the insulator 224, an insulator 250 disposed on the oxide 230, and an insulator 250 disposed on the insulator. Conductor 260 (conductor 260a and conductor 260b) on 250, conductor 242a and conductor 242b in contact with a portion of the top surface of oxide 230b, and insulator 254 configured to be in contact with a portion of the top surface of insulator 222, the side surface of insulator 224, the side surface of oxide 230a, the side surface of oxide 230b, the side surface of conductor 242a, the top surface of conductor 242a, the side surface of conductor 242b, and the top surface of conductor 242b.

[0050] Conductor 260 serves as the gate electrode of transistor 200, while conductors 242a and 242b serve as source and drain electrodes. In transistor 200, conductor 260 serving as the gate electrode is formed in a self-aligned manner so as to fit within an opening formed in insulator 280 or the like. Forming conductor 260 in this manner allows conductor 260 to be reliably positioned in the region between conductors 242a and 242b without requiring alignment.

[0051] The conductor 260 preferably includes a conductor 260a and a conductor 260b provided on the conductor 260a. For example, the conductor 260a is preferably configured to surround the bottom and side surfaces of the conductor 260b. Figure 1B As shown, the top surface of conductor 260 is substantially aligned with the top surface of insulator 250 and the top surface of oxide 230c. Note that in transistor 200, conductor 260 has a two-layer stacked structure, but the present invention is not limited to this. For example, conductor 260 may have a single-layer structure or a stacked structure of three or more layers.

[0052] Insulators 222, 254, and 274 preferably have the function of inhibiting the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules). Furthermore, insulators 222, 254, and 274 preferably have the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). For example, the permeability of insulators 222, 254, and 274 to one or both of hydrogen and oxygen is preferably lower than that of insulator 224. The permeability of insulators 222, 254, and 274 to one or both of hydrogen and oxygen is preferably lower than that of insulator 250. The permeability of insulators 222, 254, and 274 to one or both of hydrogen and oxygen is preferably lower than that of insulator 280.

[0053] The oxide 230 preferably includes an oxide 230 a disposed on the insulator 224 , an oxide 230 b disposed on the oxide 230 a , and an oxide 230 c disposed on the oxide 230 b and having at least a portion in contact with a top surface of the oxide 230 b .

[0054] Note that in transistor 200, three layers of oxide 230a, oxide 230b, and oxide 230c are stacked in and around the region where the channel is formed (hereinafter also referred to as the channel formation region), but the present invention is not limited to this. For example, oxide 230b may be a single layer, a two-layer structure of oxide 230a and oxide 230b, a two-layer structure of oxide 230b and oxide 230c, or a stacked structure of four or more layers.

[0055] In the transistor 200 , a metal oxide used as a semiconductor (hereinafter sometimes referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxide 230 a , the oxide 230 b , and the oxide 230 c ) including the channel formation region.

[0056] Since the transistor 200 using an oxide semiconductor for the channel formation region has extremely low leakage current (off-state current) in the non-conducting state, a low-power semiconductor device can be provided. In addition, since the oxide semiconductor can be formed using a sputtering method or the like, it can be used to form the transistor 200 of a highly integrated semiconductor device.

[0057] For example, a metal oxide such as In-M-Zn oxide (where the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) is preferably used as the oxide 230. In particular, aluminum, gallium, yttrium, or tin can be used as the element M. Alternatively, In-Ga oxide, In-Zn oxide, or Ga-Zn oxide can be used as the oxide 230.

[0058] In addition, in a transistor using an oxide semiconductor, if impurities and oxygen defects are present in the channel formation region in the oxide semiconductor, the electrical characteristics are prone to change, sometimes reducing reliability. In addition, when the channel formation region in the oxide semiconductor contains oxygen defects, the transistor tends to have a normally-on characteristic. Therefore, it is preferred to reduce the oxygen defects in the channel formation region as much as possible. For example, oxygen defects can be filled by supplying oxygen to the oxide 230 through an insulator 250 or the like. Thus, a transistor can be provided in which electrical characteristic variations are suppressed, having stable electrical characteristics and improved reliability.

[0059] In addition, when the element contained in the conductor 242 (conductor 242a and conductor 242b) provided in contact with the oxide 230 and used as the source electrode or the drain electrode has the function of absorbing oxygen of the oxide 230, a low resistance region may be partially formed between the oxide 230 and the conductor 242 or near the surface of the oxide 230. In this case, in this low resistance region, impurities (hydrogen, nitrogen, metal elements, etc.) that enter the oxygen vacancy are used as donors, and the carrier density is increased. In addition, hydrogen that enters the oxygen vacancy is sometimes referred to as V O H.

[0060] in addition, Figure 3A Show Figure 1B FIG. 2 is an enlarged view of a portion of the transistor 200 shown in FIG. Figure 3A As shown, a conductor 242 is provided in contact with the oxide 230, and a region 243 (region 243a and region 243b) serving as a low-resistance region may be formed at and near the interface between the oxide 230 and the conductor 242. The oxide 230 includes a region 234 serving as a channel formation region for the transistor 200, and a region 231 (region 231a and region 231b) including at least a portion of the region 243 and serving as a source region or a drain region. Note that in the following drawings, even if the region 243 is not shown in an enlarged view, the same region 243 may be formed.

[0061] In addition, although an example is shown in which regions 243a and 243b are provided in a manner diffused in the depth direction near the conductor 242 of the oxide 230b, the present invention is not limited to this. Regions 243a and 243b may be formed appropriately according to the required electrical characteristics of the transistor. In the oxide 230, it is sometimes difficult to clearly observe the boundaries between the regions. The concentration of the element detected in each region is not limited to changing in stages for each region, but may also change gradually in each region (also called gradation).

[0062] In addition, if Figure 1BAs shown, insulator 254 preferably contacts the top surfaces of conductors 242a and 242b, the side surfaces of conductors 242a and 242b other than the opposing side surfaces, the side surfaces of oxides 230a and 230b, the side surfaces of insulator 224, and a portion of the top surface of insulator 222. With this structure, insulator 280 is separated from insulator 224, oxides 230a, and oxides 230b by insulator 254. This prevents impurities such as hydrogen in insulator 280 and the like from entering insulator 224, oxides 230a, and oxides 230b.

[0063] The insulator 274 is in contact with the top surface of each of the conductor 260, the insulator 250, and the oxide 230c. Figure 3A As shown, in the transistor 200 according to one embodiment of the present invention, the insulator 274 is in contact with the insulator 250. This structure can prevent impurities such as hydrogen in the insulator 281 and the like from entering the insulator 250. This can suppress negative effects on the electrical characteristics and reliability of the transistor.

[0064] In addition, if Figure 3A As shown, the bottom surface of conductor 260 in the region overlapping with region 234 may be lower than the top surface heights of conductors 242a and 242b, with reference to the bottom surface of insulator 224. For example, the difference between the bottom surface height of conductor 260 in the region overlapping with region 234 and the top surface heights of conductors 242a and 242b may be 0 nm to 30 nm or 0 nm to 15 nm.

[0065] in addition, Figure 3B Show Figure 1C FIG. 2 is an enlarged view of a portion of the transistor 200 shown in FIG. Figure 1C and Figure 3BAs shown, in the channel width direction of transistor 200, with the bottom surface of insulator 222 as a reference, the bottom surface height of conductor 260 in the region where oxide 260 and oxide 230b do not overlap is preferably lower than the bottom surface height of oxide 230b. By adopting a structure in which conductor 260, used as a gate electrode, covers the side and top surfaces of oxide 230b in the channel formation region via oxide 230c and insulator 250, this structure makes it easier for the electric field of conductor 260 to act on the entire region 234 of oxide 230b. As a result, the on-state current of transistor 200 can be increased, thereby improving frequency characteristics. The difference between the bottom surface height of conductor 260 in the region where oxide 230a and oxide 230b do not overlap with conductor 260 and the bottom surface height of oxide 230b is denoted as T2, and T2 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0066] In addition, if Figure 3B As shown, in the channel width direction of transistor 200, preferably, at least a portion of oxide 230c in a region that does not overlap with oxide 230b, oxide 230a, and insulator 224 is in contact with insulator 222. This structure prevents oxygen in oxide 230c from diffusing through insulator 224 to the outside of transistor 200. Alternatively, oxygen in oxides 230b and 230a from diffusing through insulator 224 to the outside of transistor 200 can be prevented. Alternatively, by reducing the area of ​​insulator 224, the amount of oxygen entering insulator 224 is reduced, thereby suppressing a decrease in the amount of oxygen supplied to oxide 230. This allows oxygen in oxide 230c to be efficiently supplied to oxides 230b and 230a, thereby suppressing a decrease in the resistance of oxide 230 in region 234. This improves reliability while suppressing variations in transistor electrical characteristics and achieving stable electrical characteristics.

[0067] Alternatively, by adopting the above structure, it is possible to suppress the incorporation of impurities such as hydrogen in the insulator 224 into the oxide 230. In other words, it is possible to suppress the reduction in resistance of the oxide 230. This can suppress fluctuations in the electrical characteristics of the transistor, achieve stable electrical characteristics, and improve reliability. Alternatively, this structure can be formed by removing the insulator 224 from regions that do not overlap with the oxides 230b and 230a.

[0068] In addition, by removing the insulator 224 in the region that does not overlap with the oxide 230b and the oxide 230a, the Figure 1CAs shown, in the channel width direction of transistor 200, the bottom surface of conductor 260 in the region where oxide 230a and oxide 230b do not overlap with conductor 260 can be easily made lower than the bottom surface height of oxide 230b, with reference to the bottom surface of insulator 222. This can increase the on-state current of transistor 200 and improve frequency characteristics.

[0069] By adopting the above structure, a semiconductor device including a transistor with a large on-state current can be provided. Furthermore, a semiconductor device including a transistor with high frequency characteristics can be provided. Furthermore, a semiconductor device with improved reliability can be provided while suppressing fluctuations in electrical characteristics to achieve stable electrical characteristics. Furthermore, a semiconductor device including a transistor with a low off-state current can be provided.

[0070] A detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention is shown below.

[0071] The conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. In addition, the conductor 205 is preferably provided so as to be embedded in the insulator 214 and the insulator 216. Here, it is preferred that the top surface of the conductor 205 has good flatness. For example, the average surface roughness (Ra) of the top surface of the conductor 205 can be 1 nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. As a result, the insulator 224 formed on the conductor 205 can have good flatness, thereby improving the crystallinity of the oxides 230a, 230b, and 230c.

[0072] Here, the conductor 260 is sometimes used as a first gate (also called a top gate) electrode. In addition, the conductor 205 is sometimes used as a second gate electrode. In this case, by independently changing the potential supplied to the conductor 205 without interlocking it with the potential supplied to the conductor 260, the threshold voltage (Vth) of the transistor 200 can be controlled. In particular, by supplying a negative potential to the conductor 205, the Vth of the transistor 200 can be made larger and the off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential supplied to the conductor 260 is 0V can be reduced compared to when no negative potential is applied to the conductor 205.

[0073] In addition, if Figure 1A As shown in FIG. 1 , the conductor 205 is preferably larger than the channel formation region in the oxide 230. In particular, Figure 1C As shown, conductor 205 preferably extends to a region outside the end of oxide 230 intersecting the channel width direction. In other words, conductor 205 and conductor 260 preferably overlap with an insulator outside the side surface of oxide 230 in the channel width direction.

[0074] With this structure, the channel formation region of the oxide 230 can be electrically surrounded by the electric field of the conductor 260 used as the first gate electrode and the electric field of the conductor 205 used as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gate electrodes is referred to as a surrounded channel (S-channel) structure.

[0075] In addition, if Figure 1C As shown, the conductor 205 is extended to serve as wiring. However, the present invention is not limited to this, and a conductor serving as wiring may be provided under the conductor 205. Furthermore, a conductor 205 need not necessarily be provided for each transistor. For example, the conductor 205 may be shared by multiple transistors.

[0076] Furthermore, a conductive material mainly composed of tungsten, copper, or aluminum is preferably used as the conductor 205. Although the conductor 205 is shown as a single layer in the drawings, the conductor 205 may also have a stacked structure, for example, a stacked structure of titanium, titanium nitride, and the above conductive materials.

[0077] Alternatively, a conductor that has the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (such as those impurities are not easily permeable) may be used under the conductor 205. Furthermore, a conductor that has the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (such as those oxygen atoms and oxygen molecules) is preferably used (such as those oxygen atoms and oxygen molecules). In this specification, "the function of inhibiting the diffusion of impurities or oxygen" refers to the function of inhibiting the diffusion of any one or all of the above impurities and oxygen.

[0078] Furthermore, when a conductor having the function of suppressing the diffusion of oxygen is used under the conductor 205, a decrease in conductivity due to oxidation of the conductor 205 can be suppressed. As conductors having the function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, or ruthenium oxide are preferably used. Therefore, as the conductor used under the conductor 205, a single layer or a stack of these conductive materials can be used.

[0079] The insulator 214 is preferably used as a blocking insulating film that inhibits the diffusion of impurities such as water and hydrogen from the substrate side into the transistor 200. Therefore, an insulating material that inhibits the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N2O, NO, NO2, etc.), and copper atoms (prevents these impurities from penetrating) is preferably used as the insulator 214. Furthermore, an insulating material that inhibits the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) is preferably used (prevents these oxygen atoms and molecules from penetrating).

[0080] For example, aluminum oxide, silicon nitride, or the like is preferably used as the insulator 214. This can suppress diffusion of impurities such as water and hydrogen from the substrate side closer to the insulator 214 toward the transistor 200. Furthermore, diffusion of oxygen contained in the insulator 224 or the like toward the substrate side closer to the insulator 214 can be suppressed.

[0081] Furthermore, the dielectric constants of insulators 216, 280, and 281 used as interlayer films are preferably lower than that of insulator 214. By using a material with a low dielectric constant as the interlayer film, parasitic capacitance generated between wirings can be reduced. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, or silicon oxide having pores can be suitably used as insulators 216, 280, and 281.

[0082] Alternatively, insulator 216 may have a laminated structure. For example, a structure may be employed in which the same insulator as insulator 214 is provided at least in the portion of insulator 216 that contacts the side surfaces of conductor 205. This structure can suppress oxidation of conductor 205 by oxygen contained in insulator 216. Alternatively, absorption of oxygen in insulator 216 by conductor 205 can be suppressed.

[0083] Insulator 222 and insulator 224 serve as gate insulators.

[0084] Here, in the insulator 224 in contact with the oxide 230, oxygen is preferably removed by heating. In this specification, oxygen removed by heating is sometimes referred to as excess oxygen. For example, silicon oxide, silicon oxynitride, or the like can be appropriately used as the insulator 224. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced, thereby improving the reliability of the transistor 200.

[0085] Specifically, an oxide material from which a portion of oxygen is released by heating is preferably used as the insulator 224. An oxide film from which oxygen is released by heating means that the amount of oxygen released in terms of oxygen atoms in TDS (Thermal Desorption Spectroscopy) analysis is 1.0×10 18 atoms / cm 3 above, preferably 1.0×10 19 atoms / cm 3 More than 2.0×10 19 atoms / cm 3 Above, or 3.0×10 20 atoms / cm 3 Furthermore, the surface temperature of the film during the TDS analysis is preferably within the range of 100°C to 700°C, or 100°C to 400°C.

[0086] The insulator 222 is preferably used as a blocking insulating film to suppress the diffusion of impurities such as water and hydrogen from the substrate side into the transistor 200. For example, the hydrogen permeability of the insulator 222 is preferably lower than that of the insulator 224. By surrounding the insulator 224, the oxide 230, and the like with the insulator 222 and the insulator 254, the diffusion of impurities such as water and hydrogen into the insulator 224 and the oxide 230 from the outside can be suppressed.

[0087] Furthermore, the insulator 222 preferably has a function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (ie, it is difficult for such oxygen to permeate). For example, the oxygen permeability of the insulator 222 is preferably lower than that of the insulator 224. Providing the insulator 222 with the function of inhibiting the diffusion of oxygen or impurities is preferred because it can reduce the diffusion of oxygen contained in the oxide 230 to the substrate side. Furthermore, it can suppress the reaction of the conductor 205 with oxygen contained in the insulator 224 and the oxide 230.

[0088] The insulator 222 preferably uses an insulator containing an oxide of one or both of aluminum and hafnium as an insulating material. As an insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. When such a material is used to form the insulator 222, the insulator 222 is used as a layer to suppress the release of oxygen from the oxide 230 or the diffusion of impurities such as hydrogen from the surrounding part of the transistor 200 to the oxide 230. In addition, hafnium oxide is particularly preferably used as the insulator 222 among the above materials. For example, when the insulator 222 is used as a gate insulating film, by using hafnium oxide as the insulator 222, the interface energy level density can sometimes be reduced more than when aluminum oxide is used.

[0089] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the insulator. Furthermore, the insulator may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked on the insulator.

[0090] Furthermore, as the insulator 222, an insulator comprising a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba, Sr)TiO3 (BST) may be used in a single layer or a stacked layer. As transistors are miniaturized and highly integrated, the thinning of the gate insulator may cause problems such as leakage current. By using a high-k material as the insulator used as the gate insulator, the gate potential during transistor operation can be reduced while maintaining the physical thickness.

[0091] In addition, if Figure 1C As shown in FIG. 1 , the film thickness of the region where the insulator 222 does not overlap with the oxide 230 b may be thinner than the thickness of the region other than the region. In the insulator 222, the film thickness of the region that does not overlap with the oxide 230 b is preferably thick enough to serve as an etching stopper when forming an opening provided in the insulator 280 or the like, or is thick enough not to expose the surfaces of the insulator 216 or the conductor 205.

[0092] Furthermore, insulator 222 and insulator 224 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to being made of the same material; a stacked structure made of different materials may also be used. For example, an insulator similar to insulator 224 may be provided below insulator 222.

[0093] Oxide 230 includes oxide 230a, oxide 230b on oxide 230a, and oxide 230c on oxide 230b. When oxide 230a is provided below oxide 230b, diffusion of impurities from structures formed below oxide 230a to oxide 230b can be suppressed. When oxide 230c is provided above oxide 230b, diffusion of impurities from structures formed above oxide 230c to oxide 230b can be suppressed.

[0094] In addition, oxide 230 preferably has a stacked structure of oxides having different chemical compositions. Specifically, in the metal oxide used for oxide 230a, the atomic ratio of element M among the constituent elements is preferably greater than the atomic ratio of element M among the constituent elements in the metal oxide used for oxide 230b. In addition, the atomic ratio of element M to In in the metal oxide used for oxide 230a is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 230b. In addition, the atomic ratio of In to element M in the metal oxide used for oxide 230b is preferably greater than the atomic ratio of In to element M in the metal oxide used for oxide 230a. In addition, the metal oxide used for oxide 230c can use the metal oxide that can be used for oxide 230a or oxide 230b.

[0095] Furthermore, oxide 230b and oxide 230c are preferably crystalline. For example, CAAC-OS (c-axis aligned crystalline oxide semiconductor) is preferably used. Crystalline oxides such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (such as oxygen vacancies). Therefore, oxygen extraction from oxide 230b by the source or drain electrode can be suppressed. Therefore, even when heat treatment is performed, oxygen extraction from oxide 230b can be reduced, and transistor 200 is therefore stable against the high temperatures (so-called thermal budget) during the manufacturing process.

[0096] It is preferred that the conduction band bottoms of oxides 230a and 230c be closer to the vacuum level than the conduction band bottom of oxide 230b. In other words, the electron affinity of oxides 230a and 230c is preferably lower than that of oxide 230b. In this case, oxide 230c preferably uses a metal oxide that can be used for oxide 230a. Specifically, in the metal oxide used for oxide 230c, the atomic number ratio of element M in the constituent elements is preferably greater than the atomic number ratio of element M in the constituent elements of the metal oxide used for oxide 230b. In addition, in the metal oxide used for oxide 230c, the atomic number ratio of element M to In is preferably greater than the atomic number ratio of element M to In in the metal oxide used for oxide 230b. In addition, in the metal oxide used for oxide 230b, the atomic number ratio of In to element M is preferably greater than the atomic number ratio of In to element M in the metal oxide used for oxide 230c.

[0097] Furthermore, when the oxide 230c has a stacked structure including the oxide 230c1 and the oxide 230c2, the conduction band bottoms of the oxides 230a and 230c2 are preferably closer to the vacuum level than the conduction band bottoms of the oxides 230b and 230c1. In other words, the electron affinities of the oxides 230a and 230c2 are preferably lower than those of the oxides 230b and 230c1. In this case, the metal oxide that can be used for the oxide 230a is preferably used for the oxide 230c2, and the metal oxide that can be used for the oxide 230b is preferably used for the oxide 230c1.

[0098] Here, the conduction band bottom changes smoothly at the junction of oxide 230a, oxide 230b, and oxide 230c. In other words, the above situation can also be expressed as the conduction band bottom of the junction of oxide 230a, oxide 230b, and oxide 230c changing continuously or being continuously joined. To this end, it is preferable to reduce the defect state density of the mixed layer formed at the interface between oxide 230a and oxide 230b, and at the interface between oxide 230b and oxide 230c.

[0099] Specifically, by making oxide 230a and oxide 230b, and oxide 230b and oxide 230c contain a common element (as a main component) in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, when oxide 230b is an In-Ga-Zn oxide, oxide 230a and oxide 230c can use In-Ga-Zn oxide, Ga-Zn oxide, and gallium oxide, etc. In addition, when oxide 230c uses a stacked structure of oxide 230c1 and oxide 230c2, for example, a stacked structure of In-Ga-Zn oxide and Ga-Zn oxide on the In-Ga-Zn oxide can be used, or a stacked structure of In-Ga-Zn oxide and gallium oxide on the In-Ga-Zn oxide can be used. In other words, a stacked structure of In-Ga-Zn oxide and an oxide that does not contain In can also be used as oxide 230c.

[0100] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:Ga:Zn = 1:3:4 or In:Ga:Zn = 1:1:0.5. Furthermore, the oxide 230b may be a metal oxide having an atomic ratio of In:Ga:Zn = 4:2:3 or In:Ga:Zn = 3:1:2. Furthermore, the oxide 230c may be a metal oxide having an atomic ratio of In:Ga:Zn = 1:3:4, In:Ga:Zn = 4:2:3, Ga:Zn = 2:1, or Ga:Zn = 2:5. In addition, as specific examples of the case where the oxide 230c has a stacked structure, there can be cited a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and In:Ga:Zn=1:3:4 [atomic ratio], a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:1 [atomic ratio], a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and Ga:Zn=2:5 [atomic ratio], a stacked structure of In:Ga:Zn=4:2:3 [atomic ratio] and gallium oxide, etc.

[0101] At this time, the main path for carriers is oxide 230b. Alternatively, when oxide 230c has a stacked structure including oxide 230c1 and oxide 230c2, sometimes not only oxide 230b but also oxide 230c1 may become the main path for carriers. By making oxide 230a and oxide 230c have the above structure, the defect state density at the interface between oxide 230a and oxide 230b and the interface between oxide 230b and oxide 230c can be reduced. Therefore, the effect of interface scattering on carrier conduction is reduced, so that transistor 200 can obtain high on-state current and high frequency characteristics. In addition, when oxide 230c has a stacked structure, it is expected to reduce the defect state density at the interface between oxide 230b and oxide 230c and suppress the diffusion of constituent elements contained in oxide 230c to the insulator 250 side. More specifically, when oxide 230c has a stacked structure, because the oxide that does not contain In is located above the stacked structure, the diffusion of In to the insulator 250 side can be suppressed. Since the insulator 250 is used as a gate insulator, the characteristics of the transistor may be deteriorated if In enters the insulator 250. Thus, by providing the oxide 230c with a stacked structure, a highly reliable semiconductor device can be provided.

[0102] A metal oxide used as an oxide semiconductor is preferably used as the oxide 230. For example, the metal oxide used in the region 234 is preferably a metal oxide having a band gap of 2 eV or greater, preferably 2.5 eV or greater. By using a metal oxide with a wide band gap, the off-state current of the transistor can be reduced. By using such a transistor, a low-power semiconductor device can be provided.

[0103] Conductors 242 (conductors 242a and 242b) serving as a source electrode and a drain electrode are provided on the oxide 230b. The thickness of the conductors 242 is, for example, 1 nm to 50 nm, preferably 2 nm to 25 nm.

[0104] As the conductor 242, preferably used are metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, alloys containing these metal elements, or alloys combining these metal elements. For example, preferably used are tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even when absorbing oxygen, and therefore are preferred.

[0105] The insulator 254 is preferably used as a blocking insulating film to suppress the diffusion of impurities such as water and hydrogen from the insulator 280 side to the transistor 200, similar to the insulator 214. For example, the hydrogen permeability of the insulator 254 is preferably lower than that of the insulator 224. Figure 1B and Figure 1C As shown, the insulator 254 is preferably in contact with the top and side surfaces of the conductor 242a, the top and side surfaces of the conductor 242b, the side surfaces of the oxide 230a and the oxide 230b, and the top surface of the insulator 224. With this structure, the insulator 254 separates the insulator 280 from the insulator 224 and the oxide 230. As a result, hydrogen contained in the insulator 280 can be suppressed from diffusing from the top or side surfaces of the conductors 242a, the conductor 242b, the oxide 230a, the oxide 230b, and the insulator 224 to the oxide 230, thereby enabling the transistor 200 to have good electrical characteristics and reliability.

[0106] Furthermore, the insulator 254 also has the function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (preventing oxygen from penetrating easily). For example, the oxygen permeability of the insulator 254 is preferably lower than that of the insulator 280 or the insulator 224.

[0107] The insulator 254 is preferably formed by a sputtering method. By forming the insulator 254 using a sputtering method in an atmosphere containing oxygen, oxygen can be added to the vicinity of the region where the insulator 224 contacts the insulator 254. As a result, oxygen can be supplied from this region through the insulator 224 to the oxide 230. Here, by giving the insulator 254 the function of suppressing oxygen diffusion to the upper side, oxygen can be prevented from diffusing from the oxide 230 to the insulator 280. In addition, by giving the insulator 222 the function of suppressing oxygen diffusion to the lower side, oxygen can be prevented from diffusing from the oxide 230 to the substrate side. In this way, oxygen is supplied to the channel formation region of the oxide 230. As a result, the oxygen vacancies in the oxide 230 can be reduced and the normally-on state of the transistor can be suppressed.

[0108] Insulator 254 can be formed, for example, from an oxide of one or more of aluminum and hafnium. Insulators containing oxides of one or both of aluminum and hafnium are preferably aluminum oxide, hafnium oxide, or an oxide containing both aluminum and hafnium (hafnium aluminate). In this case, insulator 254 is preferably formed using atomic layer deposition (ALD). ALD provides excellent coverage, preventing disconnection caused by unevenness in insulator 254.

[0109] In this manner, by covering the insulator 224 and the oxide 230 with the insulator 254 having a hydrogen barrier property, the insulator 280 is separated from the insulator 224 and the oxide 230. This can suppress the infiltration of impurities such as hydrogen from outside the transistor 200, thereby enabling the transistor 200 to have good electrical characteristics and reliability.

[0110] As the insulator 254, for example, an insulator containing aluminum nitride can be used. As the insulator 254, it is preferred to use a nitride insulator whose composition formula satisfies AlNx (x is a real number greater than 0 and less than 2, and x is preferably a real number greater than 0.5 and less than 1.5). Therefore, a film with high insulation and high thermal conductivity can be formed, thereby improving the heat dissipation of heat generated when driving the transistor 200. In addition, as the insulator 254, aluminum titanium nitride, titanium nitride, etc. can also be used. In this case, by using a sputtering method, a film can be formed without using a highly oxidizing gas such as oxygen or ozone as a deposition gas, so this is preferred. In addition, silicon nitride or silicon oxynitride, etc. can also be used.

[0111] In addition, the insulator 254 may have a multilayer structure with more than two layers. For example, as the insulator 254, a first layer may be formed using a sputtering method in an atmosphere containing oxygen, and then a second layer may be formed using an ALD method to form a two-layer structure. Because the ALD method is a film-forming method with good coverage, disconnection caused by the unevenness of the first layer can be prevented. In the case where the insulator 254 has a multilayer structure with more than two layers, a multilayer structure composed of different materials may also be used. For example, a stacked structure of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride and an insulator having a function of inhibiting the permeation of impurities such as hydrogen and oxygen may be used. As an insulator having a function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be used.

[0112] Insulator 250 serves as a gate insulator. Insulator 250 is preferably disposed in contact with at least a portion of oxide 230c. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or silicon oxide with pores can be used as insulator 250. Silicon oxide and silicon oxynitride are particularly preferred due to their thermal stability.

[0113] Similar to insulator 224, insulator 250 is preferably formed using an insulator that releases oxygen upon heating. Providing an insulator that releases oxygen upon heating as insulator 250 in contact with at least a portion of oxide 230c allows efficient supply of oxygen to region 234 of oxide 230b. Similar to insulator 224, the concentration of impurities such as water and hydrogen in insulator 250 is preferably low. The thickness of insulator 250 is preferably not less than 1 nm and not more than 20 nm.

[0114] Alternatively, a metal oxide may be provided between insulator 250 and conductor 260. This metal oxide preferably inhibits the diffusion of oxygen from insulator 250 to conductor 260. Providing a metal oxide that inhibits oxygen diffusion suppresses oxygen diffusion from insulator 250 to conductor 260. In other words, a decrease in the amount of oxygen supplied to oxide 230 can be suppressed. Furthermore, oxidation of conductor 260 due to oxygen in insulator 250 can be suppressed.

[0115] In addition, the above-mentioned metal oxide is sometimes used as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 250, it is preferable to use a metal oxide that is a high-k material with a high relative dielectric constant as the above-mentioned metal oxide. By making the gate insulator have a stacked structure of the insulator 250 and the above-mentioned metal oxide, a stacked structure with thermal stability and a high relative dielectric constant can be formed. Therefore, the gate potential applied when the transistor is operating can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0116] Alternatively, the metal oxide may be used as part of the first gate. For example, an oxide semiconductor that can be used as the oxide 230 may be used as the metal oxide. In this case, by forming the conductor 260 by sputtering, the resistance of the metal oxide can be reduced, thereby converting it into a conductor. The conductor may be referred to as an OC (Oxide Conductor) electrode.

[0117] By providing the metal oxide, the on-state current of the transistor 200 can be increased without reducing the influence of the electric field from the conductor 260. In addition, by maintaining the distance between the conductor 260 and the oxide 230 by utilizing the physical thickness of the insulator 250 and the metal oxide, leakage current between the conductor 260 and the oxide 230 can be suppressed. In addition, by providing a stacked structure of the insulator 250 and the metal oxide, the physical distance between the conductor 260 and the oxide 230 and the intensity of the electric field applied from the conductor 260 to the oxide 230 can be easily adjusted.

[0118] Specifically, a metal oxide containing one or more metals selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium can be used. In particular, aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate), which are insulators containing one or both of aluminum and hafnium oxides, are preferably used. Furthermore, an oxide semiconductor that can be used for the oxide 230 can be used as the metal oxide by reducing its resistance.

[0119] Although FIG. 1 shows an example in which the conductor 260 has a double-layer structure, it may also have a single-layer structure or a stacked-layer structure of three or more layers.

[0120] As the conductor 260a, a conductive material having the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms is preferably used. In addition, a conductive material having the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) is preferably used.

[0121] Furthermore, when the conductor 260a has the function of suppressing the diffusion of oxygen, it is possible to suppress the decrease in conductivity caused by oxidation of the conductor 260b by oxygen contained in the insulator 250. As a conductive material having the function of suppressing the diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0122] Since conductor 260 also functions as wiring, it is preferable to use a highly conductive material. For example, conductor 260b can be made of a conductive material primarily composed of tungsten, copper, or aluminum. Alternatively, conductor 260b can have a laminated structure, for example, a laminated structure of titanium, titanium nitride, and one of the above conductive materials.

[0123] Insulator 280 is preferably provided over insulator 222, insulator 224, oxide 230, and conductor 242 via insulator 254. For example, insulator 280 preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, or silicon oxide with pores. Silicon oxide and silicon oxynitride are particularly preferred due to their thermal stability. Silicon oxide, silicon oxynitride, or silicon oxide with pores is particularly preferred because it easily forms a region containing oxygen that is released by heating.

[0124] Furthermore, it is preferable to reduce the concentration of impurities such as water and hydrogen in the insulator 280. Furthermore, the top surface of the insulator 280 may be planarized.

[0125] Like the insulator 214, the insulator 274 is preferably used as a barrier insulating film to suppress diffusion of impurities such as water and hydrogen from above into the insulator 280. For example, the insulator 274 can be any insulator that can be used for the insulator 214 or the insulator 254.

[0126] In addition, an insulator 281 serving as an interlayer film is preferably provided on the insulator 274. As with the insulator 224 and the like, the concentration of impurities such as water and hydrogen in the insulator 281 is preferably reduced.

[0127] Furthermore, conductors 240a and 240b are disposed in openings formed in insulators 281, 274, 280, and 254. Conductors 240a and 240b are disposed so as to sandwich conductor 260. Furthermore, the top surfaces of conductors 240a and 240b may be flush with the top surface of insulator 281.

[0128] Insulator 241a is provided in contact with the side walls of the openings of insulators 281, 274, 280, and 254, and a first conductor of conductor 240a is formed in contact with the side surfaces thereof. Conductor 242a is located at least partially at the bottom of the openings, with conductors 240a and 242a in contact. Similarly, insulator 241b is provided in contact with the side walls of the openings of insulators 281, 274, 280, and 254, and a first conductor of conductor 240b is formed in contact with the side surfaces thereof. Conductor 242b is located at least partially at the bottom of the openings, with conductors 240b and 242b in contact.

[0129] The conductors 240a and 240b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component.

[0130] When a stacked structure is employed as conductor 240, a conductive material that inhibits the permeation of impurities such as water and hydrogen is preferably used as the conductor in contact with oxide 230a, oxide 230b, conductor 242, insulator 254, insulator 280, insulator 274, and insulator 281. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, and the like are preferably used. A conductive material that inhibits the permeation of impurities such as water and hydrogen can be used in a single layer or in a stacked layer. By using such a conductive material, oxygen added to insulator 280 can be prevented from being absorbed into conductors 240a and 240b. Furthermore, impurities such as water and hydrogen contained in the layer above insulator 281 can be prevented from diffusing through conductors 240a and 240b into oxide 230.

[0131] Insulators 241a and 241b can be any insulators that can be used for insulator 254, for example. Since insulators 241a and 241b are provided in contact with insulator 254, impurities such as water and hydrogen contained in insulator 280 and the like can be prevented from diffusing through conductors 240a and 240b into oxide 230. Furthermore, oxygen contained in insulator 280 can be prevented from being absorbed by conductors 240a and 240b. Insulators 241a and 241b can be formed using ALD or chemical vapor deposition (CVD).

[0132] Although not shown, a conductor serving as wiring may be arranged in contact with the top surfaces of conductor 240a and conductor 240b. The conductor serving as wiring is preferably a conductive material primarily composed of tungsten, copper, or aluminum. Furthermore, the conductor may have a laminated structure, for example, a laminated structure of titanium, titanium nitride, and the aforementioned conductive materials. Furthermore, the conductor may be embedded in an opening in the insulator.

[0133] In addition, although not shown in the figure, it is preferable to provide a conductive material having a resistivity of 1.0×10 13 Ωcm or more and 1.0×10 15 Ωcm or less, preferably 5.0×10 13 Ωcm or more and 5.0×10 14 An insulator with a resistivity of Ωcm or less is provided on the above-mentioned conductor. Providing an insulator with such a resistivity on the above-mentioned conductor not only maintains the insulating properties but also disperses the charge accumulated in the transistor 200, wiring (e.g., the above-mentioned conductor), etc., thereby suppressing characteristic defects or electrostatic damage of the transistor or an electronic device having the transistor caused by the charge, which is preferable.

[0134] <Materials Constituting Semiconductor Devices> Hereinafter, constituent materials that can be used for semiconductor devices will be described.

[0135] Substrate As the substrate for forming the transistor 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Furthermore, examples of semiconductor substrates include semiconductor substrates composed of silicon or germanium, or compound semiconductor substrates composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, examples include semiconductor substrates having an insulating region within the above-mentioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, examples include substrates containing metal nitrides and substrates containing metal oxides. Furthermore, examples include insulating substrates provided with conductors or semiconductors, semiconductor substrates provided with conductors or insulators, and conductive substrates provided with semiconductors or insulators. Alternatively, substrates having elements provided on these substrates may be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light-emitting element, and a memory element.

[0136] Insulator Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0137] For example, as transistors become increasingly miniaturized and highly integrated, problems such as leakage current may arise due to thinner gate insulators. Using a high-k material as the gate insulator allows for lower transistor operating voltages while maintaining the physical thickness. On the other hand, using a material with a low relative dielectric constant as the interlayer insulator reduces parasitic capacitance between wiring lines. Therefore, it is preferable to select the insulator material based on its function.

[0138] In addition, as insulators with a relatively high dielectric constant, gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium can be cited.

[0139] Insulators with a relatively low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, and silicon oxide or resin having pores.

[0140] Furthermore, by surrounding a transistor using an oxide semiconductor with an insulator (such as insulator 214, insulator 222, insulator 254, and insulator 274) that has the function of inhibiting the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator that has the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or a stacked layer. Specifically, as an insulator that has the function of inhibiting the permeation of impurities such as hydrogen and oxygen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide, or a metal nitride such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxynitride, or silicon nitride can be used.

[0141] Furthermore, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that is desorbed by heating. For example, by employing a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is desorbed by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be filled.

[0142] Conductors As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy containing the above metal elements as a component, or an alloy combining the above metal elements. For example, it is preferred to use tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, so they are preferred. Alternatively, a semiconductor with high conductivity, such as polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0143] Alternatively, multiple conductive layers formed from the above-mentioned materials may be stacked. For example, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing oxygen. Alternatively, a laminated structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing nitrogen. Alternatively, a laminated structure may be formed by combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0144] Furthermore, when an oxide is used in the channel formation region of a transistor, a laminated structure combining a material containing the aforementioned metal element and a conductive material containing oxygen is preferably employed as the conductor used as the gate electrode. In this case, the conductive material containing oxygen is preferably positioned on the channel formation region side. By positioning the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is more easily supplied to the channel formation region.

[0145] In particular, as the conductor used as the gate electrode, it is preferable to use a conductive material containing a metal element contained in the metal oxide forming the channel and oxygen. In addition, a conductive material containing the above-mentioned metal elements and nitrogen can also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, can also be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide forming the channel can sometimes be captured. Alternatively, hydrogen entering from an external insulator can sometimes be captured.

[0146] Metal Oxides A metal oxide used as an oxide semiconductor is preferably used as the oxide 230. Hereinafter, metal oxides that can be used for the oxide 230 according to the present invention will be described.

[0147] The metal oxide preferably contains at least indium or zinc. Indium and zinc are particularly preferred. Furthermore, it preferably contains aluminum, gallium, yttrium, or tin. Alternatively, it may contain one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium.

[0148] Here, consider the case where the metal oxide is an In-M-Zn oxide containing indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, or tin, for example. Other elements that can be used as element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that a combination of multiple elements may also be used as element M.

[0149] Note that in this specification and other documents, a metal oxide containing nitrogen may also be referred to as a metal oxide. Alternatively, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

[0150] [Structure of Metal Oxides] Oxide semiconductors (metal oxides) are classified into single-crystalline oxide semiconductors and non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous oxide semiconductors (amorphous-like oxide semiconductors), and amorphous oxide semiconductors.

[0151] CAAC-OS has c-axis orientation, with multiple nanocrystals linked in the ab-plane direction, resulting in a distorted crystal structure. Note that distortion refers to the difference in lattice alignment between regions where multiple nanocrystals are linked and other regions where the lattice alignment is consistent.

[0152] Although nanocrystals are basically hexagonal, they are not limited to regular hexagons, and there are cases where they are not regular hexagons. In addition, in the distortion, there are sometimes lattice arrangements such as pentagons and heptagons. In addition, in CAAC-OS, it is difficult to observe clear grain boundaries (also called grain boundaries) even near the distortion. That is, it can be seen that the formation of grain boundaries can be suppressed due to the distortion of the lattice arrangement. This is because CAAC-OS can accommodate distortion due to the low density of oxygen atoms arranged in the ab plane direction or the change in the bond distance between atoms due to the substitution of metal elements.

[0153] In addition, CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. In addition, indium and element M are mutually replaceable. When indium replaces element M in the (M, Zn) layer, the layer can also be expressed as an (In, M, Zn) layer. In addition, when indium in the In layer is replaced by element M, the layer can also be expressed as an (In, M) layer.

[0154] CAAC-OS is a metal oxide with high crystallinity. On the other hand, it is not easy to observe clear grain boundaries in CAAC-OS, so it can be said that a decrease in electron mobility due to grain boundaries is not likely to occur. In addition, the crystallinity of metal oxides is sometimes reduced due to the entry of impurities or the generation of defects, so it can be said that CAAC-OS is a metal oxide with few impurities or defects (oxygen defects (also called Vo: oxygen vacancy)). Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Therefore, the metal oxide containing CAAC-OS has high heat resistance and high reliability.

[0155] In nc-OS, the atomic arrangement in tiny regions (e.g., regions between 1 nm and 10 nm, and particularly between 1 nm and 3 nm) is periodic. Furthermore, in nc-OS, no regularity in crystal orientation is observed between different nanocrystals. Therefore, no orientation is observed in the entire film. Consequently, nc-OS can sometimes be indistinguishable from a-like OS or amorphous oxide semiconductors in certain analytical methods.

[0156] In addition, indium-gallium-zinc oxide (hereinafter, IGZO), a metal oxide containing indium, gallium, and zinc, may have a stable structure when it is the above-mentioned nanocrystal. In particular, since IGZO tends to be difficult to grow in the air, it is likely that the structure of IGZO is stable when it is a small crystal (for example, the above-mentioned nanocrystal) compared to when it is a large crystal (here, a crystal of several mm or a crystal of several cm).

[0157] a-like OS is a metal oxide with a structure intermediate between nc-OS and amorphous oxide semiconductors. It contains voids or low-density regions. In other words, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0158] Oxide semiconductors (metal oxides) have various structures and properties. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a nc-OS, and a CAAC-OS.

[0159] [Impurities] Here, the influence of various impurities in the metal oxide will be described.

[0160] When the metal oxide contains an alkali metal or an alkaline earth metal, a defect state is sometimes formed to form carriers. Therefore, a transistor using a metal oxide containing an alkali metal or an alkaline earth metal as a channel formation region tends to have a normally-on characteristic. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of the alkali metal or alkaline earth metal in the metal oxide obtained by secondary ion mass spectrometry (SIMS) (the concentration measured by SIMS) is 1×10 18 atoms / cm 3 Below, preferably 2×10 16 atoms / cm 3 the following.

[0161] Hydrogen contained in metal oxides reacts with oxygen bonded to metal atoms to produce water, sometimes forming oxygen vacancies. When hydrogen enters these oxygen vacancies, electrons, which serve as carriers, are sometimes generated. Furthermore, electrons, which serve as carriers, are sometimes generated by some of the hydrogen bonding to oxygen bonded to metal atoms. Therefore, transistors using metal oxides containing hydrogen tend to have normally-on characteristics.

[0162] Therefore, it is preferable to reduce the amount of hydrogen in the metal oxide as much as possible. Specifically, the hydrogen concentration in the metal oxide measured by SIMS is set to less than 1×10 20 atoms / cm 3 , preferably less than 1×10 19 atoms / cm 3 , more preferably less than 5×10 18 atoms / cm 3 , more preferably less than 1×10 18 atoms / cm 3 By using a metal oxide with sufficiently reduced impurities in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0163] As the metal oxide semiconductor used in transistors, a highly crystalline thin film is preferably used. Using such a thin film can improve the stability and reliability of the transistor. Examples of such thin films include single-crystalline metal oxide thin films and polycrystalline metal oxide thin films. However, forming single-crystalline metal oxide thin films or polycrystalline metal oxide thin films on a substrate requires a high-temperature or laser heating process. This increases manufacturing process costs and reduces throughput.

[0164] Non-Patent Documents 1 and 2 report the discovery of In-Ga-Zn oxide (also known as CAAC-IGZO) with a CAAC structure in 2009. These documents report that CAAC-IGZO has c-axis orientation, unclear grain boundaries, and can be formed on a substrate at low temperatures. Furthermore, they report that transistors using CAAC-IGZO exhibit excellent electrical properties and reliability.

[0165] In 2013, an In-Ga-Zn oxide with an nc structure (called nc-IGZO) was discovered (see Non-Patent Document 3). This report reported that the atomic arrangement of nc-IGZO in tiny regions (e.g., regions between 1 nm and 3 nm) is periodic, and no regularity in crystal orientation is observed between different regions.

[0166] Non-patent literature 4 and non-patent literature 5 show the change in the average crystal size when the thin films of the above-mentioned CAAC-IGZO, nc-IGZO and IGZO with low crystallinity are irradiated with electron beams, respectively. In the IGZO thin film with low crystallinity, crystalline IGZO of about 1 nm can be observed before it is irradiated with an electron beam. Therefore, it is reported here that the existence of a completely amorphous structure has not been confirmed in IGZO. Furthermore, it is disclosed that the stability of the CAAC-IGZO thin film and the nc-IGZO thin film with respect to electron beam irradiation is higher than that of the IGZO thin film with low crystallinity. Therefore, it is preferable to use a CAAC-IGZO thin film or a nc-IGZO thin film as a semiconductor of a transistor.

[0167] Non-patent document 6 discloses that a transistor using metal oxide has extremely low leakage current in the non-conducting state. Specifically, the off-state current of the transistor is yA / μm (10 -24 For example, a low-power CPU that utilizes the low leakage current characteristic of a transistor using a metal oxide has been disclosed (see Non-Patent Document 7).

[0168] In addition, there are reports of applying transistors using metal oxides to display devices by utilizing their low leakage current characteristic (see non-patent document 8). In a display device, the displayed image is switched dozens of times in 1 second. The number of image switches per 1 second is called the refresh rate. In addition, the refresh rate is sometimes called the drive frequency. Such high-speed screen switching that is difficult for the human eye to recognize is considered to be a cause of eye fatigue. Therefore, a technology has been proposed to reduce the refresh rate of the display device to reduce the number of image rewrites. In addition, a drive with a reduced refresh rate can reduce the power consumption of the display device. This driving method is called an idle stop (IDS) drive.

[0169] The discovery of CAAC and nc structures has contributed to improvements in the electrical properties and reliability of transistors using metal oxides with CAAC or nc structures, as well as reductions in manufacturing costs and increased throughput. Furthermore, research is underway to utilize these transistors' low leakage current characteristics for applications in display devices and LSIs.

[0170] <Method for Manufacturing Semiconductor Device> Next, a method for manufacturing a semiconductor device including a transistor 200 according to one embodiment of the present invention shown in FIG1 will be described with reference to FIG4 to FIG11. In FIG4 to FIG11, A in each figure shows a top view. In addition, B in each figure shows a cross-sectional view of a portion along the dot-dash line A1-A2 in A, which corresponds to a cross-sectional view in the channel length direction of the transistor 200. C in each figure shows a cross-sectional view of a portion along the dot-dash line A3-A4 in A, which corresponds to a cross-sectional view in the channel width direction of the transistor 200. For the sake of clarity, some components are omitted in the top view of A in each figure.

[0171] First, a substrate (not shown) is prepared, and an insulator 214 is formed on the substrate. The insulator 214 can be formed by sputtering, CVD, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), ALD, or the like.

[0172] Note that CVD methods can be categorized into plasma-enhanced CVD (PECVD) using plasma, thermal CVD (TCVD) using heat, and photo CVD using light. Furthermore, CVD methods can be categorized into metal CVD (MCVD) and metal organic CVD (MOCVD) depending on the source gas used.

[0173] By utilizing the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since plasma is not used, the thermal CVD method is a film forming method that can reduce the plasma damage caused to the object to be processed. For example, the wiring, electrodes, components (transistors, capacitors, etc.) included in the semiconductor device sometimes generate charge accumulation (charge up) due to receiving charges from the plasma. At this time, the wiring, electrodes, components, etc. included in the semiconductor device are sometimes damaged due to the accumulated charge. On the other hand, since the above-mentioned plasma damage is not generated in the case of the thermal CVD method without plasma, the yield of the semiconductor device can be improved. In addition, in the thermal CVD method, plasma damage is not generated during film formation, so a film with fewer defects can be obtained.

[0174] In addition, the ALD method can utilize the self-regulation as a property of atoms to deposit the atoms of each layer, thereby achieving the effects of being able to form extremely thin films, being able to form films on structures with high aspect ratios, being able to form films with fewer defects such as pinholes, being able to form films with excellent coverage, and being able to form films at low temperatures. In addition, the ALD method also includes the PEALD (Plasma Enhanced ALD) method using plasma. By utilizing plasma, film formation can be performed at lower temperatures, so it is sometimes preferred. Note that the precursors used in the ALD method sometimes contain impurities such as carbon. Therefore, films formed using the ALD method sometimes contain more impurities such as carbon than films formed using other film forming methods. In addition, the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).

[0175] Unlike film-forming methods that deposit particles released from a target material, etc., CVD and ALD methods form films due to reactions on the surface of the workpiece. Therefore, films formed using CVD and ALD methods are less susceptible to the shape of the workpiece and have good step coverage. In particular, films formed using the ALD method have good step coverage and thickness uniformity, making the ALD method suitable for covering surfaces with openings with high aspect ratios. Note that the ALD method has a relatively slow film-forming speed, so it is sometimes preferable to use it in combination with other film-forming methods with faster film-forming speeds, such as the CVD method.

[0176] CVD and ALD methods can control the composition of the resulting film by adjusting the flow ratio of source gases. For example, when using CVD or ALD, a film of any composition can be formed by adjusting the flow ratio of source gases. Furthermore, when using CVD and ALD, for example, a film whose composition continuously changes can be formed by changing the flow ratio of source gases while the film is formed. When forming a film while changing the flow ratio of source gases, the time required for transfer and pressure adjustment is eliminated, so the film formation time can be shortened compared to when film formation is performed using multiple film formation chambers. Therefore, the productivity of semiconductor devices can sometimes be improved.

[0177] In this embodiment, aluminum oxide is formed by sputtering as the insulator 214. The insulator 214 may also have a multilayer structure. For example, aluminum oxide may be formed by sputtering, and then another aluminum oxide layer may be formed on top of the aluminum oxide layer by ALD. Alternatively, aluminum oxide may be formed by ALD, and then another aluminum oxide layer may be formed on top of the aluminum oxide layer by sputtering.

[0178] Next, a conductive film serving as the conductor 205 is formed on the insulator 214. The conductive film serving as the conductor 205 is formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductive film serving as the conductor 205 may be a multilayer film. In this embodiment, tungsten is formed as the conductive film serving as the conductor 205.

[0179] Next, the conductive film to be the conductor 205 is processed using a photolithography method, whereby the conductor 205 is formed.

[0180] In addition, in photolithography, first, the resist is exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, an etching process is performed through the resist mask to process the conductor, semiconductor, insulator, etc. into the desired shape. For example, a resist mask can be formed by exposing the resist using KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. In addition, a liquid immersion technique can be used in which the exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens. In addition, an electron beam or an ion beam can be used instead of the above-mentioned light. Note that when an electron beam or an ion beam is used, the above-mentioned resist exposure mask is not required. In addition, when removing the resist mask, a dry etching process such as ashing or a wet etching process can be performed, or a wet etching process can be performed after a dry etching process, or a dry etching process can be performed after a wet etching process.

[0181] Alternatively, a hard mask made of an insulator or a conductor can be used instead of a resist mask. When using a hard mask, an insulating film or a conductive film serving as a hard mask material can be formed on the conductive film serving as the conductor 205, and a resist mask can be formed thereon. The hard mask material can then be etched to form a hard mask of the desired shape. The etching of the conductive film serving as the conductor 205 can be performed either after removing the resist mask or without removing the resist mask. In the latter case, the resist mask may disappear during etching. Alternatively, the hard mask can be removed by etching after the etching of the conductive film serving as the conductor 205. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, the hard mask does not necessarily need to be removed.

[0182] As a dry etching device, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching device including parallel plate electrodes can be used. The capacitively coupled plasma etching device including parallel plate electrodes can also adopt a structure in which high-frequency power is applied to one of the parallel plate electrodes. Alternatively, a structure in which multiple different high-frequency powers are applied to one of the parallel plate electrodes can be adopted. Alternatively, a structure in which high-frequency power of the same frequency is applied to each of the parallel plate electrodes can be adopted. Alternatively, a structure in which high-frequency power of different frequencies is applied to each of the parallel plate electrodes can be adopted. Alternatively, a dry etching device having a high-density plasma source can be used. For example, as a dry etching device having a high-density plasma source, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching device or the like can be used.

[0183] Next, an insulating film serving as the insulator 216 is formed over the insulator 214 and the conductor 205. This insulating film is formed so as to be in contact with the top and side surfaces of the conductor 205. This insulator can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon oxide is formed by CVD as the insulating film serving as the insulator 216.

[0184] Here, the thickness of the insulating film serving as the insulator 216 is preferably greater than or equal to the thickness of the conductor 205. For example, when the thickness of the conductor 205 is 1, the thickness of the insulating film serving as the insulator 216 is greater than or equal to 1 and less than or equal to 3. In this embodiment, the thickness of the conductor 205 is 150 nm, and the thickness of the insulating film serving as the insulator 216 is 350 nm.

[0185] Next, the insulating film that will become the insulator 216 is partially removed by CMP (Chemical Mechanical Polishing) to expose the surface of the conductor 205. This allows the conductor 205 to have a flat top surface and the insulator 216 to be in contact with the side surface of the conductor 205 (see FIG4 ). Improving the flatness of the top surfaces of the insulator 216 and the conductor 205 improves the crystallinity of the CAAC-OS forming the oxides 230 b and 230 c.

[0186] Next, a method for forming the conductor 205 which is different from the above-described method will be described.

[0187] An insulator 216 is formed on the insulator 214. The insulator 216 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0188] Next, an opening is formed in insulator 216 that reaches insulator 214. The opening includes, for example, a groove or a slit. The region where the opening is formed is sometimes referred to as an opening portion. Wet etching can be used to form this opening, but dry etching is preferred for microfabrication. Insulator 214 is preferably selected from an insulator that functions as an etch stop film when etching insulator 216 to form the groove. For example, when a silicon oxide film is used as insulator 216 for forming the groove, a silicon nitride film, an aluminum oxide film, or a hafnium oxide film is preferably used as insulator 214.

[0189] After the opening is formed, a conductive film serving as the conductor 205 is formed. This conductive film preferably includes a conductor that inhibits oxygen transmission. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a laminated film of the conductor and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film serving as the conductor 205 can be formed using sputtering, CVD, MBE, PLD, ALD, or the like.

[0190] In this embodiment, a multilayer structure is employed as the conductive film serving as the conductor 205. First, a tantalum nitride film is formed by sputtering, and titanium nitride is stacked on the tantalum nitride. By using this metal nitride as the lower layer of the conductive film serving as the conductor 205, even if a readily diffusible metal such as copper is used as the upper layer of the conductive film serving as the conductor 205 (described later), diffusion of the metal from the conductor 205 to the outside can be suppressed.

[0191] Next, a conductive film is formed on the upper layer of the conductive film serving as the conductor 205. This conductive film can be formed using a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film on the upper layer of the conductive film serving as the conductor 205.

[0192] Next, a CMP process is performed to remove the upper layer of the conductive film that will become the conductor 205 and a portion of the lower layer of the conductive film that will become the conductor 205, thereby exposing the insulator 216. As a result, only the conductive film that will become the conductor 205 remains in the opening. This allows the conductor 205 to have a flat top surface. Note that this CMP process may also remove a portion of the insulator 216. This is a method for forming the conductor 205 that differs from the above.

[0193] Next, an insulator 222 is formed on the insulator 216 and the conductor 205. As the insulator 222, it is preferable to form an insulator containing an oxide of one or both of aluminum and hafnium. In addition, as the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property to oxygen, hydrogen, and water. When the insulator 222 has a barrier property to hydrogen and water, it is possible to suppress the diffusion of hydrogen and water contained in the structure surrounding the transistor 200 through the insulator 222 into the inner side of the transistor 200, thereby suppressing the generation of oxygen defects in the oxide 230.

[0194] The insulator 222 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0195] Next, an insulating film 224A serving as the insulator 224 is formed over the insulator 222. The insulating film 224A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0196] Next, heat treatment is preferably performed. The heat treatment can be performed at a temperature of 250°C or higher and 650°C or lower, preferably 300°C or higher and 500°C or lower, and more preferably 320°C or higher and 450°C or lower. The heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then in order to compensate for the oxygen that has been released, the heat treatment is performed in an atmosphere containing an oxidizing gas of 10 ppm or higher, 1% or higher, or 10% or higher.

[0197] In this embodiment, heat treatment is performed at 400°C for one hour in a nitrogen atmosphere after forming the insulating film 224A. This heat treatment removes impurities such as water and hydrogen from the insulating film 224A. Alternatively, heat treatment can be performed after forming the insulator 222.

[0198] Here, in order to form an excess oxygen region in the insulating film 224A, a plasma treatment containing oxygen may be performed under reduced pressure. The plasma treatment containing oxygen preferably uses, for example, a device including a power supply for generating high-density plasma using microwaves. Alternatively, it may include a power supply for applying RF (Radio Frequency) to one side of the substrate. High-density oxygen radicals can be generated by using high-density plasma, and the oxygen radicals generated by the high-density plasma can be efficiently introduced into the insulating film 224A by applying RF to one side of the substrate. Alternatively, after performing a plasma treatment containing an inert gas using such a device, a plasma treatment containing oxygen may be performed to compensate for the detached oxygen. In addition, by appropriately selecting the conditions for the plasma treatment, impurities such as water and hydrogen contained in the insulating film 224A can be removed. At this time, heat treatment may not be performed.

[0199] Here, aluminum oxide may be formed on the insulating film 224A, for example, by sputtering, and then subjected to CMP treatment until it reaches the insulating film 224A. This CMP treatment allows the surface of the insulating film 224A to be flattened and smoothed. By placing the aluminum oxide on the insulating film 224A and performing the CMP treatment, it is easy to detect the end point of the CMP treatment. Furthermore, the thickness of the insulating film 224A may sometimes be reduced due to a portion of the insulating film 224A being polished by the CMP treatment. However, this thickness can be adjusted during the formation of the insulating film 224A. By flattening and smoothing the surface of the insulating film 224A, it is sometimes possible to prevent a reduction in the coverage of the oxide formed below and thus prevent a reduction in the yield of the semiconductor device. Furthermore, by forming the aluminum oxide on the insulating film 224A by sputtering, oxygen can be added to the insulating film 224A, which is preferable.

[0200] Next, an oxide film 230A, which will become the oxide 230a, and an oxide film 230B, which will become the oxide 230b, are sequentially formed on the insulating film 224A (see FIG4 ). It is preferable to form these oxide films continuously without exposing them to the atmosphere. Forming the oxide films without exposing them to the atmosphere prevents impurities and moisture from the atmosphere from adhering to the oxide films 230A and 230B, thereby keeping the interface between the oxide films 230A and 230B clean.

[0201] The oxide film 230A and the oxide film 230B can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0202] For example, when the oxide film 230A and the oxide film 230B are formed by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the formed oxide film can be increased. In addition, when the above-mentioned oxide film is formed by sputtering, for example, the above-mentioned In-M-Zn oxide target can be used. In addition, the target is connected to an alternating current (AC) power supply such as a direct current (DC) power supply or a high frequency (RF) power supply, and the required power can be applied according to the conductivity of the target.

[0203] In particular, when forming the oxide film 230A, some of the oxygen contained in the sputtering gas may be supplied to the insulating film 224A. Therefore, the ratio of oxygen contained in the sputtering gas for the oxide film 230A may be 70% or more, preferably 80% or more, and more preferably 100%.

[0204] In addition, when the oxide film 230B is formed by sputtering, when the film is formed under the condition that the ratio of oxygen contained in the sputtering gas is set to 1% or more and 30% or less, preferably 5% or more and 20% or less, an oxygen-deficient oxide semiconductor is formed. A transistor using an oxygen-deficient oxide semiconductor in a channel formation region can have a higher field effect mobility. In addition, by forming the film while heating the substrate, the crystallinity of the oxide film can be improved. Note that one embodiment of the present invention is not limited to this. When the oxide film 230b is formed by sputtering, an oxygen-excess oxide semiconductor is formed by forming the film under the condition that the ratio of oxygen contained in the sputtering gas is greater than 30% and less than 100%, preferably 70% or more and less than 100%. A transistor using an oxygen-excess oxide semiconductor in a channel formation region can obtain relatively high reliability.

[0205] In this embodiment, oxide film 230A is formed by sputtering using an In-Ga-Zn oxide target having an atomic ratio of In:Ga:Zn = 1:1:0.5 (2:2:1) or an atomic ratio of In:Ga:Zn = 1:3:4. Furthermore, oxide film 230B is formed by sputtering using an In-Ga-Zn oxide target having an atomic ratio of In:Ga:Zn = 4:2:4.1. These oxide films can be formed by appropriately selecting film formation conditions and atomic ratios depending on the desired properties of oxide 230.

[0206] Here, the insulator 222, the insulating film 224A, the oxide film 230A, and the oxide film 230B are preferably formed without being exposed to the air. For example, a multi-chamber film formation apparatus can be used.

[0207] Next, heat treatment may be performed. The heat treatment conditions described above can be used. Heat treatment can remove impurities such as water and hydrogen from oxide films 230A and 230B. In this embodiment, treatment is performed at 400°C for 1 hour in a nitrogen atmosphere, followed by treatment at 400°C for 1 hour in an oxygen atmosphere.

[0208] Next, a conductive film 242A is formed over the oxide film 230B. The conductive film 242A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like (see FIG. 4 ).

[0209] Next, the insulating film 224A, the oxide film 230A, the oxide film 230B, and the conductive film 242A are processed into island shapes to form the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B (see FIG. 5).

[0210] Here, the insulator 224, oxide 230a, oxide 230b, and conductive layer 242B are formed so that at least a portion thereof overlaps with the conductor 205. Furthermore, the side surfaces of the insulator 224, oxide 230a, oxide 230b, and conductive layer 242B are preferably substantially perpendicular to the top surface of the insulator 222. When the side surfaces of the insulator 224, oxide 230a, oxide 230b, and conductive layer 242B are substantially perpendicular to the top surface of the insulator 222, a smaller area and higher density can be achieved when multiple transistors 200 are provided. Alternatively, a structure can be employed in which the angle formed by the side surfaces of the insulator 224, oxide 230a, oxide 230b, and conductive layer 242B and the top surface of the insulator 222 is relatively low. In this case, the angle formed by the side surfaces of the insulator 224, oxide 230a, oxide 230b, and conductive layer 242B and the top surface of the insulator 222 is preferably greater than or equal to 60 degrees and less than 70 degrees. By adopting such a shape, the coverage of the insulator 254 and the like can be improved in the subsequent steps, and defects such as voids can be reduced.

[0211] Furthermore, a curved surface is provided between the side surface and the top surface of the conductive layer 242B. Specifically, the ends of the side surface and the top surface are preferably curved (hereinafter also referred to as rounded). For example, at the ends of the conductive layer 242B, the curved surface has a radius of curvature of not less than 3 nm and not more than 10 nm, more preferably not less than 5 nm and not more than 6 nm. When the ends do not have corners, the coverage of the film in the subsequent film formation process can be improved.

[0212] The insulating film 224A, the oxide film 230A, the oxide film 230B, and the conductive film 242A can be processed using photolithography. Dry etching or wet etching can be used for this processing. Dry etching is suitable for microfabrication. Furthermore, the insulating film 224A, the oxide film 230A, the oxide film 230B, and the conductive film 242A can be formed under different conditions.

[0213] Next, an insulating film 254A is formed over the insulator 222 , the insulator 224 , the oxide 230 a , the oxide 230 b , and the conductive layer 242B (see FIG. 6 ).

[0214] As the insulating film 254A, an insulating film having a function of suppressing oxygen permeation is preferably used. For example, an aluminum oxide film is preferably formed by sputtering. By forming the aluminum oxide film by sputtering using a gas containing oxygen, oxygen can be introduced into the insulator 224. In other words, the insulator 224 can contain excess oxygen.

[0215] Next, an insulating film serving as insulator 280 is formed on insulating film 254A. The insulating film serving as insulator 280 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. Next, CMP treatment is performed on the insulating film serving as insulator 280 to form insulator 280 with a flat top surface (see FIG. 6 ).

[0216] Next, a portion of the insulator 280, a portion of the insulating film 254A, and a portion of the conductive layer 242B are processed to form an opening that reaches the oxide 230b. This opening is preferably formed so as to overlap with the conductor 205. The conductors 242a, 242b, and the insulator 254 are formed from this opening (see FIG. 7 ).

[0217] Alternatively, a portion of the insulator 280, a portion of the insulating film 254A, and a portion of the conductive layer 242B may be processed under different conditions. For example, a portion of the insulator 280 may be processed by dry etching, a portion of the insulating film 254A may be processed by wet etching, and a portion of the conductive layer 242B may be processed by dry etching.

[0218] By performing the dry etching process, impurities caused by etching gas may adhere to or diffuse on the surface or inside of the oxide 230a and the oxide 230b, etc. Examples of the impurities include fluorine and chlorine.

[0219] Cleaning is performed to remove the above-mentioned impurities, etc. Examples of the cleaning method include wet cleaning using a cleaning liquid, plasma treatment using plasma, and cleaning using a heat treatment, and these cleaning methods may be appropriately combined.

[0220] As wet cleaning, an aqueous solution of oxalic acid, phosphoric acid, hydrofluoric acid, or the like diluted with carbonated water or pure water can be used for cleaning. Alternatively, ultrasonic cleaning using pure water or carbonated water can be performed.

[0221] Next, a heat treatment may be performed. The heat treatment may also be performed under reduced pressure, and the oxide film 230C may be continuously formed without being exposed to the atmosphere. By performing this treatment, moisture and hydrogen attached to the surface of the oxide 230b can be removed, and the moisture concentration and hydrogen concentration in the oxides 230a and 230b can be reduced. The temperature of the heat treatment is preferably 100°C or higher and 400°C or lower. In this embodiment, the temperature of the heat treatment is 200°C (see FIG8 ).

[0222] Oxide film 230C can be formed using a sputtering method, CVD method, MBE method, PLD method, ALD method, or the like. The oxide film to be used as oxide film 230C can be formed using the same film formation method as oxide film 230A or oxide film 230B, depending on the desired properties of oxide film 230C. In this embodiment, oxide film 230C is formed using a sputtering method using an In—Ga—Zn oxide target with an atomic ratio of In:Ga:Zn = 1:3:4 or an atomic ratio of In:Ga:Zn = 4:2:4.1.

[0223] In particular, when forming oxide film 230C, some of the oxygen contained in the sputtering gas may be supplied to oxides 230a and 230b. Therefore, the ratio of oxygen contained in the sputtering gas for oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%.

[0224] Next, heat treatment may be performed. Heat treatment may be performed under reduced pressure, and the insulating film 250A may be continuously formed without exposure to the atmosphere. This treatment removes moisture and hydrogen adhering to the surface of the oxide film 230C, and reduces the moisture and hydrogen concentrations in the oxides 230a and 230b, as well as the oxide film 230C. The heat treatment temperature is preferably 100° C. or higher and 400° C. or lower (see FIG. 9 ).

[0225] The insulating film 250A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Silicon oxynitride is preferably formed using a CVD method as the insulating film 250A. The film formation temperature during the formation of the insulating film 250A is preferably 350°C or higher and lower than 450°C, particularly preferably around 400°C. Forming the insulating film 250A at 400°C allows the formation of an insulating film with low impurities.

[0226] Next, a conductive film 260A and a conductive film 260B are formed. The conductive film 260A and the conductive film 260B can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, CVD is preferably used. In this embodiment, the conductive film 260A is formed by ALD, and the conductive film 260B is formed by CVD (see FIG. 10 ).

[0227] Next, oxide film 230C, insulating film 250A, conductive film 260A, and conductive film 260B are polished by CMP until insulator 280 is exposed, thereby forming oxide 230c, insulator 250, and conductors 260 (conductors 260a and 260b) (see FIG11 ). Thus, oxide 230c is arranged so as to cover the inner walls (side walls and bottom surface) of the opening that reaches oxide 230b. Insulator 250 is arranged so as to cover the inner walls of the opening via oxide 230c. Furthermore, conductor 260 is arranged so as to fit into the opening via oxide 230c and insulator 250.

[0228] Next, a heat treatment may be performed. In this embodiment, the treatment is performed at 400° C. for 1 hour in a nitrogen atmosphere. This heat treatment can reduce the water concentration and hydrogen concentration in the insulator 250 and the insulator 280 .

[0229] Next, insulator 274 can be formed over oxide 230c, insulator 250, conductor 260, and insulator 280. Insulator 274 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, insulator 274 is preferably formed by sputtering as an aluminum oxide film. Sputtering can sometimes suppress the diffusion of hydrogen from insulator 281 into oxide 230. Forming insulator 274 in contact with conductor 260 is also preferred because it can suppress oxidation of conductor 260. Furthermore, forming insulator 274 allows oxygen to be supplied to insulator 280. Oxygen supplied to insulator 280 can sometimes be supplied to region 234 in oxide 230b via oxide 230c. Furthermore, supplying oxygen to insulator 280 can sometimes cause oxygen contained in insulator 280 before forming insulator 274 to be supplied to region 234 in oxide 230b via oxide 230c.

[0230] Next, a heat treatment may be performed. The heat treatment conditions described above may be used. This heat treatment can reduce the water concentration and hydrogen concentration of insulator 280. Furthermore, oxygen in insulator 274 can be implanted into insulator 280.

[0231] Alternatively, as a method for forming insulator 274 on insulator 280, an insulating film made of the same material as insulator 274 can be formed using the same method as insulator 274, followed by heat treatment using the aforementioned heat treatment conditions. The insulating film can then be removed by CMP, followed by forming insulator 274, and then heat treatment using the aforementioned heat treatment conditions. This method can form an excess oxygen region in insulator 280. Note that in this step of removing the insulating film, portions of insulator 280, conductor 260, insulator 250, and oxide 230c may be removed.

[0232] Alternatively, an insulator may be provided between insulator 280 and insulator 274. For example, silicon oxide formed by sputtering may be used as the insulator. Providing the insulator allows for the formation of an excess oxygen region in insulator 280.

[0233] Next, an insulator 281 serving as an insulating film may be formed on the insulator 274. The insulator 281 serving as the insulating film may be formed by sputtering, CVD, MBE, PLD, ALD, or the like (see FIG. 11 ).

[0234] Next, openings reaching the conductors 242a and 242b are formed in the insulators 254, 280, 274, and 281. The openings may be formed using photolithography.

[0235] Next, an insulating film serving as the insulator 241 is formed, and the insulating film is anisotropically etched to form the insulator 241. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film, an insulating film having a function of inhibiting oxygen permeation is preferably used. For example, an aluminum oxide film is preferably formed by the ALD method. Alternatively, a silicon nitride film can be formed by the ALD method or the CVD method. When the silicon nitride film is formed by the ALD method, a precursor containing silicon and halogen or an aminosilane precursor can be used. As a precursor containing silicon and halogen, SiCl4, SiH2Cl2, Si2Cl6, and Si3Cl8 can be used. In addition, as a precursor of the aminosilane, monovalent, divalent, or trivalent aminosilanes can be used. In addition, ammonia or hydrazine can be used as an oxynitride gas. In addition, as anisotropic etching, for example, dry etching can be used. By configuring the sidewalls of the opening in this manner, the penetration of oxygen from the outside can be suppressed, and oxidation of the conductors 240a and 240b to be formed next can be prevented. In addition, impurities such as water and hydrogen can be prevented from diffusing from the conductors 240a and 240b to the outside.

[0236] Next, a conductive film serving as the conductor 240a and the conductor 240b is formed. This conductive film preferably has a stacked structure including a conductive material that has the function of inhibiting the diffusion of impurities such as water and hydrogen. For example, it can be a stacked structure of tantalum nitride, titanium nitride, or the like, and tungsten, molybdenum, copper, or the like. This conductive film can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0237] Next, a CMP process is performed to remove a portion of the conductive film, exposing the insulator 281. As a result, the conductive film remains only in the opening, allowing the conductors 240a and 240b to be formed with flat top surfaces (see FIG. 1 ). Note that the CMP process may also remove a portion of the insulator 281.

[0238] Through the above steps, it is possible to manufacture the semiconductor device including the transistor 200 shown in Fig. 1. As shown in Fig. 4 to Fig. 11, the transistor 200 can be manufactured by using the method for manufacturing a semiconductor device described in this embodiment.

[0239] According to one embodiment of the present invention, a semiconductor device with a large on-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high frequency characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with good reliability can be provided. In addition, according to one embodiment of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

[0240] <Structural Example 2 of Semiconductor Device> 12 is a top view and a cross-sectional view of a transistor 200A and its surroundings according to one embodiment of the present invention. The transistor 200A is a modified example of the transistor 200 .

[0241] Figure 12A 2 is a top view of a semiconductor device including transistor 200A. Figure 12B and Figure 12C is a cross-sectional view of the semiconductor device. Figure 12B It is along Figure 12A The cross-sectional view of the portion indicated by the dot-dash line A1-A2 in FIG is also a cross-sectional view of the transistor 200A in the channel length direction. Figure 12C It is along Figure 12AThe cross-sectional view of the portion indicated by the dot-dash line A3-A4 is also a cross-sectional view of the transistor 200A in the channel width direction. Note that Figure 12A Some components are omitted in the top view for clarity.

[0242] Note that in the semiconductor device shown in FIG12, components having the same functions as those of the components constituting the semiconductor device shown in <Structural Example 1 of Semiconductor Device> are denoted by the same reference numerals.

[0243] The structure of the semiconductor device will be described below with reference to Fig. 12. In this structure, the constituent materials of the semiconductor device may be the materials described in detail in <Structural Example 1 of Semiconductor Device>.

[0244] [Transistor 200A] As shown in FIG12 , the transistor 200A includes an insulator 216 disposed on a substrate (not shown), a conductor 205 disposed in an embedded manner in the insulator 216, an insulator 222 disposed on the insulator 216 and the conductor 205, an insulator 224 disposed on the insulator 222, an oxide 230 (oxide 230a, oxide 230b, oxide 230c1, and oxide 230c2) disposed on the insulator 224, an insulator 250 disposed on the oxide 230, and a conductor 260 (conductor 260a and conductor 260c2) disposed on the insulator 250. body 260b), conductor 242a and conductor 242b in contact with a portion of the top surface of oxide 230b, a blocking film 244a arranged on conductor 242a, a blocking film 244b arranged on conductor 242b, and an insulator 254 (insulator 254a and insulator 254b) arranged in contact with a portion of the top surface of insulator 222, the side surface of insulator 224, the side surface of oxide 230a, the side surface of oxide 230b, the side surface of conductor 242a, the top surface of blocking film 244a, the side surface of conductor 242b and the top surface of blocking film 244b.

[0245] Transistor 200A differs from transistor 200 in that insulator 254 employs a two-layer stacked structure of insulators 254a and 254b, oxide 230c employs a two-layer stacked structure of oxides 230c1 and 230c2, and transistor 200A further includes barrier films 244a and 244b. The differences from transistor 200 are described below.

[0246] As shown in FIG12 , the insulator 254 includes an insulator 254 a and an insulator 254 b disposed on the insulator 254 a. For example, the insulator 254 a preferably has a barrier function that inhibits impurities such as water and hydrogen from diffusing from the insulator 280 side to the transistor 200A. Furthermore, for example, the insulator 254 b preferably inhibits oxygen in the oxide 230 from diffusing toward the insulator 280 side. By adopting this double-layer stacked structure, hydrogen can be prevented from mixing into the channel formation region of the oxide 230. Furthermore, the release of oxygen from the channel formation region of the oxide 230 can be prevented. Specifically, the insulator 254 a can be formed using a silicon nitride film formed using a sputtering method, and the insulator 254 b can be formed using an aluminum oxide film formed using an ALD method.

[0247] For example, insulator 254a is preferably made of an insulating material having an excess oxygen region or an insulating material that easily forms an excess oxygen region, while insulator 254b is preferably made of an insulating material that easily forms an excess oxygen region in the film being formed. Specifically, insulator 254a can be made of a silicon oxide film formed by sputtering, and insulator 254b can be made of an aluminum oxide film formed by sputtering. By adopting this two-layer stacked structure, excess oxygen in insulator 254a can be efficiently supplied to oxide 230.

[0248] In addition, when the insulator 254a contains excess oxygen, it is preferable to provide a barrier film 244a in contact with the top surface of the conductor 242a and a barrier film 244b in contact with the top surface of the conductor 242b. The barrier films 244a and 244b have the function of inhibiting the permeation of impurities such as water and hydrogen and oxygen. This prevents excess oxygen in the oxide 230c and the insulator 250 from diffusing into the conductors 242a and 242b. In other words, it prevents excess oxygen around the conductors 242a and 242b from being used for oxidation of the conductors 242a and 242b. Furthermore, it prevents the resistance of the conductors 242a and 242b from increasing due to oxidation of the conductors 242a and 242b. In addition, it is possible to measure the resistance of the conductors using a two-terminal method or the like.

[0249] The barrier films 244a and 244b can be made of metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon oxynitride, or silicon nitride.

[0250] Alternatively, barrier films 244a and 244b may be made of a conductive material that is less likely to allow impurities to pass through. When using a conductive material as barrier films 244a and 244b, it is preferable to use a conductive material that is less likely to release or absorb oxygen. Alternatively, barrier films 244a and 244b may not be provided.

[0251] Note that insulator 254 is not limited to a structure consisting of stacked insulators 254a and 254b. A single-layer structure may also be employed. Alternatively, a three-layer stacked structure of insulators 254a, 254b, and 254c may be employed. When a three-layer stacked structure is employed, for example, insulator 254a may be made of an insulating material that can inhibit the diffusion of impurities such as water and hydrogen, as well as oxygen; insulator 254b may be made of an insulating material that includes an excess oxygen region; and insulator 254c may be made of an insulating material that can inhibit the diffusion of oxygen. By employing this three-layer stacked structure, excess oxygen in insulator 254b can be prevented from diffusing outside insulators 254a and 254c. Consequently, excess oxygen contained in insulator 254b can be efficiently supplied to oxide 230.

[0252] In addition, when the insulator 254 adopts a stacked structure of two or more layers, the combination of insulating materials used in the insulator 254 and the stacking order can be appropriately designed according to the required transistor characteristics.

[0253] In addition, as shown in Figure 12, oxide 230c includes oxide 230c1 and oxide 230c2 provided on oxide 230c1. Oxide 230c1 preferably contains at least one of the metal elements of the metal oxide used to constitute oxide 230b, and more preferably contains all of the above metal elements. As a result, the defect state density at the interface between oxide 230b and oxide 230c1 can be reduced. In addition, oxide 230c2 is preferably a metal oxide that suppresses the diffusion or permeation of oxygen more than oxide 230c1. By providing oxide 230c2 between insulator 250 and oxide 230c1, the diffusion of oxygen contained in insulator 280 to insulator 250 can be suppressed. Therefore, the oxygen is easily supplied to oxide 230 through oxide 230c1.

[0254] In addition, the oxide 230c1 and the oxide 230c2 are preferably crystalline, and more preferably, the crystallinity of the oxide 230c2 is higher than that of the oxide 230c1. It is particularly preferred that the oxide 230c1 and the oxide 230c2 use CAAC-OS, and the c-axis of the crystals in the oxide 230c1 and the oxide 230c2 is oriented in a direction substantially perpendicular to the formed surface or top surface of the oxide 230c1 and the oxide 230c2. CAAC-OS has the characteristic of not easily allowing oxygen to move in the c-axis direction. Therefore, by providing the oxide 230c2 between the oxide 230c1 and the insulator 250, the oxygen in the oxide 230c1 can be prevented from diffusing to the insulator 250, thereby enabling the oxygen to be efficiently supplied to the oxide 230.

[0255] Specifically, oxide 230c1 can use a metal oxide with an atomic ratio of In:Ga:Zn = 4:2:3, and oxide 230c2 can use a metal oxide with an atomic ratio of In:Ga:Zn = 1:3:4. By making the atomic ratio of In in the metal oxide used in oxide 230c2 smaller than that of the metal oxide used in oxide 230c1, diffusion of In into insulator 250 can be suppressed. Since insulator 250 serves as a gate insulator, incorporation of In into insulator 250 can lead to poor transistor characteristics. Therefore, by providing oxide 230c with a stacked structure, a highly reliable semiconductor device can be provided.

[0256] Alternatively, insulator 280 may have a double-layer structure. As shown in FIG12 , when insulator 280 includes insulator 280 a and insulator 280 b disposed on insulator 280 a , insulator 280 a preferably includes an excess oxygen region. Since the physical distance between insulator 280 a and the channel formation region of oxide 230 is shorter than that between insulator 280 b and insulator 280 a , oxygen in insulator 280 can be efficiently supplied to the channel formation region of oxide 230 .

[0257] Specifically, a silicon oxide film formed by sputtering can be used for insulator 280a, and a silicon oxynitride film formed by CVD can be used for insulator 280b. The thickness of insulator 280a is preferably not less than 30 nm and not more than 100 nm, and more preferably not less than 40 nm and not more than 80 nm. Note that although insulator 280 is shown as having a stacked-layer structure in transistor 200A, the present invention is not limited to this. For example, insulator 280 may also have a single-layer structure or a stacked-layer structure of three or more layers.

[0258] Furthermore, as shown in FIG12 , an insulator 282 may be provided between insulator 274 and insulator 281. Insulator 282 is preferably an insulating film that can suppress the diffusion of impurities such as hydrogen and oxygen. For example, a silicon nitride film or an aluminum oxide film formed by sputtering or ALD is preferably used. Providing insulator 282 can prevent oxygen from insulators 280, 250, and the like from diffusing toward insulator 281.

[0259] As described above, the structure, method, etc. described in this embodiment can be implemented in combination with the structure, method, etc. described in other embodiments as appropriate.

[0260] (Implementation Method 2) An example of a semiconductor device including the transistor 200B according to one embodiment of the present invention will be described below.

[0261] <Structural Example 3 of Semiconductor Device> 13A to 13D 1 and 2 are a top view and a cross-sectional view of a transistor 200B and its surroundings according to one embodiment of the present invention. The transistor 200B is a modified example of the transistor 200 .

[0262] Note that in the semiconductor device described in this embodiment mode, components having the same functions as those of the components of the semiconductor device described in the previous embodiment mode are denoted by the same reference numerals. Furthermore, for details of components, materials, and the like of the semiconductor device described in this embodiment mode that are used in common with the components, materials, and the like of the semiconductor device described in the previous embodiment mode, and for details of components, materials, and the like denoted by the same reference numerals, reference can be made to the description of the previous embodiment mode.

[0263] Figure 13A 2 is a top view of a semiconductor device including transistor 200B. 13B to 13D is a cross-sectional view of the semiconductor device. Figure 13B It is along Figure 13A The cross-sectional view of the portion indicated by the dot-dash line A1-A2 in FIG is also a cross-sectional view of the transistor 200B in the channel length direction. Figure 13C It is along Figure 13A The cross-sectional view of the portion indicated by the dot-dash line A3-A4 in FIG is also a cross-sectional view of the transistor 200B in the channel width direction. Figure 13D It is along Figure 13A The cross-sectional view of the portion indicated by the dashed line A5-A6 in FIG is also a cross-sectional view of the vicinity of the region 243b serving as the low resistance region of the transistor 200B. Note that Figure 13A For the sake of clarity, some components are omitted in the top view.

[0264] A semiconductor device according to one embodiment of the present invention includes a transistor 200B, an insulator 214 serving as an interlayer film, an insulator 280, an insulator 274, and an insulator 281. Furthermore, the device includes a conductor 240 (conductor 240a and conductor 240b) serving as a plug electrically connected to the transistor 200B. Furthermore, an insulator 241 (insulator 241a and insulator 241b) is provided so as to contact the side surfaces of the conductor 240 serving as the plug.

[0265] In addition, the insulator 241 is provided in such a manner that the side walls of the openings of the insulator 254 (insulator 254a and insulator 254b), the insulator 280, the insulator 274, and the insulator 281 are in contact with each other, and the first conductor of the conductor 240 is provided in such a manner that it is in contact with the side surface thereof, and the second conductor of the conductor 240 is provided inside thereof. Here, the top surface height of the conductor 240 can be made substantially equal to the top surface height of the insulator 281. In addition, although the transistor 200B shows a stacked structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, the conductor 240 may also have a single-layer or three-layer or more stacked structure. When the structure has a stacked structure, an ordinal number is sometimes given in the order of formation to distinguish them.

[0266] [Transistor 200B] As shown in Figure 13, transistor 200B includes an insulator 216 arranged on a substrate (not shown), a conductor 205 arranged in a manner embedded in the insulator 216, an insulator 222 arranged on the insulator 216 and the conductor 205, an insulator 224 arranged on the insulator 222, an oxide 230 (oxide 230a, oxide 230b, oxide 230c1 and oxide 230c2) arranged on the insulator 224, an insulator 250 arranged on the oxide 230, a conductor 260 (conductor 260a and conductor 260b) arranged on the insulator 250, and an insulator 254 (insulator 254a and insulator 254b) arranged in a manner contacting a portion of the top surface of the insulator 222, the side surface of the insulator 224, the side surface of the oxide 230a, the side surface of the oxide 230b and the top surface of the oxide 230b.

[0267] Hereinafter, the oxide 230c1 and the oxide 230c2 may be collectively referred to as the oxide 230c.

[0268] 13 , a region 243 a and a region 243 b separated from each other are formed on the top surface of the oxide 230 b. In addition, an opening is provided in the insulator 280 so as to overlap with the region between the region 243 a and the region 243 b.

[0269] Conductor 260 serves as the gate electrode of the transistor, and region 243a and region 243b serve as the source region and drain region, respectively. In transistor 200B, conductor 260 is formed in a self-aligned manner, embedded within the openings formed in insulator 280 and insulator 254, and within the region sandwiched between region 243a and region 243b. Forming conductor 260 in this manner allows conductor 260 to be accurately positioned between region 243a and region 243b without requiring alignment. This reduces the area occupied by transistor 200B, thereby enabling miniaturization and increased integration of semiconductor devices.

[0270] The conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom and side surfaces of the conductor 260b. Figure 13B As shown, the top surface of the conductor 260 is preferably substantially consistent with the top surfaces of the insulator 250 , the oxide 230 c , and the insulator 280 .

[0271] The oxide 230 preferably includes an oxide 230a disposed on the insulator 224, an oxide 230b disposed on the oxide 230a, an oxide 230c1 disposed on the oxide 230b and having at least a portion in contact with the top surface of the oxide 230b, and an oxide 230c2 disposed on the oxide 230c1.

[0272] Note that although transistor 200B shows a four-layer stacked structure of oxide 230a, oxide 230b, oxide 230c1, and oxide 230c2 in the channel formation region and its vicinity, the present invention is not limited to this. For example, a single-layer structure of oxide 230b, a double-layer structure of oxide 230a and oxide 230b, a double-layer structure of oxide 230a and oxide 230c, a three-layer structure of oxide 230a, oxide 230b, and oxide 230c1, a three-layer structure of oxide 230a, oxide 230b, and oxide 230c2, or a stacked structure of five or more layers may be used. In addition, oxide 230a and oxide 230b may each have a stacked structure of two or more layers. In addition, oxide 230c may also have a single-layer structure or a stacked structure of three or more layers.

[0273] For example, when the oxide 230c has a stacked structure including an oxide 230c1 and an oxide 230c2 on the oxide 230c1, the oxide 230c1 preferably has the same composition as the oxide 230b, and the oxide 230c2 preferably has the same composition as the oxide 230a.

[0274] Note that a metal oxide having a semiconductor function (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxide 230 a , the oxide 230 b , the oxide 230 c 1 , and the oxide 230 c 2 ) including the channel formation region in the transistor 200B.

[0275] Since the transistor 200B, which uses an oxide semiconductor for its channel formation region, has extremely low leakage current (off-state current) in its non-conducting state, it can provide a low-power semiconductor device. Furthermore, since oxide semiconductors can be formed using sputtering or other methods, they can be used in the transistor 200B that constitutes a highly integrated semiconductor device.

[0276] For example, a metal oxide such as In-M-Zn oxide (where the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) is preferably used as the oxide 230. In particular, aluminum, gallium, yttrium, or tin is preferably used as the element M. Alternatively, indium oxide, zinc oxide, In-Ga oxide, In-Zn oxide, Ga-Zn oxide, or gallium oxide may be used as the oxide 230.

[0277] Here, by adding an element that forms an oxygen defect or an element that bonds to an oxygen defect to the oxide 230, the carrier density of the oxide 230 may be increased and the resistance may be reduced. Typical examples of such elements are boron or phosphorus. In addition, in addition to boron and phosphorus, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium and rare gases may also be used. In addition, typical examples of rare gases include helium, neon, argon, krypton, xenon, etc. In addition, one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum may be added to the oxide 230. Boron and phosphorus are preferably used among the above-mentioned metal elements. When adding boron and phosphorus, the equipment of the production line of amorphous silicon or low-temperature polysilicon can be used, thereby reducing equipment investment. The concentration of the above-mentioned elements can be measured using SIMS, etc.

[0278] Figure 14A Show Figure 13B FIG. 24 is an enlarged view of a portion of the transistor 200B shown in FIG. 243 is a layer formed by adding the above-mentioned elements to the oxide 230. Figure 13B and Figure 14AAs shown, regions 243a and 243b are formed facing each other with conductor 260 interposed therebetween, and their top surfaces are preferably in contact with insulator 254. Preferably, when viewed from above, the side surfaces of regions 243a and 243b on the side of conductor 260 are aligned with the side surfaces of conductor 260, or a portion of regions 243a and 243b overlap with conductor 260. The concentration of the aforementioned elements in region 243 is preferably equal to or higher than the concentration of the aforementioned elements in the portion of oxide 230 where region 243 is not formed. Furthermore, the amount of oxygen vacancies contained in region 243 is preferably equal to or higher than the amount of oxygen vacancies in the portion of oxide 230 where region 243 is not formed. Consequently, region 243 has a higher carrier density and lower resistance than the portion of oxide 230 where region 243 is not formed.

[0279] In the oxide 230, the region overlapping the conductor 260 is called region 234, the region overlapping the insulator 254 is called region 231 (region 231a and region 231b), and the region between region 234 and region 231 is called region 232 (region 232a and region 232b). Figure 14A As shown, region 234 is located between region 231a and region 231b, region 232a is located between region 231a and region 234, and region 232b is located between region 231b and region 234. Region 231 has a higher carrier density and lower resistance than region 234. Region 232 has a higher carrier density and lower resistance than region 234, and has a lower carrier density and higher resistance than region 231. Region 232 may have the same carrier density and resistance as region 231. Therefore, region 234 serves as a channel formation region for transistor 200B, region 231 serves as a source region or a drain region, and region 232 serves as a junction region.

[0280] By adopting this structure, an offset region can be prevented from being formed between the channel formation region of the oxide 230 and the source or drain region, thereby suppressing the effective channel length from being greater than the width of the conductor 260. This increases the on-state current of the transistor 200B, improves the S value (subthreshold swing, also called SS), and thus improves the frequency characteristics.

[0281] By forming a region 231 used as a source region or a drain region in the oxide 230, it is possible to eliminate the need for a source electrode and a drain electrode formed of metal, and the region 231 can be connected to the conductor 240 used as a plug. When a source electrode and a drain electrode formed of metal are formed in contact with the oxide 230, the source electrode and the drain electrode formed of metal may be oxidized during a high-temperature heat treatment during the manufacturing process or a subsequent process of the transistor 200B, resulting in degradation of the on-state current, S value, and frequency characteristics of the transistor 200B. However, the semiconductor device shown in this embodiment does not require a source electrode and a drain electrode formed of metal. Therefore, even if a high-temperature heat treatment is performed during the manufacturing process or a subsequent process of the transistor 200B, a semiconductor device with good on-state current, S value, and frequency characteristics can be provided. For example, the semiconductor device shown in this embodiment can be subjected to a process of applying a high temperature of approximately 750°C or higher and 800°C or lower after the transistor 200B is formed.

[0282] Furthermore, as described above, by adding an element that forms oxygen vacancies to the region 243 and performing heat treatment, the oxygen vacancies contained in the region 243 may capture hydrogen contained in the region 234 serving as a channel formation region. This can provide the transistor 200B with stable electrical characteristics and improve its reliability.

[0283] In addition, Figure 14A In the embodiment, the region 243 is formed near the interface between the oxide 230b and the insulator 254 in the thickness direction of the oxide 230b, but the present invention is not limited thereto. For example, the thickness of the region 243 may be substantially the same as the thickness of the oxide 230b, or the region 243 may be formed in the oxide 230a. Figure 14A In the embodiment, region 243 is formed only in region 231, but the present invention is not limited thereto. For example, region 243 may be formed in region 231 and region 232, or in part of region 231 and region 232, or in part of region 231, region 232, and region 234.

[0284] In oxide 230, it is sometimes difficult to clearly observe the boundaries between regions. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region do not necessarily change in stages for each region, but may change gradually (also called gradation) within each region. In other words, the concentrations of metal elements and impurity elements such as hydrogen and nitrogen may decrease as they approach the channel formation region.

[0285] In addition, if Figure 13BAs shown, an insulator 254 is preferably provided between the insulator 224, the oxides 230a and 230b, and the insulator 280. Here, the insulator 254 is preferably in contact with the top and side surfaces of the region 243a, the top and side surfaces of the region 243b, the side surfaces of the oxides 230a and 230b, the side surfaces of the insulator 224, and the top surface of the insulator 222. With this structure, the insulator 280 is separated from the insulator 224, the oxides 230a and 230b by the insulator 254. This prevents impurities such as hydrogen in the insulators 280 and 281 from entering the insulator 224, the oxides 230a and 230b.

[0286] Alternatively, insulator 254 may have a stacked structure including insulator 254a and insulator 254b. In this case, insulator 254a is preferably provided in contact with the top and side surfaces of region 243a, the top and side surfaces of region 243b, the side surfaces of oxide 230a and oxide 230b, the side surfaces of insulator 224, and the top surface of insulator 222. Insulator 254b is preferably provided on insulator 254a in contact with insulator 280. When insulator 254 has such a stacked structure, one of insulator 254a and insulator 254b may have a function of inhibiting hydrogen diffusion, while the other may have a function of inhibiting oxygen diffusion.

[0287] In addition, the insulator 254 a can have a function of supplying oxygen to the insulator 224 , the oxide 230 a , and the oxide 230 b .

[0288] The insulator 274 is in contact with the top surface of each of the conductor 260, the insulator 250, the oxide 230c, and the insulator 280. Figure 14A As shown, in the transistor 200B according to one embodiment of the present invention, the insulator 274 is in contact with the insulator 250. This structure can prevent impurities such as hydrogen in the insulator 281 and the like from entering the insulator 250. This can suppress negative effects on the electrical characteristics and reliability of the transistor.

[0289] in addition, Figure 14B Show Figure 13C An enlarged view of a portion of the transistor 200B is shown. Figure 13C and Figure 14BAs shown, in the channel width direction of transistor 200B, the bottom surface height of conductor 260 in the region where oxide 260 and oxide 230b do not overlap is preferably lower than the bottom surface height of oxide 230b, with reference to the bottom surface of insulator 222. By adopting a structure in which conductor 260, serving as a gate electrode, covers the side and top surfaces of oxide 230b in the channel formation region via oxide 230c and insulator 250, this structure facilitates the electric field of conductor 260 acting on the entire region 234 of oxide 230b. As a result, the on-state current of transistor 200B can be increased, thereby improving frequency characteristics. The difference between the bottom surface height of conductor 260 in the region where oxide 230a and oxide 230b do not overlap with conductor 260 and the bottom surface height of oxide 230b is denoted as T2, and T2 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, and more preferably 5 nm or more and 20 nm or less.

[0290] In addition, if Figure 14B As shown, in the channel width direction of transistor 200B, preferably, at least a portion of oxide 230c in a region that does not overlap with oxide 230b, oxide 230a, and insulator 224 is in contact with insulator 222. This structure prevents oxygen in oxide 230c from diffusing through insulator 224 to the outside of transistor 200B. Alternatively, oxygen in oxide 230b and oxide 230a from diffusing through insulator 224 to the outside of transistor 200B can be prevented. Alternatively, by reducing the area of ​​insulator 224, the amount of oxygen entering insulator 224 is reduced, thereby suppressing the reduction in the amount of oxygen supplied to oxide 230. As a result, oxygen in oxide 230c can be efficiently supplied to oxide 230b and oxide 230a, thereby suppressing the reduction in resistance of oxide 230 in region 234. This improves reliability while suppressing variations in transistor electrical characteristics and achieving stable electrical characteristics.

[0291] Alternatively, by adopting the above structure, it is possible to suppress the incorporation of impurities such as hydrogen in the insulator 224 into the oxide 230. In other words, it is possible to suppress the reduction in resistance of the oxide 230. This can suppress fluctuations in the electrical characteristics of the transistor, achieve stable electrical characteristics, and improve reliability. Alternatively, this structure can be formed by removing the insulator 224 from regions that do not overlap with the oxides 230b and 230a.

[0292] In addition, if Figure 14BAs shown, it is preferable to remove insulator 224 from regions that do not overlap with oxide 230b and oxide 230a, thereby forming insulator 224 into an island shape similar to oxide 230a and oxide 230b. This structure makes it easier to make the bottom surface of conductor 260 lower than the bottom surface of oxide 230b in regions where oxide 230a and oxide 230b do not overlap with conductor 260, relative to the bottom surface of insulator 222, in the channel width direction of transistor 200B. This increases the on-state current of transistor 200B, thereby improving frequency characteristics.

[0293] By adopting the above structure, a semiconductor device including a transistor with a large on-state current can be provided. Furthermore, a semiconductor device including a transistor with high frequency characteristics can be provided. Furthermore, a semiconductor device with improved reliability can be provided while suppressing fluctuations in electrical characteristics to achieve stable electrical characteristics. Furthermore, a semiconductor device including a transistor with a low off-state current can be provided.

[0294] The following describes a detailed structure of a semiconductor device including the transistor 200B according to one embodiment of the present invention. Details of components, materials, and the like of the semiconductor device described in this embodiment that are commonly used with those of the semiconductor device described in the previous embodiment, as well as details of components, materials, and the like with the same reference numerals, can be found in the description of the previous embodiment.

[0295] Oxide 230b and oxide 230c are preferably crystalline. For example, CAAC-OS is preferably used. Crystalline oxides such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (such as oxygen vacancies). Oxide 230b and oxide 230c stabilize transistor 200B against the high temperatures (thermal budget) encountered during the manufacturing process.

[0296] like Figure 13B and Figure 13C As shown, insulator 254 is preferably in contact with a portion of the side surfaces of oxide 230c, the top surface and side surfaces of region 243a, and the top surface and side surfaces of region 243b. In other words, insulator 254 is preferably in contact with a portion of the top surface and a portion of the side surfaces of oxide 230b, the side surfaces of oxide 230a, the side surfaces of insulator 224, and the top surface of insulator 222. With this structure, insulator 280 is separated from insulator 224 and oxide 230 by insulator 254. As a result, hydrogen in insulator 280 can be suppressed from diffusing from oxide 230a, oxide 230b, and the top surfaces or side surfaces of insulator 224 into oxide 230, thereby enabling transistor 200B to have good electrical characteristics and reliability.

[0297] As will be described later, insulator 254 can also be used as a protective film when forming regions 243a and 243b. When ion implantation or ion doping is used to form regions 243a and 243b, providing insulator 254 as a protective film prevents the surface of oxide 230 from being directly exposed to ions or plasma, thereby suppressing damage to oxide 230 during the formation of regions 243a and 243b. This is preferable. Damage to oxide 230 here refers to excessive formation of oxygen vacancies in oxide 230 or excessive reduction in the crystallinity of oxide 230. For example, insulator 254 can preferably include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or silicon oxide having pores.

[0298] In addition, in this embodiment, the insulator 254 has a stacked structure. When the insulator 254 has a stacked structure of an insulator 254a and an insulator 254b, for example, the insulator 254a can be formed by sputtering in an atmosphere containing oxygen, and then the insulator 254b can be formed by ALD. The ALD method is a film-forming method with good coverage, which can prevent the formation of disconnections caused by unevenness of the insulator 254a. Note that the insulator 254a and the insulator 254b can be made of the same material selected from the above materials, or different materials. For example, a stacked structure of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride and an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen can be used. In addition, as an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing an oxide of one or both of aluminum and hafnium can be used. Although FIG13 shows an example of an insulator 254 having a double-layer structure, it can also have a single-layer structure or a stacked structure of three or more layers.

[0299] The insulator 280 is provided on the insulator 222 , the insulator 224 , and the oxide 230 via the insulator 254 .

[0300] Furthermore, insulator 241a is provided in contact with the sidewalls of the openings of insulators 281, 274, 280, and 254, and a first conductor of conductor 240a is formed in contact with the side surfaces thereof. Region 243a is located at least partially at the bottom of the openings, and conductor 240a is in contact with region 243a. Similarly, insulator 241b is provided in contact with the sidewalls of the openings of insulators 281, 274, 280, and 254, and a first conductor of conductor 240b is formed in contact with the side surfaces thereof. Region 243b is located at least partially at the bottom of the openings, and conductor 240b is in contact with region 243b.

[0301] When a stacked structure is employed as the conductor 240 , a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen is preferably used as the conductor in contact with the oxide 230 a , the oxide 230 b , the insulator 254 , the insulator 280 , the insulator 274 , and the insulator 281 .

[0302] <Method for Manufacturing Semiconductor Device> Next, a method for manufacturing a semiconductor device including a transistor 200B according to one embodiment of the present invention shown in FIG13 will be described with reference to FIG15 to FIG22. In addition, in FIG15 to FIG22, A in each figure shows a top view. In addition, B in each figure shows a cross-sectional view corresponding to the portion indicated by the dotted line A1-A2 in A, which is also a cross-sectional view in the channel length direction of the transistor 200B. In addition, C in each figure shows a cross-sectional view corresponding to the portion indicated by the dotted line A3-A4 in A, which is also a cross-sectional view in the channel width direction of the transistor 200B. In addition, D in each figure shows a cross-sectional view corresponding to the portion indicated by the dotted line A5-A6 in A, which is also a cross-sectional view near the region 243b of the transistor 200B. Note that in the top view of each figure A, some components are omitted for clarity. In addition, note that detailed descriptions of the parts that are the same as those in embodiment 1 are omitted.

[0303] First, a substrate (not shown) is prepared, an insulator 214 is formed on the substrate, a conductor 205 and an insulator 216 are formed on the insulator 214, an insulator 222 is formed on the conductor 205 and the insulator 216, an insulating film 224A is formed on the insulator 222, and an oxide film 230A and an oxide film 230B are sequentially formed on the insulating film 224A (refer to FIG. 15 ).

[0304] Note that the steps up to the formation of the oxide film 230B in the method for manufacturing the semiconductor device including the transistor 200B are the same as those of the semiconductor device including the transistor 200 described in Embodiment 1, and therefore detailed description of the steps up to the formation of the oxide film 230B is omitted.

[0305] Next, the insulating film 224A, the oxide films 230A, and the oxide films 230B are processed into island shapes to form the insulator 224, the oxide 230a, and the oxide 230b. Note that in this step, the thickness of the insulator 222 may be reduced in regions that do not overlap with the insulator 224 (see FIG. 16 ).

[0306] Here, the insulator 224, oxide 230a, and oxide 230b are formed so that at least a portion thereof overlaps with the conductor 205. Furthermore, the side surfaces of the insulator 224, oxide 230a, and oxide 230b are preferably substantially perpendicular to the top surface of the insulator 222. When the side surfaces of the insulator 224, oxide 230a, and oxide 230b are substantially perpendicular to the top surface of the insulator 222, a smaller area and higher density can be achieved when multiple transistors 200B are provided. Alternatively, a structure can be employed in which the angle formed by the side surfaces of the insulator 224, oxide 230a, and oxide 230b and the top surface of the insulator 222 is relatively low. In this case, the angle formed by the side surfaces of the insulator 224, oxide 230a, and oxide 230b and the top surface of the insulator 222 is preferably greater than 60 degrees and less than 70 degrees. By adopting this shape, the coverage of the insulator 254 and the like is improved in the subsequent steps, and defects such as voids can be reduced.

[0307] In addition, a curved surface is formed between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the ends of the side surface and the top surface are preferably curved (hereinafter also referred to as rounded). For example, at the end of the oxide 230b, the curved surface has a radius of curvature of 3 nm to 10 nm, more preferably 5 nm to 6 nm. When the end does not have a corner, the coverage of the film in the subsequent film formation process can be improved.

[0308] The insulating film 224A, the oxide film 230A, and the oxide film 230B can be processed using photolithography. Dry etching or wet etching can be used for this processing. Dry etching is suitable for microfabrication. Furthermore, the insulating film 224A, the oxide film 230A, and the oxide film 230B can be formed using different conditions.

[0309] Furthermore, during dry etching or other processing, impurities caused by etching gas or the like may adhere to the surface of oxides 230a and 230b or diffuse into oxides 230a and 230b, etc. Examples of impurities include fluorine and chlorine.

[0310] Cleaning is performed to remove the impurities, etc. Examples of the cleaning method include wet cleaning using a cleaning liquid, plasma treatment using plasma, and cleaning using a heat treatment, and these cleaning methods may be appropriately combined.

[0311] As wet cleaning, an aqueous solution of oxalic acid, phosphoric acid, hydrofluoric acid, etc. diluted with carbonated water or pure water can be used for cleaning. Alternatively, pure water or carbonated water can be used for ultrasonic cleaning. In this embodiment, pure water or carbonated water is used for ultrasonic cleaning.

[0312] Next, heat treatment may also be performed. The heat treatment may adopt the conditions of the above-mentioned heat treatment. In addition, it is preferred to perform heat treatment before forming the insulating film 254A. The heat treatment is preferably performed at a temperature of 100°C or more and 400°C or less. For example, the heat treatment may be performed at a temperature of 200°C. Alternatively, it is preferably performed at the same temperature as the film forming temperature of the insulating film 254A. Here, the film forming temperature is used not only to indicate the substrate temperature when the film is formed, but also to indicate the set temperature of the film forming device. For example, when the insulating film 254A is formed at a temperature of 200°C, the temperature of the heat treatment is preferably 200°C. The heat treatment is preferably performed under reduced pressure, for example, in a vacuum atmosphere. The vacuum atmosphere is maintained by exhausting gas using a turbomolecular pump or the like. In a vacuum atmosphere, the pressure of the processing chamber is 1×10 -2 Pa or less, preferably 1×10 -3 Below Pa.

[0313] Next, an insulating film 254A, which serves as an insulator 254a, is formed over the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b (see FIG16 ). The insulating film 254A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For the insulating film 254A, an insulator that inhibits the permeation of impurities such as water and hydrogen, as well as oxygen, is preferably used. In this embodiment, a silicon nitride film is formed by sputtering.

[0314] Next, an insulating film 254B, which serves as an insulator 254b, is formed on the insulating film 254A (see FIG16 ). The insulating film 254B can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For the insulating film 254B, an insulator that inhibits the permeation of impurities such as water and hydrogen, as well as oxygen, is preferably used. For example, an aluminum oxide film is preferably formed using a sputtering method. By forming the aluminum oxide film using a sputtering method and a gas containing oxygen, oxygen can be introduced into the insulator 224. In other words, the insulator 224 can contain excess oxygen.

[0315] Alternatively, aluminum oxide may be formed while heating the substrate at a high temperature to form the insulating film 254B. The substrate heating temperature during the formation of the insulating film 254B may be 200° C. or higher, preferably 250° C. or higher, and more preferably 350° C. or higher. In this embodiment, the aluminum oxide film is formed by sputtering.

[0316] Next, a dummy gate film, which will become the dummy gate layer 262A, is formed on the insulating film 254B. This dummy gate film is processed and used as a dummy gate. A dummy gate is a virtual gate electrode. Specifically, the dummy gate film is processed to form a virtual gate electrode. This dummy gate is then removed in a subsequent step and replaced with a gate electrode formed of a conductive film or the like. Therefore, it is preferable to use a film that is easily microfabricated and easily removed as the dummy gate film.

[0317] The above-mentioned dummy gate film can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. For example, an insulator, a semiconductor, or a conductor can be used. Specifically, silicon films such as polycrystalline silicon, microcrystalline silicon, and amorphous silicon, and metal films such as aluminum, titanium, and tungsten can be used. In addition, a coating method can be used to form a film containing carbon, SOG (Spin On Glass), a resin film, etc. As materials for the resin film, for example, photoresist, polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate, acrylic resin, etc. can be cited. By forming SOG and a resin film by a coating method, the surface of the above-mentioned dummy gate film can be made flat. In this way, by making the surface of the dummy gate film flat, micro-machining and removal processing can be easily performed.

[0318] Furthermore, the dummy gate film can be a multilayer film composed of different types of films. For example, a two-layer structure consisting of a conductive film and a resin film on the conductive film can be used as the dummy gate film. Using a dummy gate film with such a structure allows the conductive film to be used as a stop film for the CMP process in a subsequent CMP step. Furthermore, since the end point of the CMP process can be detected, processing unevenness can be reduced.

[0319] Next, the dummy gate film is etched using photolithography to form a dummy gate layer 262A (see FIG. 17 ). At least a portion of the dummy gate layer 262A overlaps with the conductor 205 and the oxide 230 .

[0320] Next, the dopant 257 is added to the oxide 230b using the dummy gate layer 262A as a mask (see FIG. 17 ). As a result, the regions 243a and 243b containing the dopant 257 are formed in the regions of the oxide 230b that do not overlap with the dummy gate layer 262A. Note that FIG. 17 shows a case where the dopant 257 is not added to the region of the oxide 230b that overlaps with the dummy gate layer 262A. However, this embodiment is not limited to this. For example, sometimes the dopant 257 is diffused and added to the region that overlaps with the dummy gate layer 262A (e.g., Figure 14AIn this case, the region 243a and a portion of the region 243b are formed in a region overlapping with the dummy gate layer 262A. In this way, the distance between the region 243a and the region 243b, that is, the channel length, can be controlled.

[0321] As methods for adding dopant 257, the following can be used: ion implantation in which the ionized source gas is mass-separated and added; ion doping in which the ionized source gas is not mass-separated and added; and plasma immersion ion implantation. When mass separation is performed, the added ion species and their concentration can be strictly controlled. On the other hand, when mass separation is not performed, a high concentration of ions can be added in a short time. Alternatively, an ion doping method in which clusters of atoms or molecules are generated and ionized can be used. Note that dopants can also be referred to as ions, donors, acceptors, impurities, elements, etc.

[0322] As dopant 257, elements that form the above-mentioned oxygen defects or elements that bond to oxygen defects can be used. Typical examples of such elements are boron or phosphorus. In addition, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium and rare gases can be used. Typical examples of rare gases include helium, neon, argon, krypton and xenon. In addition, any one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum can be added. Among the above-mentioned metal elements, boron and phosphorus are preferably used as dopant 257. When boron and phosphorus are used as dopant 257, the equipment of the production line of amorphous silicon or low-temperature polysilicon can be used, thereby reducing equipment investment.

[0323] 17 , dopant 257 is added substantially perpendicularly to the top surface of insulator 214. However, the present invention is not limited thereto, and dopant 257 may be added obliquely to the top surface of insulator 214. By adding dopant obliquely to the top surface of insulator 214, region 243a and region 243b can be easily formed in a portion of the region overlapping with dummy gate layer 262A.

[0324] Furthermore, in the manufacturing method of this embodiment, dopant 257 is added to oxide 230 via insulating film 254A and insulating film 254B. Due to this manufacturing method, dopant 257 is also added to insulating film 254A and insulating film 254B. That is, oxide 230 and insulating films 254A and 254B all contain the element included in dopant 257. Furthermore, if insulating film 254A and insulating film 254B contain excess oxygen, dopant 257 may suppress diffusion of the excess oxygen to the outside.

[0325] By forming the region 243 as described above, the conductor 260 to be formed in a subsequent step can be arranged in a self-aligned manner between the region 243 a and the region 243 b .

[0326] Next, an insulating film 280A (see FIG. 18 ) serving as the insulator 280 is formed over the insulating film 254B and the dummy gate layer 262A. The insulating film 280A can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0327] Next, the insulating film 280A and a portion of the dummy gate layer 262A are removed until a portion of the dummy gate layer 262A is exposed, thereby forming the insulator 280 and the dummy gate 262 (see FIG. 19 ). The insulator 280 and the dummy gate 262 are preferably formed by CMP.

[0328] Furthermore, for example, by using a film having a structure of a first layer and a second layer formed on the first layer as the dummy gate layer 262A, the first layer can be used as a stop film for the CMP process in some cases. In addition, since the end point of the CMP process of the first layer can be detected, the unevenness of the height of the dummy gate 262 can be reduced. Figure 19B As shown, the top surface of the dummy gate 262 and the top surface of the insulator 280 are substantially consistent.

[0329] Next, the dummy gate 262 and a portion of the insulating film 254A and the insulating film 254B overlapping with the dummy gate 262 are removed to form an opening 263 (refer to FIG20 ). The dummy gate 262, the insulating film 254A, and the insulating film 254B can be removed by performing a process such as wet etching, dry etching, or ashing. Alternatively, the above-mentioned processes can be appropriately combined. For example, a wet etching process can also be performed after ashing. Insulators 254a and 254b are formed by removing a portion of the insulating film 254A and the insulating film 254B. By removing the dummy gate 262, the insulating film 254A, and the insulating film 254B, a portion of the surface of the oxide 230b is exposed from the opening 263. At this time, it is possible that a portion of the surface of the region 243 is exposed from the opening 263.

[0330] Next, it is preferred to perform heat treatment before forming the oxide film 230C1. The heat treatment is preferably performed at a temperature of 100°C or more and 400°C or less. For example, the heat treatment can be performed at a temperature of 200°C. Alternatively, it is preferably performed at the same temperature as the film forming temperature of the oxide film 230C1 or the oxide film 230C2. Here, the film forming temperature is used not only to indicate the substrate temperature when the film is formed, but also to indicate the set temperature of the film forming device. For example, when the oxide film 230C1 or the oxide film 230C2 is formed at a temperature of 300°C, the temperature of the heat treatment is preferably 300°C. The heat treatment is preferably performed under reduced pressure, for example, it can also be performed in a vacuum atmosphere. The vacuum atmosphere is maintained by exhausting the gas using a turbomolecular pump or the like. In the vacuum atmosphere, the pressure of the processing chamber is 1×10 -2 Pa or less, preferably 1×10 -3 Below Pa.

[0331] Next, an oxide film 230C1 and an oxide film 230C2 are formed in sequence in such a manner as to embed the opening 263 (refer to FIG. 21 ). In addition, it is preferred that the oxide film 230C1 and the oxide film 230C2 are formed continuously without being exposed to the atmosphere after the above-mentioned heat treatment. For example, it is preferred that the heat treatment and the film forming treatment be performed continuously in different treatment chambers using the following multi-chamber film forming apparatus. By performing such a treatment, impurities such as moisture, hydrogen, and carbon adsorbed on the surfaces of the oxide 230a and the oxide 230b can be removed to further reduce the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b. The impurities removed by the heat treatment include impurities including bonds between hydrogen and carbon or impurities including bonds between hydrogen and oxygen. Furthermore, by performing the heat treatment and the film forming treatment continuously without being exposed to the outside air, impurities such as hydrogen can be prevented from invading the oxide 230 again.

[0332] Oxide films 230C1 and 230C2 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The oxide films forming oxide films 230C1 and 230C2 can be formed using the same film formation method as oxide films 230A and 230B, depending on the desired properties of oxide films 230C1 and 230C2. In-Ga-Zn oxide or an oxide that does not contain In can be used as oxide films 230C1 and 230C2. As an oxide that does not contain In, Ga-Zn oxide or gallium oxide can be used. Alternatively, a stacked structure of In-Ga-Zn oxide and an oxide that does not contain In can be used as oxide films 230C1 and 230C2. The oxide film 230C1 and the oxide film 230C2 are formed by sputtering using an oxide target having an In:Ga:Zn ratio of 1:3:4, an In:Ga:Zn ratio of 4:2:4.1, a Ga:Zn ratio of 2:1, or a Ga:Zn ratio of 2:5. In this embodiment, the oxide film 230C1 is formed by sputtering using an oxide target having an In:Ga:Zn ratio of 4:2:4.1, and the oxide film 230C2 is formed by sputtering using an oxide target having an In:Ga:Zn ratio of 1:3:4.

[0333] That is, the oxide film 230C1 can be formed using the same target as that used to form the oxide film 230B, and the oxide film 230C2 can be formed using the same target as that used to form the oxide film 230A.

[0334] The oxide films 230C1 and 230C2 are preferably formed while the substrate is heated. Setting the substrate temperature to 300°C or higher can reduce oxygen vacancies in the oxides 230a and 230b, as well as the oxide films 230C1 and 230C2. Furthermore, for example, the oxides 230a and 230b can be formed at the same temperature as the insulating film 250A described later. By forming the films while the substrate is heated, the crystallinity of the oxides 230a and 230b, as well as the oxide films 230C1 and 230C2, can also be improved.

[0335] In particular, during the formation of oxide films 230C1 and 230C2, some of the oxygen contained in the sputtering gas may be supplied to oxides 230a and 230b. Therefore, the oxygen content of the sputtering gas for oxide films 230C1 and 230C2 may be 70% or greater, preferably 80% or greater, and more preferably 100%. Furthermore, by heating the substrate while forming the films, the crystallinity of the oxide films can be improved.

[0336] Next, it is preferred to perform heat treatment before forming the insulating film 250A. The heat treatment is preferably performed at a temperature of 100°C or higher and 400°C or lower. For example, the heat treatment can be performed at a temperature of 200°C. Alternatively, it is preferably performed at the same temperature as the film forming temperature of the insulating film 250A. Here, the film forming temperature is used not only to indicate the substrate temperature when the film is formed, but also to indicate the set temperature of the film forming device. For example, when the insulating film 250A is formed at a temperature of 350°C, the temperature of the heat treatment is preferably 350°C. The heat treatment is preferably performed under reduced pressure, for example, it can also be performed in a vacuum atmosphere. The vacuum atmosphere is maintained by exhausting the air using a turbomolecular pump or the like. In the vacuum atmosphere, the pressure of the processing chamber is 1×10 -2 Pa or less, preferably 1×10 -3 Below Pa.

[0337] Next, an insulating film 250A is formed (see FIG21 ). The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 250A, it is preferable to form silicon oxide, hafnium oxide, gallium oxide, or the like by the ALD method. For example, as the insulating film 250A, a stacked film of silicon oxide and gallium oxide on silicon oxide can be used. Note that the film formation temperature when forming the insulating film 250A is preferably 300°C or higher and lower than 450°C, and preferably 350°C or higher and lower than 400°C. For example, by forming the insulating film 250A at a temperature of 400°C, a dense film with few impurities can be formed.

[0338] Alternatively, by exciting oxygen with microwaves to generate high-density oxygen plasma and exposing the insulating film 250A to the oxygen plasma, oxygen can be introduced into the insulating film 250A.

[0339] Alternatively, heat treatment may be performed. The heat treatment conditions described above may be used for the heat treatment. This heat treatment can reduce the water concentration and hydrogen concentration in the insulating film 250A.

[0340] Next, a conductive film 260A and a conductive film 260B are formed. The conductive film 260A and the conductive film 260B can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, CVD is preferably used. In this embodiment, the conductive film 260A is formed by ALD, and the conductive film 260B is formed by CVD (see FIG. 21 ).

[0341] Next, oxide film 230C1, oxide film 230C2, insulating film 250A, conductive film 260A, and conductive film 260B are polished by CMP until insulator 280 is exposed, thereby forming oxide 230c (oxide 230c1 and oxide 230c2), insulator 250, and conductor 260 (conductor 260a and conductor 260b) (see FIG. 22 ). Thus, oxide 230c is arranged so as to cover the inner walls (side walls and bottom surface) of the opening that reaches oxide 230b. Insulator 250 is arranged so as to cover the inner walls of the opening via oxide 230c. Furthermore, conductor 260 is arranged so as to fit into the opening via oxide 230c and insulator 250.

[0342] Next, heat treatment may also be performed. The heat treatment is preferably performed at a temperature of 100°C or more and 400°C or less. For example, the heat treatment may be performed at a temperature of 200°C. Alternatively, it is preferably performed at the same temperature as the film forming temperature of the insulator 274. Here, the film forming temperature is used not only to indicate the substrate temperature when the film is formed, but also to indicate the set temperature of the film forming device. For example, when the insulator 274 is formed at a temperature of 250°C, the temperature of the heat treatment is preferably 250°C. The heat treatment is preferably performed under reduced pressure, for example, in a vacuum atmosphere. The vacuum atmosphere is maintained by exhausting gas using a turbomolecular pump or the like. In a vacuum atmosphere, the pressure of the processing chamber is 1×10 -2 Pa or less, preferably 1×10 -3 Pa or less. This heat treatment can reduce the water concentration and hydrogen concentration in the insulator 280 .

[0343] Next, an insulator 274 can be formed on the oxide 230c, the insulator 250, the conductor 260, and the insulator 280. The film formation of the insulator 274 can be performed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, the insulator 274 is preferably formed by sputtering as an aluminum oxide film. Sputtering as an aluminum oxide film can sometimes suppress the diffusion of hydrogen in the insulator 281 into the oxide 230. Furthermore, forming the insulator 274 in contact with the conductor 260 is preferred because it can suppress oxidation of the conductor 260. Furthermore, forming the insulator 274 allows oxygen to be supplied to the insulator 280. The oxygen supplied to the insulator 280 can sometimes be supplied to the region 234 in the oxide 230b via the oxide 230c1. In addition, by supplying oxygen to the insulator 280 , oxygen contained in the insulator 280 before the insulator 274 is formed may be supplied to the region 234 in the oxide 230 b through the oxide 230 c 1 .

[0344] Next, a heat treatment may be performed. The heat treatment conditions described above may be used. This heat treatment can reduce the water concentration and hydrogen concentration of insulator 280. Furthermore, oxygen in insulator 274 can be implanted into insulator 280.

[0345] Alternatively, as a method for forming insulator 274 on insulator 280, an insulating film made of the same material as insulator 274 is first formed using the same method as insulator 274, followed by heat treatment using the aforementioned heat treatment conditions. This insulating film is then removed by CMP, and insulator 274 is then formed, which can then be heat treated using the aforementioned heat treatment conditions. This method can form an excess oxygen region in insulator 280. Note that during this step of removing the insulating film, portions of insulator 280, conductor 260, insulator 250, and oxide 230c may be removed.

[0346] Alternatively, an insulator may be provided between insulator 280 and insulator 274. For example, silicon oxide formed by sputtering may be used as the insulator. Providing the insulator allows for the formation of an excess oxygen region in insulator 280.

[0347] Next, an insulator 281 serving as an insulating film may be formed on the insulator 274. The insulator 281 serving as the insulating film may be formed by sputtering, CVD, MBE, PLD, ALD, or the like (see FIG. 22 ).

[0348] Next, openings reaching the regions 243a and 243b are formed in the insulators 254, 280, 274, and 281. The openings may be formed using photolithography.

[0349] Note that in the semiconductor device including the transistor 200B, steps after the formation of the opening are the same as those of the semiconductor device including the transistor 200 described in Embodiment 1, and thus detailed description of the steps after the formation of the opening is omitted.

[0350] According to one embodiment of the present invention, a semiconductor device having a large on-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having high reliability can be provided. In addition, according to one embodiment of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having a small off-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having reduced power consumption can be provided. In addition, according to one embodiment of the present invention, a semiconductor device having high productivity can be provided.

[0351] As described above, the structure, method, etc. described in this embodiment can be implemented in combination with the structure, method, etc. described in other embodiments as appropriate.

[0352] (Implementation 3) In this embodiment, referring to Figures 23 to 26 One embodiment of a semiconductor device will be described.

[0353] [Storage device 1] Figure 23 An example of a semiconductor device (memory device) using a transistor as one embodiment of the present invention is shown. In the semiconductor device as one embodiment of the present invention, transistor 200 is provided above transistor 300, and capacitor 100 is provided above transistor 300 and transistor 200. The transistor 200 described in the above embodiment, for example, can be used as transistor 200.

[0354] Transistor 200 is a transistor whose channel is formed in a semiconductor layer containing an oxide semiconductor. Because transistor 200 has a low off-state current, its use in a memory device allows for long-term retention of stored data. In other words, since refresh operations are unnecessary or performed at an extremely low frequency, the memory device's power consumption can be significantly reduced.

[0355] exist Figure 23In the semiconductor device shown, wiring 1001 is electrically connected to the source of transistor 300, and wiring 1002 is electrically connected to the drain of transistor 300. Furthermore, wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the first gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Furthermore, the gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one electrode of capacitor 100, and wiring 1005 is electrically connected to the other electrode of capacitor 100. Note that hereinafter, the node where the gate of transistor 300, the other of the source and drain of transistor 200, and one of the electrodes of capacitor 100 are connected may be referred to as node FG.

[0356] Figure 23 The semiconductor device shown has a characteristic of being able to hold the potential of the gate (node ​​FG) of the transistor 300 by the switching of the transistor 200 , and thus data can be written, held, and read.

[0357] In addition, by Figure 23 The memory devices shown are arranged in a matrix to form a memory cell array.

[0358] <Transistor 300> Transistor 300 is provided on substrate 311 and includes a conductor 316 serving as a gate electrode, an insulator 315 serving as a gate insulator, a semiconductor region 313 comprising a portion of substrate 311, and low-resistance regions 314a and 314b serving as source and drain regions. Transistor 300 may be a p-channel transistor or an n-channel transistor.

[0359] Here, in Figure 23 In the transistor 300 shown, the semiconductor region 313 (a part of the substrate 311) forming the channel has a convex shape. In addition, a conductor 316 is provided in a manner that covers the side and top surfaces of the semiconductor region 313 via an insulator 315. In addition, the conductor 316 can use a material that adjusts the work function. Because the convex portion of the semiconductor substrate is utilized, this transistor 300 is also called a FIN-type transistor. In addition, an insulator for forming a mask for the convex portion can also be provided in a manner that contacts the upper surface of the convex portion. In addition, although a case where a part of the semiconductor substrate is processed to form the convex portion is shown here, an SOI substrate can also be processed to form a semiconductor film having a convex shape.

[0360] Notice, Figure 23 The structure of the transistor 300 shown is only an example and is not limited to the above structure. An appropriate transistor may be used according to the circuit structure or driving method.

[0361] <Capacitor 100> The capacitor 100 is disposed above the transistor 200. The capacitor 100 includes a conductor 110 serving as a first electrode, a conductor 120 serving as a second electrode, and an insulator 130 serving as a dielectric.

[0362] Alternatively, for example, the conductor 112 provided on the conductor 240 may be formed simultaneously with the conductor 110. The conductor 112 serves as a plug or wiring for electrically connecting the capacitor 100, the transistor 200, or the transistor 300.

[0363] exist Figure 23 In the embodiment, the conductor 112 and the conductor 110 have a single-layer structure, but the structure is not limited thereto and a stacked structure of two or more layers may be used. For example, a conductor having high adhesion to the conductor with barrier properties and the conductor with high conductivity may be formed between the conductor with barrier properties and the conductor with high conductivity.

[0364] In addition, the insulator 130 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or the like, and can be provided in a stacked layer or a single layer.

[0365] For example, insulator 130 preferably comprises a laminated structure of a material having a high dielectric strength such as silicon oxynitride and a high dielectric constant (high-k) material. This structure allows capacitor 100 to include a high dielectric constant (high-k) insulator to ensure sufficient capacitance and an insulator having a high dielectric strength to improve the dielectric strength, thereby suppressing electrostatic breakdown of capacitor 100.

[0366] Note that insulators that are high-k materials (materials with a relatively high dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, nitrides containing silicon and hafnium, and the like.

[0367] On the other hand, materials with high insulation withstand voltage (materials with low relative dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-added silicon oxide, carbon-added silicon oxide, carbon and nitrogen-added silicon oxide, silicon oxide with pores, resins, etc.

[0368] <Wiring Layer> A wiring layer, including interlayer films, wiring, plugs, etc., may also be provided between the various structures. Furthermore, the wiring layer may be provided in multiple layers depending on the design. Here, in a conductor that functions as a plug or wiring, the same reference numeral may sometimes be used to represent multiple structures. Furthermore, in this specification and other text, a wiring and a plug electrically connected to the wiring may also be considered a single component. That is, a portion of a conductor may sometimes function as wiring, and a portion of the conductor may sometimes function as a plug.

[0369] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on a substrate 311. An insulator 315 and a conductor 316 are provided so as to be embedded in the insulator 320. Furthermore, conductors 328 and 330, etc., which are electrically connected to the capacitor 100 or the transistor 200, are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 serve as plugs or wiring.

[0370] Alternatively, the insulator used as an interlayer film may be used as a planarization film to cover the concavo-convex shape thereunder. For example, to improve the flatness of the top surface of the insulator 322, planarization may be achieved by a planarization process such as chemical mechanical polishing (CMP).

[0371] A wiring layer may be provided on the insulator 326 and the conductor 330. Figure 23 Insulator 350, insulator 352, and insulator 354 are stacked in this order. In addition, conductor 356 is formed in insulator 350, insulator 352, and insulator 354. Conductor 356 serves as a plug or wiring.

[0372] Insulator 210, insulator 212, insulator 214, and insulator 216 are stacked in this order on insulator 354 and conductor 356. Furthermore, conductor 218 and the conductor (conductor 205) constituting transistor 200 are embedded in insulator 210, insulator 212, insulator 214, and insulator 216. Conductor 218 serves as a plug or wiring for electrically connecting capacitor 100 or transistor 300. Furthermore, insulator 150 is provided on conductor 120 and insulator 130.

[0373] Examples of insulators that can be used as the interlayer film include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0374] For example, by using a material with a low relative dielectric constant for an insulator used as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select a material based on the function of the insulator.

[0375] For example, insulator 212, insulator 352 and insulator 354 preferably have an insulator with a low relative dielectric constant. For example, the insulator preferably contains silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide with pores, resin, etc. Alternatively, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, or silicon oxide with pores and resin. Since silicon oxide and silicon oxynitride have thermal stability, by combining them with resin, a laminated structure with thermal stability and a low relative dielectric constant can be achieved. As resins, for example, polyesters, polyolefins, polyamides (nylon, aromatic polyamide, etc.), polyimides, polycarbonates, acrylic resins, etc. can be cited.

[0376] In addition, the resistivity of one or both of the insulator 130 and the insulator 150 provided on the conductor 112 or the conductor 120 is 1.0×10 12 Ωcm or more and 1.0×10 15 Ωcm or less, preferably 5.0×10 12 Ωcm or more and 1.0×10 14 Ωcm or less, more preferably 1.0×10 13 Ωcm or more and 5.0×10 13 An insulator with a resistivity of Ωcm or less. When one or both of insulator 130 and insulator 150 have this resistivity, the insulator preferably disperses charge between the wiring of accumulation transistor 200, transistor 300, capacitor 100, and conductors 112 and 120 while maintaining insulation properties. This can suppress characteristic defects and electrostatic damage in the transistors and memory devices including these transistors caused by this charge. Silicon nitride or silicon oxynitride can be used as the insulator.

[0377] Alternatively, as an insulator having the aforementioned resistivity, insulator 140 may be provided as a layer below conductor 112. In this case, insulator 140 is formed on insulator 281, and openings are formed in insulator 140, insulator 281, insulator 274, insulator 280, insulator 254, and the like. Insulator 241 is formed within the openings, thereby forming conductor 240 electrically connected to transistor 200, conductor 218, and the like. Insulator 140 can be made of the same material as insulator 130 or insulator 150.

[0378] Furthermore, by surrounding a transistor using an oxide semiconductor with an insulator that inhibits the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, insulators that inhibit the permeation of impurities such as hydrogen and oxygen can be used as insulators 210 and 350.

[0379] As an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or a stacked layer. Specifically, as an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon oxynitride, and silicon nitride can be used.

[0380] As conductors that can be used for wiring and plugs, preferably used are materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium. Alternatively, highly conductive semiconductors, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may be used.

[0381] For example, as conductor 328, conductor 330, conductor 356, conductor 218, conductor 110, conductor 112, and conductor 120, conductive materials such as metal materials, alloy materials, metal nitride materials, and metal oxide materials formed from the above materials can be used in a single layer or a stacked layer. Preferably, a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity is used, with tungsten being particularly preferred. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, wiring resistance can be reduced.

[0382] <<Wiring or plug provided with an oxide semiconductor layer>> Note that when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In this case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and the conductor provided therewith.

[0383] For example, in Figure 23 In the embodiment, it is preferable to provide insulator 241 between insulators 280 and 281 and conductor 240. Since insulator 241 exists between insulators 280 and 281 and conductor 240, it is possible to suppress conductor 240 from absorbing oxygen contained in insulators 280 and 281, that is, oxidation of conductor 240.

[0384] That is, the insulator 241 can be provided to suppress excess oxygen contained in the insulator 280 from being absorbed by the conductor 240. Furthermore, the insulator 241 can suppress diffusion of hydrogen as an impurity into the transistor 200 through the conductor 240.

[0385] Insulator 241 is preferably an insulating material that has the function of inhibiting the diffusion of impurities such as water and hydrogen, as well as oxygen. For example, aluminum oxide or hafnium oxide is preferably used. Alternatively, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, silicon oxynitride, and silicon nitride may be used.

[0386] The above is a description of a structural example. By adopting this structure, it is possible to suppress variations in electrical characteristics while improving reliability in a semiconductor device using a transistor containing an oxide semiconductor. Furthermore, it is possible to provide a transistor containing an oxide semiconductor with a large on-state current. Furthermore, it is possible to provide a transistor containing an oxide semiconductor with a small off-state current. Furthermore, it is possible to provide a semiconductor device with reduced power consumption.

[0387] [Storage device 2] Figure 24 An example of a semiconductor device (memory device) using a transistor as one embodiment of the present invention is shown. In the semiconductor device as one embodiment of the present invention, transistor 200 is provided above transistor 300, and capacitor 100 is provided above transistor 300 and transistor 200. Alternatively, transistor 200B described in the above embodiment mode can be used as transistor 200.

[0388] Note that in the semiconductor device (memory device) shown in [memory device 2], components having the same functions as those constituting the semiconductor device (memory device) shown in [memory device 1] are denoted by the same reference numerals. For detailed descriptions of the structure, materials, etc. of the semiconductor device (memory device) shown in [memory device 2] that are common to those of the semiconductor device (memory device) shown in [memory device 1], as well as for detailed descriptions of components and materials denoted by the same reference numerals, refer to the previous description.

[0389] [Storage device 3] Figure 25 An example of a memory device using a semiconductor device as one embodiment of the present invention will be described. Figure 25 The storage device shown includes Figure 23 The semiconductor device including the transistor 200 , the transistor 300 , and the capacitor 100 further includes a transistor 400 .

[0390] Transistor 400 can control the second gate voltage of transistor 200. For example, a structure is employed in which the first and second gates of transistor 400 are diode-connected to the source, and the source of transistor 400 is connected to the second gate of transistor 200. In this structure, when the second gate of transistor 200 is held at a negative potential, the voltage between the first gate and the source of transistor 400 and the voltage between the second gate and the source of transistor 400 become 0V. In transistor 400, since the drain current is very small when the second gate voltage and the first gate voltage are 0V, the negative potential of the second gate of transistor 200 can be maintained for a long time even when power is not supplied to transistors 200 and 400. As a result, a memory device including transistors 200 and 400 can retain stored data for a long period of time.

[0391] Therefore, in Figure 25 In FIG. 1 , wiring 1001 is electrically connected to the source of transistor 300, and wiring 1002 is electrically connected to the drain of transistor 300. Furthermore, wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Furthermore, the gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one electrode of capacitor 100, and wiring 1005 is electrically connected to the other electrode of capacitor 100. Wiring 1007 is electrically connected to the source of transistor 400, wiring 1008 is electrically connected to the gate of transistor 400, wiring 1009 is electrically connected to the second gate of transistor 400, and wiring 1010 is electrically connected to the drain of transistor 400. Here, wiring 1006, wiring 1007, wiring 1008, and wiring 1009 are electrically connected.

[0392] In addition, by Figure 25 The storage device shown is Figure 23 The memory device shown is similarly arranged in a matrix to form a memory cell array. Note that one transistor 400 can control the second gate voltages of multiple transistors 200. Therefore, it is preferable to have fewer transistors 400 than transistors 200.

[0393] <Transistor 400> Transistor 400 is formed on the same layer as transistor 200, allowing them to be manufactured simultaneously. Transistor 400 includes: conductor 460 (conductor 460a and conductor 460b) serving as a first gate electrode; conductor 405 (conductor 405a and conductor 405b) serving as a second gate electrode; insulator 222, insulator 424a, insulator 424b, and insulator 450 serving as gate insulators; oxide 430c including a region forming a channel; conductor 442a, oxide 431a, and oxide 431b serving as one of a source and a drain; conductor 442b, oxide 432a, and oxide 432b serving as the other of the source and drain; and conductor 440 (conductor 440a and conductor 440b).

[0394] In transistor 400, conductor 405 is formed in the same layer as conductor 205. Insulators 424a and 424b are formed in the same layer as insulator 224. Oxide 431a and 432a are formed in the same layer as oxide 230a, and oxide 431b and 432b are formed in the same layer as oxide 230b. Conductor 442 is formed in the same layer as conductor 242. Oxide 430c is formed in the same layer as oxide 230c. Insulator 450 is formed in the same layer as insulator 250. Conductor 460 is formed in the same layer as conductor 260.

[0395] Note that structures formed in the same layer may be formed simultaneously. For example, the oxide 430 c may be formed by processing an oxide film to be the oxide 230 c.

[0396] Similar to the oxide 230 and the like, oxygen vacancies and impurities such as water and hydrogen are reduced in the oxide 430c used as the active layer of the transistor 400. Therefore, the threshold voltage of the transistor 400 can be increased, the off-state current can be reduced, and the drain current can be made very small when the second gate voltage and the first gate voltage are 0 V.

[0397] Cutting Line The following describes the dicing lines (also called dividing lines, splitting lines, or cutting lines) used when dividing a large-area substrate into individual semiconductor elements to obtain multiple chip-shaped semiconductor devices. In some cases, for example, the dicing method involves first forming grooves (dicing lines) in the substrate to separate the semiconductor elements. The substrate is then cut along the dicing lines to obtain multiple separated (divided) semiconductor devices.

[0398] At the edges of the transistor 200 described in the above embodiment and the transistor 400 described in this embodiment, as shown in FIG. Figure 25As shown, insulator 254 and insulator 222 are in contact. Therefore, if the design is such that the area where insulator 254 and insulator 222 contact serves as the cut line, the design freedom of the cut line can be increased. In this case, insulator 222 and insulator 254 can also be formed using the same material and the same method. By forming insulator 222 and insulator 254 using the same material and the same method, the tightness can be improved. For example, aluminum oxide is preferably used.

[0399] With this structure, the insulator 222 and the insulator 254 can surround the insulator 224, the transistor 200, and the transistor 400. Since the insulator 222 and the insulator 254 have the function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is divided into multiple chips for each circuit region in which the semiconductor element described in this embodiment is formed, impurities such as water and hydrogen can be prevented from entering from the side surfaces of the divided substrate and diffusing into the transistor 200 or the transistor 400.

[0400] By adopting this structure, excess oxygen in the insulator 224 can be prevented from diffusing to the outside of the insulator 254 and the insulator 222. Therefore, the excess oxygen in the insulator 224 is efficiently supplied to the oxide forming the channel of the transistor 200 or the transistor 400. This oxygen can reduce oxygen vacancies in the oxide forming the channel of the transistor 200 or the transistor 400. As a result, the oxide forming the channel of the transistor 200 or the transistor 400 can be made into an oxide semiconductor with a low defect state density and stable characteristics. In other words, it is possible to improve reliability while suppressing fluctuations in the electrical characteristics of the transistor 200 or the transistor 400.

[0401] [Storage device 4] Figure 26 An example of a memory device using a semiconductor device as one embodiment of the present invention will be described. Figure 26 The storage device shown includes Figure 24 The semiconductor device including the transistor 200 , the transistor 300 , and the capacitor 100 further includes a transistor 400 .

[0402] Note that in the storage device shown in [Storage device 4], components having the same functions as those constituting the storage device shown in [Storage device 3] are denoted by the same reference numerals. For detailed descriptions of the structure, materials, etc. of the storage device shown in [Storage device 4] that are common to those of the storage device shown in [Storage device 3], as well as for detailed descriptions of components and materials denoted by the same reference numerals, refer to the preceding description.

[0403] <Transistor 400> Transistor 400 is formed on the same layer as transistor 200, allowing them to be manufactured simultaneously. Transistor 400 includes: a conductor 460 (conductors 460a and 460b) serving as a first gate electrode; a conductor 405 (conductors 405a and 405b) serving as a second gate electrode; insulators 222, 424a, 424b, and 450 serving as gate insulators; an oxide 430c (oxide 430c1 and oxide 403c2) including a region forming a channel; a region 443a, oxide 431a, and oxide 431b serving as one of a source and a drain; a region 443b, oxide 432a, and oxide 432b serving as the other of a source and a drain; and a conductor 440 (conductors 440a and 440b).

[0404] In transistor 400, conductor 405 is formed in the same layer as conductor 205. Insulators 424a and 424b are formed in the same layer as insulator 224. Oxide 431a and 432a are formed in the same layer as oxide 230a. Oxide 431b and 432b are formed in the same layer as oxide 230b. Regions 443a and 443b are formed using the same process as regions 243a and 243b. Oxide 430c1 and 430c2 are formed in the same layer as oxide 230c1 and oxide 230c2, respectively. Insulator 450 is formed in the same layer as insulator 250. Conductor 460 is formed in the same layer as conductor 260.

[0405] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0406] (Implementation 4) In this embodiment, a memory device using a transistor using an oxide for a semiconductor (hereinafter sometimes referred to as an OS transistor) and a capacitor (hereinafter sometimes referred to as an OS memory device) according to one embodiment of the present invention is described with reference to Figures 27 and 28. The OS memory device includes at least a capacitor and an OS transistor that controls the charging and discharging of the capacitor. Because the off-state current of the OS transistor is extremely low, the OS memory device has excellent retention characteristics and can be used as a nonvolatile memory.

[0407] <Configuration Example of Storage Device> Figure 27A An example of the structure of an OS memory device is shown. The memory device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

[0408] Column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit precharges the wiring. The sense amplifier amplifies the data signal read from the memory cell. Note that the wiring described above is connected to the memory cells included in memory cell array 1470, and its details are described below. The amplified data signal is output as data signal RDATA to the outside of memory device 1400 via output circuit 1440. Furthermore, row circuit 1420 includes, for example, a row decoder and a word line driver circuit, and is capable of selecting the row to be accessed.

[0409] The memory device 1400 is externally supplied with a low power supply voltage (VSS) as a power supply voltage, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470. Furthermore, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are externally input to the memory device 1400. The address signal ADDR is input to the row decoder and the column decoder, and the data signal WDATA is input to the write circuit.

[0410] Control logic circuit 1460 processes external control signals (CE, WE, RE) to generate control signals for the row decoder and column decoder. Control signal CE is a chip enable signal, control signal WE is a write enable signal, and control signal RE is a read enable signal. The signals processed by control logic circuit 1460 are not limited to these; other control signals may be input as needed.

[0411] The memory cell array 1470 includes a plurality of memory cells MC arranged in rows and columns and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 depends on the structure of the memory cell MCs, the number of memory cells MCs included in a column, and other factors. Furthermore, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 depends on the structure of the memory cell MCs, the number of memory cells MCs included in a row, and other factors.

[0412] In addition, although Figure 27A 14 shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, but this embodiment is not limited thereto. Figure 27B As shown, the memory cell array 1470 may be provided so as to overlap a portion of the peripheral circuit 1411. For example, a structure in which a sense amplifier is provided so as to overlap below the memory cell array 1470 may be employed.

[0413] FIG28 illustrates a structural example of a memory cell that can be applied to the above-described memory cell MC.

[0414] [DOSRAM] Figures 28A to 28C An example of a circuit structure of a DRAM memory cell is shown. In this specification, etc., a DRAM using a 1-OS transistor 1-capacitor type memory cell is sometimes referred to as a DOSRAM. Figure 28A The memory cell 1471 shown includes a transistor M1 and a capacitor CA. In addition, transistor M1 includes a gate (sometimes referred to as a top gate) and a back gate.

[0415] A first terminal of transistor M1 is connected to a first terminal of capacitor CA, a second terminal of transistor M1 is connected to wiring BIL, a gate of transistor M1 is connected to wiring WOL, and a back gate of transistor M1 is connected to wiring BGL. A second terminal of capacitor CA is connected to wiring CAL.

[0416] Wiring BIL serves as a bit line, and wiring WOL serves as a word line. Wiring CAL is used to apply a specified potential to the second terminal of capacitor CA. When writing or reading data, a low-level potential is preferably applied to wiring CAL. Wiring BGL is used to apply a potential to the back gate of transistor M1. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased.

[0417] In addition, the memory cell MC is not limited to the memory cell 1471, and its circuit structure can be changed. For example, the memory cell MC can also be used as follows Figure 28B The back gate of the transistor M1 is not connected to the wiring BGL but to the wiring WOL as in the memory cell 1472 shown in FIG. Figure 28C The memory cell 1473 shown is a memory cell composed of a transistor with a single gate structure, that is, a transistor M1 that does not include a back gate.

[0418] When the semiconductor device described in the above embodiment is used in the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be minimized. In other words, because the transistor M1 can retain written data for a long time, the refresh frequency of the memory cell can be reduced. In addition, the memory cell refresh operation can be omitted. In addition, because the leakage current is extremely low, multi-valued data or analog data can be retained in the memory cells 1471, 1472, and 1473.

[0419] Furthermore, in DOSRAM, when a sense amplifier is provided so as to overlap below the memory cell array 1470 as described above, the bit lines can be shortened. This reduces the bit line capacitance, thereby reducing the storage capacitance of the memory cell.

[0420] [NOSRAM] Figures 28D to 28G An example circuit structure of a gain unit type memory cell with two transistors and one capacitor is shown. Figure 28D The illustrated memory cell 1474 includes a transistor M2, a transistor M3, and a capacitor CB. Furthermore, transistor M2 includes a top gate (sometimes simply referred to as a gate) and a back gate. In this specification and other documents, a memory device including a gain-unit type memory cell using an OS transistor for transistor M2 is sometimes referred to as a NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor RAM).

[0421] A first terminal of transistor M2 is connected to a first terminal of capacitor CB, a second terminal of transistor M2 is connected to wiring WBL, a gate of transistor M2 is connected to wiring WOL, and a back gate of transistor M2 is connected to wiring BGL. A second terminal of capacitor CB is connected to wiring CAL. A first terminal of transistor M3 is connected to wiring RBL, a second terminal of transistor M3 is connected to wiring SL, and a gate of transistor M3 is connected to a first terminal of capacitor CB.

[0422] Wiring WBL serves as a write bit line, wiring RBL serves as a read bit line, and wiring WOL serves as a word line. Wiring CAL serves as a wiring for applying a specified potential to the second terminal of capacitor CB. When writing, retaining, and reading data, a low-level potential is preferably applied to wiring CAL. Wiring BGL serves as a wiring for applying a potential to the back gate of transistor M2. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased.

[0423] In addition, the memory cell MC is not limited to the memory cell 1474, and its circuit structure can be changed appropriately. For example, the memory cell MC can also adopt Figure 28E The back gate of the transistor M2 is not connected to the wiring BGL but to the wiring WOL as in the memory cell 1475 shown in FIG. Figure 28F The memory cell MC may also have a single-gate structure transistor, that is, a memory cell composed of a transistor M2 without a back gate, such as the memory cell 1476 shown in FIG. Figure 28G The memory cell 1477 shown has a structure in which the wiring WBL and the wiring RBL are combined into one wiring BIL.

[0424] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor 100 can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be made extremely small. Thus, since the written data can be retained by the transistor M2 for a long time, the refresh frequency of the memory cell can be reduced. In addition, the refresh operation of the memory cell can be omitted. In addition, since the leakage current is extremely small, multi-valued data or analog data can be retained in the memory cell 1474. The same applies to the memory cells 1475 to 1477.

[0425] In addition, the transistor M3 may also be a transistor containing silicon in the channel formation region (hereinafter sometimes referred to as a Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The field effect mobility of the Si transistor is sometimes higher than that of the OS transistor. Therefore, a Si transistor may also be used as the transistor M3 used as a readout transistor. In addition, by using a Si transistor for the transistor M3, the transistor M2 may be stacked on the transistor M3, thereby reducing the area occupied by the memory cell and achieving high integration of the memory device.

[0426] Alternatively, the transistor M3 may be an OS transistor. When OS transistors are used for the transistors M2 and M3, the memory cell array 1470 can be configured with only n-type transistors.

[0427] in addition, Figure 28H An example of a gain unit type memory cell having three transistors and one capacitor is shown. Figure 28H The illustrated memory cell 1478 includes transistors M4 to M6 and a capacitor CC. Capacitor CC can be provided as appropriate. Memory cell 1478 is electrically connected to wiring BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. Wiring GNDL is a wiring that supplies a low-level potential. Alternatively, memory cell 1478 can be electrically connected to wiring RBL and wiring WBL without being electrically connected to wiring BIL.

[0428] The transistor M4 is an OS transistor including a back gate, and the back gate is electrically connected to the wiring BGL. Alternatively, the back gate and gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not include a back gate.

[0429] Alternatively, transistors M5 and M6 may each be an n-channel Si transistor or a p-channel Si transistor. Alternatively, transistors M4 to M6 may all be OS transistors. In this case, the memory cell array 1470 may be constructed using only n-type transistors.

[0430] When the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistor M5 and the transistor M6, and the capacitor 100 can be used as the capacitor CC. Using an OS transistor as the transistor M4 can minimize leakage current of the transistor M4.

[0431] Note that the structure of the peripheral circuit 1411 and the memory cell array 1470 described in this embodiment is not limited to the above-described structure. The arrangement or function of these circuits and wirings connected to these circuits, circuit elements, and the like can be changed, removed, or added as needed.

[0432] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes and the like as appropriate.

[0433] Implementation 5 In this embodiment, an example of a chip 1200 on which a semiconductor device of the present invention is mounted is described with reference to FIG 29. Multiple circuits (systems) are mounted on chip 1200. This technology of integrating multiple circuits (systems) on a single chip is sometimes referred to as a system on chip (SoC).

[0434] like Figure 29A As shown, the chip 1200 includes a central processing unit (CPU) 1211, a graphics processing unit (GPU) 1212, one or more simulation operation units 1213, one or more storage controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.

[0435] Bumps (not shown) are provided on the chip 1200. Figure 29B As shown, it is connected to the first side of the printed circuit board (PCB) 1201. In addition, a plurality of bumps 1202 are provided on the back side of the first side of the PCB 1201, and the bumps 1202 are connected to the motherboard 1203.

[0436] Furthermore, a storage device such as a DRAM 1221 or a flash memory 1222 may be provided on the motherboard 1203. For example, the DOS RAM described in the above embodiment may be applied to the DRAM 1221. Furthermore, the NOS RAM described in the above embodiment may be applied to the flash memory 1222.

[0437] The CPU 1211 preferably has a plurality of CPU cores. In addition, the GPU 1212 preferably has a plurality of GPU cores. In addition, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory commonly used by the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The above-mentioned NOSRAM or DOSRAM may be applied to the memory. In addition, the GPU 1212 is suitable for parallel calculation of multiple data, which can be used for image processing or product-sum operations. By providing an image processing circuit or product-sum operation circuit using the oxide semiconductor of the present invention as the GPU 1212, image processing and product-sum operations can be performed with low power consumption.

[0438] In addition, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data can be transferred from the CPU 1211 to the GPU 1212, data can be transferred between the memories of the CPU 1211 and the GPU 1212, and calculation results can be transferred from the GPU 1212 to the CPU 1211 after the calculation in the GPU 1212 is completed at high speed.

[0439] The analog operation unit 1213 includes one or both of an analog / digital (A / D) conversion circuit and a digital / analog (D / A) conversion circuit. Furthermore, the analog operation unit 1213 may also include the aforementioned product-sum operation circuit.

[0440] The memory controller 1214 includes a circuit serving as a controller for the DRAM 1221 and a circuit serving as an interface for the flash memory 1222 .

[0441] The interface 1215 includes an interface circuit for connecting to external devices such as a display device, a speaker, a microphone, an image capture device, and a controller. Controllers include a mouse, a keyboard, and a game console controller. Examples of these interfaces include the Universal Serial Bus (USB) and the High-Definition Multimedia Interface (HDMI) (registered trademark).

[0442] The network circuit 1216 includes a network circuit such as a local area network (LAN), and may also include a network security circuit.

[0443] The above circuits (systems) can be formed on the chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the number of manufacturing steps, and the chip 1200 can be manufactured at low cost.

[0444] The motherboard 1203 including the PCB 1201 provided with the chip 1200 having the GPU 1212 , the DRAM 1221 , and the flash memory 1222 may be referred to as a GPU module 1204 .

[0445] Because the GPU module 1204 includes chip 1200 using SoC technology, its size can be reduced. Furthermore, due to its high image processing capabilities, the GPU module 1204 is suitable for use in portable electronic devices such as smartphones, tablets, laptops, and portable (portable) game consoles. Furthermore, by utilizing the product-sum operation circuit using GPU 1212, methods such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs) can be implemented. This allows the chip 1200 to be used as an AI chip, or the GPU module to be used as an AI system module.

[0446] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes and the like as appropriate.

[0447] (Implementation 6) In this embodiment, an application example of a storage device using the semiconductor device shown in the above embodiment is described. The semiconductor device shown in the above embodiment can be applied to, for example, storage devices of various electronic devices (for example, information terminals, computers, smart phones, e-book reader terminals, digital cameras (including video cameras), video playback devices, navigation systems, etc.). Note that here, computers include tablet computers, notebook computers, desktop computers, and large computers such as server systems. Alternatively, the semiconductor device shown in the above embodiment is applied to various removable storage devices such as memory cards (for example, SD cards), USB memories, and SSDs (solid state drives). Figure 30 schematically shows several structural examples of removable storage devices. For example, the semiconductor device shown in the above embodiment is processed into a packaged memory chip and used in various storage devices or removable memories.

[0448] Figure 30A Schematic diagram of a USB memory device. USB memory device 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. Substrate 1104 is housed in housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on substrate 1104. The semiconductor devices described in the above embodiment modes can be incorporated into memory chip 1105 and the like.

[0449] Figure 30B This is a schematic diagram of the appearance of an SD card. Figure 30CThe figure is a schematic diagram of the internal structure of an SD card. SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. Substrate 1113 is housed in housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on substrate 1113. By also providing memory chip 1114 on the back side of substrate 1113, the capacity of SD card 1110 can be increased. Furthermore, a wireless chip with wireless communication capabilities can also be provided on substrate 1113. Thus, data can be read from and written to memory chip 1114 through wireless communication between a host device and SD card 1110. The semiconductor device described in the above embodiment can be incorporated into memory chip 1114, etc.

[0450] Figure 30D This is a schematic diagram of the appearance of SSD. Figure 30E This is a schematic diagram of the internal structure of an SSD. SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. Substrate 1153 is housed in housing 1151. For example, memory chip 1154, memory chip 1155, and controller chip 1156 are mounted on substrate 1153. Memory chip 1155 serves as working memory for controller chip 1156 and, for example, a DOSRAM chip can be used. Providing memory chip 1154 on the back side of substrate 1153 also increases the capacity of SSD 1150. The semiconductor devices described in the above embodiments can be incorporated into memory chip 1154 and the like.

[0451] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate.

[0452] (Implementation 7) The semiconductor device according to one embodiment of the present invention can be applied to processors or chips such as CPUs and GPUs. FIG31 shows a specific example of an electronic device including a processor or chip such as CPUs and GPUs according to one embodiment of the present invention.

[0453] <Electronic equipment and systems> A GPU or chip according to one embodiment of the present invention can be installed in a variety of electronic devices. Examples of electronic devices include televisions, desktop or notebook personal computers, displays for computers, digital signage, large-scale game consoles such as pinball machines, and other electronic devices with large screens. Examples include digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, portable information terminals, and sound reproduction devices. Furthermore, by incorporating an integrated circuit or chip according to one embodiment of the present invention into an electronic device, the electronic device can be provided with artificial intelligence.

[0454] An electronic device according to one embodiment of the present invention may also include an antenna. By receiving signals through the antenna, an image or information can be displayed on a display unit. In addition, when the electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0455] An electronic device of one embodiment of the present invention may also include a sensor (the sensor has the function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, odor or infrared).

[0456] An electronic device according to one embodiment of the present invention can have various functions. For example, it can have the following functions: displaying various information (static images, moving pictures, text images, etc.) on a display; using a touch panel; displaying a calendar, date, or time; executing various software (programs); conducting wireless communications; and reading programs or data stored in a storage medium. Figure 31 shows an example of an electronic device.

[0457] [Mobile phone] Figure 31A The figure shows a mobile phone (smartphone) which is one of the information terminals. The information terminal 5500 includes a housing 5510 and a display portion 5511 . The display portion 5511 includes a touch panel as an input interface, and the housing 5510 is provided with buttons.

[0458] By applying a chip according to one embodiment of the present invention to information terminal 5500, applications utilizing artificial intelligence can be executed. Examples of applications utilizing artificial intelligence include applications that recognize conversations and display the contents of those conversations on display unit 5511, applications that recognize text or graphics input by a user into a touch panel provided on display unit 5511 and display those text or graphics on display unit 5511, and applications that perform biometric recognition such as fingerprints or voiceprints.

[0459] [Information Terminal] Figure 31B 1 and 2. The tabletop information terminal 5300 is shown. The tabletop information terminal 5300 includes an information terminal body 5301, a display 5302, and a keyboard 5303.

[0460] Similar to the aforementioned information terminal 5500, by applying a chip according to one embodiment of the present invention to the desktop information terminal 5300, applications utilizing artificial intelligence can be executed. Examples of applications utilizing artificial intelligence include design support software, text proofreading software, and automatic menu generation software. Furthermore, the use of the desktop information terminal 5300 enables the development of novel artificial intelligence.

[0461] Note that in the above example, Figure 31A and Figure 31B While smartphones and desktop information terminals are shown as examples of electronic devices, information terminals other than smartphones and desktop information terminals may also be applied. Examples of information terminals other than smartphones and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0462] [Electrical appliances] Figure 31C An electric refrigerator-freezer 5800 is shown as an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0463] By applying a chip according to one embodiment of the present invention to an electric refrigerator-freezer 5800, an electric refrigerator-freezer 5800 equipped with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator-freezer 5800 can be equipped with functions such as automatically generating menus based on the food stored in the refrigerator-freezer 5800 or the expiration dates of the food, and automatically adjusting the temperature of the refrigerator-freezer 5800 according to the food stored.

[0464] In the above example, an electric refrigerator-freezer is described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, IH cookers, water dispensers, air conditioners including heating and cooling units, washing machines, dryers, audio-visual equipment, etc.

[0465] [Game console] Figure 31D 1 shows a portable game machine 5200 as an example of a game machine. The portable game machine includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0466] By applying a GPU or chip according to one embodiment of the present invention to the portable game console 5200, a low-power portable game console 5200 can be realized. Furthermore, low power consumption can reduce heat generated by the circuit, thereby reducing the negative effects of heat on the circuit itself, peripheral circuits, and modules.

[0467] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5200 , a portable game console 5200 equipped with artificial intelligence can be realized.

[0468] While the game's progress, the behavior of game creatures, and other phenomena are typically dictated by the game's program, the application of artificial intelligence to the portable game console 5200 enables expressions beyond the game's program. For example, the content of a player's questions, the game's progress, the time, and the changes in the behavior of game characters can be displayed.

[0469] In addition, when using the portable game console 5200 to play a game that requires multiple players, artificial intelligence can be used to create an anthropomorphic player, whereby the artificial intelligence player can be used as an opponent, allowing one person to play the game with multiple players.

[0470] Although Figure 31D While a portable game console is shown as an example of a game console, game consoles that utilize a GPU or chip according to one embodiment of the present invention are not limited thereto. Examples of game consoles that utilize a GPU or chip according to one embodiment of the present invention include home-use stationary game consoles, arcade game consoles installed in entertainment facilities (such as game centers and amusement parks), and batting practice pitching machines installed in sports facilities.

[0471] [Mobile Object] The GPU or chip according to one embodiment of the present invention can be applied to a vehicle as a mobile object and the vicinity of a driver's seat of the vehicle.

[0472] Figure 31E1 FIG. 5 is a diagram showing a car 5700 as an example of a moving object. Figure 31E2 It is a diagram showing the periphery of the front windshield in the interior of a vehicle. Figure 31E2 Display panels 5701, 5702, and 5703 installed on the instrument panel and 5704 installed on the pillar are shown.

[0473] Display panels 5701 through 5703 can display a speedometer, tachometer, distance traveled, fuel level, gear status, air conditioning settings, and various other information. Furthermore, users can modify the display content and layout of the display panels to suit their preferences, enhancing design. Display panels 5701 through 5703 can also function as lighting devices.

[0474] By displaying images captured by a camera (not shown) installed in vehicle 5700 on display panel 5704, it is possible to supplement the field of view (blind spots) blocked by pillars. In other words, by displaying images captured by a camera installed outside vehicle 5700, blind spots can be supplemented, thereby improving safety. Furthermore, by displaying images that supplement the unseen areas, safety confirmation can be made more natural and comfortable. Display panel 5704 can also function as a lighting device.

[0475] Because a GPU or chip according to one embodiment of the present invention can be used as a component of artificial intelligence, for example, the chip can be used in an autonomous driving system of automobile 5700. The chip can also be used in systems that perform navigation, hazard prediction, and the like. Furthermore, navigation, hazard prediction, and other information can be displayed on display panels 5701 to 5704.

[0476] While the above examples illustrate an automobile as an example of a mobile object, mobile objects are not limited to automobiles. Examples of mobile objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (UAVs), airplanes, and rockets). A chip according to one embodiment of the present invention can be applied to these mobile objects to provide systems utilizing artificial intelligence.

[0477] [Broadcast and Television System] A GPU or chip according to one embodiment of the present invention can be applied to a broadcast television system.

[0478] Figure 31F Schematically illustrates data transmission in a broadcast television system. Specifically, Figure 31F The diagram shows the path of radio waves (broadcast television signals) transmitted from a broadcasting station 5680 to a television receiver (TV) 5600 in each home. The TV 5600 includes a receiver (not shown), and the broadcast television signals received by an antenna 5650 are input to the TV 5600 via the receiver.

[0479] Although Figure 31F An ultra-high frequency (UHF) antenna is shown as the antenna 5650 , but a BS antenna, a 110-degree CS antenna, a CS antenna, or the like can be used as the antenna 5650 .

[0480] Radio waves 5675A and 5675B are terrestrial broadcast television signals. Radio tower 5670 amplifies received radio waves 5675A and transmits radio waves 5675B. Each household receives radio waves 5675B with antenna 5650 and can watch terrestrial TV broadcasts on TV 5600. In addition, the broadcast television system may be satellite broadcast television using artificial satellites, data broadcast television using optical lines, etc., and is not limited to Figure 31F Terrestrial broadcast television shown.

[0481] In addition, a chip according to one embodiment of the present invention can also be applied to the above-mentioned broadcasting and television system to form a broadcasting and television system that utilizes artificial intelligence. When broadcasting and television data is transmitted from a broadcasting and television station 5680 to each household's TV 5600, an encoder is used to compress the broadcasting and television data; when the antenna 5650 receives the broadcasting and television data, a decoder of a receiver included in the TV 5600 is used to restore the broadcasting and television data. By utilizing artificial intelligence, for example, a display model included in a displayed image can be identified in a variation compensation prediction, which is one of the compression methods of the encoder. In addition, intra-frame prediction and the like using artificial intelligence can also be performed. For example, when the TV 5600 receives low-resolution broadcasting and television data and displays it at high resolution, supplementary image processing such as up-conversion can be performed in the restoration of the broadcasting and television data performed by the decoder.

[0482] The above-mentioned broadcasting and television system using artificial intelligence is suitable for ultra-high-definition television (UHDTV: 4K, 8K) playback with increasing amounts of broadcasting and television data.

[0483] Furthermore, as an application of artificial intelligence on the TV 5600 side, for example, a recording device equipped with artificial intelligence can be installed in the TV 5600. With this configuration, the recording device equipped with artificial intelligence can learn the user's preferences and automatically record television programs that suit the user's preferences.

[0484] The electronic devices, functions of the electronic devices, application examples of artificial intelligence, and effects thereof, etc. described in this embodiment can be implemented in combination with descriptions of other electronic devices as appropriate.

[0485] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and the like as appropriate. [Explanation of symbols]

[0486] 100 capacitor, 110 conductor, 112 conductor, 120 conductor, 130 insulator, 140 insulator, 150 insulator, 200 transistor, 200A transistor, 200B transistor, 205 conductor, 210 insulator, 212 insulator, 214 insulator, 216 insulator, 218 conductor, 222 insulator, 224 insulator, 224A insulating film, 230 oxide, 230a oxide, 230A oxide film, 230b oxide, 230B oxide film, 230c oxide, 230c1 oxide, 230c2 oxide, 230C oxide film, 230C1 oxide film, 230C2 oxide film, 231 region, 231a region, 231b region, 232 Region, 232a region, 232b region, 234 region, 240 conductor, 240a conductor, 240b conductor, 241 insulator, 241a insulator, 241b insulator, 242 conductor, 242a conductor, 242A conductive film, 242b conductor, 242B conductive layer, 243 region, 243a region, 243b region, 250 insulator, 250A insulating film, 254 insulator, 254a insulator, 254A insulating film, 254b insulator, 254B insulating film, 254c insulator, 260 conductor, 260a conductor, 260A conductive film, 260B conductive film, 260b conductor, 262 dummy gate, 262A dummy gate layer, 274 insulator 280 insulator, 280a insulator, 280A insulating film, 280b insulator, 281 insulator, 282 insulator, 300 transistor, 311 substrate, 313 semiconductor region, 314a low resistance region, 314b low resistance region, 315 insulator, 316 conductor, 320 insulator, 322 insulator, 324 insulator, 326 insulator, 328 conductor, 330 conductor, 350 insulator, 352 insulator, 354 insulator, 356 conductor, 400 transistor, 405 conductor, 405a conductor, 405b conductor, 424a insulator, 424b insulator, 430c oxide, 430c1 oxide, 430c2 oxide, 431a oxide compound, 431b oxide, 432a oxide, 432b oxide, 440 conductor, 440a conductor, 440b conductor, 442 conductor, 442a conductor, 442b conductor, 443a region, 443b region, 450 insulator, 460 conductor, 460a conductor, 460b conductor, 1001 wiring, 1002 wiring, 1003 wiring, 1004 wiring, 1005 wiring, 1006 wiring, 1007 wiring, 1008 wiring, 1009 wiring, 1010 wiring, 1100 USB memory, 1101 housing, 1102 cover, 1103 USB connector, 1104 substrate, 1105 memory chip, 1106 controller chip,1110 SD card, 1111 housing, 1112 connector, 1113 substrate, 1114 memory chip, 1115 controller chip, 1150 SSD, 1151 housing, 1152 connector, 1153 substrate, 1154 memory chip, 1155 memory chip, 1156 controller chip, 1200 chip, 1201 PCB, 1202 bump, 1203 motherboard, 1204 GPU module, 1211 CPU, 1212 GPU, 1213 analog operation unit, 1214 storage controller, 1215 interface, 1216 network circuit, 1221 DRAM, 1222 flash memory, 1400 storage device, 1411 peripheral circuit, 1420 row circuit, 1430 column circuit, 1440 output circuit, 1460 control logic circuit, 1470 storage cell array, 14 71 Storage unit, 1472 Storage unit, 1473 Storage unit, 1474 Storage unit, 1475 Storage unit, 1476 Storage unit, 1477 Storage unit, 1478 Storage unit, 5200 Portable game console, 5201 Housing, 5202 Display unit, 5203 Button, 5300 Desktop information terminal, 5301 Main body, 5302 Display, 5303 Keyboard, 5500 Information terminal, 5510 Housing, 5511 Display unit, 5600 TV, 5650 Antenna, 5670 Radio tower, 5675A radio wave, 5675B radio wave, 5680 Radio station, 5700 Automobile, 5701 Display panel, 5702 Display panel, 5703 Display panel, 5704 Display panel, 5800 Electric refrigerator / freezer, 5801 Housing, 5802 Refrigerator door, 5803 Freezer door,

Claims

1. A semiconductor device comprising: a first insulator; a first oxide on the first insulator; a second insulator on the first oxide; a first conductor on the second insulator; a second electrical conductor and a third electrical conductor on the first oxide; as well as a third insulator on the second conductive body and the third conductive body, The third insulator is provided with an opening that reaches the first oxide. The second insulator is provided in a manner covering the inner wall of the opening, The first conductor is provided in a manner of being embedded in the opening via the second insulator. Furthermore, in the channel width direction, a bottom surface height of the first conductor in a region where the first conductor and the first oxide do not overlap is lower than a bottom surface height of the first oxide.

2. The semiconductor device according to claim 1, The first oxide includes a first region, a second region, and a third region located between the first region and the second region. Furthermore, the resistance of the first region and the resistance of the second region are lower than the resistance of the third region.

3. A semiconductor device comprising: a first insulator; a first oxide on the first insulator; a second insulator and a third insulator on the first oxide; as well as a first conductor on the second insulator, The first oxide includes a first region, a second region, and a third region located between the first region and the second region. The resistance of the first region and the resistance of the second region are lower than the resistance of the third region. The first conductor is arranged above the third region in a manner overlapping with the third region, A portion of the second insulator is disposed between a side surface of the first conductor and a side surface of the third insulator. Furthermore, in the channel width direction, a bottom surface height of the first conductor in a region where the first conductor and the first oxide do not overlap is lower than a bottom surface height of the first oxide.

4. The semiconductor device according to claim 2 or 3, The first region and the second region contain phosphorus or boron.

5. The semiconductor device according to claim 1 or 3, further comprising a second oxide between the first oxide and the first insulator, wherein the first oxide comprises indium, And the second oxide contains one or more of gallium and zinc, and indium. 6 . The semiconductor device according to claim 1 , further comprising a fourth insulator in contact with a top surface of the second insulator, a top surface of the first conductor, and a top surface of the third insulator.

7. The semiconductor device according to claim 6, The fourth insulator has lower permeability to one or both of hydrogen and oxygen than the first insulator.

8. The semiconductor device according to claim 6, wherein the fourth insulator has a stacked structure including a first layer and a second layer, The first layer is in contact with the first insulator, And the second layer is in contact with the third insulator.

9. The semiconductor device according to claim 8, wherein the first layer comprises silicon oxide, And the second layer includes aluminum oxide.

10. A method for manufacturing a semiconductor device, comprising: forming a first insulator; forming an oxide film on the first insulator; forming a first conductive film on the oxide film; processing the oxide film and the first conductive film into island shapes to form an oxide and a conductive layer; forming a second insulator on the first insulator, the oxide, and the conductive layer; forming openings in the conductive layer and the second insulator, and forming a first conductor and a second conductor from the conductive layer; forming an insulating film on the second insulator and the opening; forming a second conductive film on the insulating film; as well as The insulating film and the second conductive film are subjected to CMP treatment to expose a top surface of the second insulator, thereby forming a third insulator and a third conductor.

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