Automatic test system for integrated circuit board

Abstract

The embodiment of the invention provides an automatic test system for an integrated circuit board, and the system comprises a signal collection module which collects the multi-channel synchronous signal data of the integrated circuit board in real time, and extracts the time sequence characteristics of the signal transmission of each channel; the analysis module is used for constructing a time sequence deviation distribution model according to a preset time sequence constraint condition and analyzing delay inconsistency among multiple channels; the adjusting module is used for dynamically adjusting a phase compensation parameter of the synchronizing signal of each channel based on the time sequence deviation analysis result; and the test module is used for executing a closed-loop test according to the compensated synchronizing signal and verifying whether the data transmission time sequence of each channel accords with a preset synchronizing threshold value or not. Through the scheme of the embodiment of the invention, the synchronization signal can be regulated and controlled according to the time sequence deviation analysis so as to solve the problem of inconsistent delay in multi-channel data transmission.

Description

Technical Field

[0001] The present application relates to the field of electronic testing technology, and in particular to an automated testing system for integrated circuit boards. Background Art

[0002] Automated testing of integrated circuit boards mainly uses an automated test system combined with a signal generator and a multi-channel data acquisition module to quickly detect the electrical performance and signal integrity of the circuit board. Its core is to control the signal input and automatically analyze the output response based on a preset test program, thereby improving test efficiency and consistency. However, in multi-channel data transmission scenarios, there is a challenge in controlling temporary sequence deviations. That is, due to differences in the physical paths of different channels, signal interference or inconsistent component response times, there are differences in the data transmission delays of each channel, which in turn affects the alignment of the synchronization signal. It is necessary to dynamically adjust the phase or frequency of the synchronization signal through timing deviation analysis to compensate for the delay. However, existing methods are difficult to accurately quantify the deviation and achieve real-time adaptive control in complex timing environments, which may cause problems such as data sampling misalignment or inaccurate test results. Summary of the Invention

[0003] In view of this, an embodiment of the present disclosure provides an automated testing system for an integrated circuit board, which at least partially solves the problems existing in the prior art.

[0004] An automated testing system for an integrated circuit board, comprising:

[0005] The signal acquisition module collects the multi-channel synchronous signal data of the integrated circuit board in real time and extracts the timing characteristics of the signal transmission of each channel;

[0006] An analysis module is used to build a timing deviation distribution model based on preset timing constraints and analyze delay inconsistencies between multiple channels;

[0007] An adjustment module, configured to dynamically adjust the phase compensation parameters of the synchronization signals of each channel based on the timing deviation analysis result;

[0008] The test module is used to perform closed-loop testing based on the compensated synchronization signal to verify whether the data transmission timing of each channel meets the preset synchronization threshold.

[0009] Preferably, the dynamically adjusting the phase compensation parameters based on the timing deviation analysis result includes:

[0010] Calculate the delay offset Δτ_i of each channel signal relative to the reference channel, where i is the channel number;

[0011] The following formula is used to determine whether phase compensation is triggered: if max(Δτ_i)min(Δτ_i)>δ_th, where δ_th is the preset synchronization threshold, compensation is triggered;

[0012] Variance σ of the delay offsets of each channel Dynamically allocate compensation weight w_i = 1 / (σ 2 + ε), where ε is a constant to prevent division by zero;

[0013] Write the compensated phase parameter φ_i = φ_i0 + w_i * Δτ_i to each channel controller.

[0014] Preferably, the dynamic allocation of the compensation weight further includes:

[0015] Introduce the inter-channel coupling coefficient k_ij, where i and j are the channel pair numbers, and calculate the inter-channel delay correlation matrix C = [k_ij * Δτ_i * Δτ_j];

[0016] Determine the global compensation strength α = 1 / (1 + exp(β(λ_max - λ0))) based on the maximum eigenvalue λ_max of the matrix C, where β is the gain coefficient and λ0 is the eigenvalue threshold;

[0017] Modify the compensation weight to w_i = α * w_i + (1 - α) * w_i_prev, where w_i_prev is the weight of the previous cycle;

[0018] Limit the fluctuation range of the compensation weight w_i: if w_i > w_max, then w_i = w_max; if w_i < w_min, then w_i = w_min.

[0019] Preferably, the calculation of the coupling coefficient k_ij includes:

[0020] Collect the channel delay sequences {D_i(t)} in the historical test data;

[0021] Calculate the delay cross-correlation function R_ij(τ) = E[D_i(t)D_j(t + τ)] of the channel pair (i, j);

[0022] Determine the optimal delay τ_peak according to the peak position of the cross-correlation function;

[0023] Set k_ij = exp(|τ_peak| / T_c), where T_c is the channel correlation time constant.

[0024] Preferably, the dynamic adjustment of the phase compensation parameter includes: [[ID=4D]]

[0025] Establish the probability density function f(Δφ_i) of the phase deviation of each channel;

[0026] Calculate the optimal compensation amount according to the formula Δφ_opt = argmin Σ|Δφ_i - Δφ_opt|^2;

[0027] If Δφ_i exceeds the range of 3σ, where σ is the standard deviation, the abnormal channel isolation mechanism is activated;

[0028] The gradient descent method is used to iteratively update the compensation parameters: Where η is the learning rate and E is the error function.

[0029] Preferably, the gradient descent method iterative update further includes:

[0030] Dynamically adjust the learning rate η = η0 / (1+γ*n), where η0 is the initial learning rate, γ is the decay coefficient, and n is the number of iterations;

[0031] Calculating the momentum term Where μ is the momentum factor;

[0032] The update rule is modified to φ_i^(n+1)=φ_i^nη*(m_i+λ*φ_i^n), where λ is the regularization coefficient;

[0033] The iteration is terminated when the error change rate is less than 1e6 for 5 consecutive iterations.

[0034] Preferably, the dynamic adjustment includes:

[0035] Construct a sliding window statistic Q_i(t)=median{Δτ_i(tk),...,Δτ_i(t)} for each channel delay, where k is the window length;

[0036] The trend direction is determined by the difference ΔQ_i between Q_i(t) and Q_i(t1): if ΔQ_i>θ_up, the compensation intensity is increased; if ΔQ_i<θ_down, the compensation intensity is reduced;

[0037] The compensation intensity adjustment formula is S_i(t)=S_i(t1)*exp(sign(ΔQ_i)*ΔQ_i / κ), where κ is the sensitivity coefficient;

[0038] The compensation parameter φ_i is convolved with S_i(t) to obtain the final output value.

[0039] Preferably, the calculation of the sliding window statistics further includes:

[0040] Dynamically adjust the window length k = ceil(f_s / (2*f_c)) according to the signal frequency f_c, where f_s is the sampling frequency;

[0041] Apply Hanning window weighting processing to the data in the window: w_n=5*(1cos(2πn / (k1)));

[0042] Calculate the weighted median Q_i^w = argminΣw_n|Δτ_i(n)Q_i^w|;

[0043] When it is detected that the difference between adjacent samples of data in the window is greater than 3σ, the window is automatically shrunk to 1 / 2 of its original length.

[0044] Preferably, the dynamic adjustment includes:

[0045] Establish a temperature delay compensation lookup table T_delay(T) = a*T 2 +b*T+c, a, b, c are calibration coefficients;

[0046] Real-time collection of temperature sensor data T_i(t) of each channel;

[0047] The corrected phase compensation amount Δφ_i = Δφ_i + α*T_delay(T_i(t)), where α is the temperature influence factor;

[0048] If the temperature change rate dT_i / dt exceeds the safety threshold, compensation is suspended and an overheating alarm is triggered.

[0049] Preferably, the establishment of the temperature delay compensation look-up table includes:

[0050] The calibration experiment was carried out in a constant temperature box with a temperature scanning range of [T_min, T_max];

[0051] Record the reference delay τ_ref(T) at each temperature point;

[0052] Use the least squares method to fit the cubic polynomial τ_fit(T)=p0+p1*T+p2*T 2 +p3*T 3 ;

[0053] Verify the fitting error: If max|τ_ref(T)τ_fit(T)|>ε_max, increase the segmented fitting interval.

[0054] The disclosed embodiments provide an automated testing method for an integrated circuit board (ICB), including: real-time acquisition of multi-channel synchronization signal data from the ICB and extraction of the timing characteristics of each channel's signal transmission; constructing a timing deviation distribution model based on preset timing constraints to analyze delay inconsistencies between multiple channels; dynamically adjusting the phase compensation parameters of each channel's synchronization signal based on the timing deviation analysis results; and performing a closed-loop test based on the compensated synchronization signal to verify whether the data transmission timing of each channel meets a preset synchronization threshold. The disclosed embodiments address the problem of delay inconsistencies in multi-channel data transmission by regulating the synchronization signal based on timing deviation analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions of the exemplary implementation methods of the embodiments of the present disclosure, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the embodiments of the present disclosure and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0056] Figure 1 It is a flow chart of an automated testing method for an integrated circuit board;

[0057] Figure 2 It is a flow chart for dynamically adjusting phase compensation parameters based on timing deviation analysis results;

[0058] Figure 3 is a flow chart of the dynamic allocation of compensation weights;

[0059] Figure 4 This is the flow chart of the calculation of the coupling coefficient k_ij;

[0060] Figure 5 It is a flow chart for dynamically adjusting phase compensation parameters;

[0061] Figure 6 It is a flowchart of the iterative update of the gradient descent method;

[0062] Figure 7 It is a dynamically adjusted flow chart;

[0063] Figure 8 It is a flowchart of the calculation of sliding window statistics;

[0064] Figure 9 It is a dynamically adjusted flow chart;

[0065] Figure 10 This is a flow chart for establishing a temperature delay compensation lookup table;

[0066] Figure 11 This is a block diagram of an automated testing system for an integrated circuit board of the present application. DETAILED DESCRIPTION

[0067] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure more clear, the embodiments of the present disclosure are further described in detail below in combination with the embodiments and drawings. The schematic implementation methods of the embodiments of the present disclosure and their descriptions are only used to explain the embodiments of the present disclosure and are not intended to limit the embodiments of the present disclosure.

[0068] First, refer to Figure 11 , describing an automated testing system 1100 for an integrated circuit board according to the present invention, the system comprising:

[0069] The signal acquisition module 1101 is used to collect the multi-channel synchronous signal data of the integrated circuit board in real time and extract the timing characteristics of the signal transmission of each channel;

[0070] An analysis module 1102 is configured to construct a timing deviation distribution model based on preset timing constraints and analyze delay inconsistencies among multiple channels;

[0071] An adjustment module 1103 is configured to dynamically adjust a phase compensation parameter of a synchronization signal of each channel based on the timing deviation analysis result;

[0072] The testing module 1104 is configured to perform a closed-loop test based on the compensated synchronization signal to verify whether the data transmission timing of each channel meets a preset synchronization threshold.

[0073] Next, refer to Figures 1-10 , specifically describe the specific implementation of the test method performed by the automated test system for integrated circuit boards of this application, first refer to Figure 1 , the method comprising:

[0074] S101: Real-time acquisition of multi-channel synchronous signal data from the integrated circuit board and extraction of the timing characteristics of the signal transmission of each channel. This step is achieved through the cooperation of a high-precision ADC module and an FPGA logic unit, synchronously capturing the waveforms of multi-channel signals, and using an edge detection algorithm to extract the rising and falling edge timestamps, combined with clock recovery technology to separate the clock domain information of each channel. For example, in a high-speed communication circuit board test scenario, the system simultaneously acquires 8-channel LVDS differential signals with a sampling rate of 2GHz, and aligns the signal edges to the 1ps resolution of the reference clock through a time-to-digital converter (TDC), ultimately generating a timing characteristic matrix containing channel ID, trigger time, and pulse width.

[0075] S102: Construct a timing deviation distribution model based on preset timing constraints to analyze the delay inconsistency between multiple channels. In this stage, the timing margins (such as setup time and hold time) in the design specifications are converted into mathematical constraints, the mean and variance of the relative delay between channels are calculated by statistical methods, and a multi-dimensional Gaussian mixture model is constructed to describe the deviation distribution. Specifically, in an image sensor interface board test instance, the system detected that channel 3 had a fixed offset of 12.3ns relative to channel 0, and the delay jitter variance of channel 5 exceeded the threshold by 3 times. Cluster analysis found that the physical layout of the abnormal channel was directly related to the difference in clock tree branch length, thereby locating the root cause of the PCB trace impedance mismatch.

[0076] S103: Based on the results of the timing deviation analysis, dynamically adjust the phase compensation parameters of the synchronization signals of each channel. This process uses a closed-loop feedback mechanism to apply phase compensation to each channel through a programmable delay line (DLY) or a digital phase-locked loop (DPLL). The compensation amount is dynamically calculated by a gradient descent algorithm output by the deviation model. For example, in the storage controller test, for the timing deviation between the DQ and DQS signals in the DDR4 data bus, the system calculates the compensation step required for each DQ channel in real time, and configures the delay register of the clock generator chip through the I2C interface, converging the deviation originally scattered in the range of ±800ps to within ±50ps.

[0077] S104: Perform a closed-loop test based on the compensated synchronization signal to verify whether the data transmission timing of each channel meets the preset synchronization threshold. The system verifies by injecting test patterns and monitoring the bit error rate (BER), while using eye diagram analysis tools to quantify the timing margin. In an actual case, in a multi-channel video data transmission test of the compensated HDMI interface board, the deviation of all data channels and clock channels was controlled within 0.3ns, meeting the 0.5ns synchronization threshold required by the protocol, and the eye opening was increased from 0.7UI before compensation to 0.9UI. The test system automatically generates a report containing a deviation heat map, a compensation parameter table, and timing margin statistics, completing a quantitative evaluation of the synchronization performance of the entire circuit board.

[0078] The core innovation of this method lies in combining timing deviation modeling with dynamic compensation, solving the delay inconsistency problem through the following mechanisms: first, a hybrid deviation model that includes spatial distribution (channel position) and timing characteristics (jitter, offset) is established, and second, an adaptive filtering algorithm is used to distinguish between fixed delay and random jitter components. For example, when dealing with dynamic deviations caused by temperature drift, the system updates the model parameters online and adjusts the compensation weight coefficients in real time to ensure that the inter-channel offset in a certain optical module test remains stable within the temperature range of -40°C to 85°C. Compared with the traditional fixed margin method, this model prediction-based compensation strategy increases test coverage from 82% to 97%, while reducing the power consumption overhead caused by overcompensation by 23%.

[0079] Next, the method of dynamically adjusting the phase compensation parameters based on the timing deviation analysis result of the present invention is described.

[0080] S201: Calculate the delay offset Δτ_i (where i is the channel number) of each channel's signal relative to the reference channel. This offset is defined as the difference between the actual signal arrival time of each channel and the reference channel, and is used to quantify timing deviation. For example, in integrated circuit board testing, if the reference channel is the clock signal source and the other channels are data acquisition channels, measuring Δτ_i can determine the synchronization error of the data sampling. Δτ_i is measured in nanoseconds (ns) and typically ranges from ±100ns, depending on the circuit design.

[0081] S202: Determine whether to trigger phase compensation based on the formula max(Δτ_i)-min(Δτ_i)>δ_th (δ_th is the preset synchronization threshold). This formula determines whether dynamic adjustment is required by comparing the difference between the maximum and minimum delays of all channels to see if it exceeds a threshold. For example, if δ_th is set to 5ns, and the maximum delay in a test is +7ns and the minimum is -2ns, the difference of 9ns exceeds the threshold, triggering compensation. The reasonable range of δ_th is 1–10ns, and the optimal value depends on the specific circuit timing tolerance.

[0082] S203: Based on the variance σ of each channel delay offset 2 Dynamically allocate compensation weight w_i=1 / (σ 2 +ε), where ε is an anti-zero constant (such as 1e-6). Variance σ 2 Reflects the degree of delay fluctuation of each channel. The greater the fluctuation (σ 2 Assign smaller weights to channels with high (high) values ​​to reduce the impact of unstable channels on the overall compensation. For example, if the σ of channel 1 is 2 =0.1ns 2 , σ of channel 2 2 =0.5ns 2 , then the weight of channel 1 is higher (w_1≈10, w_2≈2), and the channel with high stability is corrected first during compensation.

[0083] S204: Write the compensated phase parameter φ_i = φ_i0 + w_i * Δτ_i into each channel controller. φ_i0 is the initial phase, and w_i * Δτ_i is the dynamic adjustment amount. For example, if Δτ_i = 3ns and w_i = 0.3 for channel 3, then its phase compensation amount is 0.9ns. This formula compensates for delay deviation and avoids overcorrection of channels with noise interference through weighted adjustment. The role of ε is to prevent σ 2 When the denominator is zero, it is abnormal and usually takes a very small value, which does not affect the weight distribution logic.

[0084] Next, the dynamic allocation of compensation weights of the present invention is described.

[0085] S301: Introduce the inter-channel coupling coefficient k_ij (where i and j are the channel pair numbers), and calculate the inter-channel delay correlation matrix C = [k_ij * Δτ_i * Δτ_j]. Here, Δτ_i and Δτ_j are the delay deviations of the i-th and j-th channels respectively. The value range of k_ij is [0, 1], which reflects the inter-channel crosstalk intensity, and the optimal value is calibrated through experiments. This matrix quantifies the mutual influence of inter-channel delays. For channel pairs with larger coupling coefficients or higher delay deviations, their correlation contributions are more significant. For example, in a 16-channel circuit board test system, if there is strong crosstalk between channel 3 and channel 5 (k_35 = 0.8), and their delay deviations are Δτ3 = 2.1 ns and Δτ5 = 1.8 ns respectively, then the matrix element C(3, 5) = 0.8 × 2.1 × 1.8 ≈ 3.02.

[0086] S302: Determine the global compensation intensity α = 1 / (1 + exp(β(λ_max - λ0))) based on the maximum eigenvalue λ_max of matrix C, where β is the gain coefficient and λ0 is the eigenvalue threshold.

[0087] This formula maps λ_max to the interval (0, 1) through the sigmoid function. When λ_max exceeds λ0, α rapidly decays to suppress overcompensation. For example, if λ_max = 120, β = 5, and λ0 = 100, then α ≈ 1 / (1 + exp(5 × 20)) = 0.006, indicating that the compensation intensity needs to be significantly reduced to avoid system oscillation.

[0088] S303: Modify the compensation weight to w_i = α * w_i + (1 - α) * w_i_prev, where w_i_prev is the weight of the previous cycle. α controls the mixing ratio of the historical weight and the new weight. When α approaches 0, more historical information is retained to improve stability. Specifically, in high-speed signal integrity testing, if the current weight of a certain channel w_i = 0.6, the weight of the previous cycle w_i_prev = 0.55, and α = 0.3, then after modification, w_i = 0.3 × 0.6 + 0.7 × 0.55 = 0.565.

[0089] S304: Limit the fluctuation range of the compensation weight w_i: if w_i > w_max, then w_i = w_max; if w_i < w_min, then w_i = w_min. When the weight of a certain channel becomes w_i = 0.9 due to sudden interference, it will be truncated to w_max = 0.8. This mechanism ensures the robustness of the compensation system and is particularly important in industrial environments with transient noise.

[0090] In one embodiment, in a 32-channel BGA package board test scenario, channel 12 and channel 15 are coupled due to physical proximity (k_12,15 = 0.7). When the delay skew between them reaches Δτ12 = 3.2ns and Δτ15 = 2.9ns, respectively, the corresponding element in matrix C is 0.7 × 3.2 × 2.9 ≈ 6.5. The system calculates λ_max = 150 (β = 5, λ0 = 120), resulting in α ≈ 0.017. When the compensation weight is updated, the historical weight accounts for 98.3%. After correction, the weight of channel 12 changes from 0.72 to 0.017 × 0.72 + 0.983 × 0.70 ≈ 0.701, and is constrained within the range [0.2, 0.8]. This process dynamically balances delay compensation and system stability, adapting to the time-varying crosstalk environment of circuit board testing.

[0091] Next, calculation of the coupling coefficient k_ij of the present invention is described.

[0092] S401: Collect channel delay sequences {D_i(t)} from historical test data, where D_i(t) represents the delay measurement value of the i-th channel at time t. This sequence is typically derived from timing records from multiple tests. This step establishes a basis for delay correlation between channels by accumulating actual test data. For example, in integrated circuit board testing, which may contain delay data for hundreds of signal channels, the sampling frequency must be higher than the signal change rate to ensure sequence integrity.

[0093] S402: Calculate the delay cross-correlation function R_ij(τ) = E[D_i(t)D_j(t+τ)] for the channel pair (i, j), where E represents the mathematical expectation and τ is the time offset. This function quantifies the synchronization of the delay fluctuations of the two channels, reflecting the instantaneous correlation when τ = 0. Specifically, in circuit board testing, if crosstalk from channel i causes delay fluctuations in channel j, R_ij(τ) will exhibit a peak at a specific τ. The range of the parameter τ is typically determined by the signal propagation time; for example, in high-speed circuit boards, τ may be limited to 0-20ns.

[0094] S403: Determine the optimal delay τ_peak based on the peak position of the cross-correlation function. The peak value τ_peak indicates the most significant correlated time shift in the delay fluctuations between the two channels, which may be the propagation delay of the signal coupling path. For example, if electromagnetic coupling between adjacent signal lines causes the delay fluctuation of channel j to lag behind that of channel i by 5 ns, then τ_peak = 5 ns. This step requires interpolation or a sliding window algorithm to accurately capture the peak position.

[0095] S404: Set k_ij = exp(-|τ_peak| / T_c), where T_c is the channel correlation time constant, reflecting the decay rate of the coupling effect. The formula converts the delay into a coupling strength of 0 to 1 through an exponential function. The larger T_c is, the slower the coupling decays. For example, when T_c is set to 10ns, if τ_peak = 5ns, then k_ij = exp(-0.5) ≈ 0.606, indicating moderate coupling. The optimal value of T_c needs to be calibrated experimentally, and is usually taken from the typical delay level of the system. For example, 5-20ns can be selected for high-speed circuits. This formula is designed so that the shorter the delay, the stronger the coupling, which conforms to physical laws and meets normalization requirements.

[0096] In one example, analyzing the power-signal channel coupling of a multilayer PCB, after collecting 100,000 delay data sets, R_35(τ) was calculated for Channels 3 and 5, revealing a peak at τ_peak = 8ns. When T_c = 15ns, k_35 = exp(-8 / 15) ≈ 0.58. This indicates the need for additional shielding measures for these two channels to reduce crosstalk risk. This method optimizes test isolation strategies by quantifying coupling strength.

[0097] Next, the dynamic adjustment of phase compensation parameters of the present invention is described.

[0098] S501: Establish a probability density function f(Δφ_i) for the phase deviation of each channel. This function is constructed by statistically analyzing historical test data or real-time phase differences Δφ_i (in radians, typically in the range [-π, π]). This function is used to quantify the distribution characteristics of phase deviation across different channels. For example, in the synchronous testing of multi-channel signals on an integrated circuit board, by collecting phase difference data from 10 sets of high-frequency signal transmissions, a probability density function that follows a Gaussian distribution is fitted. The central value reflects the inherent deviation of the system, and the variance reflects the influence of environmental noise.

[0099] S502: Calculate the optimal compensation amount according to the formula Δφ_opt=argminΣ|Δφ_i-Δφ_opt|^2. This formula solves Δφ_opt that minimizes the overall deviation by minimizing the sum of the square errors of the phase differences and compensation amounts of all channels (the optimal value is the minimum point of the error function). The parameter Δφ_i is the original phase difference of the i-th channel, and the physical meaning of Δφ_opt is the global optimal compensation phase angle. For example, when the phase differences of the 8 channels are [0.1, 0.2, -0.05, 0.15, 0.25, 0.18, 0.12, 0.3] radians respectively, Δφ_opt≈0.17 radians can be quickly obtained through matrix operations, which improves the overall phase consistency by 62% after compensation.

[0100] S503: If Δφ_i exceeds the range of 3σ (σ is the standard deviation), the abnormal channel isolation mechanism is activated. This condition eliminates occasional interference or hardware failure channels through the principle of statistical process control. Specifically, in the high-speed digital signal integrity test, when a channel causes the phase difference to reach 4.5σ (for example, the threshold value is ±0.15 radians when σ=0.05 radians) due to poor contact, the system automatically cuts off the power supply of the channel and marks it as abnormal to prevent it from affecting the compensation accuracy of other channels.

[0101] S504: Iteratively update the compensation parameters using the gradient descent method: Where η is the learning rate, E = Σ|Δφ_i-Δφ_opt|^2 is the error function, is the gradient direction. This formula gradually approaches the optimal value in the negative gradient direction, ensuring parameter convergence. For example, in a DDR4 memory bus test, the initial phase compensation error was 0.25 radians, which decreased to 0.02 radians after 50 iterations. When the iteration step size η = 0.05, the optimal balance between convergence speed and stability was achieved.

[0102] Next, the iterative update of the gradient descent method of the present invention is described.

[0103] S601: Dynamically adjust the learning rate: The learning rate formula is η = η0 / (1 + γ n), where η0 is the initial learning rate (usually set to 0.1-0.01), γ is the attenuation coefficient (range 0.001-0.1, the optimal value is about 0.01), and n is the current number of iterations. This formula makes the learning rate decay as the number of iterations increases, avoiding oscillations caused by excessive step size in the later stages of optimization. For example, in integrated circuit board testing, test parameters (such as signal thresholds) need to be adjusted quickly in the early stages, and fine-tuning is required in the later stages. Dynamic attenuation can balance convergence speed and stability.

[0104] S602: Calculate the momentum term Where μ is the momentum factor (range 0.8-0.99, optimal value 0.9), is the gradient of the loss function with respect to the parameter φ_i. The momentum term accelerates convergence and suppresses oscillations by taking a weighted average of historical gradients. Specifically, when optimizing electrical parameters for circuit board testing (such as the signal frequency weight φ_i), the momentum term can avoid local noise interference and guide parameter updates towards stability.

[0105] S603: The update rule is modified to φ_i^(n+1)=φ_i^n-η·(m_i+λ·φ_i^n), where λ is the regularization coefficient (range 1e-4-1e-2, optimal value 1e-3). This formula introduces the L2 regularization term λ·φ_i^n into the gradient update to prevent overfitting. For example, when testing parameter optimization, if some signal gain coefficients φ_i are too large, regularization can constrain their amplitudes and improve the model's generalization ability.

[0106] S604: Terminate the iteration when the error change rate is less than 1e-6 for five consecutive iterations. This condition monitors the change in the loss function to determine convergence and avoid invalid calculations. In one embodiment, after the integrated circuit board test error drops to the order of 1e-6, the parameters have stabilized and adapted to the test environment, and further iterations will not improve accuracy.

[0107] In one embodiment, taking the optimization of the circuit board signal sampling interval φ_i as an example, the initial learning rate η0 = 0.1, γ = 0.01, momentum factor μ = 0.9, λ = 0.001. The first iteration calculates the gradient The momentum term m_i = 0.9 0 + (1 - 0.9) 0.5 = 0.05, and the update φ_i = φ_i - 0.1 / (1 + 0.01 1) (0.05 + 0.001 φ_i). As the number of iterations increases, the learning rate gradually decreases, the momentum term accumulates the gradient direction, and the regularization term suppresses φ_i from being too large. Ultimately, the test is terminated when the error changes stabilize, resulting in robust test parameters.

[0108] Next, the dynamic adjustment of the present invention is described.

[0109] Dynamic adjustment includes the following steps:

[0110] S701: Construct a sliding window statistic Q_i(t) = median{Δτ_i(tk),...,Δτ_i(t)} for each channel's delay, where k is the window length. The window length k is typically set to 5 to 20 to balance real-time performance and noise immunity. The median statistic suppresses outlier interference. For example, a sudden increase in delay in a channel due to transient electromagnetic interference will not be misinterpreted as a trend.

[0111] S702: Determine the trend direction based on the difference ΔQ_i between Q_i(t) and Q_i(t1). If ΔQ_i > θ_up, increase the compensation strength; if ΔQ_i < θ_down, decrease the compensation strength. The thresholds θ_up and θ_down are set based on the noise level of the test environment; typically, θ_up is set between 1.2 and 1.5 times the upper limit of the historical fluctuation.

[0112] S703: The compensation strength adjustment formula is S_i(t) = S_i(t1)*exp(sign(ΔQ_i)*ΔQ_i / κ), where κ is the sensitivity coefficient. This controls the magnitude of the adjustment. This formula implements a nonlinear response using an exponential function: the larger the ΔQ_i, the more significant the adjustment. Meanwhile, sign(ΔQ_i) ensures the correct direction of increase or decrease. For example, when ΔQ_i = 15ns and κ = 20, the compensation strength increases by approximately 2.1 times, rapidly suppressing latency degradation.

[0113] S704: Convolve the compensation parameter φ_i with S_i(t) to obtain the final output value. The convolution operation can smooth step changes in the compensation parameter and prevent the impact of instantaneous adjustments on the test signal integrity. For example, in high-frequency signal testing, the compensation parameter needs to change gradually over time. The convolution kernel can be selected as a Gaussian function to achieve a low-pass filtering effect.

[0114] In one embodiment, in a multi-channel synchronous test scenario on an integrated circuit board, the signal delay Δτ_i of a certain channel gradually increases due to temperature increase. The sliding window (k=5) statistics show that Q_i(t) increases from the initial 5ns to 18ns, with ΔQ_i=13ns. Assuming θ_up=10ns and κ=20, the compensation strength S_i(t) is increased to exp(13 / 20)≈1.9 times the original value according to the formula. After the adjusted compensation parameter is convolved with φ_i, the output value slowly increases the compensation amount, reducing the signal synchronization error from 15ns to 3ns. If ΔQ_i subsequently recovers to -6ns (lower than θ_down=-5ns) due to heat dissipation, S_i(t) is exponentially reduced to exp(-6 / 20)≈0.74 times the original value according to the formula, avoiding overcompensation.

[0115] Median statistics reduce the impact of transient interference. If the window length k is too small, it is prone to fluctuations, while if it is too large, the response will be delayed.

[0116] The exponential formula controls sensitivity through κ. If κ is too small, it is easy to oscillate, and if it is too large, the adjustment is slow. 20 is the experimental equilibrium value.

[0117] The threshold θ_up / θ_down needs to be slightly higher than the peak value of noise fluctuation to avoid frequent false triggering.

[0118] Next, the calculation of the sliding window statistics of the present invention is described.

[0119] S801: Dynamically adjust the window length k = ceil(f_s / (2*f_c)) based on the signal frequency f_c, where f_s is the sampling frequency and ceil represents rounding up. This formula ensures that the window length matches the signal period, avoiding aliasing and improving statistical validity. For example, when testing the transmission quality of digital signals on an integrated circuit board, if f_s = 1 GHz and f_c = 10 MHz, then k = ceil(109 / (2×107)) = 50, and the window covers 2.5 signal periods, balancing real-time performance and accuracy.

[0120] S802: Apply a Hanning window weighting process to the data within the window: w_n = 5*(1cos(2πn / (k1))). The Hanning window suppresses spectral leakage by distributing weights with lower values ​​at the ends and higher values ​​in the middle. For example, when analyzing high-frequency noise on a circuit board, sudden noise at the edges of the window is weakened, making the central signal more prominent. A factor of 5 is used to normalize the sum of the weights to ensure an unbiased statistic.

[0121] S803: Calculate the weighted median Q_i^w = argminΣw_n|Δτ_i(n)Q_i^w|. The weighted median enhances robustness to outliers by minimizing the weighted absolute deviation. Specifically, when testing circuit board clock jitter, the traditional mean is susceptible to single large jitter events, while the weighted median can eliminate marginal outliers and preserve the core characteristics of the actual jitter distribution.

[0122] S804: When the difference between adjacent samples within the window is detected to be greater than 3σ, the window is automatically contracted to half its original length. This mechanism prevents sudden changes from contaminating the statistics. For example, if a sudden drop in the power supply voltage on a circuit board causes a sample jump, window contraction can quickly focus on the sudden change area, avoiding statistical distortion. After contraction, the window continues to adjust dynamically until the sudden change disappears and is restored to its original length.

[0123] In one embodiment, when testing the integrity of serial communication signals on a circuit board, a dynamic window length adapts to varying baud rates, a Hanning window suppresses clock edge ringing, a weighted median filter eliminates occasional electromagnetic interference pulses, and sudden change detection identifies transient disconnects caused by poor connector contact. This approach significantly improves the test system's noise immunity and adaptability.

[0124] Next, the dynamic adjustment of the present invention is described.

[0125] S901: Create a temperature delay compensation lookup table T_delay(T) = a*T 2 +b*T+c, where a, b, and c are calibration coefficients. The value range for a is typically [-0.005, 0.005], b is [-0.1, 0.1], and c is [-5, 5]. The optimal value should be optimized based on the circuit board material properties. This formula captures nonlinear temperature effects through quadratic terms, such as the nonlinear increase in delay caused by increased dielectric loss in high-frequency signals at high temperatures.

[0126] S902: Real-time acquisition of temperature sensor data T_i(t) for each channel, where i represents the channel number and t is the timestamp. For example, in integrated circuit board testing, each signal channel is equipped with a high-precision temperature sensor, which collects data at a frequency of 10 Hz to ensure that temperature fluctuations are captured in a timely manner.

[0127] S903: Corrected phase compensation Δφ_i = Δφ_i + α * T_delay(T_i(t)), where α is the temperature influence factor. For example, when the temperature of a channel rises to 60°C, the table outputs T_delay = 12ns. If α = 0.6, the phase compensation increases by 7.2ns, offsetting the signal synchronization deviation caused by temperature.

[0128] S904: If the temperature change rate dT_i / dt exceeds the safety threshold, compensation is suspended and an overheat alarm is triggered. This design addresses sudden overheating scenarios, such as when abnormal heat dissipation in test equipment causes a channel temperature to rise 8°C in one second. The system immediately interrupts the compensation algorithm to prevent erroneous corrections and activates the protection mechanism. This threshold is determined through thermal gradient testing of circuit board materials to avoid thermal stress damage. The synergy between formulas and logic lies in: the first two steps establish a dynamic model and input real-time data, the third step implements closed-loop compensation, and the fourth step provides safety assurance, forming a complete adaptive temperature compensation system.

[0129] Next, the creation of the temperature delay compensation look-up table of the present invention is described.

[0130] S1001: Perform a calibration experiment in a constant temperature chamber, scanning the temperature range [T_min, T_max]. This step simulates the temperature changes in the circuit board's actual operating environment by controlling the constant temperature of the chamber. T_min and T_max must cover the typical operating temperature range of the circuit board under test. For example, if the operating temperature range of an integrated circuit board is -40°C to 85°C, the calibration experiment will require a temperature scan within this range with a fixed step size (e.g., 5°C).

[0131] S1002: Record the reference delay τ_ref(T) at each temperature point. Specifically, at each temperature point, a standard test signal is sent to the circuit board through automated test equipment, and the actual delay time of the signal transmission path is measured as a reference value. For example, when the constant temperature box is stable at 25°C, the delay of a key signal path is measured to be 12.3ns, and this value will be recorded as τ_ref(25).

[0132] S1003: Fitting the cubic polynomial τ_fit(T)=p0+p1*T+p2*T using the least squares method 2 +p3*T 3 . Among them, p0-p3 are fitting coefficients, and their numerical range is determined by the nonlinear relationship between delay and temperature. The optimal value is determined by minimizing the sum of squares of the residuals between the measured data and the fitting curve. The cubic polynomial can effectively describe the nonlinear effect of temperature on delay while ensuring computational efficiency. For example, the fitting results of a circuit board are p0=12.5, p1=0.02, p2=-0.0003, p3=1e-6, and the corresponding temperature coefficient unit is ℃ -n .

[0133] S1004: Verify the fitting error: If max|τ_ref(T)-τ_fit(T)|>ε_max (e.g., ε_max = 0.5ns), increase the segmented fitting interval. For example, if the error of a certain fitting in the high temperature range (above 70°C) reaches 0.8ns, exceeding the threshold, the temperature range is divided into two segments [-40°C, 70°C] and [70°C, 85°C], and a cubic polynomial fit is performed separately. The segmented strategy improves the compensation accuracy of local temperature ranges by reducing the global fitting complexity. The resulting lookup table contains the segmented interval boundaries and the corresponding polynomial coefficients, which the test system can use in real-time to compensate for delays.

[0134] An automated testing method for an integrated circuit board (ICB) comprises the following steps: first, using a high-precision sensor array to collect synchronous signal data from each channel of the ICB in real time, and then using wavelet transform and time-frequency analysis algorithms to extract timing characteristics such as rising edge time, pulse width, and period jitter of each channel's signal transmission. Next, a multidimensional timing deviation distribution model is constructed based on preset timing constraints. Covariance matrix analysis and principal component decomposition techniques are used to quantitatively evaluate delay inconsistencies between multiple channels, specifically modeling timing offsets caused by impedance mismatch and crosstalk in high-frequency signal transmission. Based on the timing deviation analysis results, an adaptive phase compensation algorithm is designed. A minimum mean square error (MMSE) optimization model is constructed to dynamically calculate the required phase compensation coefficients for each channel. Synchronous signals are adjusted in real time with sub-nanosecond precision using an FPGA-programmable delay line, while a feedback loop is established to continuously monitor the compensation effect. Finally, in a closed-loop testing phase, a dynamically changing test stimulus signal is injected, combined with eye diagram analysis and timing margin detection techniques, to verify whether the data transmission of each channel meets the preset ±50ps synchronization threshold requirement. The verification results are fed back to the compensation system for iterative parameter optimization. This method innovatively solves the difficulty of controlling inconsistent multi-channel delays through a collaborative mechanism of feature extraction-deviation modeling-dynamic compensation-closed-loop verification: the use of a multidimensional distribution model in the timing deviation analysis stage breaks through the limitations of traditional single-parameter analysis and can accurately capture the coupling effect between channels; the dynamic compensation stage converts the timing deviation into an executable phase parameter to achieve active control of signal synchronization; the closed-loop verification mechanism ensures continuous optimization of compensation parameters through real-time feedback, thereby effectively eliminating the cumulative delay differences in multi-channel signal transmission and significantly improving the signal integrity test accuracy of high-speed digital circuits.

[0135] The above is a preferred embodiment of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present invention. These improvements and modifications should also be regarded as the scope of protection of this application.

Claims

1. An automated testing system for an integrated circuit board, characterized in that: It includes: A signal acquisition module that collects multi-channel synchronous signal data of an integrated circuit board in real time and extracts the timing characteristics of signal transmission for each channel; An analysis module for constructing a timing deviation distribution model according to preset timing constraint conditions and analyzing the delay inconsistency between multiple channels; An adjustment module for dynamically adjusting the phase compensation parameters of synchronous signals for each channel based on the timing deviation analysis result; A test module for performing a closed-loop test according to the compensated synchronous signals to verify whether the data transmission timing of each channel meets the preset synchronization threshold.

2. An automated testing system for an integrated circuit board according to claim 1, characterized in that: The dynamic adjustment of the phase compensation parameters based on the timing deviation analysis result includes: Calculating the delay offset Δτ_i of the signal of each channel relative to the reference channel, where i is the channel number; Judging whether to trigger phase compensation according to the following formula: If max(Δτ_i) - min(Δτ_i) > δ_th, where δ_th is the preset synchronization threshold, then trigger compensation; Based on the variance σ of each channel delay offset 2 Dynamically allocate compensation weight w_i=1 / (σ 2 +ε), where ε is the anti-zero constant; Writing the compensated phase parameter φ_i = φ_i0 + w_i * Δτ_i into the controller of each channel.

3. An automated testing system for an integrated circuit board according to claim 2, characterized in that: The dynamic allocation of the compensation weight further includes: Introducing the channel coupling coefficient k_ij, where i and j are the channel pair numbers, and calculating the channel delay correlation matrix C = [k_ij * Δτ_i * Δτ_j]; Determining the global compensation intensity α = 1 / (1 + exp(β(λ_max - λ0))) based on the maximum eigenvalue λ_max of the matrix C, where β is the gain coefficient and λ0 is the eigenvalue threshold; Correcting the compensation weight to w_i = α * w_i + (1 - α) * w_i_prev, where w_i_prev is the weight of the previous cycle; Limiting the fluctuation range of the compensation weight w_i: If w_i > w_max, then w_i = w_max; if w_i < w_min, then w_i = w_min.

4. An automated testing system for an integrated circuit board according to claim 3, characterized in that: The calculation of the coupling coefficient k_ij includes: Collecting the channel delay sequence {D_i(t)} in historical test data; Calculating the delay cross-correlation function R_ij(τ) = E[D_i(t)D_j(t + τ)] of the channel pair (i, j); Determining the optimal delay τ_peak according to the peak position of the cross-correlation function; Setting k_ij = exp(|τ_peak| / T_c), where T_c is the channel correlation time constant.

5. The automated testing system for an integrated circuit board according to claim 1, wherein: The dynamic adjustment of the phase compensation parameters includes: Establishing the probability density function f(Δφ_i) of the phase deviation of each channel; Calculating the optimal compensation amount according to the formula Δφ_opt = argmin Σ|Δφ_i - Δφ_opt|^2; If there is a Δφ_i exceeding the 3σ range, where σ is the standard deviation, then start the abnormal channel isolation mechanism; The gradient descent method is used to iteratively update the compensation parameters: Where η is the learning rate and E is the error function.

6. An automated testing system for an integrated circuit board according to claim 5, characterized in that: The iterative update of the gradient descent method further includes: Dynamically adjusting the learning rate η = η0 / (1 + γ * n), where η0 is the initial learning rate, γ is the attenuation coefficient, and n is the number of iterations; Calculating the momentum term Where μ is the momentum factor; Correcting the update rule to φ_i^(n + 1) = φ_i^n - η * (m_i + λ * φ_i^n), where λ is the regularization coefficient; Terminating the iteration when the change rate of the iteration error is less than 1e - 6 for 5 consecutive times.

7. The automated testing system for an integrated circuit board according to claim 1, wherein: The dynamic adjustment includes: Construct a sliding window statistic Q_i(t)=median{Δτ_i(tk),...,Δτ_i(t)} for each channel delay, where k is the window length; The trend direction is determined by the difference ΔQ_i between Q_i(t) and Q_i(t1): if ΔQ_i>θ_up, the compensation intensity is increased; if ΔQ_i<θ_down, the compensation intensity is reduced; The compensation intensity adjustment formula is S_i(t)=S_i(t1)*exp(sign(ΔQ_i)*ΔQ_i / κ), where κ is the sensitivity coefficient; The compensation parameter φ_i is convolved with S_i(t) to obtain the final output value.

8. An automated testing system for an integrated circuit board according to claim 7, characterized in that: The calculation of the sliding window statistics further includes: Dynamically adjust the window length k = ceil(f_s / (2*f_c)) according to the signal frequency f_c, where f_s is the sampling frequency; Apply Hanning window weighting processing to the data in the window: w_n=5*(1cos(2πn / (k1))); Calculate the weighted median Q_i^w = argminΣw_n|Δτ_i(n)Q_i^w|; When it is detected that the difference between adjacent samples of data in the window is greater than 3σ, the window is automatically shrunk to 1 / 2 of its original length.

9. The automated testing system for an integrated circuit board according to claim 1, wherein: The dynamic adjustment includes: Establish a temperature delay compensation lookup table T_delay(T) = a*T 2 +b*T+c, a, b, c are calibration coefficients; Real-time collection of temperature sensor data T_i(t) of each channel; The corrected phase compensation amount Δφ_i = Δφ_i + α*T_delay(T_i(t)), where α is the temperature influence factor; If the temperature change rate dT_i / dt exceeds the safety threshold, compensation is suspended and an overheating alarm is triggered.

10. An automated testing system for an integrated circuit board according to claim 9, characterized in that: The establishment of the temperature delay compensation look-up table includes: The calibration experiment was carried out in a constant temperature box with a temperature scanning range of [T_min, T_max]; Record the reference delay τ_ref(T) at each temperature point; Use the least squares method to fit the cubic polynomial τ_fit(T)=p0+p1*T+p2*T 2 +p3*T 3 ; Verify the fitting error: If max|τ_ref(T)τ_fit(T)|>ε_max, increase the segmented fitting interval.

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