High-performance logic controller
By combining the ARM core control module, FPGA and multi-level bus architecture, the IO number is expanded and the data transmission rate is improved, which solves the problems of limited IO number and slow response speed of traditional logic controllers and realizes efficient and stable logic control.
Patent Information
- Application Number
- CN202510639871.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-19
- Publication Date
- 2025-09-05
AI Technical Summary
Traditional programmable logic controllers are difficult to use in situations where the number of IO is limited, the operating speed is slow, the programming is difficult, the functions are limited, and the logic timing requirements are strict. In particular, in high-efficiency production environments, there are problems such as high system complexity, high cost, and delayed response.
It adopts ARM core control module, programmable logic module FPGA, IO expansion module, LVDS module and multi-level bus architecture. Through the combination of high-speed LVDS bus and 8080 bus, the number of IO can be expanded to thousands. It has strong parallel processing capabilities and a data transmission rate of up to 155Mbps. The FPGA logic code is written in Verilog language to achieve independent parallel access.
The high-performance logic controller has thousands of IOs and a response speed of 1uS, which reduces system complexity, increases working speed, enhances real-time performance, and improves stability and reliability, making it suitable for high-efficiency production environments.
Smart Images
Figure CN120595704A_ABST
Abstract
Description
Technical Field
[0001] The present invention mainly relates to the technical field of industrial automation control, and in particular relates to a high-performance logic controller. Background Art
[0002] A logic controller, also known as a programmable logic controller (PLC), is a digital computing control system designed specifically for use in industrial environments. Logic controllers used for digital automation control utilize a programmable memory that allows control instructions to be loaded and executed at any time. They internally store instructions for performing logical operations, sequential control, timers, counters, and arithmetic calculations, controlling various types of machinery or production processes through digital or analog input and output. A PLC is a modular system consisting of an internal CPU, instruction and data memory, input and output units, power supply modules, and digital analog modules. Despite its wide range of applications and significant advantages, PLCs offer a wide range of applications and significant advantages.
[0003] However, traditional programmable logic controllers also have certain disadvantages when used, mainly including the following shortcomings:
[0004] 1. Limited number of IOs: Traditional programmable logic controllers include "PLC, single-chip microcomputer, ARM chip, FPGA, IPC", etc., which usually have only tens to hundreds of IOs. For application scenarios with thousands of IOs, multiple modules need to be expanded. However, the more expansion modules there are, the higher the system redundancy and complexity will inevitably be. Managing thousands of IOs is a tedious task. For example: PLC using the most advanced EtherCAT bus IO module can only achieve a response speed of milliseconds, but the price of traditional expansion methods is usually higher than that of relay control systems and higher than general single-board computer systems. In addition, there are very few signal input and output modules. If necessary, it is necessary to add expansion IO, which is costly. This increases the initial investment cost, which may be a consideration for users with limited budgets;
[0005] 2. Slow working speed: Compared with computers, traditional programmable logic controllers work slowly, with delayed output and input responses. The communication interface is generally only a serial port, which limits the data transmission rate. All of these may affect the real-time performance of the system.
[0006] 3. High cost and programming difficulty: Compared with single-chip microcomputers, PLC hardware and development costs are relatively high, and its programming language is relatively complex, which makes it difficult for beginners to learn. This limits the use of traditional programmable logic controllers in certain cost-sensitive or low-tech application scenarios;
[0007] 4. Limited functionality: Compared to MCUs, traditional PLCs have limited programming functionality and expansion capabilities. This may not be suitable for applications that require highly customized or complex control logic.
[0008] 5. In situations where strict logic timing is required, the traditional programmable logic controller itself has a lag in response, so it is difficult to meet the application requirements of some applications that require fast response and precise control of logic timing.
[0009] To sum up, the technical shortcomings of being difficult to apply to occasions with limited IO number, slow working speed, relatively high programming difficulty, limited functions, and strict requirements on logical timing are technical problems that need to be urgently solved by personnel in this technical field, especially in the field of product testing with an efficiency of up to tens of thousands of products per minute. Summary of the Invention
[0010] Based on this, an object of the present invention is to provide a high-performance logic controller to solve the technical problems raised in the above background technology.
[0011] To achieve the above object, the present invention provides the following technical solutions:
[0012] A high-performance logic controller includes an ARM core control module, the ARM core control module is connected to a memory module for storing system programs and user programs; the ARM core control module is also connected to a programmable logic module FPGA for parallel port communication control output and reading input status;
[0013] The programmable logic module FPGA is connected to an IO expansion module in parallel for expanding multiple inputs and outputs; the programmable logic module FPGA is also connected to an LVDS module for an LVDS communication interface;
[0014] The ARM core control module is also connected to an Ethernet module for a network communication interface, an RS232 module for a serial communication interface, and a USB module for a USB communication interface.
[0015] The IO expansion module is connected to an input module and an output module.
[0016] Preferably, the ARM core control module communicates with the programmable logic module FPGA at high speed, and is used for synchronously exchanging memory data between the ARM core control module and the programmable logic module FPGA in real time.
[0017] Preferably, the programmable logic module FPGA adopts a star structure topology, and uses a high-speed LVDS bus to connect the main FPGA1 and FPGA1-n in a star structure topology.
[0018] Preferably, the expanded FPGAs 1 - n further expand two independent 8080 communication buses for connecting to a dedicated IO expansion chip.
[0019] Preferably, each bus of the 8080 communication is connected to 4 expansion chips, and each dedicated IO expansion chip has 4*8=32 IOs.
[0020] Preferably, the LVDS bus adopts a 4-line mode and only uses four key signals of "TX_DAT, TX_CLK, RX_DAT, RX_CLK".
[0021] Preferably, any one of the expanded FPGAs 1 - n uses an 8080 bus including five key signals of “DATA[0-7], ADDR[0-2], WR, RD, and CS”, which amounts to 14 IOs.
[0022] Preferably, each bus of the 8080 communication is connected to four dedicated IO expansion chips after its driving capability is enhanced by a buffer chip.
[0023] Preferably, the programmable logic module FPGA uses Verilog language to write FPGA logic code to achieve independent parallel access of 4 expansion chips for each bus.
[0024] In summary, the present invention mainly has the following beneficial effects:
[0025] In the present invention, 1. System complexity is reduced: the logic controller has more than one thousand IOs, and the response speed of each IO must reach 1uS. Therefore, the timing logic of IO timing management is crucial. For thousands of control units, if the internal design of the controlled object's high-performance logic controller meets user needs while the hardware design is simple, the input and output are designed in an expandable manner, without the need for additional expansion;
[0026] 2. Improved operating speed: The programmable logic module FPGA3 is implemented by millions of logic units, so it has parallel processing capabilities and runs much faster than single-chip microcomputers and DSPs. There is no lag in output and input response.
[0027] 3. Improve the real-time performance of the system: The LVDS module 8 is connected to the programmable logic module FPGA3. The data transmission rate here can reach more than 155Mbps after instrument testing, and can reach up to 800Mbps; there is no lag in the response of the front-end output and input, and the logic controller system can fully achieve real-time performance.
[0028] 4. Improve stability and reliability: The high-performance logic controller has a single manufacturing process and can provide a stable, reliable and high-performance logic control system to avoid equipment failure or damage caused by improper operation.
[0029] In summary, the technical benefits of high-performance logic controllers are primarily reflected in the stability and reliability of logic control systems, improved efficiency, rapid response and control, high safety, low costs, and reduced environmental impact. These technical benefits have made high-performance logic controllers an indispensable component in the passive component industry and other fields. In terms of device logic control, they can precisely control the measurement logic of the entire automation equipment, improving the real-time performance of automation equipment and ensuring a high-efficiency production rhythm. BRIEF DESCRIPTION OF THE DRAWINGS
[0030] Figure 1 It is the overall structural framework diagram of the present invention;
[0031] Figure 2 Schematic diagram of constructing multiple independent LVDS buses for the main FPGA1 of the present invention;
[0032] Figure 3 Schematic diagram of the main FPGA 1 and the extended FPGA 1-6 of the present invention;
[0033] Figure 4 Schematic diagram of the system solution of the present invention.
[0034] Description of the drawings: 1. ARM core control module; 2. Memory module; 3. Programmable logic module FPGA; 4. IO expansion module; 5. Ethernet module; 6. RS232 module; 7. USB module; 8. LVDS module; 9. Input module; 10. Output module; DETAILED DESCRIPTION
[0035] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.
[0036] like Figures 1 to 3 As shown, a high-performance logic controller includes an ARM core control module 1, the ARM core control module 1 is connected to a memory module 2 for storing system programs and user programs; the ARM core control module 1 is also connected to a programmable logic module FPGA3 for parallel port communication control output and reading input status;
[0037] The programmable logic module FPGA3 is connected to an IO expansion module 4 in parallel for expanding multiple inputs and outputs; the programmable logic module FPGA3 is also connected to an LVDS module 8 for an LVDS communication interface;
[0038] The ARM core control module 1 is also connected to an Ethernet module 5 for a network communication interface, an RS232 module 6 for a serial communication interface, and a USB module 7 for a USB communication interface.
[0039] The IO expansion module 4 is connected to an input module 9 and an output module 10 .
[0040] The ARM core control module 1 communicates with the programmable logic module FPGA3 at high speed, and is used to synchronously exchange memory data between the ARM core control module 1 and the programmable logic module FPGA3 in real time.
[0041] The programmable logic module FPGA3 adopts a star structure topology, and uses a high-speed LVDS bus to connect the main FPGA1 and FPGA1-n in a star structure topology.
[0042] The expanded FPGA1-n further expands two independent 8080 communication buses for connecting to dedicated IO expansion chips.
[0043] Each 8080 communication bus connects 4 expansion chips, and each dedicated IO expansion chip has 4*8=32 IOs.
[0044] The LVDS bus adopts the 4-line mode and only uses four key signals: "TX_DAT, TX_CLK, RX_DAT, RX_CLK".
[0045] Any of the expanded FPGAs 1-n uses the 8080 bus, which includes five key signals: DATA[0-7], ADDR[0-2], WR, RD, and CS, for a total of 14 IOs.
[0046] Each bus of the 8080 communication is connected to four dedicated IO expansion chips after its driving capability is enhanced by a buffer chip.
[0047] The programmable logic module FPGA3 uses Verilog language to write FPGA logic code to achieve independent and parallel access of each bus to four expansion chips.
[0048] Example 1:
[0049] It should be noted that, in this embodiment, user program instructions and related data of the logic controller are stored in the memory module 2, which is connected to the ARM core control module 1, so as to facilitate reading for subsequent human-computer interaction; the ARM core control module 1 has three different communication interfaces with the outside world, so that users have more choices;
[0050] In addition, the ARM core control module 1 also needs to communicate with the programmable logic module FPGA3 in parallel, which is the main logic control module for input and output. The programmable logic module FPGA3 obtains external input through the IO expansion module 4 and can control external output. It can transmit data to the ARM core control module 1 and also transmit data out through the LVDS module 8. The data transmission rate here can reach more than 155Mbps and up to 800Mbps.
[0051] It is worth further explaining the design method of the IO expansion module: IO expansion can achieve more available IO, connect to the parallel port of the programmable logic module FPGA3, and provide stable and reliable data transmission. It has obvious advantages in logic control rate over traditional logic controllers, and these expanded IO will not increase the cost.
[0052] In the existing technology, IO expansion is implemented using SPI bus, IIC bus, serial-to-parallel conversion chip, etc., and its controller is mostly MCU time-sharing processing. Usually, the expanded IO can only operate at an operating frequency below 10KHz, and due to the existence of bus time-sharing multiplexing, it is impossible to achieve parallel execution of multiple IOs.
[0053] Furthermore, due to the address limit of the expansion chip itself, the number of expansion IOs is limited by the chip address and the number of processor pins, making unlimited expansion impossible. The combined effect of these factors means that the expanded IO cannot achieve high-speed, real-time, and parallel control.
[0054] Different from the traditional IO expansion method, this invention adopts a four-layer expansion method:
[0055] First layer: First, ARM and FPGA communicate at high speed to exchange memory data between them and synchronize their data in real time;
[0056] The second layer uses the FPGA's star topology to expand the main FPGA chip's I / O capacity by six times. A high-speed LVDS bus is used between the main FPGA1 and the expansion FPGAs 1-6 for real-time memory data exchange.
[0057] The third layer: The expanded FPGAs 1-6 each extend two independent 8080 communication buses for connecting to dedicated IO expansion chips.
[0058] Fourth layer: The expanded FPGAs 1-6 connect each 8080 bus to a dedicated IO expansion chip. Each bus connects to four expansion chips, and each dedicated IO expansion chip has 4*8=32 IOs.
[0059] After combining the above four steps, the actual number of expanded IOs reaches: 6*2*4*4*8=1536, achieving the goal of expanding the IO number by thousands of times; after three layers of expansion, ARM operations on its own memory units can be immediately executed on the expanded IOs of FPGA1-n.
[0060] Theoretical analysis:
[0061] Currently, the number of commonly used FPGA chips on the market is generally around 100 after removing dedicated IO. The LVDS bus uses a 4-line method and only uses four key signals: "TX_DAT, TX_CLK, RX_DAT, and RX_CLK." Therefore, in theory, the number of LVDS bus groups that can be expanded in FPGA1 is around 100 / 4 = 25. The 8080 bus used by any of the expanded FPGAs 1-6 includes key signals such as "DATA[0-7], ADDR[0-2], WR, RD, and CS," totaling 14 IOs. Therefore, in theory, the expanded FPGA can construct (100-4) / 14≈6 buses.
[0062] Based on the above calculations, the principle of the present invention can theoretically expand the number of IOs to: 25*6*4*4*8=19200.
[0063] 1. Innovative application of hybrid bus architecture
[0064] Combination of LVDS and 8080 buses: This solution cleverly combines the high-speed LVDS bus and the classic 8080 bus to form a hybrid bus architecture. The LVDS bus is used for high-speed, long-distance data transmission, especially for star-shaped topology connections between FPGAs, solving the problem of limited FPGA chip I / O ports. The 8080 bus is used for connection to ARM chips and dedicated I / O expansion chips, enabling flexible system expansion.
[0065] 2. Efficient IO expansion
[0066] Multi-level IO expansion: The 8080 bus is expanded through the FPGA, connected to a buffer chip to enhance the driving capability, and then connected to a dedicated IO expansion chip to form a multi-level IO expansion. This strategy not only increases the number of IO ports, but also improves signal stability and driving capability through the buffer chip, ensuring reliable data transmission.
[0067] 3. Parallel access and real-time response
[0068] Independent parallel access mechanism: FPGA logic code written in Verilog enables independent parallel access to four expansion chips for each bus. This mechanism greatly improves data access efficiency, enabling the system to process multiple data access requests simultaneously and achieve high-speed real-time access.
[0069] Optimized state machine logic: Optimized state machine logic is implemented in the FPGA to manage data access and bus control. The design of the state machine logic enables the system to perform corresponding operations based on different states, thereby improving the system's response speed and stability.
[0070] 4. Real-time data exchange between multiple chips
[0071] The LVDS bus and the 8080 bus work together: The main FPGA and expansion FPGAs exchange memory data in real time via the LVDS bus, while the ARM chip and the main FPGA exchange memory data in real time via the 8080 bus. This collaborative mechanism enables seamless connectivity and fast data communication between multiple chips, improving overall system performance and real-time capabilities.
[0072] 5. Modularity and customizability
[0073] Modular Design: The entire solution adopts a modular design philosophy, allowing each component (such as the LVDS bus connection, 8080 bus connection, and I / O expansion chip) to be independently designed and optimized based on specific needs. This modular design enhances system flexibility and customizability, making the solution adaptable to diverse application scenarios and requirements.
[0074] The working principle of this embodiment is:
[0075] Principle 1: FPGA1 uses the FPGA1-n star topology principle composed of LVDS high-speed bus;
[0076] 1. The main FPGA1 constructs multiple independent LVDS buses and uses high-speed LVDS buses to connect FPGA1 and FPGA1-n in a star topology to solve the problem of IO limitation of the FPGA chip itself. Figure 2 As shown;
[0077] The expanded FPGA is used to construct an 8080 bus for communication, which is connected to four dedicated IO expansion chips after its driving capability is enhanced by the buffer chip. Figure 3 As shown;
[0078] The ARM chip and the main FPGA exchange memory data in real time via the 8080 bus, achieving seamless connectivity between the ARM chip and the FPGA. This design allows the system to fully utilize the processing power of the ARM chip and the FPGA's IO expansion capabilities, enabling more complex control logic and data processing functions.
[0079] The main FPGA1 constructs multiple independent LVDS buses and uses high-speed LVDS buses to connect to multiple FPGAs (FPGA1-n) in a star topology. This design effectively breaks through the limitations of a single FPGA chip's IO ports.
[0080] LVDS, or low-voltage differential signaling technology, has the advantages of high speed, low power consumption, and strong anti-interference, making it very suitable for high-speed data transmission. Through the LVDS bus, long-distance, high-speed data communication can be achieved, thus meeting the data transmission needs in complex systems.
[0081] Principle 2: FPGA1-n multiple independent buses access the expansion chip in parallel to achieve high-speed real-time expansion IO principle;
[0082] Use Verilog language to write FPGA logic code to achieve independent and parallel access of each bus to four expansion chips, thereby achieving high-speed real-time access to thousands of IOs, including its state machine logic;
[0083] Verilog language to write FPGA logic code:
[0084] The FPGA logic code was written using the Verilog hardware description language, enabling each bus to independently and concurrently access four expansion chips. This design enabled the system to efficiently handle large numbers of data access requests, improving data access speed.
[0085] Design of state machine logic:
[0086] State machine logic is implemented in the FPGA to manage data access and bus control. The design of the state machine logic enables the system to perform corresponding operations based on different states, thereby achieving efficient data management and real-time response.
[0087] Principle 4: The main FPGA1 and the expansion FPGA1-n exchange register data in real time via a high-speed LVDS bus, thereby expanding the number of FPGA chip pins:
[0088] The main FPGA and the expanded FPGA exchange memory data in real time through the LVDS bus and its state machine logic.
[0089] Principle 5: ARM and FPGA exchange memory data in real time, thereby enabling access to their own memory to be mapped to the FPGA's extended IO:
[0090] The ARM chip and the main FPGA exchange memory data in real time through the 8080 bus, so that access to the ARM's own memory unit can be immediately executed on the FPGA's extended IO, and its state machine logic.
[0091] Example 2: Implementing a system-level solution
[0092] like Figure 4 As shown, the system is connected to 4 Agilent E4981A instruments, and implements the Handler interface, Scanner interface, and GPIB communication interface of each instrument; connects 4 AS7810 instruments, and implements the Handler interface of each instrument; connects 2 AS7860 instruments, and implements the handler interface of each instrument; implements an LVDS high-speed communication interface for connecting an AirControl valve island control unit to control an array of 72 solenoid valves; implements a DD motor control unit as an axis control AIX1 unit; implements a feeder loading area stepper motor control unit as an axis control AIX2 unit; implements 4 DIO interaction units and 32 fiber optic sensor control units; implements 8 AI and AO interaction units each for controlling the connection of the air pressure unit; implements 3 AIOs and several DIO units and an RS232 communication interface to implement three blower negative pressure units.
[0093] The above embodiments are only for illustrating the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the present invention.
Claims
1. A high-performance logic controller, comprising an ARM core control module (1), characterized in that: The ARM core control module (1) is connected to a memory module (2) for storing system programs and user programs; the ARM core control module (1) is also connected to a programmable logic module FPGA (3) for parallel port communication control output and reading input status; The programmable logic module FPGA (3) is connected to an IO expansion module (4) in parallel for expanding multiple inputs and outputs; the programmable logic module FPGA (3) is also connected to an LVDS module (8) for an LVDS communication interface; The ARM core control module (1) is also connected to an Ethernet module (5) for a network communication interface, an RS232 module (6) for a serial communication interface, and a USB module (7) for a USB communication interface. The IO expansion module (4) is connected to an input module (9) and an output module (10).
2. A high-performance logic controller according to claim 1, characterized in that: The ARM core control module (1) communicates with the programmable logic module FPGA (3) at high speed, and is used for synchronously exchanging memory data between the ARM core control module (1) and the programmable logic module FPGA (3) in real time.
3. A high-performance logic controller according to claim 1, characterized in that: The programmable logic module FPGA (3) adopts a star structure topology, and uses a high-speed LVDS bus to connect the main FPGA1 and FPGA1-n in a star structure topology.
4. A high-performance logic controller according to claim 3, characterized in that: The expanded FPGAs 1-n further expand two independent 8080 communication buses for connecting to a dedicated IO expansion chip.
5. A high-performance logic controller according to claim 4, characterized in that: Each bus of the 8080 communication is connected to 4 expansion chips, and each dedicated IO expansion chip has 4*8=32 IOs.
6. A high-performance logic controller according to claim 1, characterized in that: The LVDS bus adopts a 4-line mode and only uses four key signals: "TX_DAT, TX_CLK, RX_DAT, and RX_CLK".
7. A high-performance logic controller according to claim 3, characterized in that: After expansion, any one of the FPGAs 1-n uses the 8080 bus, which includes five key signals: DATA[0-7], ADDR[0-2], WR, RD, and CS, totaling 14 IOs.
8. A high-performance logic controller according to claim 5, characterized in that: Each bus of the 8080 communication is connected to four dedicated IO expansion chips after its driving capability is enhanced by a buffer chip.
9. A high-performance logic controller according to claim 1, characterized in that: The programmable logic module FPGA (3) uses Verilog language to write FPGA logic code to achieve independent parallel access of each bus to four expansion chips.