Low dropout regulator with bidirectional current conduction capability

Abstract

The invention discloses a low dropout linear regulator with bidirectional current conduction capability, which is characterized in that two input ends of an error amplifier are respectively connected with signals VB and FB, and a power level of a linear transconductance ring is used as a light load power level; the first output end of the error amplifier is connected with the first input end of the linear transconductance ring, the first input end of the light load power level and the input end of the first source follower, and the output end of the first source follower is connected with the first input end of the heavy load power level. The second output end of the error amplifier is connected with the second input end of the linear transconductance ring, the second input end of the light load power level and the input end of the second source follower, and the output end of the second source follower is connected with the second input end of the heavy load power level. The problem that the quiescent current of a traditional bidirectional current conduction LDO is too large under the conditions of light load and no load is solved, and it is guaranteed that the output power tube can be completely conducted when the LDO works in an open loop mode.

Description

Technical Field

[0001] The present invention relates to a low voltage difference linear regulator, in particular to a low voltage difference linear regulator with bidirectional current conduction capability, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] Low-Dropout Voltage Regulators (LDOs) are commonly used in battery-powered systems to provide a stable voltage that doesn't fluctuate with the power supply or load. Traditional LDOs consist of three modules: an error amplifier, a power regulator, and a feedback resistor. The power regulator is typically a single P-type or N-type transistor, and therefore can only conduct current in one direction to the output. However, applications such as motor drives, DDR memories, and semiconductor thermoelectric coolers require LDOs to be able to conduct current in both directions. This means the output can both supply current to the load and absorb current from the load. Rail-to-rail output capability is also required, and the output-stage power transistor must be fully conductive.

[0003] Prior art 1 [R. Hogervorst, JP Tero, RGH Eschauzier and JH Huijsing, "A compact power-efficient 3 V CMOS rail-to-rail input / output operational amplifier for VLSI cell libraries," Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94, San Francisco, CA, USA, 1994, pp. 244-245, doi: 10.1109 / ISSCC.1994.344656.] uses a CLASS-AB operational amplifier structure to build an LDO. This implements bidirectional current conduction based on the operating principle of a linear transconductance loop. However, if the output power regulator is large, the quiescent current of the LDO will be large at light load and no load, resulting in high quiescent power consumption.

[0004] Prior art 2 [S. Asefi, A. Saberkari, H. Martinez-Garcia and E. Alarcon,"Low-Quiescent Current Class-AB CMOS LDO Voltage Regulator," 2018 IEEEInternational Symposium on Circuits and Systems (ISCAS), Florence, Italy, 2018, pp. 1-4, doi: 10.1109 / ISCAS.2018.8351006.] introduces an error into the output stage of the error amplifier so that the PMOS power regulator and the NMOS regulator are not turned on at the same time when the load is light or no load, effectively reducing static power consumption. However, this means that the LDO cannot work properly under light load or no load conditions, the output accuracy cannot be guaranteed, and the output stage power transistor cannot be fully turned on.

[0005] Prior art 3 Chinese patent number CN202410339151.3 discloses a Class-AB operational amplifier circuit and system. Based on prior art 1, the bias current of the linear transconductance loop is adjusted to achieve the purpose of controlling the quiescent current of the output stage. However, if the size of the output stage power adjustment tube is large, the problem of excessive quiescent current cannot be fundamentally improved, and the loop stability will be affected.

[0006] Prior art 4 Chinese patent number CN202410442690.X discloses a bidirectional current low-voltage difference linear regulator. On the basis of prior art 1, two operational amplifiers are additionally introduced as level shifters to reduce the quiescent current of the LDO when it is lightly loaded or no-loaded. However, the circuit is complex, additional static power consumption is introduced, and a larger chip area is increased. In addition, due to the presence of the level shifter, when the LDO is in open-loop operation, the large-size output stage power tube cannot be fully turned on.

[0007] In summary, traditional LDOs only conduct current in one direction. However, applications such as motor drives, DDR memory, and semiconductor thermoelectric coolers require bidirectional current conduction capabilities. This means the LDO's output can both supply current to the load and sink current from the output. Furthermore, rail-to-rail output is required, and the output-stage power transistors must be fully conductive. Prior Art 1 and Prior Art 3 use a Class-AB op amp architecture to implement bidirectional current conduction and rail-to-rail output LDOs. However, under light or no-load operating conditions, both the PMOS and NMOS power regulators conduct simultaneously. With large power regulators, even with a linear transconductance loop to control the power stage's gate voltage, a high quiescent current is unavoidable. Prior Art 4 adds a level shifter to Prior Art 1, addressing the issue of excessive quiescent current under no-load and light-load conditions. However, this results in a drawback: the output-stage power transistors cannot fully conduct. Summary of the Invention

[0008] The technical problem to be solved by the present invention is to provide a low voltage dropout linear regulator with bidirectional current conduction capability, which has a low quiescent current under light load and no-load conditions, and when the LDO is in open-loop operation, the heavy-load power stage output adjustment tube can be fully turned on.

[0009] In order to solve the above technical problems, the technical solution adopted by the present invention is: A low-voltage-dropout linear regulator with bidirectional current conduction capability includes an error amplifier, a linear transconductance loop, a light-load power stage, a heavy-load power stage, a first source follower, a second source follower, and a voltage divider feedback circuit. The first input of the error amplifier is connected to a signal VB, the second input of the error amplifier is connected to a signal FB, the power stage of the linear transconductance loop serves as a light-load power stage, the first output of the error amplifier is connected to the first input of the linear transconductance loop, the first input of the light-load power stage, and the input of the first source follower, the output of the first source follower is connected to the first input of the heavy-load power stage, the second output of the error amplifier is connected to the second input of the linear transconductance loop, the second input of the light-load power stage, and the input of the second source follower, the output of the second source follower is connected to the second input of the heavy-load power stage, the output of the light-load power stage and the output of the heavy-load power stage are connected to the input of the voltage divider feedback circuit and generate an output signal VOUT, and the output of the voltage divider feedback circuit generates a signal FB.

[0010] Furthermore, the error amplifier includes a PMOS tube M1, a PMOS tube M2, an NMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, a PMOS tube M7, a PMOS tube M8 and a tail current source I1. The gate of the PMOS tube M1 serves as a first input terminal of the error amplifier and is connected to the signal VB. The gate of the PMOS tube M2 serves as a second input terminal of the error amplifier and is connected to the signal FB. The source of the PMOS tube M1 is connected to one end of the tail current source I1 and the source of the PMOS tube M2. The drain of the PMOS tube M1 is connected to the drain of the NMOS tube M3, the gate of the NMOS tube M3 and the gate of the NMOS tube M6 and is connected to the bias voltage VBN2. The drain of the PMOS tube M2 is connected to the gate of the NMOS tube M3 and the gate of the NMOS tube M6 and is connected to the bias voltage VBN2. The drain of M4, the gate of the NMOS transistor M4, and the gate of the NMOS transistor M5 are connected and connected to the bias voltage VBN1. The drain of the NMOS transistor M5 serves as the second output terminal of the error amplifier and generates the bias voltage VGN1. The source of the NMOS transistor M3, the source of the NMOS transistor M4, the source of the NMOS transistor M5, and the source of the NMOS transistor M6 are grounded. The drain of the NMOS transistor M6 is connected to the drain of the PMOS transistor M7, the gate of the PMOS transistor M7, and the gate of the PMOS transistor M8 and connected to the bias voltage VBP1. The drain of the PMOS transistor M8 serves as the first output terminal of the error amplifier and generates the bias voltage VGP1. The source of the PMOS transistor M7, the other end of the tail current source I1, and the source of the PMOS transistor M8 are connected to the power supply VDD.

[0011] Furthermore, the linear transconductance loop includes a PMOS transistor M9, an NMOS transistor M10, a PMOS transistor M11, a PMOS transistor M12, an NMOS transistor M13, an NMOS transistor M14, a PMOS transistor MP1, an NMOS transistor MN1, a current source I2, and a current source I3. The source of the PMOS transistor M9 is connected to the drain of the NMOS transistor M10 and is connected to the bias voltage VGP1 as a first input end of the linear transconductance loop. The drain of the PMOS transistor M9 is connected to the source of the NMOS transistor M10 and is connected to the bias voltage VGN1 as a second input end of the linear transconductance loop. The gate of the PMOS transistor M9 is connected to the gate of the PMOS transistor M12, the PMOS transistor M13, the PMOS transistor M14, the PMOS transistor MP1, the NMOS transistor MN1, the current source I2, and the current source I3. The drain of the OS transistor M12 is connected to one end of the current source I3, the source of the PMOS transistor M12 is connected to the drain of the PMOS transistor M11 and the gate of the PMOS transistor M11, the gate of the NMOS transistor M10 is connected to the gate of the NMOS transistor M13, the drain of the NMOS transistor M13 is connected to one end of the current source I2, the source of the NMOS transistor M13 is connected to the drain of the NMOS transistor M14 and the gate of the NMOS transistor M14, the source of the PMOS transistor M11, the other end of the current source I2, and the source of the PMOS transistor MP1 are connected to the power supply VDD, and the other end of the current source I3, the source of the NMOS transistor M14, and the source of the NMOS transistor MN1 are grounded.

[0012] Furthermore, the PMOS transistor MP1 and the NMOS transistor MN1 constitute a light-load power stage, the gate of the PMOS transistor MP1 serves as a first input terminal of the light-load power stage and is connected to the bias voltage VGP1, the gate of the NMOS transistor MN1 serves as a second input terminal of the light-load power stage and is connected to the bias voltage VGN1, and the drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1 and serves as an output terminal of the light-load power stage to generate an output signal VOUT.

[0013] Furthermore, the heavy-load power stage includes a PMOS transistor MP2 and an NMOS transistor MN2. The source of the PMOS transistor MP2 is connected to the power supply VDD, the gate of the PMOS transistor MP2 serves as the first input terminal of the heavy-load power stage and is connected to the bias voltage VGP2, the drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN2 and serves as the output terminal of the heavy-load power stage to generate the output signal VOUT, the gate of the NMOS transistor MN2 serves as the second input terminal of the heavy-load power stage and is connected to the bias voltage VGN2, and the source of the NMOS transistor MN2 is grounded.

[0014] Furthermore, the first source follower includes a PMOS tube M15, a PMOS tube M16, an NMOS tube M17 and a resistor R3, the source of the PMOS tube M15 is connected to the power supply VDD, the gate of the PMOS tube M15 is connected to the bias voltage VBP1, the drain of the PMOS tube M15 is connected to the source of the PMOS tube M16 and the drain of the NMOS tube M17 and serves as the output end of the first source follower to generate the bias voltage VGP2, the gate of the PMOS tube M16 serves as the input end of the first source follower and is connected to the bias voltage VGP1, the drain of the PMOS tube M16 is connected to one end of the resistor R3, the gate of the NMOS tube M17 is connected to the bias voltage VBN1, and the other end of the resistor R3 and the source of the NMOS tube M17 are grounded.

[0015] Furthermore, the second source follower includes an NMOS tube M18, an NMOS tube M19, a PMOS tube M20 and a resistor R4, one end of the resistor R4 is connected to the source of the PMOS tube M20 to the power supply VDD, the other end of the resistor R4 is connected to the drain of the NMOS tube M18, the gate of the NMOS tube M18 serves as the input end of the second source follower and is connected to the bias voltage VGN1, the source of the NMOS tube M18 is connected to the drain of the NMOS tube M19 and the drain of the PMOS tube M20 and serves as the output end of the second source follower and generates the bias voltage VGN2, the gate of the PMOS tube M20 is connected to the bias voltage VBP1, the gate of the NMOS tube M19 is connected to the bias voltage VBN1, and the source of the NMOS tube M19 is grounded.

[0016] Furthermore, the voltage divider feedback circuit includes a resistor R1 and a resistor R2, one end of the power supply R1 is connected to the signal VC, the other end of the resistor R1 is connected to one end of the resistor R2 and serves as the output end of the voltage divider feedback circuit to generate a signal FB, and the other end of the resistor R2 is connected to the output signal VOUT.

[0017] Furthermore, it also includes a load circuit, which includes a load resistor RL and a load capacitor CL. One end of the resistor RL and one end of the capacitor CL are connected to the output signal VOUT, the other end of the resistor R1 is connected to the signal VS, and the other end of the capacitor CL is grounded.

[0018] Compared with the prior art, the present invention has the following advantages and effects: The present invention provides a low-voltage dropout linear regulator with bidirectional current conduction capability. The error amplifier adopts a CLASS-AB output structure, and two power branches are designed, namely a light-load power stage and a heavy-load power stage. A linear transconductance loop structure is used to control the gate voltage of the light-load power stage output adjustment tube. The gate voltage of the light-load power stage power adjustment tube is level-shifted by a first-stage source follower circuit and then controls the gate voltage of the heavy-load power stage output adjustment tube. This ensures that under light-load and no-load conditions, the heavy-load output stage can be nearly turned off, thereby achieving the purpose of reducing quiescent current. As the load current increases, the heavy-load power stage can be gradually turned on. When the LDO is in open-loop operation, the source follower circuit of the present invention can fully turn on the heavy-load power stage output adjustment tube. The present invention solves the problem of excessive quiescent current under light-load and no-load conditions in conventional bidirectional current-conducting LDOs, and ensures that the output power tube can be fully turned on when the LDO is in open-loop operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of a low voltage difference linear regulator with bidirectional current conducting capability of the present invention.

[0020] Figure 2 Schematic diagram of a typical linear transconductance ring structure according to an embodiment of the present invention.

[0021] Figure 3 FIG. 1 is a schematic diagram showing how the gate voltage of a power regulating tube varies with load current according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to elaborate on the technical solutions adopted by the present invention to achieve the predetermined technical purpose, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0023] like Figure 1 As shown, a low-voltage difference linear regulator with bidirectional current conduction capability of the present invention includes an error amplifier, a linear transconductance loop, a light-load power stage, a heavy-load power stage, a first source follower, a second source follower and a voltage divider feedback circuit. The first input end of the error amplifier is connected to the signal VB, the second input end of the error amplifier is connected to the signal FB, the power stage of the linear transconductance loop serves as the light-load power stage, the first output end of the error amplifier is connected to the first input end of the linear transconductance loop, the first input end of the light-load power stage and the input end of the first source follower, the output end of the first source follower is connected to the first input end of the heavy-load power stage, the second output end of the error amplifier is connected to the second input end of the linear transconductance loop, the second input end of the light-load power stage and the input end of the second source follower, the output end of the second source follower is connected to the second input end of the heavy-load power stage, the output end of the light-load power stage and the output end of the heavy-load power stage are connected to the input end of the voltage divider feedback circuit and generate an output signal VOUT, and the output end of the voltage divider feedback circuit generates a signal FB.

[0024] The error amplifier includes a PMOS transistor M1, a PMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6, a PMOS transistor M7, a PMOS transistor M8 and a tail current source I1. The gate of the PMOS transistor M1 serves as the first input terminal of the error amplifier and is connected to the signal VB. The gate of the PMOS transistor M2 serves as the second input terminal of the error amplifier and is connected to the signal FB. The source of the PMOS transistor M1 is connected to one end of the tail current source I1 and the source of the PMOS transistor M2. The drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M3, the gate of the NMOS transistor M3 and the gate of the NMOS transistor M6 and is connected to the bias voltage VBN2. The drain of the PMOS transistor M2 is connected to the drain of the NMOS transistor M4. The drain, the gate of the NMOS transistor M4, and the gate of the NMOS transistor M5 are connected and connected to the bias voltage VBN1. The drain of the NMOS transistor M5 serves as the second output terminal of the error amplifier and generates the bias voltage VGN1. The source of the NMOS transistor M3, the source of the NMOS transistor M4, the source of the NMOS transistor M5, and the source of the NMOS transistor M6 are grounded. The drain of the NMOS transistor M6 is connected to the drain of the PMOS transistor M7, the gate of the PMOS transistor M7, and the gate of the PMOS transistor M8 and connected to the bias voltage VBP1. The drain of the PMOS transistor M8 serves as the first output terminal of the error amplifier and generates the bias voltage VGP1. The source of the PMOS transistor M7, the other end of the tail current source I1, and the source of the PMOS transistor M8 are connected to the power supply VDD.

[0025] The linear transconductance loop includes a PMOS transistor M9, an NMOS transistor M10, a PMOS transistor M11, a PMOS transistor M12, an NMOS transistor M13, an NMOS transistor M14, a PMOS transistor MP1, an NMOS transistor MN1, a current source I2, and a current source I3. The source of the PMOS transistor M9 is connected to the drain of the NMOS transistor M10 and is connected to the bias voltage VGP1 as the first input end of the linear transconductance loop. The drain of the PMOS transistor M9 is connected to the source of the NMOS transistor M10 and is connected to the bias voltage VGN1 as the second input end of the linear transconductance loop. The gate of the PMOS transistor M9 is connected to the gate of the PMOS transistor M12, the gate of the PMOS transistor M The drain of the PMOS transistor M12 is connected to one end of the current source I3, the source of the PMOS transistor M12 is connected to the drain of the PMOS transistor M11 and the gate of the PMOS transistor M11, the gate of the NMOS transistor M10 is connected to the gate of the NMOS transistor M13, the drain of the NMOS transistor M13 is connected to one end of the current source I2, the source of the NMOS transistor M13 is connected to the drain of the NMOS transistor M14 and the gate of the NMOS transistor M14, the source of the PMOS transistor M11, the other end of the current source I2, and the source of the PMOS transistor MP1 are connected to the power supply VDD, and the other end of the current source I3, the source of the NMOS transistor M14, and the source of the NMOS transistor MN1 are grounded.

[0026] In order to explain the embodiments of the present invention, it is necessary to briefly introduce the working principle of a typical linear transconductance loop. Figure 2 As shown, ignoring the body effect and channel modulation effect, according to the saturation current formula of the MOS tube:

[0027]

[0028] in Is the source-drain current of the MOS tube; It is the mobility of the carriers in the MOS tube. There are differences between NMOS and PMOS, so no distinction is made here. is the gate oxide capacitance of the MOS tube; W / L is the width-to-length ratio of the MOS tube; is the gate-source voltage value of the MOS tube; is the threshold voltage of the MOS tube.

[0029] Figure 2 The gate-source voltages of M21, M23, M24, and MP satisfy the following relationship:

[0030] Assume that the threshold voltage of all PMOS tubes is The same, by setting the current values ​​of I6, I5, I4 reasonably, so that M21 and M23 can match, we get , according to the above The expression of MP's static current The following relationship is satisfied:

[0031] According to the above formula, the quiescent current of the output PMOS is determined by the fixed bias current source And it is determined by the size of MP and M24.

[0032] Similarly, Figure 2 The gate-source voltages of M22, M25, M26, and MN satisfy the following relationship:

[0033] By deducing the formula, the static current of MN The following relationship is satisfied:

[0034] According to the above formula, the quiescent current of the output NMOS is determined by the fixed bias current source And it is determined by the sizes of MN and M26.

[0035] Usually in applications with large load currents, MP and MN must ensure low on-resistance. Figure 2 The size of the medium output power tube MP and MN is often much larger than that of M24 and M26. According to the above formula, the reduction and multiples or reduce branch current and Both can control the output stage quiescent current. However, when the output capacitance is large, the output stage uses a large-size power tube, and the parasitic capacitance of the power tube gate is large. In this case, the LDO has two poles: an internal pole formed by the parasitic capacitance of the power tube gate, and an output pole formed by the output capacitance. If the output stage quiescent current is too small at light no-load, the internal pole and the output pole are both at very low frequency positions, making it difficult to achieve loop stability across the full load range. Therefore, the traditional LDO structure based on a linear transconductance loop needs to compromise between the output stage quiescent current and loop stability.

[0036] The PMOS transistor MP1 and the NMOS transistor MN1 form a light-load power stage. The gate of the PMOS transistor MP1 serves as a first input terminal of the light-load power stage and is connected to a bias voltage VGP1. The gate of the NMOS transistor MN1 serves as a second input terminal of the light-load power stage and is connected to a bias voltage VGN1. The drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1 and serves as an output terminal of the light-load power stage to generate an output signal VOUT.

[0037] The heavy-duty power stage includes a PMOS transistor MP2 and an NMOS transistor MN2. The source of the PMOS transistor MP2 is connected to the power supply VDD. The gate of the PMOS transistor MP2 serves as a first input terminal of the heavy-duty power stage and is connected to the bias voltage VGP2. The drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN2 and serves as an output terminal of the heavy-duty power stage to generate an output signal VOUT. The gate of the NMOS transistor MN2 serves as a second input terminal of the heavy-duty power stage and is connected to the bias voltage VGN2. The source of the NMOS transistor MN2 is grounded.

[0038] The sizes of the heavy-load power stage PMOS transistor MP2 and the NMOS transistor MN2 are much larger than the sizes of the light-load power stage PMOS transistor MP1 and the NMOS transistor MN1.

[0039] The first source follower includes a PMOS transistor M15, a PMOS transistor M16, an NMOS transistor M17 and a resistor R3. The source of the PMOS transistor M15 is connected to the power supply VDD, the gate of the PMOS transistor M15 is connected to the bias voltage VBP1, the drain of the PMOS transistor M15 is connected to the source of the PMOS transistor M16 and the drain of the NMOS transistor M17 and serves as the output end of the first source follower to generate the bias voltage VGP2, the gate of the PMOS transistor M16 serves as the input end of the first source follower and is connected to the bias voltage VGP1, the drain of the PMOS transistor M16 is connected to one end of the resistor R3, the gate of the NMOS transistor M17 is connected to the bias voltage VBN1, and the other end of the resistor R3 and the source of the NMOS transistor M17 are grounded.

[0040] PMOS transistor M16 acts as a source follower, raising the bias voltage VGP1 to generate a voltage signal for bias VGP2. PMOS transistor M15 and NMOS transistor M17 act as current sources, and the difference between the two serves as the bias current for PMOS transistor M16. The raised voltage value can be adjusted by adjusting the dimensions of PMOS transistors M15, M16, and NMOS transistor M17. When the LDO operates in a closed-loop mode, the pull-up current of PMOS transistor M15 is greater than the pull-down current of NMOS transistor M17, raising the voltage at the bias voltage node VGP1 by a certain value, controlling the voltage of bias voltage VGP2 and thus switching the heavy-load power stage on and off. When the LDO operates in an open-loop mode, the pull-up current of PMOS transistor M15 is less than the pull-down current of NMOS transistor M17 due to the error amplifier's load current source, pulling bias voltage VGP2 down to GND. This allows the output-stage power transistor PMOS transistor MP2 to fully conduct.

[0041] The second source follower includes an NMOS transistor M18, an NMOS transistor M19, a PMOS transistor M20 and a resistor R4. One end of the resistor R4 is connected to the source of the PMOS transistor M20 and the power supply VDD. The other end of the resistor R4 is connected to the drain of the NMOS transistor M18. The gate of the NMOS transistor M18 serves as the input end of the second source follower and is connected to the bias voltage VGN1. The source of the NMOS transistor M18 is connected to the drain of the NMOS transistor M19 and the drain of the PMOS transistor M20 and serves as the output end of the second source follower and generates the bias voltage VGN2. The gate of the PMOS transistor M20 is connected to the bias voltage VBP1, the gate of the NMOS transistor M19 is connected to the bias voltage VBN1, and the source of the NMOS transistor M19 is grounded.

[0042] NMOS transistor M18 acts as a source follower, reducing the voltage of bias voltage VGN1 to generate a voltage signal for bias voltage VGN2. NMOS transistor M19 and PMOS transistor M20 act as current sources, and the difference between the two serves as the bias current for NMOS transistor M18. The reduced voltage value can be adjusted by adjusting the dimensions of NMOS transistors M18, M19, and M20. When the LDO operates in a closed-loop mode, the pull-down current of NMOS transistor M19 is greater than the pull-up current of PMOS transistor M20, reducing the voltage at the bias voltage node VGN1 by a certain value, controlling the voltage of bias voltage VGN2 and thus the quiescent current of the heavily loaded power stage. When the LDO operates in an open-loop mode, the pull-down current of NMOS transistor M19 is less than the pull-up current of PMOS transistor M20 due to the error amplifier's load current source, allowing bias voltage VGN2 to be pulled up to VDD. This allows the output-stage power transistor NMOS transistor MN2 to fully conduct.

[0043] The voltage divider feedback circuit includes resistors R1 and R2. One end of the power supply R1 is connected to the signal VC. The other end of the resistor R1 is connected to one end of the resistor R2 and serves as the output end of the voltage divider feedback circuit to generate the signal FB. The other end of the resistor R2 is connected to the output signal VOUT.

[0044] A low-voltage-dropout linear regulator with bidirectional current conduction capability of the present invention further includes a load circuit, which includes a load resistor RL and a load capacitor CL. One end of the resistor RL and one end of the capacitor CL are connected to the output signal VOUT, the other end of the resistor R1 is connected to the signal VS, and the other end of the capacitor CL is grounded.

[0045] like Figure 3As shown, when VS < VOUT, the output signal VOUT at the output terminal supplies current SourceCurrent to the load circuit; when VS > VOUT, the output terminal absorbs the current Sink Current injected by the load circuit. When the load current is 0 or light load, the gate bias voltage VGP2 of the heavy-load power stage PMOS transistor MP2 is raised to near the VDD potential by the first source follower. At this time, VDD - VGP2 < VTHP (high-side power transistor threshold voltage), which can completely turn off the PMOS transistor MP2; the gate drive voltage VGN2 of the heavy-load power adjustment transistor MN2 is lowered to near 0 potential by the second source follower circuit. At this time, VGN2 < VTHN (low-side power transistor threshold voltage), which can completely turn off MN2. Therefore, under light-load and no-load conditions, only the light-load power stage loop works, and the heavy-load power stage of the LDO can be completely turned off. When Sink Current gradually increases, VGN2 gradually rises with VGN1, and the heavy-load power stage NMOS transistor MN2 can be gradually turned on; similarly, when Source Current gradually increases, VGP2 gradually drops with VGP1, and the heavy-load power stage PMOS transistor MP2 can be gradually turned on. Therefore, as the load current gradually increases, the light-load power stage and the heavy-load power stage can work simultaneously. And when the output signal VOUT of the LDO reaches VDD or 0, that is, when the LDO is in open-loop operation, under the action of the first source follower and the second source follower, VGP2 can be pulled down to 0, and VGN2 can be pulled up to VDD, realizing full conduction of the heavy-load power transistor.

[0046] The present invention provides a low-dropout linear regulator with bidirectional current conduction ability. The error amplifier adopts a CLASS-AB output structure, designs two power branches of a light-load power stage and a heavy-load power stage, uses a linear transconductance loop structure to control the gate voltage of the output adjustment transistor of the light-load power stage, and the gate voltage of the power adjustment transistor of the light-load power stage is level-shifted by a first source follower circuit to control the gate voltage of the output adjustment transistor of the heavy-load power stage. This can ensure that under light-load and no-load conditions, the heavy-load output stage can be nearly turned off, achieving the purpose of reducing the static current, and as the load current increases, the heavy-load power stage can be gradually turned on. And when the LDO is in open-loop operation, the source follower circuit of the present invention can make the output adjustment transistor of the heavy-load power stage fully conduct. The present invention solves the problem of excessive static current of the traditional bidirectional current-conducting LDO under light-load and no-load conditions, and ensures that the output power transistor of the LDO can fully conduct when in open-loop operation.

[0047] The above description is merely a preferred embodiment of the present invention and does not constitute any form of limitation to the present invention. Although the present invention has been disclosed as a preferred embodiment as above, it is not intended to limit the present invention. Any technician familiar with the present profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical content disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement of the above embodiments made according to the technical essence of the present invention, within the spirit and principles of the present invention, without departing from the content of the technical solution of the present invention, shall still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A low-dropout linear regulator with bidirectional current conduction capability, characterized in that: It includes an error amplifier, a linear transconductance loop, a light-load power stage, a heavy-load power stage, a first source follower, a second source follower and a voltage divider feedback circuit, the first input end of the error amplifier is connected to a signal VB, the second input end of the error amplifier is connected to a signal FB, the power stage of the linear transconductance loop serves as a light-load power stage, the first output end of the error amplifier is connected to the first input end of the linear transconductance loop, the first input end of the light-load power stage and the input end of the first source follower, the output end of the first source follower is connected to the first input end of the heavy-load power stage, the second output end of the error amplifier is connected to the second input end of the linear transconductance loop, the second input end of the light-load power stage and the input end of the second source follower, the output end of the second source follower is connected to the second input end of the heavy-load power stage, the output end of the light-load power stage and the output end of the heavy-load power stage are connected to the input end of the voltage divider feedback circuit and generate an output signal VOUT, and the output end of the voltage divider feedback circuit generates a signal FB.

2. The low-dropout linear regulator with bidirectional current conduction capability according to claim 1, characterized in that: The error amplifier includes a PMOS transistor M1, a PMOS transistor M2, an NMOS transistor M3, an NMOS transistor M4, an NMOS transistor M5, an NMOS transistor M6, a PMOS transistor M7, a PMOS transistor M8 and a tail current source I1. The gate of the PMOS transistor M1 serves as a first input terminal of the error amplifier and is connected to a signal VB. The gate of the PMOS transistor M2 serves as a second input terminal of the error amplifier and is connected to a signal FB. The source of the PMOS transistor M1 is connected to one end of the tail current source I1 and the source of the PMOS transistor M2. The drain of the PMOS transistor M1 is connected to the drain of the NMOS transistor M3, the gate of the NMOS transistor M3 and the gate of the NMOS transistor M6 and is connected to a bias voltage VBN2. The drain of the PMOS transistor M2 is connected to the drain of the NMOS transistor M4. The drain of the NMOS transistor M3, the gate of the NMOS transistor M4, and the gate of the NMOS transistor M5 are connected and connected to the bias voltage VBN1. The drain of the NMOS transistor M5 serves as the second output terminal of the error amplifier and generates the bias voltage VGN1. The source of the NMOS transistor M3, the source of the NMOS transistor M4, the source of the NMOS transistor M5, and the source of the NMOS transistor M6 are grounded. The drain of the NMOS transistor M6 is connected to the drain of the PMOS transistor M7, the gate of the PMOS transistor M7, and the gate of the PMOS transistor M8 and connected to the bias voltage VBP1. The drain of the PMOS transistor M8 serves as the first output terminal of the error amplifier and generates the bias voltage VGP1. The source of the PMOS transistor M7, the other end of the tail current source I1, and the source of the PMOS transistor M8 are connected to the power supply VDD.

3. The low-dropout linear regulator with bidirectional current conduction capability according to claim 1, wherein: The linear transconductance loop includes a PMOS transistor M9, an NMOS transistor M10, a PMOS transistor M11, a PMOS transistor M12, an NMOS transistor M13, an NMOS transistor M14, a PMOS transistor MP1, an NMOS transistor MN1, a current source I2, and a current source I3. The source of the PMOS transistor M9 is connected to the drain of the NMOS transistor M10 and serves as a first input end of the linear transconductance loop to be connected to the bias voltage VGP1. The drain of the PMOS transistor M9 is connected to the source of the NMOS transistor M10 and serves as a second input end of the linear transconductance loop to be connected to the bias voltage VGN1. The gate of the PMOS transistor M9 is connected to the gate of the PMOS transistor M12, the gate of the PMOS transistor M14, and the gate of the PMOS transistor M14. The drain of M12 is connected to one end of the current source I3, the source of the PMOS transistor M12 is connected to the drain of the PMOS transistor M11 and the gate of the PMOS transistor M11, the gate of the NMOS transistor M10 is connected to the gate of the NMOS transistor M13, the drain of the NMOS transistor M13 is connected to one end of the current source I2, the source of the NMOS transistor M13 is connected to the drain of the NMOS transistor M14 and the gate of the NMOS transistor M14, the source of the PMOS transistor M11, the other end of the current source I2, and the source of the PMOS transistor MP1 are connected to the power supply VDD, and the other end of the current source I3, the source of the NMOS transistor M14, and the source of the NMOS transistor MN1 are grounded.

4. The low-dropout linear regulator with bidirectional current conduction capability according to claim 3, characterized in that: The PMOS transistor MP1 and the NMOS transistor MN1 constitute a light-load power stage. The gate of the PMOS transistor MP1 serves as a first input terminal of the light-load power stage and is connected to a bias voltage VGP1. The gate of the NMOS transistor MN1 serves as a second input terminal of the light-load power stage and is connected to a bias voltage VGN1. The drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1 and serves as an output terminal of the light-load power stage to generate an output signal VOUT.

5. The low-dropout linear regulator with bidirectional current conduction capability according to claim 1, characterized in that: The heavy-load power stage includes a PMOS transistor MP2 and an NMOS transistor MN2. The source of the PMOS transistor MP2 is connected to the power supply VDD. The gate of the PMOS transistor MP2 serves as the first input terminal of the heavy-load power stage and is connected to the bias voltage VGP2. The drain of the PMOS transistor MP2 is connected to the drain of the NMOS transistor MN2 and serves as the output terminal of the heavy-load power stage to generate an output signal VOUT. The gate of the NMOS transistor MN2 serves as the second input terminal of the heavy-load power stage and is connected to the bias voltage VGN2. The source of the NMOS transistor MN2 is grounded.

6. The low-dropout linear regulator with bidirectional current conduction capability according to claim 1, characterized in that: The first source follower includes a PMOS transistor M15, a PMOS transistor M16, an NMOS transistor M17 and a resistor R3. The source of the PMOS transistor M15 is connected to the power supply VDD, the gate of the PMOS transistor M15 is connected to the bias voltage VBP1, the drain of the PMOS transistor M15 is connected to the source of the PMOS transistor M16 and the drain of the NMOS transistor M17 and serves as the output end of the first source follower to generate the bias voltage VGP2, the gate of the PMOS transistor M16 serves as the input end of the first source follower and is connected to the bias voltage VGP1, the drain of the PMOS transistor M16 is connected to one end of the resistor R3, the gate of the NMOS transistor M17 is connected to the bias voltage VBN1, and the other end of the resistor R3 and the source of the NMOS transistor M17 are grounded.

7. The low-dropout linear regulator with bidirectional current conduction capability according to claim 1, characterized in that: The second source follower includes an NMOS transistor M18, an NMOS transistor M19, a PMOS transistor M20 and a resistor R4. One end of the resistor R4 is connected to the source of the PMOS transistor M20 and the power supply VDD. The other end of the resistor R4 is connected to the drain of the NMOS transistor M18. The gate of the NMOS transistor M18 serves as the input end of the second source follower and is connected to the bias voltage VGN1. The source of the NMOS transistor M18 is connected to the drain of the NMOS transistor M19 and the drain of the PMOS transistor M20 and serves as the output end of the second source follower and generates the bias voltage VGN2. The gate of the PMOS transistor M20 is connected to the bias voltage VBP1, the gate of the NMOS transistor M19 is connected to the bias voltage VBN1, and the source of the NMOS transistor M19 is grounded.

8. The low-dropout linear regulator with bidirectional current conduction capability according to claim 1, characterized in that: The voltage divider feedback circuit includes a resistor R1 and a resistor R2. One end of the power supply R1 is connected to the signal VC. The other end of the resistor R1 is connected to one end of the resistor R2 and serves as the output end of the voltage divider feedback circuit to generate a signal FB. The other end of the resistor R2 is connected to the output signal VOUT.

9. The low-dropout linear regulator with bidirectional current conduction capability according to claim 1, characterized in that: It also includes a load circuit, which includes a load resistor RL and a load capacitor CL. One end of the resistor RL and one end of the capacitor CL are connected to the output signal VOUT, the other end of the resistor R1 is connected to the signal VS, and the other end of the capacitor CL is grounded.

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