Static soft error sensitive bit rapid identification method

Abstract

The invention discloses a static soft error sensitive bit rapid identification method. The method comprises the following steps: establishing a signal topological relation of each module of a circuit and storing related information of each module; establishing a complex network model of each module from top to bottom; obtaining a complex network circuit and numbering each node; the adjacent signal ratio, the shortest path ratio and the signal connection ratio of each node are obtained and serve as evaluation indexes; constructing an evaluation matrix; constructing a weighted normalized matrix; and obtaining a key signal which has a great influence on the circuit, and the like. The method can be applied to circuit design of aircraft airborne equipment and the like in a complex environment, and reference can be provided for the initial stage of reliability design of a digital circuit of the aircraft airborne equipment. The method can accurately identify the soft error sensitive bit during subsequent reliability analysis of the digital circuit, and can be used for subsequently judging the influence of fault injection of the soft error sensitive bit on the function and performance of the digital circuit. The method is high in sensitive position identification applicability, and can be suitable for accurately identifying sensitive positions under various architectures.

Description

Technical field:

[0001] The present invention belongs to the field of integrated circuit design and reliability technology, and particularly relates to a method for quickly identifying static soft error-sensitive bits. This method can be used to quickly identify signals and modules in a circuit network that are more sensitive to soft errors in the early stages of digital circuit design, thereby improving the architecture in the early stages of design and reducing the fault-tolerant design iteration cycle. Background technology:

[0002] Soft errors are caused by external radiation. When the charge induced by radiation exceeds a certain threshold, a soft error occurs, leading to bit flips in the hardware, particularly SEUs (Single Event Upsets). With the continuous advancement of integrated circuit technology and the shrinking feature sizes of devices, the supply voltage of circuits has also decreased. Therefore, electronic hardware in complex operating environments such as aerospace, automotive, and medical is more susceptible to soft errors, posing a significant safety threat. Accurately identifying critical bits in the hardware circuits of different processors when exposed to external radiation has become a design priority for integrated circuits in high-security applications.

[0003] For example, aviation airborne equipment chips face complex aviation environments and are easily interfered with by SEUs during operation, which can lead to timeouts, system failures, or output errors, causing unpredictable security threats (such as system shutdown, operation failure, etc.), which is unacceptable in high-security fields.

[0004] Currently, hardware-level reliability verification for circuit designs is primarily conducted through two types of fault injection experiments. Software-level simulation experiments offer advantages such as low cost, requiring no complex physical environment, and simulating fault scenarios using computer software and simulation tools. They are highly repeatable, allowing precise control of experimental conditions and parameters to generate stable and reliable data over repeated attempts. They are also highly flexible, enabling easy simulation of a wide range of complex and diverse fault scenarios. However, their disadvantages are that simulations differ from actual conditions, making it difficult to fully replicate the complex real-world environments and physical effects. Furthermore, they require extensive simulation experiments, leading to long experimental cycles. Actual irradiation experiments, on the other hand, offer a realistic representation of fault conditions and directly obtain data close to actual application scenarios under realistic irradiation conditions. However, these experiments are costly, requiring specialized irradiation equipment, which carries high purchase, maintenance, and site construction costs. Environmental factors can also be unstable, making experimental conditions difficult to control, and parameters such as the irradiation dose difficult to precisely control. Furthermore, the experimental cycle is long and complex, making the entire process from preparation to completion complex and time-consuming. Summary of the invention:

[0005] In order to solve the above problems, the purpose of the present invention is to provide a method for quickly identifying static soft error sensitive bits, thereby providing support for subsequent reliability analysis.

[0006] In order to achieve the above object, the method for quickly identifying static soft error sensitive bits provided by the present invention includes the following steps performed in sequence:

[0007] Step 0): Search and traverse the source files of all hardware descriptions of the project, establish the signal topology relationship of each module of the circuit, and save the relevant information of each module; the information includes the circuit single module port topology description, the module internal signal topology description and the topology description of the instantiation relationship between modules;

[0008] Step 1): Using the relevant information of each module obtained in step 0), a single-module complex network is established, and based on the circuit signal topology, a complex network model of each module is established from top to bottom;

[0009] Step 2): The complex network models of each module obtained in step 1) and the instantiation relationship between modules obtained in step 0) are subjected to multi-module complex network fusion to obtain a complex network circuit, and each node is numbered;

[0010] Step 3): Perform node analysis on the complex circuit network obtained in step 2) to obtain the adjacent signal ratio, shortest path ratio, and signal connection ratio of each node and use them as evaluation indicators;

[0011] Step 4): Based on the evaluation index obtained in step 3) and the node numbers in the complex network model obtained in step 2), an evaluation matrix containing n nodes, each node having three evaluation indexes, is constructed, and the evaluation matrix is ​​standardized;

[0012] Step 5): Using an objective weighting method based on entropy, the three evaluation indicators of the n nodes obtained in step 4) are assigned weights, and a weighted normalized matrix is ​​constructed based on the standardized evaluation matrix and weights. The degree of proximity of each element in the weighted normalized matrix to the maximum element and the minimum element is then calculated.

[0013] Step 6) According to step 5), the proximity of each element in the weighted normalized matrix to the maximum element and the minimum element is obtained, the importance index of the circuit node is obtained, and finally the key signal with the greatest impact on the circuit is obtained.

[0014] In step 0), the method of searching and traversing the source files of all hardware descriptions of the project, establishing the signal topology relationship of each module of the circuit, and saving the relevant information of each module; the information includes the circuit single module port topology description, the module internal signal topology description and the inter-module instantiation relationship topology description is:

[0015] (1) Search and traverse all .v files in the engineering design, and define the interface part of the .v file as module_name{port name 1 (bit width), port name 2 (bit width), ..., port name n (bit width)}, where n is the port number;

[0016] (2) Retrieve the instantiation relationship between modules and define it as module_(module name instantiation name)<signal name 1 (bit width), signal name 2 (bit width)>. In addition, it is necessary to save the link relationship between the top-level module and the instantiation module module_connect(module top-level module name, module_instantiated module name)<port name 1 (bit width), port name 2 (bit width)>;

[0017] (3) Search each module to see if there are logical statement blocks, including always statement blocks and assign statement blocks, and record the topological relationships therein;

[0018] (4) The instantiation modules retrieved from the top-level module are searched in the user project file in turn to retrieve the logical statements with logical functions; the saved information includes the single module port topology description, the module internal signal topology description, and the topology description of the instantiation relationship between modules.

[0019] In step 1), the method of establishing a single-module complex network using the relevant information of each module obtained in step 0), and establishing the complex network model of each module from top to bottom based on the circuit signal topology relationship is:

[0020] Read the HDL file inside the processor, establish a process based on the topological relationship, and build the complex network model of each module from top to bottom, including the top module network model and the network models of other instantiated modules;

[0021] The saving formats of each module are as follows:

[0022] module_name{port_1[width],port_2[width],signal_3[wdith]}

[0023] module_name{<signal_1[width],signal_2[width]>}

[0024] module_connect(nameA,nameB){<port_1[width],port_2[width]>}

[0025] module_name{port_1[width],port_2[width],signal_3[wdith]}: represents the topology description of a single module port; module_name represents the module name, the module ports are named port_1, port_2 and signal_3, and their signal width is width;

[0026] module_name{<signal_1[width],signal_2[width]>}: represents the signal topology description within the module. The <> indicates that there is a link relationship between the two signals, with the left signal pointing to the right signal. The entire record describes the link relationship between the signals within the module.

[0027] module_connect(nameA,nameB){<port_1[width],port_2[width]>}: represents the topological description of the instantiation relationship between modules. The connect statement indicates that module B is a submodule of module A. The <> indicates that there is a link relationship between the two signals, and the direction of the connection is from the left signal to the right signal.

[0028] In step 2), the formula of the complex network circuit G is:

[0029] G=(VA,EA,SW)

[0030] The nodes of the circuit complex network G are used to represent the signals in the actual project. The circuit complex network G contains all the sub-networks in the processor, where VA is the node set, VA = {va1, va2, ..., va3}; EA is the edge set, EA = {ea1, ea2, ..., ea n}, SW is the weight set, SW={sw1,sw2,…,sw n}, 1≤i≤n, i is the node number, and n is the total number of nodes in the circuit complex network G.

[0031] In step 3), the adjacent signal ratio S d : Describes the density of a signal directly connected to other signals in the circuit, the adjacent signal ratio S d The larger the value, the more influence the signal directly connected to it has when it is flipped, and the greater the error propagation caused. The formula is as follows:

[0032]

[0033] Where sw i is the signal v in the circuit i The sum of the bit widths of all directly connected signals, is the sum of the bit widths of all signals in the circuit, i∈[1,n], n is the total number of nodes in the circuit complex network G, and the adjacent signal ratio S d dimensionless;

[0034] Shortest path ratio S r : Take any two signals in the circuit and get the shortest edge connecting the two signals, which is the shortest path; the shortest path ratio S r It is defined as the ratio of the shortest number of paths passing through a certain signal to the total number of the shortest paths between any two signals in the circuit; if the shortest path of a certain signal is greater than S r The error caused by a single-particle upset will have a greater impact on the entire circuit. The formula is as follows:

[0035]

[0036] Where, σ lb (va i ) is the signal va in the circuit l To signal va b All paths through which the signal va i The number of paths with the least signal among the paths, σ lb Signal va l To signal va b The total number of shortest paths containing the least signals, i, l, b ∈ [1, n], n is the total number of nodes in the circuit complex network G, the shortest path ratio S r dimensionless;

[0037] Signal connection ratio S c : The reciprocal of the sum of the shortest paths from a signal to all other signals is called the signal connection ratio S c If the connection ratio of a signal is large, it means that the signal is more susceptible to the flip of other signals in the circuit. This indicator reflects the impact of single-particle flip in the local circuit. The formula is as follows:

[0038]

[0039] In the formula, c(va i ,va b ) is the signal va in the circuit i With signal va b The shortest path distance between them, i,b∈[1,n], n is the total number of nodes in the circuit complex network G, and the signal connection ratio S c Dimensionless.

[0040] In step 4), based on the evaluation index obtained in step 3) and the node numbers in the complex network model obtained in step 2), an evaluation matrix containing n nodes, each node having three evaluation indexes, is constructed, and the method for standardizing the evaluation matrix is:

[0041] Assume that there are n nodes in the circuit complex network G. The evaluation matrix is ​​constructed based on the node numbers in the complex network model obtained in step 2) and the evaluation index obtained in step 3):

[0042]

[0043] Where n is the total number of nodes in the circuit complex network G; d 11 , d 12 , d 13 Represents the adjacent signal ratio S of the first node d , shortest path ratio S r and signal connection ratio S c ; Then standardize the above evaluation matrix.

[0044] In step 5), the objective weighting method based on entropy is used to assign weights to the three evaluation indicators of the n nodes obtained in step 4), and a weighted normalized matrix is ​​constructed based on the standardized evaluation matrix and the weights. The method for calculating the proximity of each element in the weighted normalized matrix to the maximum element and the minimum element is as follows:

[0045] (1) Calculate the signal v under the jth evaluation index i The proportion of θ ij :

[0046]

[0047] Where, d ij is the evaluation index of the signal, 1≤i≤n,1≤j≤3;

[0048] (2) Based on the above specific gravity θ ij , calculate the entropy value e of the j-th evaluation index j :

[0049]

[0050] Where n is the total number of nodes in the circuit complex network G, 1≤i≤n, 1≤j≤3;

[0051] (3) Based on the above entropy value e j , calculate the weight w of the j-th evaluation index e (j):

[0052]

[0053] Where, 1≤j≤3;

[0054] (4) Finally, according to the evaluation matrix D n and weight w e (j) Construct the weighted normalization matrix Z n :

[0055] Z n =D n ×w e (j),j∈[1,3]

[0056] The maximum element among all elements in the weighted normalization matrix is ​​Z max =maxZ ij , the smallest element is Z min =minZ ij ; Calculate each element Z in the weighted normalization matrix separately ij With the largest element Z max and the smallest element Z min The degree of closeness is as follows:

[0057]

[0058] Where n is the total number of nodes in the circuit complex network G, 1≤i≤n, 1≤j≤3.

[0059] In step 6), the method of obtaining the proximity of each element in the weighted normalized matrix to the maximum element and the minimum element according to step 5), obtaining the circuit node importance index, and finally obtaining the key signal with a greater impact on the circuit is:

[0060] The calculation formula of the circuit node importance index is as follows:

[0061]

[0062] Circuit node importance index R i Indicates the importance of the signal in the circuit. The larger the value, the greater the impact on the result when the signal is abnormal. At the same time, when other signals with topological relationships are abnormal, the circuit node importance index R i The larger the signal, the greater the probability of anomaly.

[0063] When X imax =0 or X imin = 0, the circuit node importance index R i Directly equal to 0;

[0064] According to the above steps, the circuit node importance index R of all signals is obtained i , refer to the circuit node importance index R i, we can obtain the key signals that have a greater impact on the circuit, and thus statically identify the relevant soft error sensitive bits.

[0065] The static soft error sensitive bit fast identification method provided by the present invention has the following beneficial effects:

[0066] This method can be applied to circuit designs in complex environments, such as aircraft-borne equipment, and can provide a reference for the initial stage of digital circuit reliability design. The results provided by this method can be used to accurately identify soft error-sensitive bits during subsequent reliability analysis of digital circuits, and can be used to determine the impact of soft error-sensitive bit fault injection on the function and performance of digital circuits. In addition, this method has strong applicability for sensitive bit identification and can be used to accurately identify sensitive bits under a variety of architectures. Therefore, it can solve the problem of soft error-sensitive bits being difficult to accurately identify in different digital circuit designs. This method does not require repeated dynamic experiments, and only requires evaluation of key nodes in circuit engineering to statically identify relevant soft error-sensitive bits, providing a new approach for product reliability analysis. Description of the drawings:

[0067] Figure 1 This is a flow chart of the method for quickly identifying static soft error sensitive bits provided by the present invention.

[0068] Figure 2 This is a flow chart of the signal topology relationship of each module of the circuit in step 0) of the present invention.

[0069] Figure 3 For engineering design drawings.

[0070] Figure 4 This is a schematic diagram of the network model of the project's top module.

[0071] Figure 5 This is a schematic diagram of the network model for the remaining instantiated modules of the project.

[0072] Figure 6 Schematic diagram of the complex circuit network after multi-module fusion. Specific implementation method:

[0073] The present invention will be described in detail below with reference to the accompanying drawings.

[0074] like Figure 1 As shown, the method for quickly identifying static soft error sensitive bits provided by the present invention includes the following steps performed in sequence:

[0075] Step 0): Figure 2 As shown, the source files of all hardware descriptions of the project are retrieved and traversed, the signal topology relationship of each module of the circuit is established, and the relevant information of each module is saved; the information includes the circuit single module port topology description, the module internal signal topology description and the topology description of the instantiation relationship between modules;

[0076] (1) Search and traverse all .v files in the engineering design, and define the interface part of the .v file as module_name{port name 1 (bit width), port name 2 (bit width), ..., port name n (bit width)}, where n is the port number;

[0077] (2) Retrieve the instantiation relationship between modules and define it as module_(module name instantiation name)<signal name 1 (bit width), signal name 2 (bit width)>. In addition, it is necessary to save the link relationship between the top-level module and the instantiation module module_connect(module top-level module name, module_instantiated module name)<port name 1 (bit width), port name 2 (bit width)>;

[0078] (3) Search each module to see if there are logical statement blocks, including always statement blocks and assign statement blocks, and record the topological relationships therein;

[0079] (4) The instantiation modules retrieved from the top-level module are searched in the user project file in turn to retrieve the logical statements with logical functions; the saved information includes the single module port topology description, the module internal signal topology description, and the topology description of the instantiation relationship between modules.

[0080] Step 1): Using the relevant information of each module obtained in step 0), a single-module complex network is established, and based on the circuit signal topology, a complex network model of each module is established from top to bottom;

[0081] Read the HDL file inside the processor, establish the process based on the topological relationship, and build the complex network model of each module from top to bottom, including Figure 4 The top module network model shown in the figure and Figure 5 The remaining instantiated module network models are shown;

[0082] The saving formats of each module are as follows:

[0083] module_name{port_1[width],port_2[width],signal_3[wdith]}

[0084] module_name{<signal_1[width],signal_2[width]>}

[0085] module_connect(nameA,nameB){<port_1[width],port_2[width]>}

[0086] module_name{port_1[width],port_2[width],signal_3[wdith]}: represents the topology description of a single module port; module_name represents the module name, the module ports are named port_1, port_2 and signal_3, and their signal width is width;

[0087] module_name{<signal_1[width],signal_2[width]>}: represents the signal topology description within the module. The <> indicates that there is a link relationship between the two signals, with the left signal pointing to the right signal. The entire record describes the link relationship between the signals within the module.

[0088] module_connect(nameA,nameB){<port_1[width],port_2[width]>}: represents the topological description of the instantiation relationship between modules. The connect statement indicates that module B is a submodule of module A. The <> indicates that there is a link relationship between the two signals, and the direction of the connection is from the left signal to the right signal.

[0089] Step 2): The complex network models of each module obtained in step 1) and the instantiation relationship between modules obtained in step 0) are integrated into a multi-module complex network to obtain a complex network circuit G, such as Figure 6 As shown, each node is numbered;

[0090] G=(VA,EA,SW)

[0091] The nodes of the circuit complex network G are used to represent the signals in the actual project. The circuit complex network G contains all the sub-networks in the processor, where VA is the node set, VA = {va1, va2, ..., va3}; EA is the edge set, EA = {ea1, ea2, ..., ea n}, SW is the weight set, SW={sw1,sw2,…,sw n}, 1≤i≤n, i is the node number, and n is the total number of nodes in the circuit complex network G.

[0092] Step 3): Perform node analysis on the complex circuit network G obtained in step 2) to obtain the adjacent signal ratio S of each node. d , shortest path ratio S r and signal connection ratio S c and serve as evaluation indicators;

[0093] Adjacent signal ratio S d : Describes the density of a signal directly connected to other signals in the circuit, the adjacent signal ratio Sd The larger the value, the more influence the signal directly connected to it has when it is flipped, and the greater the error propagation caused. The formula is as follows:

[0094]

[0095] Where sw i is the signal v in the circuit i The sum of the bit widths of all directly connected signals, is the sum of the bit widths of all signals in the circuit, i∈[1,n], n is the total number of nodes in the circuit complex network G, and the adjacent signal ratio S d dimensionless;

[0096] Shortest path ratio S r : Take any two signals in the circuit and get the shortest edge connecting the two signals, which is the shortest path; the shortest path ratio S r It is defined as the ratio of the shortest number of paths passing through a certain signal to the total number of the shortest paths between any two signals in the circuit; if the shortest path of a certain signal is greater than S r The error caused by a single-particle upset will have a greater impact on the entire circuit. The formula is as follows:

[0097]

[0098] Where, σ lb (va i ) is the signal va in the circuit l To signal va b All paths through which the signal va i The number of paths with the least signal among the paths, σ lb Signal va l To signal va b The total number of shortest paths containing the least signals, i, l, b ∈ [1, n], n is the total number of nodes in the circuit complex network G, the shortest path ratio S r dimensionless;

[0099] Signal connection ratio S c : The reciprocal of the sum of the shortest paths from a signal to all other signals is called the signal connection ratio S c If the connection ratio of a signal is large, it means that the signal is more susceptible to the flip of other signals in the circuit. This indicator reflects the impact of single-particle flip in the local circuit. The formula is as follows:

[0100]

[0101] In the formula, c(va i ,va b ) is the signal va in the circuiti With signal va b The shortest path distance between them, i,b∈[1,n], n is the total number of nodes in the circuit complex network G, and the signal connection ratio S c Dimensionless.

[0102] Step 4): Based on the evaluation index obtained in step 3) and the node numbers in the complex network model obtained in step 2), an evaluation matrix containing n nodes, each node having three evaluation indexes, is constructed, and the evaluation matrix is ​​standardized;

[0103] Assume that there are n nodes in the circuit complex network G. The evaluation matrix is ​​constructed based on the node numbers in the complex network model obtained in step 2) and the evaluation index obtained in step 3):

[0104]

[0105] Where n is the total number of nodes in the circuit complex network G; d 11 , d 12 , d 13 Represents the adjacent signal ratio S of the first node d , shortest path ratio S r and signal connection ratio S c ; Then standardize the above evaluation matrix.

[0106] Step 5): Use the objective weighting method based on entropy value to assign weights to the three evaluation indicators of the n nodes obtained in step 4), and construct a weighted normalization matrix based on the standardized evaluation matrix and weights. Then calculate the weight of each element Z in the weighted normalization matrix. ij With the largest element Z max and the smallest element Z min the degree of proximity;

[0107] (1) Calculate the signal v under the jth evaluation index i The proportion of θ ij :

[0108]

[0109] Where, d ij is the evaluation index of the signal, 1≤i≤n,1≤j≤3;

[0110] (2) Based on the above specific gravity θ ij , calculate the entropy value e of the j-th evaluation index j :

[0111]

[0112] Where n is the total number of nodes in the circuit complex network G, 1≤i≤n, 1≤j≤3;

[0113] (3) Based on the above entropy value e j , calculate the weight w of the j-th evaluation index e (j):

[0114]

[0115] Where, 1≤j≤3;

[0116] (4) Finally, according to the evaluation matrix D n and weight w e (j) Construct the weighted normalization matrix Z n :

[0117] Z n =D n ×w e (j),j∈[1,3]

[0118] The maximum element among all elements in the weighted normalization matrix is ​​Z max =maxZ ij , the smallest element is Z min =minZ ij ; Calculate each element Z in the weighted normalization matrix separately ij With the largest element Z max and the smallest element Z min The degree of closeness is as follows:

[0119]

[0120] Where n is the total number of nodes in the circuit complex network G, 1≤i≤n, 1≤j≤3.

[0121] Step 6) Obtain each element Z in the weighted normalized matrix according to step 5) ij With the largest element Z max and the smallest element Z min The closeness of the circuit node is obtained by i , and finally obtain the key signal that has a greater impact on the circuit.

[0122] The calculation formula of the circuit node importance index is as follows:

[0123]

[0124] Circuit node importance index R i Indicates the importance of the signal in the circuit. The larger the value, the greater the impact on the result when the signal is abnormal. At the same time, when other signals with topological relationships are abnormal, the circuit node importance index Ri The larger the signal, the greater the probability of anomaly.

[0125] When X imax =0 or X imin = 0, the circuit node importance index R i Directly equal to 0.

[0126] According to the above steps, the circuit node importance index R of all signals can be obtained i , refer to the circuit node importance index R i , we can obtain the key signals that have a greater impact on the circuit, and thus statically identify the relevant soft error sensitive bits.

Claims

1. A method for quickly identifying static soft error sensitive bits, characterized by: The method for quickly identifying static soft error sensitive bits comprises the following steps performed in sequence: Step 0): Search and traverse the source files of all hardware descriptions of the project, establish the signal topology relationship of each module of the circuit, and save the relevant information of each module; the information includes the circuit single module port topology description, the module internal signal topology description and the topology description of the instantiation relationship between modules; Step 1): Using the relevant information of each module obtained in step 0), a single-module complex network is established, and based on the circuit signal topology, a complex network model of each module is established from top to bottom; Step 2): The complex network models of each module obtained in step 1) and the instantiation relationship between modules obtained in step 0) are subjected to multi-module complex network fusion to obtain a complex network circuit, and each node is numbered; Step 3): Perform node analysis on the complex circuit network obtained in step 2) to obtain the adjacent signal ratio, shortest path ratio, and signal connection ratio of each node and use them as evaluation indicators; Step 4): Based on the evaluation index obtained in step 3) and the node numbers in the complex network model obtained in step 2), an evaluation matrix containing n nodes, each node having three evaluation indexes, is constructed, and the evaluation matrix is ​​standardized; Step 5): Using an objective weighting method based on entropy, the three evaluation indicators of the n nodes obtained in step 4) are assigned weights, and a weighted normalized matrix is ​​constructed based on the standardized evaluation matrix and weights. The degree of proximity of each element in the weighted normalized matrix to the maximum element and the minimum element is then calculated. Step 6) According to step 5), the proximity of each element in the weighted normalized matrix to the maximum element and the minimum element is obtained, the importance index of the circuit node is obtained, and finally the key signal with the greatest impact on the circuit is obtained.

2. The method for rapidly identifying static soft error sensitive bits according to claim 1, wherein: In step 0), the method of searching and traversing the source files of all hardware descriptions of the project, establishing the signal topology relationship of each module of the circuit, and saving the relevant information of each module; the information includes the circuit single module port topology description, the module internal signal topology description and the inter-module instantiation relationship topology description is: (1) Search and traverse all .v files in the engineering design, and define the interface part of the .v file as module_name{port name 1 (bit width), port name 2 (bit width), ..., port name n (bit width)}, where n is the port number; (2) Retrieve the instantiation relationship between modules and define it as module_(module name instantiation name)<signal name 1 (bit width), signal name 2 (bit width)>. In addition, it is necessary to save the link relationship between the top-level module and the instantiation module module_connect(module top-level module name, module_instantiated module name) connect<port name 1 (bit width), port name 2 (bit width)>; (3) Search each module to see if there are logical statement blocks, including always statement blocks and assign statement blocks, and record the topological relationships therein; (4) The instantiation modules retrieved from the top-level module are searched in the user project file in turn to retrieve the logical statements with logical functions; the saved information includes the single module port topology description, the module internal signal topology description, and the topology description of the instantiation relationship between modules.

3. The method for rapidly identifying static soft error sensitive bits according to claim 1, wherein: In step 1), the method of establishing a single-module complex network using the relevant information of each module obtained in step 0), and establishing the complex network model of each module from top to bottom based on the circuit signal topology relationship is: Read the HDL file inside the processor, establish a process based on the topological relationship, and build the complex network model of each module from top to bottom, including the top module network model and the network models of other instantiated modules; The saving formats of each module are as follows: module_name{port_1[width],port_2[width],signal_3[wdith]} module_name{<signal_1[width],signal_2[width]>} module_connect(nameA,nameB){<port_1[width],port_2[width]>} module_name{port_1[width],port_2[width],signal_3[wdith]}: represents the topology description of a single module port; module_name represents the module name, the module ports are named port_1, port_2 and signal_3, and their signal width is width; module_name{<signal_1[width],signal_2[width]>}: Represents the signal topology description within the module. The <> indicates a link relationship between two signals, with the left signal pointing to the right signal. The entire record describes the link relationship between the signals within the module. module_connect(nameA,nameB){<port_1[width],port_2[width]>}: Represents the topological description of the instantiation relationship between modules; connect indicates that module B is a submodule of module A, and <> indicates that there is a link relationship between the two signals, with the connection direction being from the left signal to the right signal.

4. The method for rapidly identifying static soft error sensitive bits according to claim 1, wherein: In step 2), the formula of the complex network circuit G is: G=(VA,EA,SW) The nodes of the circuit complex network G are used to represent the signals in the actual project. The circuit complex network G contains all the sub-networks in the processor, where VA is the node set, VA = {va1, va2, ..., va3}; EA is the edge set, EA = {ea1, ea2, ..., ea n }, SW is the weight set, SW={sw1,sw2,…,sw n }, 1≤i≤n, i is the node number, and n is the total number of nodes in the circuit complex network G.

5. The method for rapidly identifying static soft error sensitive bits according to claim 1, wherein: In step 3), the adjacent signal ratio S d : Describes the density of a signal directly connected to other signals in the circuit, the adjacent signal ratio S d The larger the value, the more influence the signal directly connected to it has when it is flipped, and the greater the error propagation caused. The formula is as follows: Where sw i is the circuit with the signal v i The sum of the bit widths of all directly connected signals, is the sum of the bit widths of all signals in the circuit, i∈[1,n], n is the total number of nodes in the circuit complex network G, and the adjacent signal ratio S d dimensionless; Shortest path ratio S r : Take any two signals in the circuit and get the shortest edge connecting the two signals, which is the shortest path; the shortest path ratio S r It is defined as the ratio of the shortest number of paths passing through a certain signal to the total number of the shortest paths between any two signals in the circuit; if the shortest path of a certain signal is greater than S r The error caused by a single-particle upset will have a greater impact on the entire circuit. The formula is as follows: Where, σ lb (va i ) is the signal va in the circuit l To signal va b All paths through which the signal va i The number of paths with the least signal among the paths, σ lb Signal va l To signal va b The total number of shortest paths containing the least signals, i, l, b ∈ [1, n], n is the total number of nodes in the circuit complex network G, the shortest path ratio S r dimensionless; Signal connection ratio S c : The reciprocal of the sum of the shortest paths from a signal to all other signals is called the signal connection ratio S c If the connection ratio of a signal is large, it means that the signal is more susceptible to the flip of other signals in the circuit. This indicator reflects the impact of single-particle flip in the local circuit. The formula is as follows: In the formula, c(va i ,va b ) is the signal va in the circuit i With signal va b The shortest path distance between them, i,b∈[1,n], n is the total number of nodes in the circuit complex network G, and the signal connection ratio S c Dimensionless.

6. The method for rapidly identifying static soft error sensitive bits according to claim 1, wherein: In step 4), based on the evaluation index obtained in step 3) and the node numbers in the complex network model obtained in step 2), an evaluation matrix containing n nodes, each node having three evaluation indexes, is constructed, and the method for standardizing the evaluation matrix is: Assume that there are n nodes in the circuit complex network G. The evaluation matrix is ​​constructed based on the node numbers in the complex network model obtained in step 2) and the evaluation index obtained in step 3): Where n is the total number of nodes in the circuit complex network G; d 11 , d 12 , d 13 Represents the adjacent signal ratio S of the first node d , shortest path ratio S r and signal connection ratio S c ; Then standardize the above evaluation matrix.

7. The method for rapidly identifying static soft error sensitive bits according to claim 1, wherein: In step 5), the objective weighting method based on entropy is used to assign weights to the three evaluation indicators of the n nodes obtained in step 4), and a weighted normalized matrix is ​​constructed based on the standardized evaluation matrix and the weights. The method for calculating the proximity of each element in the weighted normalized matrix to the maximum element and the minimum element is as follows: (1) Calculate the signal v under the jth evaluation index i The proportion of θ ij : Where, d ij is the evaluation index of the signal, 1≤i≤n,1≤j≤3; (2) Based on the above specific gravity θ ij , calculate the entropy value e of the j-th evaluation index j : Where n is the total number of nodes in the circuit complex network G, 1≤i≤n, 1≤j≤3; (3) Based on the above entropy value e j , calculate the weight w of the j-th evaluation index e (j): Where, 1≤j≤3; (4) Finally, according to the evaluation matrix D n and weight w e (j) Construct the weighted normalization matrix Z n : Z n =D n ×w e (j),j∈[1,3] The maximum element among all elements in the weighted normalization matrix is ​​Z max =maxZ ij , the smallest element is Z min =minZ ij ; Calculate each element Z in the weighted normalization matrix separately ij With the largest element Z max and the smallest element Z min The degree of closeness is as follows: Where n is the total number of nodes in the circuit complex network G, 1≤i≤n, 1≤j≤3.

8. The method for rapidly identifying static soft error sensitive bits according to claim 1, wherein: In step 6), the method of obtaining the proximity of each element in the weighted normalized matrix to the maximum element and the minimum element according to step 5), obtaining the circuit node importance index, and finally obtaining the key signal with a greater impact on the circuit is: The calculation formula of the circuit node importance index is as follows: Circuit node importance index R i Indicates the importance of the signal in the circuit. The larger the value, the greater the impact on the result when the signal is abnormal. At the same time, when other signals with topological relationships are abnormal, the circuit node importance index R i The larger the signal, the greater the probability of anomaly. When X imax =0 or X imin = 0, the circuit node importance index R i Directly equal to 0; According to the above steps, the circuit node importance index R of all signals is obtained i , refer to the circuit node importance index R i , we can obtain the key signals that have a greater impact on the circuit, and thus statically identify the relevant soft error sensitive bits.

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