Parallel self-servo write circuit in data storage device

Abstract

The present disclosure describes example circuits, data storage devices, and methods to provide parallel self-servo writes in a data storage device. The data storage device may include a plurality of heads actuated over respective surfaces of a storage medium, and at least two preamplifiers and a read path to a channel circuit. The control circuit can select the magnetic heads connected through different preamplifiers to perform parallel self-servo writing and receive read signals from the selected magnetic heads in parallel. The read signals, which may be based on a self-servo write reference spiral previously written to the storage medium, may be used to determine respective position error signals for the two heads and to control their respective positions with respective control signals to respective micro and / or milliactuators on shared voice control motors and arms supporting the heads.

Description

Technical Field

[0001] The present disclosure relates to a self-servo writing process for a data storage device. In particular, the present disclosure relates to using a data storage device hardware circuit that may include a read / write path for two-dimensional magnetic recording to write servo tracks on two heads in parallel. Background Art

[0002] The self-servo writing (SSW) process is a critical step in the manufacturing of hard disk drives (HDDs), which are widely used for data storage in various computing devices. This process involves creating servo tracks on the disk surface within the HDD. The drive's control system uses the servo tracks to accurately position the read / write head over the data track during operation. The accuracy of the servo track writing is crucial to the drive's performance, as it directly affects the areal density and reliability of data storage.

[0003] Traditionally, servo track writing can be categorized into two primary methods: external and internal. External servo writing requires writing positioning information to the disk before the disk is assembled into the HDD, typically using specialized equipment. In contrast, internal writing, or SSW, utilizes the HDD's own read / write heads to write the servo information after the disk assembly is installed in the drive. SSW offers the advantage of aligning the servo tracks to the drive's final assembled state, accounting for any variations that may have occurred during assembly.

[0004] The SSW process begins with the disk surface initially blank. As the disk rotates, a servo writer embedded in the HDD writes a series of spiral reference patterns onto the disk, such as by sweeping the write head between the inner and outer diameters at a known rate and writing a known pattern of magnetic transitions. These spiral reference patterns provide positioning information that can be used to write production servo patterns onto the disk surface.

[0005] Figure 1A Example servo patterns are illustrated. Figure 1A The prior art disc format includes a plurality of servo sectors 60-6 recorded around the circumference of the disc 2. N , these servo sectors define a plurality of servo tracks, wherein the data track 4 is defined relative to the servo tracks. Each servo sector 6 i The servo data field 12 stores coarse head positioning information, such as the track address, used to position the head over the target data track during a seek operation. Each servo sector 6 iA servo burst group 14 (e.g., A, B, C, and D bursts) may further be included, the servo burst group comprising a plurality of consecutive transitions recorded at precise intervals and offsets relative to the centerline of the data track. The servo burst group 14 provides fine head position information for centerline tracking while accessing the data track during write / read operations. In some configurations, the servo and data tracks may be combined to form different physical regions written at different track densities or frequencies, such as from the inner diameter (Z0) of the disk to the outer diameter (Z2) of the disk.

[0006] Self-servo writing can be a lengthy process, particularly for data storage devices that include a large number of storage media disks. For example, some HDD form factors may include up to 10 platters, each including two storage media surfaces. Therefore, it may be advantageous to use multiple read / write heads to write servo tracks in parallel on multiple surfaces. However, the HDD control circuitry may not be designed to support simultaneous reading and writing by different heads on different surfaces. While dedicated control circuitry can be provided external to the HDD control circuitry (with appropriate interfaces and data channels to and from the internal heads and actuators) or added to the internal HDD circuitry, the impact on the cost of the HDD of hardware used only during the self-servo writing process may be undesirable.

[0007] Techniques are needed to improve the on-board hardware efficiency of self-servo write control circuitry for parallel self-servo writes. Summary of the Invention

[0008] Various aspects of a data storage device supporting parallel self-servo writing are described, particularly using control circuitry that supports both self-servo writing and production read / write operations in a data storage device configured for two-dimensional magnetic recording (TDMR) using multiple read / write elements and corresponding read / write paths on each head.

[0009] One general aspect includes a data storage device comprising a first magnetic head actuated over a first storage medium surface, wherein the first magnetic head may include a first plurality of read elements, and each read element in the first plurality of read elements is configured to generate a corresponding read signal in response to the first storage medium surface. The device also includes a second magnetic head actuated over a second storage medium surface, wherein the second magnetic head may include a second plurality of read elements, and each read element in the second plurality of read elements is configured to generate a corresponding read signal in response to the first storage medium surface. The device also includes a control circuit configured to: select a first corresponding read signal from a first plurality of read elements; select a second corresponding read signal from a second plurality of read elements; receive the first corresponding read signal and the second corresponding read signal in parallel by a channel circuit; determine a first position error signal based on the first corresponding read signal by the channel circuit; determine a second position error signal based on the second corresponding read signal by the channel circuit; control a first position of the first head in response to the first position error signal; control a second position of the second head in response to the second position error signal; write a servo pattern at the first head in response to the first position being within a first error tolerance value relative to a first self-servo write reference spiral; and write a servo pattern at the second head in response to the second position being within a second error tolerance value relative to a second self-servo write reference spiral.

[0010] Specific implementations may include one or more of the following features. The first storage medium surface may include a first self-servo write reference spiral, the second storage medium surface may include a second self-servo write reference spiral, the first position error signal may be responsive to the first self-servo write reference spiral, and the second position error signal may be responsive to the second self-servo write reference spiral. During the self-servo write mode, the control circuit may also be configured to: control the first head to write a first set of servo tracks to the first storage medium surface; and control the second head to write a second set of servo tracks to the second storage medium surface. The device may include: a first motor configured to position at least one set of read heads relative to a stack of storage medium disks including a first storage medium surface and a second storage medium surface; and a plurality of head actuators disposed on at least one set of arms corresponding to at least one set of magnetic disks, wherein each of the plurality of head actuators corresponds to a corresponding arm in the at least one set of arms and a corresponding head in the at least one set of heads. The control circuit may include: a motor control circuit configured to provide a motor control signal to a first motor; a first actuator control circuit configured to provide a first actuator control signal to a first selected magnetic head actuator; and a second actuator control circuit configured to provide a second actuator control signal to a second selected magnetic head actuator. The control circuit may also be configured to: control the overall position of the first magnetic head and the second magnetic head using the motor control circuit; selectively control a first position of the first magnetic head using the first actuator control circuit; and selectively control a second position of the second magnetic head using the second actuator control circuit. The device may include a plurality of arm actuators arranged on at least one group of arms, wherein each arm actuator in the plurality of arm actuators corresponds to a corresponding arm in the at least one group of arms and a corresponding head in the at least one group of heads; during a self-servo write mode using the first head and the second head, the first actuator control circuit is electrically connected to the head actuator for the first head, and the second actuator control circuit is electrically connected to the head actuator for the second head; and during a data read / write mode using the first head, the first actuator control circuit is electrically connected to the arm actuator, and the second actuator control circuit is electrically connected to the head actuator. The control circuit may also include at least one switch configured to select electrical connection between the first actuator control circuit and the second actuator control circuit in the self-servo write mode and the data read / write mode. The control circuit may also include a third actuator control circuit configured to control the corresponding arm actuator for the first head and the corresponding arm actuator for the second head during the self-servo write mode.The control circuitry may include: a first preamplifier circuit configured to control read and write signals to a first group of magnetic heads including a first magnetic head; a second preamplifier circuit configured to control read and write signals to a second group of magnetic heads including a second magnetic head; and a channel circuit configured for a group of read signal paths corresponding to a number of a first plurality of read elements for two-dimensional magnetic recording, wherein the number of the second plurality of read elements is equal to the number of the first plurality of read elements. The control circuitry may also be configured to: receive, by the channel circuit, a first read signal from the first preamplifier circuit to a first read signal path in the group of read signal paths during a self-servo write mode; and receive, by the channel circuit, a second read signal from the second preamplifier circuit to a second read signal path in the group of read signal paths. The control circuitry may also be configured to: set, in the first preamplifier circuit, a first set of parameters for the first magnetic head; and set, in the second preamplifier circuit, a second set of parameters for the second magnetic head, wherein the first set of parameters is different from the second set of parameters. The device may include: a first group of magnetic heads, which are arranged in sequence relative to the spaced-apart storage medium surface and include a first magnetic head; and a second group of magnetic heads, which are arranged in sequence relative to the spaced-apart storage medium surface and include a second magnetic head, wherein the control circuit is further configured to: select the first magnetic head based on a first sequential position of the first magnetic head in the first group of magnetic heads; and select the second magnetic head based on a second sequential position in the second group of magnetic heads; and the first sequential position and the second sequential position are equal.

[0011] Another general aspect includes a method comprising: actuating a first magnetic head over a first storage medium surface in a data storage device, wherein the first magnetic head may include a first plurality of read elements and each read element in the first plurality of read elements is configured to generate a corresponding read signal in response to the first storage medium surface; actuating a second magnetic head over a second storage medium surface in the data storage device, wherein the second magnetic head may include a second plurality of read elements and each read element in the second plurality of read elements is configured to generate a corresponding read signal in response to the first storage medium surface; selecting a first corresponding read signal from the first plurality of read elements; and selecting a second corresponding read signal from the second plurality of read elements. a read signal; receiving a first corresponding read signal and a second corresponding read signal in parallel by a channel circuit in a data storage device; determining a first position error signal by the channel circuit based on the first corresponding read signal; determining a second position error signal by the channel circuit based on the second corresponding read signal; controlling a first position of the first magnetic head in response to the first position error signal; controlling a second position of the second magnetic head in response to the second position error signal; writing a servo pattern at the first magnetic head in response to the first position being within a first error tolerance value relative to a first self-servo write reference spiral; and writing a servo pattern at the second magnetic head in response to the second position being within a second error tolerance value relative to a second self-servo write reference spiral.

[0012] Specific implementations may include one or more of the following features. The first storage medium surface may include a first self-servo write reference spiral; the second storage medium surface may include a second self-servo write reference spiral; the first position error signal may be responsive to the first self-servo write reference spiral; and the second position error signal may be responsive to the second self-servo write reference spiral. The method may include, during a self-servo write mode: controlling the first magnetic head to write a first set of servo tracks for a servo pattern to the first storage medium surface; and controlling the second magnetic head to write a second set of servo tracks for a servo pattern to the second storage medium surface. The method may include: controlling the overall position of a first head and a second head using a motor control signal, wherein the data storage device may include a first motor configured to position at least one set of read heads relative to a stack of storage media disks including a first storage media surface and a second storage media surface in response to the motor control signal; selectively controlling a first position of the first head using a first actuator control signal, wherein the data storage device may include a first selected head actuator corresponding to a first arm supporting the first head; and selectively controlling a second position of the second head using a second actuator control signal, wherein the data storage device may include a second selected head actuator corresponding to a second arm supporting the second head. The method may include, during a self-servo write mode in which a servo track is written in parallel using the first and second heads: sending a first actuator control signal to a first selected head actuator for the first head; and sending a second actuator control signal to a second selected head actuator for the second head. The method may include, during the self-servo write mode, sending a third actuator control signal to the first arm actuator for the first head and the second arm actuator for the second head. The method may include, during a data read / write mode using a first magnetic head: sending a first actuator control signal to a first arm actuator of the first magnetic head; and sending a second actuator control signal to a first selected head actuator of the first magnetic head. The method may include, during a self-servo write mode: receiving, by a channel circuit, a first read signal from a first preamplifier circuit to a first read signal path in a set of read signal paths, the set of read signal paths corresponding to a plurality of read elements for two-dimensional magnetic recording; and receiving, by the channel circuit, a second read signal from a second preamplifier circuit to a second read signal path in a set of read signal paths. The method may include: selecting the first magnetic head based on a first sequential position of the first magnetic head in a first set of magnetic heads, wherein the first set of magnetic heads are sequentially arranged relative to a spaced storage medium surface and selectively connected to the first preamplifier circuit; and selecting the second magnetic head based on a second sequential position of the second magnetic head in a second set of magnetic heads, wherein the first set of magnetic heads are sequentially arranged relative to a spaced storage medium surface and selectively connected to the second preamplifier circuit, and the first sequential position and the second sequential position are equal.

[0013] Another general aspect includes a data storage device comprising: a first magnetic head actuated over a first storage medium surface, wherein the first magnetic head may include a first plurality of read elements and each of the first plurality of read elements is configured to generate a corresponding read signal in response to the first storage medium surface; a second magnetic head actuated over a second storage medium surface, wherein the second magnetic head may include a second plurality of read elements and each of the second plurality of read elements is configured to generate a corresponding read signal in response to the first storage medium surface; means for selecting a first corresponding read signal from the first plurality of read elements; means for selecting a second corresponding read signal from the second plurality of read elements; and means for transmitting, by channel circuitry and a component for receiving a first corresponding read signal and a second corresponding read signal in a row; a component for determining, by a channel circuit, a first position error signal based on the first corresponding read signal; a component for determining, by the channel circuit, a second position error signal based on the second corresponding read signal; a component for controlling a first position of the first magnetic head in response to the first position error signal; a component for controlling a second position of the second magnetic head in response to the second position error signal; a component for writing a servo pattern at the first magnetic head in response to the first position being within a first error tolerance value relative to a first self-servo write reference spiral; and a component for writing the servo pattern at the second magnetic head in response to the second position being within a second error tolerance value relative to a second self-servo write reference spiral.

[0014] The present disclosure describes various aspects of innovative technologies that can improve self-servo writing to reduce the production time / cost of data storage devices, while also controlling the cost impact on control circuits within the data storage devices. Various embodiments include operating and control circuits to overcome or at least reduce problems previously encountered in data storage devices, and are therefore more efficient, reliable and / or more cost-effective than other data storage devices. That is, the various embodiments disclosed herein include hardware and / or software that have the function of improving the cost, quality and manufacturing time of data storage devices, such as by using control circuits that support dual-head parallel self-servo writing (hereinafter referred to as self-servo writing or SSW) and single-head production read / write operations in data storage devices. Therefore, the embodiments disclosed herein provide various improvements to data storage devices and computing systems that include such data storage devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The technology described herein is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like reference numerals are used to refer to similar elements.

[0016] Figure 1A is a schematic diagram of a prior art disk format including a plurality of servo sectors defining a servo track.

[0017] Figure 1B and Figure 1C is a schematic diagram of a prior art data storage device in the form of a disk drive including at least one head actuated over a disk surface using control circuitry, and a corresponding side view of an arm / actuator assembly for two sets of heads.

[0018] Figure 2A and Figure 2B is a schematic diagram of a control circuit operating in two different modes to support self-servo write and read / write operations.

[0019] Figure 2C and Figure 2D is used for Figure 2A and Figure 2B Schematic diagram of another example servo interface circuit of the control circuit in self-servo write and read / write operation modes.

[0020] Figure 3 is a block diagram of a configuration of a data storage device including control circuitry and a storage medium format that is written using self-servo writing.

[0021] Figure 4 is a schematic diagram illustrating parallel self-servo writing using two head groups with corresponding preamplifier circuits.

[0022] Figure 5A and Figure 5B is an example preamplifier configuration for parallel self-servo writing using a TDMR head.

[0023] Figure 5C is an example preamplifier configuration for parallel self-servo writing using a single read head.

[0024] Figure 5D is an example selection logic component for controlling the preamplifier circuit to switch between the self-servo write mode and the read / write operation mode.

[0025] Figure 6A and Figure 6B is an example logic component for determining servo control signals for parallel self-servo writing.

[0026] Figure 7 is an example method of parallel self-servo writing.

[0027] Figure 8 is another example method of servo writing using an additional actuator controller.

[0028] Figure 9 This is an example method for data read / write operations after the self-servo write is completed.

[0029] Figure 10 is an example method of positioning the head for parallel self-servo writing.

[0030] Figure 11 is an example method of compensating for different track positions between two heads in parallel self-servo writing.

[0031] Figure 12 is an example method of managing the seams between adjacent servo regions having different frequencies.

[0032] Figure 13 is an example method for managing thermal creep during parallel self-servo writing.

[0033] Figure 14A is an example method of controlling multiple actuators for each head during self-servowriting and data read / write operations.

[0034] Figure 14B is another example method of controlling multiple actuators for each head during self-servowriting and data read / write operations.

[0035] Figure 15A is an example method of controlling the preamplifier circuit during self-servo writing.

[0036] Figure 15B is an example method of controlling a preamplifier circuit during data read / write operations. DETAILED DESCRIPTION

[0037] Parallel self-servo writing (SSW) based on concurrent SSW filling using onboard data storage device electronics and independent micro dual-stage actuator position control can reduce SSW test time without significantly affecting the cost of the electronics. In some configurations, the data storage device reads one head from the upper set of preamplifier circuits and one head from the lower set of preamplifier circuits in parallel based on a spiral reference pattern previously written to the disk. This channel uses the storage device controller and a decoupled two-dimensional magnetic recording (TDMR) channel to handle spiral position and timing detection. Separate microactuator drivers for the two sets of heads provide independent positioning based on the shared voice coil motor (VCM) position. The SSW firmware can calculate the position error and phase error of the two heads in parallel. The VCM can track the average decoupled position error signal (PES), while each microactuator compensates for its corresponding PES. In some configurations, phase control can also be handled separately for the two heads. In some configurations, multiple positioning based on previously written spirals can be used to write a better spiral before finally writing the concentric servo tracks and corresponding servo sectors used to produce the servo pattern.

[0038] exist Figure 1B In the embodiment, the control circuit 20 of the data storage device (such as a hard disk drive (HDD)) processes the read signal 42 sent from the head 16 to demodulate the servo sectors 380-38 N , and generates a position error signal (PES) representing the error between the actual position of the magnetic head and the target position relative to the target track in a track following operation. The control circuit 20 filters the PES using an appropriate compensation filter to generate a plurality of control signals for positioning the magnetic head 16 relative to the surface of the disk 22. A VCM control signal can be applied to the VCM 46, which causes the actuator arm 18 to pivot, thereby actuating the magnetic head 16 radially above the disk 22 in a direction that reduces the PES. A milliactuator control signal 48 can be applied to the piezoelectric actuator 36 on the suspension 17 near the top of the arm 18 to provide fine lateral positioning, thereby further reducing the PES. Hereinafter, this actuator may be referred to as a milliactuator or suspension actuator. In some configurations, an additional actuator can be provided on the suspension 17, such as a microactuator positioned closer to the magnetic head 16 and receiving another control signal from the control circuit 20. Hereinafter, the actuator may be referred to as a microactuator or a head actuator. Servo sectors 380-38 N Any suitable position information may be included, such as servo tracks and wedge addresses for coarse positioning, and servo bursts for fine positioning, as described above with reference to Figure 1A The servo bursts may include any suitable pattern, such as Figure 1A During data read / write operations, the control circuit 20 may use the servo patterns from the servo sectors 380-381. N The feedback from the control circuit 20 positions the magnetic head 16 on the disk 22 to seek and follow the desired data track for data read and write operations. For example, the control circuit 20 can receive host storage commands from the host 24 through the host interface and determine corresponding data read and write operations to read previously written data from the disk 22 or write new data to the disk 22.

[0039] exist Figure 1C , is a side view of a head and disk stack of a data storage device consisting of a plurality of disks 22 and corresponding magnetic heads 16. For example, each disk 22 may include two recordable storage media surfaces located on opposite surfaces of the disk and read by corresponding magnetic heads. Figure 1CIn the embodiment of the present invention, the disk stack includes four disks, eight storage medium surfaces and eight corresponding magnetic heads. The magnetic heads and disks can be grouped into groups. For example, disk 22A and magnetic head 16A can correspond to a first group of magnetic heads and media, and disk 22B and magnetic head 16B can correspond to a second group of magnetic heads and media. In some configurations, a single VCM 46 can provide total positioning of two magnetic head groups on corresponding media surfaces. In some configurations, a split actuator can include separate VCMs for different magnetic head groups (and receive corresponding control signals). In addition, each arm can include one or more arms or magnetic head actuators 36, such as piezoelectric microactuators, located somewhere along the length of the suspension 17. When the corresponding magnetic head is an active magnetic head for reading or writing data, each suspension or magnetic head actuator can be controlled separately. In some configurations, each group of magnetic heads can include a corresponding preamplifier circuit and a flexible circuit connection to a data storage device controller circuit.

[0040] Figure 2A and Figure 2B An example configuration of a control circuit 200 is shown for positioning magnetic heads organized into two head groups in a data storage device. Figure 2A In the embodiment, the control circuit 200 is configured for data read / write operations based on positioning of servo data written during a self-servo write operation, and Figure 2B , the control circuit 200 is configured for self-servo write operations (during the self-servo write portion of the manufacturing and testing process). In the configuration shown, the control circuit 200 includes a servo interface circuit 210, a servo control circuit 230 (sometimes referred to as a servo interface controller), a flexible circuit 240, a preamplifier circuit 270, a read / write channel 280, and various connections (such as wires or traces) and interfaces (R pins or connectors). The control circuit 200 interacts with the head group 260 for actuator control and read and write signals. For each head group, only a portion of one suspension assembly 262 is shown, but each head group can include multiple suspensions and heads corresponding to the number of storage media surfaces in the disk stack. For example, a four-platter HDD can include eight suspensions / heads organized into two groups of four heads, or a ten-platter HDD can include twenty suspensions / heads organized into two groups of ten heads. The control circuit 200 may be switchable to select any head (and corresponding actuator) from each stack for parallel SSW operation, so only the control path for the selected head is shown.

[0041] The servo interface circuit 210 may include a set of motor or actuator drivers for positioning the magnetic head above the surface of the medium. The servo interface circuit 210 may receive a digital servo control signal calculated by the servo control logic component 230 to generate an analog control signal for the corresponding motor or actuator. Each circuit for generating an analog control signal for a motor or actuator may be referred to as a motor or actuator control circuit. For example, the servo interface circuit 210 may include a VCM digital-to-analog converter (DAC) 212, which is configured to receive a digital position control signal from the VCM and convert the digital position control signal into a pair of analog control signals suitable for driving the VCM to a desired position. The milliactuator DAC 214 may be configured to provide an actuator control signal to the milliactuator (e.g., a piezoelectric actuator on a suspension near the top of the arm) of the selected magnetic head during read / write mode, or to provide an actuator control signal to the microactuator of the second magnetic head during self-servo write mode. The milliactuator DAC 214 can be configured to receive a digital position control signal for the milliactuator or for a second microactuator in a parallel self-servo write mode and convert the digital position control signal into an analog control signal provided to the actuator via the dual-phase driver block 222. The microactuator DAC 216 can be configured to provide an actuator control signal to the microactuator of the selected head (e.g., the piezoelectric actuator closest to the head) during read / write mode or self-servo write mode. The microactuator DAC 216 can be configured to receive a digital position control signal for the selected microactuator and convert the digital position control signal into an analog control signal provided to the actuator. In some configurations, the microactuator DAC 216 can be coupled to a pair of dual-phase driver circuits 222 and 224. The dual-phase driver circuits 222 and 224 can amplify the same phase and opposite phase of the analog control signal from the microactuator DAC 216 before sending it to the microactuator of the selected head. The dual-phase driver circuits 222 and 224 can generate AC control signals for the connected microactuator. This configuration supports read / write mode. In parallel self-servo write mode, 216 drives only block 224, while block 222 is controlled by DAC 214.

[0042] Servo interface circuit 210 may include one or more switches for changing the operation and / or control path of the DAC between a self-servo write mode and a data read / write mode. For example, switch 218 may determine whether milliactuator DAC 214 is electrically connected to the milliactuator of the target head during read / write mode, or control one of the microactuators during self-servo write mode. Switch 220 may select whether dual-phase driver circuit 222 is connected to milliactuator DAC 214 or microactuator DAC 216.

[0043] exist Figure 2A In the embodiment shown in FIG. 2 , switch 218 is closed, thereby connecting the milliactuator DAC 214 to the milliactuator of the target head for read / write operations, and the selection of the preamplifier can determine which head is being controlled (from the first head group or the second head group). Switch 220 is closed for path 220.2 to connect the microactuator DAC 216 to the dual-phase driver circuits 222 and 224. This allows the microactuator DAC 216 to also drive the microactuator of the target head for read / write operations based on the preamplifier that determines which head is being controlled. This mode corresponds to conventional read / write.

[0044] exist Figure 2B , switch 218 is opened, thereby disconnecting the milliactuator DAC 214 from the milliactuator. Switch 220 is closed for path 220.1 to connect the milliactuator DAC 214 to the dual-phase driver circuit 222, thereby controlling the microactuator of one of the target heads, while the microactuator DAC 216 remains connected to the dual-phase driver circuit 224 to control the microactuator of the other target head for parallel self-servo writing.

[0045] In some configurations, the servo interface circuit 210 can include a plurality of interface connections 226.1-226.6 to connect the control path from the DAC to the corresponding motor or actuator through the flex circuit 240. For example, the flex circuit 240 can include a plurality of wires or traces that connect to the pin interface from the servo interface circuit 210 and provide electrical connections to the input interface connections on the corresponding motor or actuator assembly. The flex circuit 240 can include an interface connector 242 that connects to a board-based circuit in the data storage device, such as a printed circuit board assembly (PCBA) that includes the device controller, the servo interface circuit 210, the servo control logic 230, and the channel 280. For illustrative purposes, the interface connection 272 between the channel 280 and the preamplifier circuit 270 is shown separately, but can be part of the same pin interface 242 and traces that pass through the flex circuit 240. The flex circuit 240 can receive a pair of VCM control signals 244 and electrically connect them to the VCM of the moving head stack in the VCM control path. The flexible circuit 240 can receive the milliactuator control signal 246 and electrically connect it to the milliactuator of the target head in the milliactuator control path. In some configurations (described later), an additional DAC may be present in the servo interface circuit 210 to drive the milliactuator using the milliactuator control signal 246 during the self-servo write mode. The flexible circuit 240 can receive microactuator control signals 248, 250, 252, and 254 to electrically connect the microactuator DAC 216 and / or the milliactuator DAC 214 in the microactuator control path to the microactuator of the target head.

[0046] Servo control logic 230 can generate motor and actuator control signals for adjusting the positioning of the magnetic head above the media surface. Servo control logic 230 can use a combination of hardware and software to receive position error signals 288 and 290 from channel 280 and generate digital VCM and actuator control signals in the form of digital adjustment values ​​for changing the position of the corresponding motor or actuator. For example, servo control logic 230 can generate digital VCM control signal 236, milli-actuator control signal 234 and micro-actuator control signal 232. In some configurations, servo control logic 230 can also provide control signals (not shown) for selecting the switch configuration of switches 218 and 220 and switching between data read / write mode and self-servo write mode.

[0047] The head group 260 can include electronic equipment, motors and actuators for positioning the magnetic head above the storage medium and generating read and write signals to interact with the storage medium. Each suspension assembly in the suspension assembly 262 can support the corresponding magnetic head 268 above the surface of the storage medium, and roughly position the magnetic head stack relative to the disk stack rotation by VCM. Each suspension assembly 262 can include multiple dual-stage or multi-stage actuators for increasingly fine positioning. For example, each suspension assembly 262 can include a milli-actuator 264 that can adjust the position of a part of the suspension laterally within the actuator range and a micro-actuator 266 that can adjust the position of the magnetic head 268 laterally near the distal end of the suspension. In some configurations, the milli-actuator can be referred to as a suspension actuator (a part of the positioning suspension), and the micro-actuator can be referred to as a head actuator (the position of the actuating magnetic head at the end of the suspension). As described above, the servo interface circuit 210 can provide a control signal to two or more actuators to control one or more target heads. For example, during a data read / write operation, magnetic head 268.1 on suspension assembly 262.1 may be selected as the target magnetic head, and actuator control signals may be sent to milliactuator 264.1 and microactuator 266.1, or magnetic head 268.2 on suspension assembly 262.2 may be selected as the target magnetic head, and actuator control signals may be sent to milliactuator 264.2 and microactuator 266.2. During a self-servo write mode, magnetic heads 268.1 and 268.2 may be selected for parallel self-servo write, and actuator control signals may be sent to microactuators 266.1 and 266.2 in parallel.

[0048] Preamplifier circuits 270 can control and amplify read and write signals between channels 280 and heads 268. In some configurations, each head group has a corresponding preamplifier circuit 270, such as preamplifier circuit 270.1 for the upper group and preamplifier circuit 270.2 for the lower group. Each preamplifier circuit 270 can be configured to provide write and read signals to a selected head in its head group and connect the read and write paths to corresponding interfaces of the channels. In the illustrated configuration, heads 268 are TDMR heads comprising two read elements and one write element. Preamplifier circuits 270 and channels 280 are configured with corresponding read and write channels. For example, preamplifier circuit 270.1 includes two read channels 274 and 276 and one write channel 278 for connection to corresponding interfaces 272 of channels 280 via flexible circuit 240. Preamplifier circuit 270.2 also includes selective electrical connections to read channels 274 and 276 and write channel 278. The preamplifier circuit 270 can be configured to receive control signals from the channel 280 and / or an associated controller to select which heads and corresponding connections to the read and write channels are active. During data read / write mode, only one preamplifier circuit 270 and the selected head 268 can be active to provide two read signals from the read element on that head. During the parallel self-servo write mode, each preamplifier can select a head and provide only one read signal (selecting between the two read elements on each head), so that the two read channels 274 and 276 receive a single read signal from each head, and the channel 280 can decouple the read signals to calculate separate PES values ​​for the two heads in parallel.

[0049] In some configurations, additional controller logic can be used to select between a data read / write mode and a self-servo write mode for the preamplifier 270. For example, a mode selection logic 282 can communicate with the channel 280 or an associated controller to receive a head select control signal 284 and send a corresponding preamplifier control signal 286 to the preamplifier circuit 270. The read / write control signal can be configured to selectively send the preamplifier control signal 286 to only one preamplifier circuit at a time. The mode selection logic 282 can provide a second control signal and corresponding switching to send head and element selection control information to both preamplifier circuits 270 in parallel via the preamplifier control signal 286.

[0050] exist Figure 2C and Figure 2D , another example configuration of a servo interface circuit 291 for use with the control circuit 200 is shown. Figure 2CA configuration 202 for a self-servo write mode of operation is shown, and Figure 2D The configuration 204 for the data read / write mode of operation is shown. The VCM DAC 212 and the microactuator DAC 216 may be substantially as described above with respect to Figure 2A and Figure 2B Perform the operation as described.

[0051] As shown in configuration 202, the milli-actuator DAC 214 can also be substantially similar during self-servo writing. Figure 2B The second head is operated as described and is connected to the dual phase driver 222 at 220.1 to generate actuator control signals 226.3 and 226.4 for the microactuators on the suspension of the second head. The third actuator DAC 292 (referred to as S-DAC 292) is configured to generate control signals for the milliactuators during parallel self-servo writing. The S-DAC 292 can be obtained from a servo controller such as Figure 2B Servo controller 230 in (290) receives third digital actuator control signal 293, and provides control signal to control milli-actuators via 226.7 and 226.8. Servo interface circuit 291 may include digital signal processor (DSP) 295 and demultiplexer 296. During parallel self-servo writing, these components may be disabled or bypassed. For example, demultiplexer 296 may include or be connected to switch 297, which is configured to disconnect demultiplexer 296 from outer channel 294.1 and inner channel 294.2 during self-servo writing operation. Similarly, DSP 295 may be disabled simultaneously. In the absence of operation of demultiplexer 296, S-DAC 292 may control the milli-actuators of the suspension for the two head groups and the magnetic heads supporting the target write pair. In some configurations, the milli-actuators that drive the magnetic heads to perform parallel servo writing are connected to move in opposite directions. Thus, the milliactuator control signal 226 will drive the head to move in the opposite direction, thereby allowing coupled position control within the limits of the milliactuator travel. Configuration 202 may include additional pins for connection to electrically adjacent components. In some configurations, switches 220 and 297 may switch between modes only when both the microactuator and the milliactuator are disabled, such as when the head is parked between operations.

[0052] As shown in configuration 204, during data read / write operations, DSP 295 and demultiplexer 296 can be activated. For example, switch 297 can connect demultiplexer 296 to inner channel 294.2 and disconnect S-DAC 292 from inner channel 294.2. DSP 295 can modify digital control signal 234 to drive S-DAC 292 to provide a second branch of the actuator control signal, thereby facilitating the switching process of the milli-actuator to outer channel 294.1. By generating milli-actuator control signals 226.7 for the outer heads and 226.8 for the remaining heads, respectively, the control signals generated by milli-actuator DAC 214 and S-DAC 292 can each facilitate control of the milli-actuator for the target head during read / write operations.

[0053] Figure 3 A portion of an example control circuit 300 and a storage medium 360 for a data storage device (such as an HDD) are shown. In the example shown, the control circuit 300 may include one or more hardware controllers. The controller 302 may include a storage device controller configured to receive host storage commands, process commands for writing, reading, and managing non-volatile storage media (such as storage medium 360 or HDD) stored in a disk drive. Figure 1A 、 Figure 1B and / or Figure 1C In some embodiments, the controller 302 may correspond to separate host interface read / write paths to subsets of disk surfaces in a data storage device having multiple controllers. In some embodiments, the controller 302 may be configured to manage servo, read / write, and self-servo write operations for one or more actuators, heads, and corresponding writer and reader elements.

[0054] Controller 302 may include a processor 304, memory 306, a host interface 308, and access to a buffer memory 310. Controller 302 may also include a read / write channel 320 and a servo controller 342, which includes a servo processor 344 and a servo logic component 346. In some embodiments, one or more of host interface 308, read / write channel 320, and servo controller 342 may be embodied in a separate package, such as an application specific integrated circuit (ASIC), a system on a chip (SOC), or other dedicated circuitry that interfaces with processor 304 and memory 306 to perform their respective functions. Controller 302 may include physical and electrical interfaces for connecting to buffer memory 310, a power supply (not shown), a preamplifier 322, a servo interface controller 348, other controllers, and / or other circuit components. In some embodiments, the components of controller 302 may be interconnected by a bus that includes one or more conductors that allow communication between the components. For example, processor 304, memory 306, host interface 308, read / write channel 320, and / or servo controller 342 may be components attached to a printed circuit board assembly (PCBA) 350 that provides one or more layers of interconnecting conductors between the components.

[0055] The processor 304 may include any type of conventional processor or microprocessor that interprets and executes instructions. The processor 304 may include multiple hardware processors configured to operate independently or in combination (such as multiple processor cores performing thread operations) to execute one or more instruction sets. The memory 306 may include random access memory (RAM) or another type of dynamic storage device that stores information and instructions executed by the processor 304, and / or read-only memory (ROM) or another type of static storage device that stores static information and instructions for use by the processor 304 and / or any suitable storage element, such as a system portion of a hard disk medium or a solid-state storage element. The memory 306 may be configured to store controller firmware 312 including instructions, including one or more modules or submodules for specific data storage device operations, and the processor 304 may execute these instructions, including controlling communications with other components (such as the host interface 308, the buffer memory 310, the read / write channel 320, and the servo controller 342).

[0056] Controller firmware 312 may include firmware for operating the control circuit 300 and the corresponding data storage device in different operating modes. For example, the controller firmware 312 may support a self-servo write mode 314 for writing a servo pattern to a storage medium using the control circuit 300. In some configurations, the self-servo write mode 314 may be enabled in the data storage device after assembly and may be capable of writing a desired servo pattern similar to that shown for the storage medium 360. The self-servo write mode 314 may begin with one or more blank storage medium surfaces and / or surfaces previously written with a spiral reference pattern. In some configurations, the self-servo write mode 314 may include a series of iteratively written spiral reference patterns and writing and rewriting servo sectors (such as servo sector 364) until the desired servo pattern and corresponding quality indicators are achieved. After achieving the desired servo pattern and servo performance level, the controller firmware 312 may end the self-servo write mode 314 and enable a data read / write mode 316 to write and read data in data tracks defined relative to the servo pattern. For example, the data read / write mode 316 may be a production configuration of the control circuit 300 for the remainder of the configuration and testing of the data storage device and during its production life in field operation.

[0057] Reference storage medium surface 360 ​​illustrates an example servo format generated from servo write pattern 314 for use during data read and write pattern 316. The data track format can be configured relative to the servo format, but may not include a one-to-one mapping of data tracks to servo tracks. For example, the servo format may define concentric servo tracks 362 defined by servo sectors 364.1-364.n. The servo sectors 364 and corresponding servo tracks 362 may have different data rates selected to more effectively utilize the varying track lengths and speeds from the inner diameter (ID) 360.1 to the outer diameter (OD) 360.2 of the rotating disk. The data tracks may be configured to overlay the servo tracks, with the data track format being either concentric, where each track forms a distinct loop with the start and end points on the same circumference, or continuous, where the tracks form a continuous spiral with the start and end points not on the same circumference, and may support varying track densities and track areas relative to the servo format. In some configurations, the servo tracks 362 can be organized into zones of varying track density or frequency. A servo zone can refer to a group of concentrically adjacent servo tracks having a shared nominal track density and / or frequency that is similar to one another but different from adjacent zones. Each pair of adjacent servo zones can also define a zone boundary 366 therebetween. Zone boundaries can require special operations to manage servo writing and / or servo positioning when crossing a zone boundary. For example, positioning information, timing, and channel settings can change when crossing a zone boundary. The track configuration can be stored in a set of media configuration parameters for the servo and data track formats for use by other components of the system, such as the read / write channel 320 and the servo controller 342.

[0058] The host interface 308 may include any transceiver-like mechanism that enables the data storage device to communicate with other devices and / or systems, such as a host system for which the storage device provides data storage. The host interface 308 may include a host storage interface that complies with one or more storage interface standards, such as a Serial Advanced Technology Attachment (SATA) interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Peripheral Computer Express (PCIe), a Universal Serial Bus (USB), etc., for connecting the host interface 308 to a peripheral interface or network port.

[0059] Buffer memory 310 may include RAM, flash memory, or another type of dynamic storage device for storing host data and other information transferred between the storage medium of the storage device and the host (via host interface 308). In some embodiments, buffer memory 310 is a storage device separate from memory 306 and the disk surface or other non-volatile memory of the data storage device.

[0060] The read / write channel 320 may include one or more dedicated circuits configured to process binary data to be written to the disk surface using an analog write signal and to process the analog read signal from the disk surface back into binary data. For example, the read / write channel 320 may include a write path consisting of various data scramblers, a stroke limit (RLL) encoder, an iterative error correction code (ECC) encoder, a pre-compensation circuit, and other data or signal processing components. The read / write channel 320 may include a read path consisting of various amplifiers, filters, equalizers, analog-to-digital converters (ADCs), soft information detectors, iterative ECC decoders, and other data or signal processing components. The write channel component may include a write channel circuit, and the read channel component may include a read channel circuit, but these circuits may share some components. The read / write channel 320 may provide an analog write signal to a preamplifier 322 and receive an analog read signal from the preamplifier, which controls and amplifies the signal to and from the magnetic head. During the data read / write mode of operation 316, binary data for recording to the storage medium can be received by the read / write channel 320 from the controller firmware 312, and the decoded data from the read / write channel 320 can be passed to the controller firmware 312 and / or directed to the buffer memory 310 for communication with the host. The read / write channel 320 can also separate the servo read signals from the data read signals to support the servo controller 342.

[0061] In some configurations, the read / write channel 320 may include an analog front end 324 configured to receive an analog read signal from the preamplifier 322 and convert the analog read signal into a digital read signal for processing by other components of the read / write channel 320. For example, the analog front end 324 may include an analog-to-digital converter (ADC), a timing circuit, and one or more filters, equalizers, and / or other signal conditioning components for generating digital read data. In some configurations, the analog front end 324 and / or other components of the read / write channel 320 may support the operation of the servo controller 342. For example, the read signal received by the preamplifier 322 and the analog front end 324 may provide a servo read signal based on a read head response generated when the head passes through a servo sector 364 during self-servo writing, track seeking, track following, and other servo operations. In some configurations, the read / write channel 320 and the analog front end 324 may be configured for TDMR read / write operations and interface with the TDMR head through the preamplifier 322. For example, each TDMR head can include a single writer element and two reader elements, and during a TDMR read / write operation, the read / write channel 320 can receive two read signals from the heads in parallel to read servo and user data. The analog front end 324 can be configured with a TDMR interface 324.1 that includes two read channel inputs and one write channel output to receive data and send the data to the selected head. In a self-servo write mode, the two read channels can be decoupled to generate separate read signals from the two heads in parallel, and provide separate servo read signals and corresponding position error signals in the servo controller 342.

[0062] In some configurations, the read / write channel 320, the servo controller 342, and / or the controller 302 may include self-servo write functionality for operating during the self-servo write mode 314. These functions may be configured in firmware running on the controller 302 and / or its subcomponents. For example, the reference spiral detector 326 may include logic for generating position information based on one or more spiral reference patterns previously written to the surface of the storage medium. The magnetic transitions and information contained in the spiral reference patterns may be different from the production servo patterns written to the servo sectors 364 or the user data patterns from the data tracks, and different position information and associated position error signals may be used. The reference spiral detector 326 may be configured with logic for processing the read signal received from the target head to generate position information and / or a PES.

[0063] The SSW pattern generator 328 can generate write signals to the target head for writing production servo sectors and / or improved spiral reference patterns. For example, during a self-servo write mode, the read / write channel 320 can write servo sectors to the storage medium surface in parallel using the write elements of two heads. The servo pattern, including frequency, servo track identifier, burst pattern, and other data patterns, can be defined for the data storage device in firmware 312, and the SSW pattern generator 328 can generate corresponding write signals via the preamplifier 322 and the target head with position and timing based on SSW servo feedback. During parallel self-servo writing, the read / write channel 320 and / or servo controller 342 can determine the head position relative to a previously written self-servo write reference spiral, and as long as the head position is calculated to be within an acceptable error tolerance for the reference spiral, the next track of the production servo pattern can be written using the active head and the corresponding storage medium surface.

[0064] The zone trimming logic 332 may include special functionality for addressing zone boundaries 366 and overwriting issues that may result from writing over a previous servo pattern during self-servo writing. For example, reworking a production servo pattern may result in residual patterns from a previous iteration, where the new pattern may not completely overwrite the old pattern. Precise alignment can be difficult, particularly due to varying thermal characteristics and different thermal compensation values. Subsequent servo zones may be slightly offset from their target positions in the ID and / or OD directions. Consequently, a second parallel fill on the same surface, outside the confines of the new pattern, may result in residual servo tracks from a previous run not being overwritten. These residual tracks will appear at zone boundaries or at the ID and OD edges of each servo zone. Such repeated tracks may confuse the servo controller during read / write mode. The zone trimming logic 332 may include logic for writing erase strips at the ID and OD edges of servo sector writes to ensure that no residual patterns are present. The width of the erase strips may be based on the maximum inter-run thermal drift to ensure that even if thermal conditions change significantly between self-servo writes, no residual servo data is left, and unnecessary servo patterns are trimmed.

[0065] The preamplifier control logic 334 may include logic for selecting a target head via the preamplifier 322. For example, during a read / write operation mode 316, a control signal may be sent to a preamplifier of a head group including a target head, and the control signal indicates the target head that will receive and generate a read / write signal for a read / write operation. For example, the preamplifier control logic 334 may generate one or more serial enable control signals to activate one or both preamplifiers. During a self-servo write mode 314 using parallel servo write, the preamplifier control logic 334 may be configured to send an SSW head select signal 336 to both preamplifiers in parallel. For example, the read / write select control signal may be supplemented with a shunt signal and selection logic to direct the head select control signal to both preamplifiers.

[0066] The servo controller 342 may include one or more dedicated circuits configured to process servo data (such as position error signals) from the disk surface and provide control signals to position the actuator in a closed-loop control system. The servo controller 342 may also receive commands from the processor 304 for positioning operations, such as seek, track following, load, unload, sweep, idle, and other actuator positioning operations. The servo controller 342 may also implement a servo error recovery process to recover from servo errors. The servo controller 342 may also operate during a self-servo write mode 314 to provide position control relative to a previously written spiral reference pattern for writing servo sectors 364. In some embodiments, the servo controller 342 may include a servo processor 344 and a servo logic component 346 (stored in servo memory). For example, the servo processor 344 may be a dedicated processor circuit, and the servo logic component 346 may be firmware stored in RAM associated with the dedicated processor to provide dedicated computing resources for managing servo functions. The servo controller 342 can use the preamplifier 322 to receive the servo read signal read from the disk surface and provide it to the servo controller 342 via the channel 320. The servo controller 342 can provide the servo control signal to the servo interface controller 348 to provide control signals to multiple motors and / or actuators. For example, the servo controller 342 can provide control signals to the VCM and at least two actuators, as described above with respect to FIG.

[0067] In some configurations, the servo logic 346 may include logic for operating differently between the self-servo write mode 314 and the read / write mode of operation 316. For example, during the self-servo write mode 314, the servo logic 346 may implement the SSW VCM logic 346.1, the SSW head 1 logic 346.2, and the SSW head 2 logic 346.3. Each head may be configured to track a spiral reference pattern on its corresponding disk surface to obtain a tracks per inch (TPI) reference, with different heads / disks configured for different target TPI values. The SSW VCM logic 346.1 may include logic for determining VCM position adjustments based on two PESs received from different heads. For example, the VCM logic 346.1 may use one of the two heads as the master head and provide coarse positioning for tracking on the master head. In another example, the VCM logic 346.1 may use the average of the PESs from the two heads. SSW Head 1 Logic 346.2 and SSW Head 2 Logic 346.3 can use the milli-actuator and micro-actuator capabilities and corresponding direct current (DC) adjustments to provide DC drift compensation up to the travel distance of each milli-actuator and micro-actuator. SSW Head 1 Logic 346.2 and SSW Head 2 Logic 346.3 can include logic for using the PES from the respective heads and adjustments made by VCM Logic 346.1 to determine position adjustments for their respective actuators. For example, the micro-actuator of each head 346.5 can receive a position compensation signal based on offsetting the PES of that head based on an expected correction to the VCM position. In some configurations, a master or leader head can provide both DC and AC position control, and the other head can follow using AC position control. In some configurations, SSW Head 1 Logic 346.2 and SSW Head 2 Logic 346.3 can also include logic for managing the relationship between their respective positions. For example, if the travel distance limit of one of the actuators is reached, the leading head may pause writing for one revolution to allow the lagging head to catch up and get back into range of its actuator. In some configurations, DC may be rejected on both heads simultaneously. For example, N% of the track DC PES of one head may be subtracted from the PES of the other head to maintain equal and opposite DC PES on both heads. In other examples, the milli-actuators of each head 346.6 may receive a low frequency (including DC) position compensation signal to remove the PES offset of both heads based on half of the expected correction. The heads on the two sets move half of the expected amount in opposite directions, resulting in a combined offset removal.

[0068] Thermal drift logic 346.7 may include compensation logic for adjusting the positioning loop during self-servo writing to compensate for relative position changes between the parallel heads caused by thermal variations during the self-servo writing operation. As servo patterns are filled in parallel on two disk surfaces, the two heads and / or reference spirals may slowly drift relative to each other due to thermal expansion of the head stack and / or disk stack and motor. Thermal drift logic 346.7 can compensate for differences in head position from a nominal (starting or cold) value to a value that increases as the device heats up by injecting a compensation value into the actuator's position control. If the heads drift too far, the milli-actuators and micro-actuators may be unable to compensate for the head position difference due to limited actuator travel distance. In some configurations, thermal drift logic 346.7 may ignore a portion of the PES and gradually change the ignored amount (compensation value) during SSW operation. To limit the impact on track squeezing, the compensation value may vary slowly and may be a direct current (DC) or constant value known as a PESDC bleed at each radial position. During parallel fill, the radial position of any given servo track may depend on the thermal state and thermal history of the drive, as determined by the PES thermal compensation value.

[0069] Figure 4A parallel self-servo write process 400 for a data storage device having two head groups and corresponding preamplifier circuits is shown. The storage media stack includes disks 410 arranged in two groups around a spindle 412. The upper group includes disk surfaces 410.1.1-410.1.n, and the lower group includes disk surfaces 410.2.1-410.2.n. Each disk includes two storage media surfaces 414 for magnetically recording data on opposing (upper and lower) surfaces of the disk. A magnetic head 420 is actuated above each surface and is suspended by a corresponding suspension 424. Each suspension 424 may include a fixed portion attached to an arm 422 and a flexible portion extending toward the corresponding disk surface. In some configurations, an actuator 426 (such as a piezoelectric milliactuator) may be positioned at the junction of the fixed portion of the suspension portion and operable to lateral position the suspension 424. In some configurations, a second actuator 428 (such as a piezoelectric microactuator) can be positioned near the head 420 at the distal end of the suspension portion 424 and can be operated for further lateral positioning. Due to the size of the actuators and their relative distance from the heads, the arm actuator 426 of the suspension portion 424 of the movable arm 422 can have a larger travel distance or range than the head actuator 428 of the adjacent head 420, but the head actuator 428 can have higher precision for fine positioning of the read / write element at the desired position on the disk. In addition, in SSW mode, only the arm actuator 426 for the parallel write head group can be controlled to move in opposite directions, so that the arm actuator is used to correct DC and low-frequency offsets between the two heads. On the other hand, the head actuator 428 with a more limited range of movement is controlled separately by the group, so that the head actuator can correct not only low-frequency errors including offsets, but also high-frequency errors to accurately place the servo pattern at the desired position. The heads 420 and corresponding suspensions 424 are similarly arranged in groups. An upper group may include heads 420.1-420.n and their corresponding arms 422, and a lower group may include heads 420.n+1-420.n+n. Each group of heads is electrically connected to a corresponding preamplifier circuit, such as preamplifier 432.1 for the upper head group and preamplifier 432.2 for the lower head group.

[0070] During parallel self-servo writing, the control circuitry uses a reference spiral 416 from the storage medium surface to provide position information for writing servo sectors or servo wedges. Reference spiral 416 can be a previously written spiral reference pattern and is present on each disk surface when writing of the servo sectors is initiated. Heads 420.1-420.n can be used to write servo sectors to the upper set of disks in parallel with heads 420.n+1-420.n+n writing servo sectors to the lower set. Due to the disk stack and head stack structure, it is preferable to use head pairs that minimize the vertical distance between the heads for parallel writing. In some configurations, write pairs 440.1-440.n are selected to pair writes with heads / surfaces in the same sequential position within each head set. For example, head 420.1 writing to surface 414.1 will be paired with head 420.n+1 writing to surface 414.n+1 as write pair 440.1. Each surface can be written sequentially downward to head 420.n writing to surface 414.n and head 420.n+n writing to surface 414.n+n as write pair 440.n. In some configurations, write pairs 440 can be selected in a different order rather than from top to bottom. Other pairings are also possible, such as the closest pair to the furthest pair, or pairing the top surface heads from one group with the bottom surface heads from another group. As each pair is selected, servo wedges 442.1-442.x are written to both disk surfaces simultaneously and sequentially. In some configurations, while the preamplifiers are wired to their respective head groups, adjacent heads can be wired to alternate preamplifiers to minimize read / write crosstalk, thereby keeping parallel-filled write pairs two heads apart, bringing them closer together and reducing cross-head motion.

[0071] like 5A to 5D As shown, many example preamplifier configurations and adjacent circuits can be used for parallel self-servo writing. Figure 5AIn the example configuration 502, preamplifier circuits 510.1 and 510.2 are included. Preamplifier circuit 510.1 is electrically connected to a set of TDMR heads 512.1-512.n. Each TDMR head 512 includes two read elements 514 electrically connected to the input interface of a corresponding sensor amplifier 516. For example, read elements 514.1.1 and 514.1.2 are connected to sensor amplifiers 516.1.1 and 516.1.2, respectively, read elements 514.2.1 and 514.2.2 are connected to sensor amplifiers 516.2.1 and 516.2.2, respectively, and read elements 514.3.1 and 514.3.2 are connected to sensor amplifiers 516.n.1 and 516.n.2, respectively. Preamplifier circuit 510.2 is electrically connected to another set of TDMR heads 512.n+1-512.nn. Read elements 514.n+1.1 and 514.n+1.2 are connected to sensor amplifiers 516.n+1.1, 516.nn2, respectively, read elements 514.n+2.1 and 514.n+2.2 are connected to sensor amplifiers 516.n+2.1 and 516.n+2.2, respectively, and read elements 514.n+n.1 and 514.n+n.2 are connected to sensor amplifiers 516.n+n.1 and 516.n+n.2, respectively.

[0072] In preamplifier circuits 510.1 and 510.2, sensor amplifiers 516 are coupled in pairs to A and B switching circuits 518, which are configured to switch amplified read signals from corresponding read elements for connection to opposing multiplexers 520. For example, the amplified read signals from sensor amplifiers 516.1.1 and 516.1.2 are switched via switching circuit 518.1 to connect the read signal from sensor amplifier 516.1.1 to multiplexer 520.2, and the read signal from sensor amplifier 516.1.2 to multiplexer 520.1. A similar configuration operates for sensor amplifiers 516.2.1 and 516.2.2 via switching circuit 518.2, and for sensor amplifiers 516.n.1 and 516.n.2 via switching circuit 518.n. Preamplifier circuit 510.2 is similarly configured for sensor amplifiers 516.n+1.1 and 516.n+1.2 by swapping circuit 518.n+1, for sensor amplifiers 516.n+2.1 and 516.n+2.2 by swapping circuit 518.n+2, and for sensor amplifiers 516.n+n1 and 516.nn2 by swapping circuit 518.n+n.

[0073] Multiplexer 520 can be a circuit configured to select among the amplified read signals to selectively connect these read signals to a read driver 522.1 that interfaces with a read channel 532 of channel 530. In some configurations, multiplexer 520 can select a target head and a corresponding read sensor based on a control signal received at a corresponding control signal input 524. During a data read / write operation, a pair of read signals from a pair of read elements in a target head can be selected by multiplexers 520.1 and 520.2 and passed to read drivers 522.1 and 522.2, respectively. During a self-servo write operation, only one of multiplexers 520.1 and 520.2 can be enabled, and a single read signal from the target head can be selected to be provided to one of read drivers 522.1 or 522.2. Preamplifier 510.2 can be similarly configured such that preamplifiers 510.1 and 510.2 can be alternately activated as needed to read from both read elements of a target head in its head stack. During a self-servo write operation, only one of multiplexers 520.4 or 520.3 can be enabled, and a single read signal from the parallel target heads can be selected to be provided to one of read drivers 522.4 or 522.3. The corresponding read driver 522 associated with the active multiplexer can provide the amplified read signal via an interface to a channel input 532 in read channel 530. In the example shown, during a self-servo write operation, multiplexer 520.1 provides an amplified read signal from a target head connected to preamplifier 510.1 to a read driver 522.1 to provide a read signal 540.1 to a read channel input 532.1, and multiplexer 520.4 provides an amplified read signal from a target head connected to preamplifier 510.2 to a read driver 522.4 to provide a parallel read signal 540.2 to a read channel input 532.2.

[0074] During a self-servo write operation, the read channel 530 can be configured to decouple the received read signals 540.1 and 540.2 and process them separately to determine their respective servo position information and PES. For example, the analog front end of the channel 530 can include separate variable gain amplifiers (VGAs) configured to receive the pair of read signals via read channel inputs 532.1 and 532.2 and direct the pair of read signals through separate read processing channels to extract servo information from the respective read signals. In some configurations, the read channel 530 can be similar to Figure 3 The read / write channel 320 in is configured.

[0075] In some configurations, head selection and preamplifier control may be managed by controller 534, such as with Figure 3 302 in the controller 534 is similarly configured as a hardware controller. The controller 534 can generate preamplifier control signals and send them to control signal inputs 524.1 and 524.2 for controlling preamplifier circuits 510.1 and 510.2 respectively. During read / write operations, the controller 534 can send control signals to the active preamplifier connected to the target head to perform read / write operations, and when the other preamplifier is active, the lack of a control signal to the other preamplifier can effectively disable the preamplifier from performing read / write. During parallel self-servo write operations, both preamplifiers 510 may need to be active and receive parameters for selecting the target head, read sensor, and read path (multiplexer to read driver to read channel input). For example, the controller 534 can be configured to generate a pair of preamplifier control signals to simultaneously send to control signal inputs 524.1 and 524.2 to set corresponding preamplifier parameters, but the preamplifier parameters can be different for each preamplifier. In some configurations, the controller 534 may include local logic components for generating parallel control signals to control the preamplifier circuits 510 . 1 and 510 . 2 in parallel during a self-servo write operation.

[0076] Figure 5B An alternative example of a configuration 504 using preamplifier circuits 510.1 and 510.2 is shown. The preamplifier circuits 510.1 and 510.2, their corresponding heads 512, and channels 530 are shown in FIG. Figure 5AThe configuration is described. In this example, preamplifier circuits 510.1 and 510.2 can operate in a read / write mode of operation. When a target head is selected in a head group including heads 512.1-512.n, multiplexers 520.1 and 520.2 can select an amplified read signal from a pair of read sensors on that head and direct the read signal to read drivers 522.1 and 522.2. TDMR read signals 542.1 and 542.2 can be sent to channel inputs 532.1 and 532.2 and corresponding coupled TDMR read channels for processing position information (and stored data) from these signals. When a target head is selected in a head group including heads 512.n+1-512.n+n, multiplexers 520.3 and 520.4 can select an amplified read signal from a pair of read sensors on that head and direct the read signal to read drivers 522.3 and 522.4. TDMR read signals 542.3 and 542.4 may be sent to channel inputs 532.1 and 532.2 and corresponding coupled TDMR read channels for processing position information (and stored data) from these signals.

[0077] In configuration 504, an alternative controller 536 is shown that does not include local generation of parallel preamplifier control signals for control signal inputs 524.1 and 524.2. Controller 536 may be used with Figure 3 Controller 302 in is similarly configured. Controller 536 may include control logic 550, which may include firmware instructions for selectively enabling control signal generator 552 to generate data read / write operation control signals, which are selectively sent to control signal input 524.1 (when preamplifier 510.1 is active) or control signal input 524.2 (when preamplifier 510.2 is active). Control logic 550 may include additional shunt signal generator 554 to generate additional shunt signals to initialize selection logic 556 to generate parallel preamplifier control signals to control signal inputs 524.1 and 524.2. Figure 5D A further description of example selection logic circuit 580 is provided.

[0078] Figure 5CAn alternative example configuration 506 for parallel self-servo writing using non-TDMR heads and preamplifiers is shown. Preamplifier circuits 560.1 and 560.2 are configured with a single sensor amplifier 566 to a single read sensor 564 on each head 562. For example, preamplifier circuit 560.1 supports a head group including heads 562.1-562.n and receives read signals from corresponding read sensors 564.1-564.n via sensor amplifiers 566.1-566.n. Preamplifier circuit 560.2 supports another head group including heads 562.n+1-562.n+n and receives read signals from corresponding read sensors 564.n+1-564.n+n via sensor amplifiers 566.n+n-566.n+n. Each of the preamplifier circuits 560.1 and 560.2 includes only a single multiplexer 570 and a read driver 572 for selecting a read signal from a target head and providing the read signal to a read channel input 582 of the channel 580. For example, each sensor amplifier 566.1-566.n is connected to the multiplexer 570.1 for selective connection to the read driver 572.1, and each sensor amplifier 566.n+1-566.n is connected to the multiplexer 570.2 for selective connection to the read driver 572.2. The preamplifier circuits 560.1 and 560.2 may also include control signal inputs 574.1 and 574.2, respectively, for receiving preamplifier control signals to select an active preamplifier and head for read / write operations and to activate a preamplifier and select a target head for parallel self-servo writing. During a read / write mode of operation, read drivers 572.1 and 572.2 can alternately send read signals 544.1 and 544.2 to corresponding read channel inputs 582.1 and 582.2 for processing by the corresponding read channels. During a parallel self-servo write mode, read drivers 572.1 and 572.2 can send read signals 544.1 and 544.2 in parallel to corresponding read channel inputs 582.1 and 582.2 for processing by the decoupled read channels to extract position information. Additional routing for the parallel read signals can be provided on a flex circuit (not shown) between read driver 572 and read channel input 582.

[0079] In configuration 506, channel 580 includes separate read channel inputs 582.1 and 582.2, similar to Figure 5A and Figure 5B The TDMR read channel in the controller 584 can be similar to Figure 5BThe controller 536 in FIG. 5 is configured to include similar control logic 550 interfaced with selection logic 556 for controlling the two preamplifier modes via control signal inputs 574.1 and 574.2. We note here that configuration 506 is a non-TDMR version of configuration 504. For the sake of brevity, the non-TDMR version of configuration 502 is omitted. A controller similar to 534 can be used to change Figure 5C Controller 584 in to create a non-TDMR version of configuration 502.

[0080] Figure 5D An example selection logic circuit 590 is shown, such as that which may be used for configurations 504 and 506. Example configuration 508 is in the context of a configuration similar to configuration 504. Preamplifier circuits 510.1 and 510.2 are controlled by corresponding control signal inputs 524.1 and 524.2. Controller 536 includes a control signal generator 552 and a shunt signal generator 554. In the configuration shown, control signal generator 552 generates a read / write operation (single active preamplifier and head) control signal, such as a serial enable control signal, and provides the control signal to selection logic 580, and shunt signal generator 554 can generate a pair of control signals for splitting the preamplifier control signal and providing the selected control signal in parallel to corresponding control signal inputs 524.1 and 524.2. For example, a pair of signals generated by shunt signal generator 554 may include a head select signal for preamplifier circuit 510.2, such as a second serial enable control signal, and a shunt signal select signal for directing control signals from control signal generator 552 in parallel to preamplifier circuit 510.1. The control signals generated by control signal generator 552 and shunt signal generator 554 may be received by selection logic 580. In some configurations, selection logic circuit 590 may include hardware logic added to controller 536 or provided as a separate device or as part of a flex circuit between controller 536 and preamplifier circuits 510.1 and 510.2.

[0081] The selection logic circuit 590 may include a pair of NOT gates 592.1 and 592.2 for control signals from the shunt signal generator 554. NOT gate 592 may control the selection of control signals sent to gates 594.1 and 594.2. OR gate 594.1 may evaluate the pair of NOT gate signals from 592.1 and 592.2, and OR gate 594.2 may evaluate the select signal from preamplifier circuit 510.2 with the signal from NOT gate 592.2. AND gates 596.1 and 596.2 may determine the control signals selectively sent to control signal inputs 524.1 and 524.2, respectively. AND gates 596.1 and 596.2 may provide a single preamplifier / head select control signal from control signal generator 552 during read / write operations, or provide modified control signals based on gates 594.1 and 594.2, respectively, during parallel self-servo write operations. Other configurations of the selection logic circuit 590 are possible.

[0082] Figure 6A An example VCM compensator logic 600 is shown that can determine a total VCM position adjustment 622 based on each head position measurement 626. The reference position 610 can be subtracted from the first head position measurement 626.1 at a summing node 612.1 to form a first head PES 616.1. Similarly, the reference position 610 can be subtracted from the second head position measurement 626.2 at a summing node 612.2 to form a second head PES 616.2. Each head PES 616 can be added together at a summing node 614 and divided by 2 by a gain 618 to obtain an average PES, which can then be processed by a VCM compensator 620 to obtain a total VCM position adjustment 622. The total VCM position adjustment 622 can be applied to the motor control circuit to simultaneously change the first head position 626.1 and the second head position 626.2 via the VCM and first arm dynamics system 624.1 and the VCM and second arm dynamics system 624.2, respectively.

[0083] Figure 6BAnother example compensator logic component 602 is shown that can determine a per-head actuator compensation value 632 and a total VCM position adjustment 648 based on a per-head position measurement 654. The reference position 610 can be subtracted from the first head position measurement 654.1 at a summing node 612.1 to form a first head PES 616.1. The first head PES 616.1 can be processed by a first actuator compensator 630.1 to produce a first actuator compensation value 632.1. The first actuator compensation value 632.1 can be processed by a first actuator model 636.1 to produce an estimated first actuator position, which can then be subtracted from the first head PES 616.1 at a summing node 638.1 to produce a first head decoupling PES 640.1. Simultaneously, the reference position 610 can be subtracted from the second head position measurement 654.2 at a summing node 612.2 to form a second head PES 616.2. The second head PES 616.2 can be processed by a second actuator compensator 630.2 to produce a second actuator compensation value 632.2. The second actuator compensation value 632.2 can be processed by the second actuator model 636.2 to produce an estimated second actuator position, which can then be subtracted from the second head PES 616.2 at a summing node 638.2 to produce a second head decoupling PES 640.2; the first head decoupling PES 640.1 and the second head decoupling PES 640.2 can be added at a summing node 642, divided by 2, and passed through a VCM compensator to obtain a total VCM position adjustment 648. The total VCM position adjustment 648 and the first actuator compensation value 632.1 can be applied to the motor control circuit and the first actuator, respectively, to change the first head position 654.1 via superposition of the VCM and the first arm dynamics system 650.1 and the first actuator dynamics system 634.1. At the same time, a second actuator compensation value 632.2 may be applied to the second actuator to change the second head position 654.2 via the superposition of the VCM and the second arm dynamics system 650.2 and the second actuator dynamics system 634.2.

[0084] like Figure 7 As shown, the control circuit 300 can be used according to the Figures 2A to 6B The example method of parallel self-servo writing performed by the various components described herein operates according to the method 700 illustrated in blocks 710 through 736 .

[0085] At blocks 710 and 712, a first head and a second head are actuated above respective surfaces of a storage medium. For example, a controller may be responsible for controlling the motion of two heads selected from different head groups in a data storage device, wherein the first head and the second head are suspended on an arm above the surface of the storage medium and positioned by a combination of at least one VCM and at least one actuator on the arm supporting each head.

[0086] At blocks 714 and 716, different heads and corresponding read elements are selected for parallel operation. For example, the controller may send control signals to two different preamplifier circuits to identify the first and second target heads and the read sensors to be used on these heads, which may include selecting one of the two read elements in each TDMR head.

[0087] Read signals may be generated from the selected read heads and elements at blocks 718 and 720. For example, a preamplifier may initiate a read voltage to the target heads and read elements and receive sensor read signals generated by the first and second target heads and read elements.

[0088] At block 722, the read signals may be received in parallel by corresponding preamplifier circuits. For example, a channel associated with a controller may include two read channel inputs connected to the preamplifier circuits and receive the read signals from each preamplifier in parallel.

[0089] At blocks 724 and 726, a PES value may be determined for each head based on the received read signal. For example, the decoupling operation of the channels may determine separate first and second PES values ​​for the first and second heads.

[0090] At block 728, the head stack may be positioned for the two heads. For example, the controller may determine a VCM adjustment based on the two PES values ​​to move the head stack including the head group and the first and second target heads.

[0091] At blocks 730 and 732, the positions of the two heads relative to the head stack may be controlled. For example, a servo controller may provide head-specific actuator adjustment values ​​to actuators on corresponding arms of the first and second heads.

[0092] Servo tracks may be written to both storage medium surfaces in parallel at blocks 734 and 736. For example, the controller may send servo pattern write signals to both the first target head and the second target head through their respective preamplifiers in response to the positions of the heads relative to the SSW reference spiral being within corresponding error tolerances.

[0093] like Figure 8As shown, the control circuit 300 can be used according to the Figures 2A to 6B An example method of parallel self-servo writing by an additional actuator controller of various components is described, operating according to the method 800 illustrated in blocks 810 through 826.

[0094] At block 810, a self-servo write reference spiral is written to a storage medium. For example, the controller may pre-write a reference spiral to each storage medium surface of a data storage device.

[0095] At block 812, a pair of heads connected through different preamplifier circuits are selected. For example, the controller may select heads from each head group, where each head group has its own preamplifier.

[0096] At block 814, the sequential positions of the heads connected through the different preamplifiers may be determined. For example, the controller may be configured with sequential position information for the configuration of the heads in each head group and may use these sequential positions at block 812 to select a write pair having one head from each group according to a desired sequence for parallel self-servo writing, such as selecting heads having the same sequential position at block 812.

[0097] At block 816, the overall position of the heads may be controlled by providing VCM control signals to the VCM. For example, the controller may determine position information based on a reference spiral for each head and use the VCM to determine adjustments for moving the head stack so that both heads are approximately positioned above the target servo write position.

[0098] At block 818, a first actuator controller may be electrically connected to the first head actuator. For example, the controller may generate a first actuator control signal for positioning the actuator on an arm supporting one of the selected heads and enable a control path between the actuator controller and the arm actuator for the head.

[0099] At block 820, a second actuator controller may be electrically connected to the second head actuator. For example, the controller may generate a second actuator control signal for positioning the actuator on an arm supporting another of the selected heads and enable a control path between the actuator controller and the arm actuator for the other head.

[0100] At block 822, a third actuator controller may be electrically connected to the arm actuator for each of the magnetic heads. For example, each arm may include two actuators, and one actuator on each arm may be controlled on each arm to provide differential positioning between the two arms, while the third actuator controller may be connected to the other actuators on the arms and provide a common signal to the other actuators to maintain the actuators in a constant (relative) position.

[0101] At block 824, the actuator control signals may be sent in parallel. For example, the controller may send the actuator control signals simultaneously through the first actuator controller, the second actuator controller, and the third actuator controller. Alternatively, the actuator control signals may be sent one after the other.

[0102] Servo tracks may be written in parallel on the different storage medium surfaces at block 826. For example, based on the positioning provided by the three actuator control signals and the VCM control signal, the controller may send servo write signals to the pair of write heads to write corresponding servo sectors defining corresponding servo tracks on the two different storage medium surfaces corresponding to the selected heads.

[0103] like Figure 9 As shown, in use Figures 2A to 6B After the various components described complete self-servo writing, control circuit 300 may operate according to an example method of data read / write operation, namely, method 900 as illustrated by blocks 910 through 926. Blocks below line 902 may operate during a data read / write mode of operation.

[0104] Servo writing may be completed at block 910. For example, the controller may complete self-servo writing such that a full set of servo sectors defining production servo tracks on one or more regions of the storage medium surface is complete and may support normal read / write servo operations based on the servo format.

[0105] At block 912, the actuator control circuitry may be switched for TDMR read / write. For example, the controller may activate a switch in the servo interface controller to change the actuator control path so that two actuator controllers will control two actuators on the arm of the target head.

[0106] At block 914, a head may be selected for a read / write operation. For example, in response to a host read, write, or other data operation, the controller may determine a head to write to or read from a target location on a corresponding storage medium surface.

[0107] At blocks 916 and 918, the first actuator controller may be electrically connected to the selected head actuator, and the second actuator controller may be electrically connected to the selected arm actuator. For example, the controller may connect control paths from the first actuator controller and the second actuator controller to the corresponding head and arm actuator on the arm supporting the head selected at block 914.

[0108] At block 920, a servo read signal may be received from the selected head through a corresponding preamplifier. For example, the controller may initiate a servo read operation of the selected head and receive the read signal into a read channel in a channel circuit through a corresponding preamplifier.

[0109] At block 922, a position error signal may be determined based on the servo component of the read signal.For example, the channel circuit may determine the position error signal based on the read signal from the selected head.

[0110] At block 924, control signals may be determined based on the position error signal.For example, the servo controller may determine separate control signals for the VCM, arm actuator, and head actuator to position the selected head for a read or write operation.

[0111] At block 926, control signals may be sent to the corresponding VCM, arm actuator, and head actuator to position the selected head for a read or write operation. For example, a servo controller may send corresponding control signals to the VCM and the suspension and head actuator for the target head.

[0112] like Figure 10 As shown, the control circuit 300 can be used according to the Figures 2A to 6B The example method of describing various components positioning a head for parallel self-servo writing operates according to the method 1000 illustrated in blocks 1010 through 1038 .

[0113] At blocks 1010 and 1012, read signals may be received from a pair of magnetic heads in parallel. For example, a servo write pair of first and second magnetic heads connected through different preamplifier circuits may generate first and second read signals from reference spirals on their respective storage medium surfaces.

[0114] A position error signal may be determined from each read signal at blocks 1014 and 1016. For example, the decoupled read channels may determine separate first and second PESs from the first and second read signals.

[0115] At blocks 1018 and 1020, a first compensation value may be determined for the first PES and a second compensation value may be determined for the second PES. For example, the servo controller may determine the compensation value for the PES of another head.

[0116] At blocks 1022 and 1024, decoupled PES values ​​may be determined for each head. For example, the servo controller may apply the compensation values ​​determined at blocks 1014 and 1016 to decouple the first and second PES signals.

[0117] The decoupled PES values ​​may be averaged at block 1026. For example, the first decoupled PES value and the second decoupled PES value may be added and then divided by two to determine an average decoupled PES value.

[0118] A total stack compensation value or head stack compensation value may be determined at block 1028. For example, based on the average decoupled PES, the servo controller may determine a VCM compensation value associated with changing the position of the VCM and thereby determine the total movement of the head stack including the two heads.

[0119] Different adjustment values ​​may be applied to the actuator and VCM on the arm of each head at blocks 1030, 1032, and 1034. For example, the servo controller may generate a first actuator adjustment value, a second actuator adjustment value, and a VCM adjustment value and send them to the servo interface to send corresponding control signals to the actuator and VCM.

[0120] At blocks 1036 and 1038, the two heads may be actuated and positioned over their respective storage medium surfaces for parallel self-servo writing. For example, a combination of VCM actuation and actuator actuation on the arms of the first and second heads may change the positions of the two heads to continue the self-servo writing operation.

[0121] like Figure 11 As shown, the control circuit 300 can be used according to the Figures 2A to 6B The various components described herein operate according to an example method 1100 illustrated in blocks 1110 through 1120 to compensate for different track positions between two heads in parallel self-servo writing.

[0122] At blocks 1110 and 1112, sequential positions of the two heads may be determined based on their TPIs. For example, when a controller manages self-servo writing of each servo track at target (possibly different) first and second TPIs for a first head and a second head in a write pair, the controller may determine the number of sequential passes (number of disk revolutions) and servo tracks written for each of the heads, as well as the head movement required for the next sequential servo track position.

[0123] At block 1114, the current distance between the heads may be determined based on the PES. For example, the controller may calculate the relative position of the heads relative to each other based on the VCM position, their corresponding decoupling PES values, and the adjustment value to be applied for the next rotation.

[0124] The next sequential position may be compared to a distance threshold at block 1116. For example, the controller may compare the relative position of the head and its next sequential position to determine whether they are within a distance threshold corresponding to a range of travel of an actuator for controlling the position of the head relative to the position of the VCM.

[0125] It may be determined that the difference is greater than a distance threshold at block 1118. For example, the controller may determine, based on the comparison to the travel distance threshold, that the next sequential track of one or both heads will be out of travel in the opposite direction and that the milli-actuator or micro-actuator position will allow writing of two tracks in parallel.

[0126] At block 1120, self-servo writing of the head having the larger sequential position (in the direction in which the servo writing operation is proceeding) may be paused for one or more revolutions. For example, the controller may pause the servo writing operation of the leading head for a series of complete revolutions while continuing to write using the lagging head until the distance between the heads decreases below a distance threshold.

[0127] like Figure 12 As shown, the control circuit 300 can be used according to the Figures 2A to 6B The various components described herein manage an example method of managing seams between adjacent servo regions having different frequencies, ie, operating according to the method 1200 illustrated in blocks 1210 through 1218 .

[0128] At block 1210, a jump distance may be determined based on head parameters. For example, the controller may be configured with reader / writer geometry parameters for each head and use these parameters to determine the jump distance based on the writer width difference and the reader / writer offset.

[0129] At block 1212, the servo region may be written at a first TPI. For example, each head may be writing a servo track of a first region at a corresponding servo TPI value.

[0130] At block 1214, a seam track between adjacent regions may be determined. For example, the controller may determine that the head is approaching a seam track and / or a butterfly seam track between a first servo region and a next or second servo region for servo writing in different directions.

[0131] The head may be positioned by the jump distance between written regions at block 1216. For example, in response to reaching a seam track, the jump distance may be applied to the arm / actuator target position for the next sequential servo track, such as the first track at the next servo TPI.

[0132] At block 1218, a second servo region may be written at a second servo TPI. For example, the next servo region may be written at a different servo TPI than the previous servo region. Note that during parallel self-servo writing, the timing of region boundaries and seam jumps may be different between the two heads.

[0133] At block 1220, a zone boundary offset can be determined for each zone boundary and used in the operation of the servo pattern. For example, the controller can measure the actual jump distance on each surface to operate with reference to the product servo pattern: the head can be commanded to seek across the servo zone boundary at a known speed. At points where the track number jumps due to adjacent servo zones having discontinuous servo track numbers, artificial velocity jumps will appear if the track number offset is not added. In other words, the track number offset that produces continuous velocity when crossing the zone boundary without changing the control command is due to track number offsets caused by thermal drift, head width variations due to using different edges of the writer, and or different reader-to-writer offsets at different servo frequencies. Note that when zone boundaries have overlapping patterns, the wedge time jump between the two servo zones also needs to be considered when calculating the head velocity.

[0134] like Figure 13 As shown, the control circuit 300 can be used according to the Figures 2A to 6B An example method in which various components are described to manage thermal creep during parallel self-servo writing operates according to the method 1300 illustrated in blocks 1310 to 1320 .

[0135] At block 1310, a thermal offset value may be determined. For example, the controller may be configured with an experimentally determined thermal model based on relative offsets between write pairs caused by thermal variations in the head and / or disk stack during operation of the data storage device, and more specifically, during a cycle of a self-servo write operation. The thermal model may determine the thermal offset value based on time and / or temperature sensor values ​​determined by the controller.

[0136] At block 1312, the position error signal may be modified based on the thermal offset value. For example, the servo controller may apply the thermal offset value to the PES-based adjustment values ​​determined for the VCM and the actuator.

[0137] At block 1314, changes in thermal gain may be determined during the self-servo write operation. For example, the thermal gain (or loss) may be modeled using a thermal model for the data storage device based on the distance between the two heads passing through the parallel SSW, the spindle motor design, the elapsed operating time, and / or varying temperature sensor inputs.

[0138] At block 1316, the thermal offset value may be varied based on the change in thermal gain. For example, the thermal model may be a transfer function that determines the thermal offset value based on operating time and / or temperature sensor input to compensate for the varying thermal loads and consequent geometric changes that affect the relative position of the write head pair. The servo controller may use the varying thermal offset value to continuously modify the position error signal and / or the resulting motor / actuator adjustment value.

[0139] The servo tracks may be written to the storage medium surface at block 1318. For example, the controller may use a write head pair to write their respective servo patterns to their storage medium surfaces based on thermally compensated position control.

[0140] An erase band may be written at block 1320. For example, at each zone seam and / or ID and OD of the servo pattern, the controller may cause the write head to write an erase band to remove any residual signal from a previously written servo pattern or reference spiral.

[0141] like Figure 14A As shown, the control circuit 300 can be used according to Figures 2A to 6B The various components described herein operate in accordance with an example method 1400 illustrated in blocks 1410 through 1438 for controlling multiple actuators for each head during self-servo write and data read / write operations.

[0142] At block 1410, motor control signals may be generated for the VCM. For example, the servo interface circuit may include a DAC to receive digital VCM control signals from a servo controller and convert them to analog VCM control information provided to the VCM.

[0143] A first actuator control signal may be generated at block 1412. For example, the servo interface circuit may include a first actuator DAC to receive the first digital actuator control signal from the servo controller and convert it into an analog actuator control signal that is provided to the selected piezoelectric actuator on the selected arm for the selected head.

[0144] A second actuator control signal may be generated at block 1414. For example, the servo interface circuit may include a second actuator DAC to receive the second digital actuator control signal from the servo controller and convert it into an analog actuator control signal that is provided to another selected piezoelectric actuator on the selected arm for the selected head.

[0145] At block 1416, the servo interface controller may switch between the first mode and the second mode.For example, the controller may select the operating mode of the servo interface controller depending on whether a data read / write or self-servo write operation is being initiated.

[0146] At block 1420, a first mode for data read / write operations may be initiated. For example, the controller may select the first mode after completing a self-servo write operation.

[0147] At block 1422, the first bi-phase driver circuit can be selectively connected to the first actuator in a control signal path. For example, the servo interface circuit can be switched to connect the first actuator DAC to the control signal path through the first bi-phase driver circuit to the first actuator on the arm of the selected head.

[0148] At block 1424, the second actuator DAC may be selectively connected to a control signal path to another actuator on the same arm. For example, the servo interface circuit may be switched to connect the second actuator DAC to the control signal path of a second actuator on the arm for the selected head.

[0149] At blocks 1426 and 1428, a first actuator control signal may be used to control a first actuator, and a second actuator control signal may be used to control a second actuator on the same arm to position the magnetic head on the arm. For example, each arm may include a milliactuator and a microactuator, and the two actuator control signals may control the actuators in parallel to position the magnetic head over a desired track location for read / write operations.

[0150] A second mode for data self-servo write operations may be initiated at block 1430. For example, the controller may select the second mode during configuration and testing of the data storage device to write a production servo pattern to the storage medium surface.

[0151] At block 1432, the first bi-phase driver circuit can be selectively connected to the first actuator in a control signal path. For example, the servo interface circuit can be switched to connect the first actuator DAC through the first bi-phase driver circuit to the control signal path to the first actuator on the arm of the first selected head in one of the headstacks connected to the corresponding preamplifier.

[0152] At block 1434, the second bi-phase driver circuit can be selectively connected to a control signal path to another actuator on another arm. For example, the servo interface circuit can be switched to connect the second actuator DAC through the second bi-phase driver circuit to a control signal path for an actuator on an arm of a different selected head from another head stack connected to a different preamplifier.

[0153] At blocks 1436 and 1438, the actuator on one arm may be controlled using a first actuator control signal, and the actuator on the other arm may be controlled using a second actuator control signal to position the two heads in parallel. For example, each arm may include a milli-actuator and a micro-actuator, and the two actuator control signals may control the micro-actuators on the two arms in parallel to position the heads over desired servo write positions for servo write operations.

[0154] like Figure 14B As shown, the control circuit 300 can also be used according to the Figures 2A to 6B The various components described herein operate in accordance with an example method for controlling multiple actuators for each head during self-servo write and data read / write operations, as illustrated in blocks 1440 through 1456. The method 1402 supplements the method 1400 in a configuration that includes a third actuator DAC in the servo interface circuit. Blocks 1416, 1420, and 1430 are repeated from method 1400, and the remaining blocks in method 1402 may be operated in conjunction with the remaining blocks in method 1400.

[0155] At block 1440, a third actuator control signal may be generated. For example, the servo interface circuit may include a third actuator DAC for receiving the third digital actuator control signal from the servo controller and converting it to an analog actuator control signal provided to another selected piezoelectric actuator.

[0156] At block 1442, a third actuator DAC can be selectively connected to an actuator in a control signal path that is connected to the second actuator control signal. For example, the third actuator DAC can provide an analog control signal to one branch for controlling the second actuator during a head switching operation.

[0157] At block 1444, the demultiplexer in the control signal path is selectively connected to the actuator, which is connected to the second actuator control signal. For example, during a head switching operation, the third actuator DAC can receive the same digital control signal from the milliactuator DAC via the digital signal processor to provide one branch of the milliactuator control signal, while the milliactuator DAC signal passes through the demultiplexer to provide the other branch of the milliactuator control signal.

[0158] At block 1446, the actuator may be controlled using the second actuator control signal and the third actuator control signal. For example, a dual-channel milli-actuator driver may receive an external analog control signal from the third actuator DAC and an internal analog control signal from the second actuator DAC to position the target head during a data read / write mode of operation.

[0159] At block 1452, the third actuator DAC can be selectively connected to a control signal path for one or more actuators that are not controlled by the first and second actuator DACs. For example, during a self-servo write operation, the third actuator DAC can be connected to two milliactuator channels, where the milliactuators of the same parallel SSW pair are connected to move in opposite directions when actuated, thereby providing relative position adjustment capabilities, such as low-frequency (including DC) position adjustment, while the milliactuator DAC is connected to the microactuator of the second head in the write pair.

[0160] At block 1454, the third actuator control signal can bypass the demultiplexer. For example, both the third actuator control signal from the third actuator DAC and the second actuator control signal from the second actuator DAC can be switched to bypass the demultiplexer because the third actuator control signal and the second actuator control signal provide separate signals to their respective connected actuators. The digital signal processor can similarly be disabled during the parallel self-servo write operation.

[0161] At block 1456, a third actuator control signal may be used to control one or more other actuators on both arms. For example, a third actuator DAC may provide a third analog actuator control signal to the milliactuator on each arm of the selected write pair via two milliactuator channels.

[0162] like Figure 15A As shown, the control circuit 300 can be used according to the Figures 2A to 6B The various components described herein control the preamplifier circuit during self-servo writing, i.e., the method 1500 operates according to blocks 1510 to 1538. At 1502, the method 1500 may pass the operation to Figure 15B Method 1504 in.

[0163] A selection between a self-servo write mode and a read / write mode of operation may be determined at block 1510. For example, a controller may select a servo mode of operation for a data storage device depending on whether a data read / write or self-servo write operation is being initiated.

[0164] At block 1512, a self-servo write mode may be selected. For example, a controller may select the self-servo write mode during manufacturing and testing of a data storage device to populate a servo pattern on a set of storage medium surfaces.

[0165] At block 1514, a first head connected through a first preamplifier circuit and a second head connected through a second preamplifier circuit may be identified. For example, the controller may select a write pair from two or more head groups supported by separate preamplifier circuits.

[0166] At block 1516, a pair of control signals may be generated for the preamplifier circuits.For example, the controller may generate sensor enable signals for two preamplifier circuits connected to the target head.

[0167] At blocks 1520 and 1530, the first and second control signals may be received by their respective preamplifier circuits. For example, a first preamplifier circuit for a first target head may receive the first control signal in parallel with a second preamplifier circuit receiving the second control signal.

[0168] At blocks 1522 and 1532, read signals may be generated from the target heads. For example, a first head may receive a read voltage from a first preamplifier circuit and return a first analog read signal to the preamplifier circuit, and a second head may receive a read voltage from a second preamplifier circuit and return a second analog read signal to the preamplifier circuit.

[0169] At blocks 1524 and 1534, the read signals from the target head may be received by their respective preamplifier circuits. For example, a first preamplifier circuit may receive a first analog read signal to a corresponding sensor amplifier input, and a second preamplifier circuit may receive a second analog read signal to a corresponding sensor amplifier input.

[0170] At blocks 1526 and 1536, a read signal path may be selected using multiplexer circuits in corresponding preamplifier circuits. For example, a first preamplifier circuit may activate a first multiplexer to select one of the read sensor signals from the target head and connect it to a corresponding read driver for that read channel, and a second preamplifier circuit may activate another multiplexer circuit to select one of the read sensor signals from another target head and connect it to a corresponding read driver for that other read channel.

[0171] The selected read signals may be sent to corresponding channel inputs on the read channel circuitry at blocks 1528 and 1538. For example, a first preamplifier may send its selected read sensor signal to one read channel input, and a second preamplifier may send its selected read sensor signal to another read channel input.

[0172] like Figure 15B As shown, the control circuit 300 can be used according to the Figures 2A to 6B The various components described herein may control an example method of a preamplifier circuit during data read / write operations, namely operating according to method 1504 as illustrated in blocks 1550 through 1570 .

[0173] At block 1550, a data read / write mode of operation may be selected. For example, after self-servo writing is complete and a functional servo pattern has been established on the surface of the storage medium, the controller may select a data read / write mode of operation. This may include ongoing testing of data formats, read / write channel settings, and other configuration operations prior to production use of the data storage device.

[0174] At block 1552, a target head connected through any preamplifier circuits may be identified for a read / write operation. For example, the controller may select a target head for a data read / write operation.

[0175] At block 1554, a control signal may be generated for a preamplifier circuit connected to the target head. For example, the controller may generate a sensor enable signal for the preamplifier circuit connected to the target head that identifies the target head.

[0176] At block 1560, a control signal may be received by the preamplifier circuit. For example, the preamplifier circuit of the target head may receive a sensor enable control signal.

[0177] At block 1562, read signals may be generated from a plurality of read sensors on the target head. For example, the target head may receive read voltages from two read sensors on the head from a preamplifier circuit and return a first analog read signal and a second analog read signal to the preamplifier circuit.

[0178] At block 1564, the read signals from the target head can be received by the preamplifier circuit.For example, the preamplifier circuit can receive the first analog read signal and the second analog read signal to corresponding sensor amplifier inputs.

[0179] At block 1566, the amplified read signal from the sensor amplifier may be directed through a sensor path that passes through a switching circuit. For example, the amplified read signal may pass through a switching circuit that directs the two sensor signals to different multiplexers and read drivers in the preamplifier circuit.

[0180] The read signal path may be selected using a multiplexer circuit in the preamplifier circuit at block 1568. For example, the preamplifier circuit may activate a multiplexer in each sensor path to select corresponding read sensor signals from the target head and connect them to corresponding read drivers for the two TDMR read channels.

[0181] At block 1570, the selected read signals may be sent to corresponding channel inputs on the read channel circuitry.For example, the preamplifier circuitry may send its selected read sensor signals for the target head to both channel inputs for the TDMR read channel.

[0182] The above describes a parallel self-servo write technique based on data storage device hardware and software that can switch between a parallel self-servo write mode and a data read / write operation mode. In the above description, many specific details are set forth for purposes of explanation. However, it will be apparent that the disclosed technology can be practiced without any given subset of these specific details. In other cases, structures and devices are shown in block diagram form. For example, in some of the above implementations, the disclosed technology is described with reference to specific hardware.

[0183] References in this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment or implementation of the disclosed technology. The phrase "in one embodiment" appearing in various places in this specification is not necessarily all referring to the same embodiment or implementation.

[0184] Some portions of the above detailed description may be presented in terms of procedures and symbolic representations of operations on data bits within a computer memory. A procedure can generally be conceived as a self-consistent sequence of operations leading to a result. The operations may involve physical manipulation of physical quantities. These quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. These signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0185] These and similar terms may be associated with the appropriate physical quantities and may be considered as labels applied to these quantities. Unless otherwise apparent from the preceding discussion, it should be understood that throughout the description, discussions utilizing terms such as "processing" or "computing" or "calculating" or "determining" or "displaying" and the like may refer to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities in the computer system's registers and memories and transforms that data into other data similarly represented as physical quantities in the computer system's memories or registers or other such information storage, transfer, or display devices.

[0186] The disclosed technology may also relate to an apparatus for performing the operations herein. The apparatus may be specially constructed for the desired purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic disks, read-only memory (ROM), random access memory (RAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic or optical cards, flash memory including a universal serial bus (USB) key with non-volatile memory, or any type of medium suitable for storing electronic instructions each coupled to a computer system bus.

[0187] The disclosed technology can take the form of a complete hardware implementation, a complete software implementation, or an implementation containing hardware and software elements. In some embodiments, the technology is implemented in software, which includes but is not limited to firmware, resident software, microcode, etc.

[0188] Furthermore, the disclosed technology may take the form of a computer program product accessible from a non-transitory computer-usable or computer-readable medium that provides program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer-readable medium can be any apparatus that can contain, store, communicate, propagate, or transport the program for use by or in connection with an instruction execution system, apparatus, or device.

[0189] A computing system or data processing system suitable for storing and / or executing program code will include at least one processor (e.g., a hardware processor) coupled directly or indirectly to a memory element via a system bus. The memory element may include local memory, mass storage devices, and cache memories employed during the actual execution of the program code, which provide temporary storage of at least some program code to reduce the number of times code must be retrieved from mass storage devices during execution.

[0190] Input / output or I / O devices (including but not limited to keyboards, displays, pointing devices, etc.) can be coupled to the system either directly or through intervening I / O controllers.

[0191] Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modem and Ethernet cards are just a few of the currently available types of network adapters.

[0192] The terms storage medium, storage device, and data block are used interchangeably throughout this disclosure to refer to the physical media that store data.

[0193] Finally, the processes and displays presented herein may not be inherently related to any particular computer or other device. Based on the teachings herein, various general-purpose systems may be used with the programs, or it may prove convenient to construct more specialized devices to perform the required method operations. From the above description, it will be apparent that the structures required for various such systems. In addition, the disclosed technology is not described with reference to any particular programming language. It should be understood that the teachings of the technology as described herein can be implemented using various programming languages.

[0194] The foregoing description of the implementation of the present invention's technology and technology has been presented for the purpose of illustration and description. It is not intended to be exhaustive or to limit the present invention's technology and technology to the precise form disclosed. Based on the above teachings, many modifications and variations are possible. It is intended that the scope of the present invention's technology and technology is not limited by this detailed description. The present invention's technology and technology can be implemented in other specific forms without departing from its spirit or basic characteristics. Similarly, the specific naming and division of modules, routines, features, attributes, methods and other aspects are not mandatory or important, and the mechanisms for implementing the present invention's technology and technology or its features can have different names, divisions and / or formats. In addition, the modules, routines, features, attributes, methods and other aspects of the present invention's technology can be implemented as software, hardware, firmware or any combination of the three. In addition, no matter where a component (an example of which is a module) is implemented as software, the component can be implemented as a stand-alone program, as part of a larger program, as multiple separate programs, as a static or dynamic link library, as a kernel loadable module, as a device driver, and / or implemented in each and any other manner known in computer programming now or in the future. Additionally, the present technology and techniques are in no way limited to implementation in any particular programming language or for any particular operating system or environment. Therefore, the disclosure of the present technology and techniques is intended to be illustrative rather than limiting.

Claims

1. A data storage device, comprising: a first magnetic head actuated above a surface of a first storage medium, wherein: The first magnetic head includes a first plurality of read elements; and each read element of the first plurality of read elements is configured to generate a corresponding read signal in response to the first storage medium surface; a second magnetic head actuated above a surface of a second storage medium, wherein: the second head comprises a second plurality of read elements; and each read element of the second plurality of read elements is configured to generate a corresponding read signal in response to the first storage medium surface; and A control circuit, the control circuit being configured to: selecting a first corresponding read signal from the first plurality of read elements; selecting a second corresponding read signal from the second plurality of read elements; receiving, by a channel circuit, the first corresponding read signal and the second corresponding read signal in parallel; determining, by the channel circuit, a first position error signal according to the first corresponding read signal; determining, by the channel circuit, a second position error signal according to the second corresponding read signal; controlling a first position of the first magnetic head in response to the first position error signal; controlling a second position of the second magnetic head in response to the second position error signal; writing a servo pattern at the first head in response to the first position being within a first error tolerance value relative to a first self-servo write reference spiral; and The servo pattern is written at the second head in response to the second position being within a second error tolerance value relative to a second self-servo write reference spiral.

2. The data storage device according to claim 1, wherein: The first storage medium surface includes the first self-servowriting reference spiral; The second storage medium surface includes the second self-servo writing reference spiral; the first position error signal being responsive to the first self-servo write reference spiral; and The second position error signal is responsive to the second self-servo written reference spiral.

3. The data storage device according to claim 2, wherein: During the self-servo write mode, the control circuit is further configured to: controlling the first magnetic head to write a first set of servo tracks for the servo pattern onto the surface of the first storage medium; as well as The second magnetic head is controlled to write a second set of servo tracks for the servo pattern onto the surface of the second storage medium.

4. The data storage device according to claim 1 , further comprising: a first motor configured to position at least one set of read heads relative to a stack of storage media disks including the first storage media surface and the second storage media surface; and a plurality of head actuators, the plurality of head actuators being disposed on at least one group of arms corresponding to the at least one group of heads, wherein: each head actuator of the plurality of head actuators corresponds to a corresponding arm of the at least one set of arms and a corresponding head of the at least one set of heads; The control circuit comprises: a motor control circuit configured to provide a motor control signal to the first motor; a first actuator control circuit configured to provide a first actuator control signal to a first selected head actuator; and a second actuator control circuit configured to provide a second actuator control signal to a second selected head actuator; and The control circuit is further configured to: controlling the overall position of the first magnetic head and the second magnetic head using the motor control circuit; selectively controlling the first position of the first head using the first actuator control circuit; and The second position of the second head is selectively controlled using the second actuator control circuit.

5. The data storage device according to claim 4, further comprising: a plurality of arm actuators disposed on the at least one set of arms, wherein: each arm actuator of the plurality of arm actuators corresponds to a corresponding arm of the at least one set of arms and a corresponding head of the at least one set of heads; During a self-servo write mode using the first head and the second head: The first actuator control circuit is electrically connected to the head actuator for the first head; and The second actuator control circuit is electrically connected to the head actuator of the second head; and During a data read / write mode using the first magnetic head: The first actuator control circuit is electrically connected to the arm actuator; and The second actuator control circuit is electrically connected to the head actuator.

6. The data storage device of claim 5 , wherein the control circuit further comprises at least one switch configured to select electrical connections for the first actuator control circuit and the second actuator control circuit in the self-servo write mode and the data read / write mode.

7. The data storage device of claim 5 , wherein the control circuit further comprises a third actuator control circuit configured to control the corresponding arm actuator for the first head and the corresponding arm actuator for the second head during the self-servo write mode.

8. The data storage device of claim 1 , wherein: The control circuit comprises: a first preamplifier circuit configured to control read and write signals to a first set of magnetic heads including the first magnetic head; a second preamplifier circuit configured to control read and write signals to a second set of heads including the second head; and The channel circuit is configured for a set of read signal paths corresponding to a number of the first plurality of read elements for two-dimensional magnetic recording; The number of said second plurality of reading elements is equal to said number of said first plurality of reading elements; and The control circuit is further configured to, during the self-servo write mode: receiving, by the channel circuit, the first read signal from the first preamplifier circuit to a first read signal path in the set of read signal paths; and The second read signal from the second preamplifier circuit is received by the channel circuit to a second read signal path in the set of read signal paths.

9. The data storage device of claim 8, wherein: The control circuit is further configured to, during the self-servo write mode: setting a first set of parameters for the first magnetic head in the first preamplifier circuit; and setting a second set of parameters for the second head in the second preamplifier circuit; and The first set of parameters is different from the second set of parameters.

10. The data storage device according to claim 1, further comprising: a first set of magnetic heads, the first set of magnetic heads being arranged sequentially relative to the spaced-apart storage medium surface and including the first magnetic heads; a second set of magnetic heads, the second set of magnetic heads being arranged sequentially relative to the spaced-apart storage medium surface and comprising the second magnetic heads, wherein: The control circuit is further configured to: selecting the first head based on a first sequential position in the first set of heads; and selecting the second head based on a second sequential position in the second set of heads; and The first sequential position and the second sequential position are equal.

11. A method comprising: A first magnetic head is actuated over a surface of a first storage medium in a data storage device, wherein: The first magnetic head includes a first plurality of read elements; and each read element of the first plurality of read elements is configured to generate a corresponding read signal in response to the first storage medium surface; actuating a second magnetic head over a surface of a second storage medium in the data storage device, wherein: the second head comprises a second plurality of read elements; and each read element of the second plurality of read elements is configured to generate a corresponding read signal in response to the first storage medium surface; and selecting a first corresponding read signal from the first plurality of read elements; selecting a second corresponding read signal from the second plurality of read elements; receiving, by a channel circuit in the data storage device, the first corresponding read signal and the second corresponding read signal in parallel; determining, by the channel circuit, a first position error signal according to the first corresponding read signal; determining, by the channel circuit, a second position error signal according to the second corresponding read signal; controlling a first position of the first magnetic head in response to the first position error signal; controlling a second position of the second magnetic head in response to the second position error signal; writing a servo pattern at the first head in response to the first position being within a first error tolerance value relative to a first self-servo write reference spiral; and The servo pattern is written at the second head in response to the second position being within a second error tolerance value relative to a second self-servo write reference spiral.

12. The method according to claim 11, wherein: The first storage medium surface includes the first self-servowriting reference spiral; The second storage medium surface includes the second self-servo writing reference spiral; the first position error signal being responsive to the first self-servo write reference spiral; and The second position error signal is responsive to the second self-servo written reference spiral.

13. The method of claim 12, further comprising, during the self-servo write mode: controlling the first magnetic head to write a first set of servo tracks for the servo pattern onto the surface of the first storage medium; and The second magnetic head is controlled to write a second set of servo tracks for the servo pattern onto the surface of the second storage medium.

14. The method according to claim 11, further comprising: controlling an overall position of the first and second heads using a motor control signal, wherein the data storage device includes a first motor configured to position at least one set of read heads relative to a stack of storage media disks including the first and second storage media surfaces in response to the motor control signal; selectively controlling the first position of the first head using a first actuator control signal, wherein the data storage device includes a first selected head actuator corresponding to a first arm supporting the first head; as well as The second position of the second head is selectively controlled using a second actuator control signal, wherein the data storage device includes a second selected head actuator corresponding to a second arm supporting the second head.

15. The method of claim 14, further comprising during a self-servo write mode of writing a servo track in parallel using the first head and the second head: sending the first actuator control signal to the first selected head actuator for the first head; and The second actuator control signal is sent to the second selected head actuator of the second head.

16. The method of claim 15, further comprising during the self-servo write mode: A third actuator control signal is sent to a first arm actuator for the first magnetic head and a second arm actuator for the second magnetic head.

17. The method of claim 14, further comprising during a data read / write mode using the first magnetic head: sending the first actuator control signal to the first arm actuator of the first magnetic head; and The second actuator control signal is sent to the first selected head actuator of the first head.

18. The method of claim 11 , further comprising, during the self-servo write mode: receiving, by the channel circuit, the first read signal from the first preamplifier circuit to a first read signal path of a set of read signal paths corresponding to a plurality of read elements for two-dimensional magnetic recording; and The second read signal from the second preamplifier circuit is received by the channel circuit to a second read signal path in the set of read signal paths.

19. The method according to claim 11, further comprising: selecting the first magnetic head based on a first ordinal position of the first magnetic head in a first group of magnetic heads, wherein the first group of magnetic heads: are arranged sequentially relative to the spaced-apart storage medium surfaces; as well as selectively connected to a first preamplifier circuit; as well as The second magnetic head is selected based on a second ordinal position of the second magnetic head in the second group of magnetic heads, wherein: The first set of heads: are arranged sequentially relative to the spaced-apart storage medium surfaces; and selectively connected to a second preamplifier circuit; and The first sequential position and the second sequential position are equal.

20. A data storage device, comprising: a first magnetic head actuated above a surface of a first storage medium, wherein: The first magnetic head includes a first plurality of read elements; and each read element of the first plurality of read elements is configured to generate a corresponding read signal in response to the first storage medium surface; a second magnetic head actuated above a surface of a second storage medium, wherein: the second head comprises a second plurality of read elements; and each read element of the second plurality of read elements is configured to generate a corresponding read signal in response to the first storage medium surface; means for selecting a first corresponding read signal from the first plurality of read elements; means for selecting a second corresponding read signal from the second plurality of read elements; means for receiving, by a channel circuit, the first corresponding read signal and the second corresponding read signal in parallel; means for determining, by the channel circuit, a first position error signal based on the first corresponding read signal; means for determining, by the channel circuit, a second position error signal based on the second corresponding read signal; means for controlling a first position of the first head in response to the first position error signal; means for controlling a second position of the second head in response to the second position error signal; means for writing a servo pattern at the first head in response to the first position being within a first error tolerance value relative to a first self-servo write reference spiral; and means for writing the servo pattern at the second head in response to the second position being within a second error tolerance value relative to a second self-servo write reference spiral.

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