Semiconductor device and manufacturing method thereof

Abstract

The present disclosure provides a semiconductor device and a manufacturing method thereof, the device comprising a plurality of cells formed based on a semiconductor layer, at least one cell comprising: a first gate structure surrounding a platform region of the semiconductor layer; the field plate structure is located in the platform area; the well region is located in a part of the epitaxial layer region of the platform region, the depth of the well region is smaller than that of the first gate structure, and the side wall of the well region is connected with the side walls of the first gate structure and the field plate structure; the source region is located in the well region, the depth of the source region is smaller than that of the well region, and the side wall of the source region is connected with the side walls of the first gate structure and the field plate structure; the source electrode conducting layer is located in the platform area, at least part of the source electrode conducting layer is located on the surface of the semiconductor layer, part of the source electrode conducting layer covers the source area, part of the source electrode conducting layer covers the epitaxial layer, and therefore reverse recovery charges of the device are reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor device manufacturing, and more particularly, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the continuous advancement of power semiconductor device technology, the shielded gate trench (SGT) structure, as an important device architecture, has been widely adopted in various electronic devices. In a traditional SGT structure, the gate and source are integrated in the same trench and isolated from the active area by an oxide dielectric. The trench and contact holes are parallel and arranged in strips. This structure utilizes a vertical trench design, with the current path perpendicular to the chip surface, which can shorten the drift region length and significantly reduce on-resistance.

[0003] However, the body diode in the device accumulates charge during forward conduction. In traditional SGT structures, due to its internal electric field distribution and structural design, the reverse recovery charge (Qrr) is relatively large. A larger Qrr will lead to increased switching losses because these charges need to be dissipated during the switching process, resulting in energy loss. In order to reduce Qrr, it is usually necessary to adopt more complex processes to optimize the device structure or increase the chip area to improve the electric field distribution. However, this will increase manufacturing costs and device size, which is not ideal for some application scenarios with strict requirements on cost and size. In addition, Qrr can also be reduced through lifetime control technology, but this method will significantly increase manufacturing costs. Summary of the Invention

[0004] In view of this, the present disclosure provides an improved semiconductor device and a method for manufacturing the same, thereby reducing the Qrr of the device.

[0005] According to one aspect of an embodiment of the present disclosure, a semiconductor device is provided, including a plurality of cells formed based on a semiconductor layer, at least one of the cells including:

[0006] a first gate structure extending inward from a surface of the semiconductor layer, the first gate structure surrounding a platform region of the semiconductor layer;

[0007] a field plate structure, located in the platform region and extending inward from the surface of the semiconductor layer;

[0008] a well region, located in the epitaxial layer region of the platform region, extending inward from the surface of the semiconductor layer, wherein the depth of the well region is less than the depth of the first gate structure, and the sidewalls of the well region are in contact with the sidewalls of the first gate structure and the field plate structure;

[0009] a source region located in the well region, extending inward from the surface of the semiconductor layer, wherein the depth of the source region is less than the depth of the well region, and the sidewalls of the source region are in contact with the sidewalls of the first gate structure and the field plate structure;

[0010] a source conductive layer, located in the platform region and at least partially located on the surface of the semiconductor layer;

[0011] Wherein, the source conductive layer partially covers the source region and partially covers the epitaxial layer.

[0012] Optionally, the source conductive layer is connected to the source region to form an ohmic contact, and the source conductive layer is connected to the epitaxial layer to form a Schottky contact.

[0013] Optionally, in at least one of the cells, the first gate structure surrounds the field plate structure.

[0014] Optionally, in at least one of the cells, the well region is in a cross or M shape, and the center of the well region corresponds to the position of the field plate structure.

[0015] Optionally, in at least one of the cells, the first gate structure forms a closed regular polygonal structure, and the source conductive layer is conformal to the first gate structure.

[0016] Alternatively, the first gate structure forms a closed regular polygonal structure, and the source conductive layer is a circular ring structure.

[0017] Optionally, an extension depth of the field plate structure in the semiconductor layer is greater than an extension depth of the first gate structure in the semiconductor layer.

[0018] Optionally, the semiconductor layer has a gate trench and a field plate trench, each extending from the surface of the semiconductor layer toward the inside.

[0019] The first gate structure includes:

[0020] a first gate dielectric layer, covering an inner surface of the gate trench; and

[0021] a first gate conductor, located in the gate trench and separated from the semiconductor layer by the first gate dielectric layer;

[0022] The field plate structure includes:

[0023] a field plate dielectric layer, covering the inner surface of the field plate trench; and

[0024] A field plate conductor is located in the field plate trench and is separated from the semiconductor layer by the field plate dielectric layer.

[0025] Optionally, the thickness of the first gate dielectric layer is smaller than the thickness of the field plate dielectric layer.

[0026] Optionally, it also includes:

[0027] The second gate conductor is located in the field plate trench, extends in the field plate dielectric layer along the thickness direction of the semiconductor layer, and is separated from the field plate conductor and the semiconductor layer respectively.

[0028] Optionally, the second gate conductor extends deeper than the well region.

[0029] Optionally, the at least one cell further includes:

[0030] a field plate conductive plug, at least partially located above the surface of the semiconductor layer and connected to the field plate conductor; and

[0031] A source wiring layer is located above the epitaxial layer and is respectively connected to the plurality of source conductive layers and the field plate conductive plugs.

[0032] According to one aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, for forming the semiconductor device as described above.

[0033] One of the above technical solutions has the following unexpected technical effects:

[0034] By separating the field plate structure from the first gate structure, the electric field concentration between the gate and the source is reduced, the voltage resistance of the device is improved, and the charge distribution in the semiconductor layer is more effectively utilized, reducing the length and resistance of the current path, thereby reducing the on-resistance.

[0035] By forming a well region in part of the semiconductor layer and not forming a well region in the rest of the layer, and connecting a portion of the source conductive layer to the source region in the well region, the source potential is extracted; in the area where the well region is not formed, the source conductive layer is directly connected to the semiconductor layer and forms a Schottky contact with the semiconductor layer, thereby reducing the reverse recovery charge Qrr. In addition, this structural design significantly improves the switching speed of the device without adding additional process steps or sacrificing the device area. Because the Schottky contact has a low reverse recovery time, this allows the device to dissipate charge more effectively during fast switching, reducing switching losses and thereby improving overall performance and reliability.

[0036] Furthermore, the first gate structure surrounds the field plate structure, allowing for more precise control of the electric field distribution between the gate and the active area. This design not only helps improve the device's voltage resistance but also effectively reduces parasitic capacitance between the gate and source, minimizing gate drive losses. Simultaneously, the introduction of the second gate trench further increases channel density, improves gate control capability, and reduces channel resistance, thereby reducing device conduction losses.

[0037] Furthermore, the dual-trench gate configuration helps enhance the depletion capability of the field plate trench, significantly improving the device's breakdown voltage (BV) in high-voltage applications. This optimizes overall performance without sacrificing other parameters or adding specialized process steps. These improvements work together to ensure that the semiconductor device of the present invention exhibits excellent high performance and low loss, making it particularly suitable for applications requiring high switching speed and withstand voltage performance.

[0038] Therefore, the semiconductor device provided by the present disclosure can improve product performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0040] Figure 1 A schematic diagram showing the three-dimensional structure of a semiconductor device according to a first embodiment of the present disclosure is shown;

[0041] Figure 2 A schematic top view of the semiconductor device according to the first embodiment of the present disclosure is shown;

[0042] Figure 3 Shown Figure 2 A schematic diagram of the enlarged structure in the middle dotted box;

[0043] Figure 4 Shown along Figure 2 Schematic diagram of the cross-section structure taken along line AA;

[0044] Figure 5 Shown along Figure 2 Schematic diagram of the cross-section structure taken along line BB;

[0045] Figures 6 to 12 sectional views showing some stages of a method for manufacturing the semiconductor device according to the first embodiment of the present disclosure;

[0046] Figure 13 A schematic top view of a semiconductor device according to a second embodiment of the present disclosure is shown;

[0047] Figure 14 Shown along Figure 13 Schematic diagram of the cross-section structure taken along the CC line;

[0048] Figure 15 A schematic top view of the structure of a semiconductor device according to a third embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0049] The present disclosure will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by similar reference numerals throughout the various figures. For clarity, parts in the figures are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps may be depicted in a single figure.

[0050] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" the other layer or region.

[0051] If the purpose is to describe the situation of being directly above another layer or another area, this article will use expressions such as "directly above..." or "above and adjacent to...".

[0052] Many specific details of the present disclosure are described below, such as device structures, materials, dimensions, processing techniques, and technologies, to provide a clearer understanding of the present disclosure. However, as will be appreciated by those skilled in the art, the present disclosure may be implemented without following these specific details.

[0053] The present disclosure may be embodied in various forms, some examples of which are described below.

[0054] Figure 1 FIG2 shows a schematic diagram of the three-dimensional structure of a semiconductor device according to the first embodiment of the present disclosure. Figure 2 FIG2 shows a schematic top view of the semiconductor device according to the first embodiment of the present disclosure. Figure 3 Shown Figure 2 The enlarged structural diagram at the dotted box 11 is shown in FIG. Figure 4 Shown along Figure 2 Schematic diagram of the cross-section structure cut by line AA, Figure 5 Shown along Figure 2 Schematic diagram of the cross-section structure cut along line BB. In order to more clearly show the positional relationship of each structure in the semiconductor device, Figures 1 to 5 The insulating layer above the semiconductor layer is not shown. Figure 2 and Figure 3Only the well region, the trench and its internal structure, as well as the source conductive layer and the conductive plug are shown.

[0055] like Figures 1 to 5 As shown, the semiconductor device of the first embodiment of the present disclosure includes: a plurality of cells formed based on a semiconductor layer 10, at least one cell includes: a well region 121, a source region 122, a field plate structure 130, a first gate structure 140, a source conductive layer 150, a field plate conductive plug 160 and a source wiring layer 170.

[0056] In this embodiment, the semiconductor layer 10 includes a substrate 101 and an epitaxial layer 11 located on the substrate 101. A well region 121 extends inward from the surface of the semiconductor layer 10. A source region 122 is located in the well region 121 and extends inward from the surface of the semiconductor layer 10. The depth of the source region 122 is less than that of the well region 121. The well region 121 is P-type, while the semiconductor layer 10 and the source region 122 are N-type. The substrate 101 can serve as a drain, and its material may be, for example, silicon, silicon carbide, germanium, gallium nitride, or the like.

[0057] The semiconductor device of this embodiment can be used as a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT), for example, a drain contact region is formed in the substrate, and the conductivity type of the drain contact region is set to P-type or N-type. However, the embodiments of the present disclosure are not limited to this. Those skilled in the art can make other settings for the conductivity type of each region in the semiconductor layer 10 as needed to use the semiconductor device as a MOSFET or IGBT. Other settings can also be made to the components of the semiconductor layer 10 as needed, for example, the semiconductor layer 10 only includes the substrate 101 but does not include the epitaxial layer 110, and the well region 121 is directly formed in the substrate 101.

[0058] In this embodiment, the field plate trench 102 and the first gate trench 103 extend from the upper surface of the semiconductor layer 10 into the interior of the semiconductor layer 10. The first gate trench 103 surrounds the field plate trench 102 and separates the field plate trench 102. The width of the field plate trench 102 is greater than the width of the first gate trench 103, and the depth of the field plate trench 102 is greater than the depth of the first gate trench 103, allowing the field plate trench 102 to penetrate deeper into the epitaxial layer 110. The penetration of the field plate trench 102 into the epitaxial layer 110, even reaching the substrate 101, can better control the electric field distribution at the bottom of the trench and enhance the auxiliary depletion effect. This helps improve the device's breakdown voltage (BV) performance, making it more stable and reliable at high voltages.

[0059] The field plate structure 130 includes a field plate dielectric layer 131 and a field plate conductor 132. The field plate dielectric layer 131 covers the inner surface of the field plate trench 102. The field plate conductor 132 is filled in the field plate trench 102 and is separated from the semiconductor layer 10 by the field plate dielectric layer 131. The first gate structure 140 includes a first gate dielectric layer 141 and a first gate conductor 142. The first gate dielectric layer 141 covers the inner surface of the gate trench 103. The first gate conductor 142 is filled in the gate trench 103 and is separated from the semiconductor layer 10 by the first gate dielectric layer 141. The material of the field plate dielectric layer 131 and the first gate dielectric layer 141 is, for example, an oxide layer, and the material of the field plate conductor 132 and the first gate conductor 142 is, for example, polysilicon. The thickness of the first gate dielectric layer 141 is less than the thickness of the field plate dielectric layer 131. The thinner first gate dielectric layer 141 can reduce the capacitance between the gate and the active area, thereby improving the control capability of the gate. This helps more effectively control the opening and closing of the channel during device operation, improving device switching speed and performance. By adjusting the thickness of the first gate dielectric layer 141, the capacitance parameters between the gate and the active area can be optimized, further improving the overall performance of the device. Especially in high-frequency applications, optimizing capacitance parameters can reduce signal delay and improve signal integrity.

[0060] In this embodiment, the field plate trenches 102 are circular and there are multiple of them, and the first gate trenches 103 are in a grid shape, with each grid corresponding to a field plate trench 102. More specifically, each grid of the first gate trenches 103 is rectangular. Figure 2 Nine grids of the first gate trench 103 are shown, corresponding to the nine cells of the device. In each grid, the well region 121 is in the shape of a cross, and the center of the well region 121 corresponds to the position of the field plate trench 102. Of course, the number and correspondence between the grids and the cells can be set as needed, and the shape of the well region 121 can also be set in other ways, such as a "M" shape. In some other embodiments, each grid of the first gate trench 103 can also be in other polygonal shapes surrounding the field plate trench 102, and the field plate trench 102 can also be in other shapes. The source region 122 is located in the well region 121, so the distribution shape is similar to that of the well region 121.

[0061] In at least one cell of this embodiment, the first gate structure 140 surrounds a terrace region 10a of the semiconductor layer 10. The field plate structure 130 is located at the center of the terrace region 10a. The well region 121 is located in the terrace region 10a between the first gate structure 140 and the field plate structure 130. The depth of the well region 121 is less than the depth of the first gate structure 140, and the sidewalls of the well region 121 are in contact with the sidewalls of the first gate structure 140 and the field plate structure 130. The sidewalls of the source region 122 are in contact with the sidewalls of the first gate structure 140 and the field plate structure 130. The source conductive layer 150 is located in the terrace region 10a between the first gate structure 140 and the field plate structure 130, and is partially located above the surface of the semiconductor layer 10.

[0062] In some specific embodiments, the first gate structure 140 in the cell forms a closed regular polygonal structure. The source conductive layer 150 is conformal to the first gate structure 140 . For example, the first gate structure 140 and the source conductive layer 150 both form a square structure. In some other embodiments, the source conductive layer 150 within the grid of the first gate trench 103 may also intermittently surround the field plate trench 102 .

[0063] The source conductive layer 150 is separated from the field plate structure 130, and is also separated from the gate structure 140. Because the well region 121 and the source region 122 are arranged in a cross shape in the terrace region 10a, a portion of the source conductive layer 150 is connected to the source region 122 and extends into the well region 121 to form an ohmic contact, while another portion is directly connected to the epitaxial layer 110 to form a Schottky contact.

[0064] The field plate conductive plug 160 corresponds to the field plate trench 102 and extends into the field plate conductor 132. The source wiring layer 170 is located above the epitaxial layer 110 and is connected to the plurality of source conductive layers 150 and the field plate conductive plug 160.

[0065] However, the embodiments of the present disclosure are not limited thereto. Those skilled in the art may make other arrangements for the shape and distribution of the well region 121, the source region 122 and the source conductive layer 150 as needed, so that the shapes of the well region 121, the source region 122 and the source conductive layer 150 are coordinated to achieve the goal of partially extending the source conductive layer 150 into the well region 121, and partially extending the source conductive layer 150 without contacting the well region 121, but directly extending into the epitaxial layer 110 to form a Schottky contact.

[0066] Compared to conventional SGT devices, the semiconductor device of the first embodiment of the present disclosure separates the field plate trench from the gate trench. The field plate trench contains source polysilicon and is separated from the active area by an oxide layer dielectric. The first gate trench contains gate polysilicon and is separated from the active area by a relatively thin oxide layer dielectric. Separate contact holes are distributed in the active area. The separate contact holes can be distributed around and on both sides of the field plate trench to achieve potential extraction. The field plate trench penetrates deep into the substrate, which helps enhance the depletion capability. By reasonably adjusting the epitaxial concentration, the Rdson, BV, and output capacitance capabilities can be improved.

[0067] Furthermore, in the source conductive layer surrounding the field plate trench, a P-well is formed in part of the epitaxial layer by ion implantation to realize the extraction of the source potential. In the area where the P-well is not formed, the source conductive layer directly contacts the epitaxial layer to realize Schottky contact, thereby achieving the effect of reducing the reverse recovery charge Qrr.

[0068] The following will be combined Figures 6 to 12 A method for manufacturing a semiconductor device according to a first embodiment of the present disclosure will be described in detail.

[0069] like Figure 6 As shown, an epitaxial layer 110 is formed on a substrate 101, and a hard mask 104 is formed on the upper surface of the epitaxial layer 110. The epitaxial layer 110 is etched through the opening in the hard mask 104 to form a field plate trench 102 and a first gate trench 103. The width of the field plate trench 102 is greater than the width of the first gate trench 103. In this step, the etching depths of the field plate trench 102 and the gate trench 103 are substantially the same.

[0070] Furthermore, a sacrificial layer 105 is formed in the field plate trench 102 and the first gate trench 103, as shown in FIG. Figure 7 shown.

[0071] In this step, a sacrificial layer 105 is deposited, for example, by chemical vapor deposition (CVD) or other suitable processes. The thickness of the deposited layer should be sufficient to completely fill the first gate trench 103. To save costs, it is not necessary to completely fill the large field plate trench 102. The material of the sacrificial layer 105 is, for example, an oxide.

[0072] Furthermore, the depth of the field plate trench 102 is extended, as shown in FIG. Figure 8 shown.

[0073] In this step, for example, the sacrificial layer 105 above the hard mask 104 is first removed by a process such as chemical mechanical polishing (CMP), and then a barrier layer is formed above the first gate trench 103. The field plate trench 102 is then etched further, extending the field plate trench 102 further into the epitaxial layer 110. The sacrificial layer 105 within the field plate trench 102 is also removed.

[0074] Furthermore, a field plate dielectric layer 131 is formed on the inner surface of the field plate trench 102 and a field plate conductor 132 is filled in the field plate trench 102, as shown in FIG. Figure 9 shown.

[0075] In this step, a field plate dielectric layer 131 is first formed on the inner surface of the field plate trench 102 by thermal oxidation, chemical vapor deposition (CVD), or other suitable processes. The thickness of the field plate dielectric layer 131 can be adjusted according to actual needs to ensure good insulation performance. Subsequently, a field plate conductor 132 is filled in the field plate trench 102 by processes such as low-pressure chemical vapor deposition (LPCVD) or physical vapor deposition (PVD). The field plate conductor 132 is separated from the epitaxial layer 110 by the field plate dielectric layer 131, ensuring reliable isolation between the source and the semiconductor layer. The material of the field plate conductor 132 can be polysilicon, metal, or other conductive materials. The specific selection depends on the design requirements of the device and the compatibility of the manufacturing process.

[0076] Furthermore, a first gate dielectric layer 141 is formed on the inner surface of the first gate trench 103, and a first gate conductor 142 is filled in the first gate trench 103. Figure 10 shown.

[0077] In this step, for example, etching, CMP, or other processes are used to remove the hard mask 104 and the barrier layer corresponding to the first gate trench 103. A barrier layer is then formed above the field plate trench 102, and the sacrificial layer 105 within the first gate trench 103 is removed. A first gate dielectric layer 141 is then formed on the inner surface of the first gate trench 103 through thermal oxidation, chemical vapor deposition (CVD), or other suitable processes. The first gate dielectric layer 141 is relatively thin to reduce capacitance between the gate and the semiconductor layer, thereby improving device switching speed and efficiency. Subsequently, a first gate conductor 142 is formed in the first gate trench 103 through processes such as low-pressure chemical vapor deposition (LPCVD) or physical vapor deposition (PVD). The first gate conductor 142 is separated from the epitaxial layer 110 by the first gate dielectric layer 141, ensuring reliable isolation between the gate and the semiconductor layer. The material of the first gate conductor 142 can also be polysilicon, metal, or other conductive material. The specific material selection should take into account compatibility with the field plate conductor 132 and overall device performance. Finally, the barrier layer above the field plate trench 102 is removed.

[0078] Further, a well region 121 and a source region 122 are formed, as shown in FIG. Figure 11 shown.

[0079] In this step, a well region 121 is first formed in a portion of the epitaxial layer 110 by an ion implantation process. The shape of the well region 121 can be referred to Figure 3 , then form source region 122 in well region 121 and epitaxial layer 110. The doping type of well region 121 is opposite that of epitaxial layer 110. For example, if substrate 101 is P-type, well region 121 is N-type, and vice versa. The doping type of source region 122 is opposite that of well region 121 to form a source contact region. By precisely controlling the energy and dose of ion implantation, the depth and doping concentration of well region 121 and source region 122 can be ensured to meet design requirements, thereby optimizing the electrical performance of the device.

[0080] Furthermore, an isolation layer 180 is formed on the upper surface of the epitaxial layer 110, and a plurality of source conductive layers 150 and field plate conductive plugs 160 are formed penetrating the isolation layer 180, as shown in FIG. Figure 12 shown.

[0081] The isolation layer 180 can be made of silicon dioxide (SiO2) or other insulating materials. Its function is to prevent the source conductive layer 150 and the field plate conductive plug 160 from short-circuiting with other parts of the epitaxial layer 110. After the isolation layer 180 is formed, a plurality of through holes are formed in the isolation layer 180 by photolithography and etching processes. The positions of these through holes are the same as those of the source conductive layer 150 and the field plate conductive plug 160. Figures 1 to 5The source conductive layer 150 and the field plate conductive plug 160 are positioned correspondingly. Subsequently, these through-holes are filled with conductive material through processes such as electroplating, chemical vapor deposition (CVD), or physical vapor deposition (PVD) to form the source conductive layer 150 and the field plate conductive plug 160. The material of the source conductive layer 150 and the field plate conductive plug 160 can be metal (such as aluminum, copper, etc.) or polysilicon, the specific choice depending on the device design requirements and the compatibility of the manufacturing process.

[0082] Furthermore, a source wiring layer 170 is formed on the isolation layer 180, as shown in FIG. Figure 12 shown.

[0083] The source wiring layer 170 electrically connects to the multiple source conductive layers 150 and the field plate conductive plug 160, thereby providing access to the field plate conductor 132 within the field plate trench 102. The source wiring layer 170 can be made of a metal (such as aluminum or copper), and its thickness and width can be adjusted based on actual application requirements to ensure good conductivity and mechanical strength. Furthermore, the design of the source wiring layer 170 can also consider heat dissipation and electromagnetic compatibility (EMC) requirements to further enhance overall device performance. For example, the portion of the source wiring layer 170 connecting the source conductive layer 150 and the field plate conductive plug 160 can be formed as a single piece to increase the heat dissipation area.

[0084] A dielectric layer covering the source wiring layer 170 may also be formed on the isolation layer 180 , and a first gate conductive plug penetrating the dielectric layer and the isolation layer 180 may be formed. The first gate conductive plug contacts the first gate conductor 142 , and a first gate wiring layer is correspondingly formed on the dielectric layer.

[0085] Figure 13 FIG2 shows a schematic top view of a semiconductor device according to a second embodiment of the present disclosure. Figure 14 Shown along Figure 13 Schematic diagram of the cross-section structure taken along the CC line.

[0086] like Figure 13 and Figure 14 As shown, the semiconductor device of the second embodiment of the present disclosure is substantially the same as that of the first embodiment, and similarities are not repeated here, and reference may be made to the relevant description.

[0087] The difference is that in this embodiment, at least one cell further includes a second gate conductor 192, which is located in the field plate trench 102 and extends in the field plate dielectric layer 131 along the thickness direction of the semiconductor layer 10. The second gate conductor 192 is separated from the field plate conductor 132 and the semiconductor layer 10 by the field plate dielectric layer 131. The extension depth of the second gate conductor 192 is greater than the depth of the well region 121. The field plate dielectric layer 131 surrounding the second gate conductor 192 also serves as the second gate dielectric layer 191. The second gate dielectric layer 191 and the second gate conductor 192 form a second gate structure surrounding the field plate conductor 132.

[0088] In this embodiment, the semiconductor device adopts a double-ring gate structure. The second gate conductor 192 and the first gate conductor 142 can be electrically connected to the gate wiring layer through a gate conductive plug, or the second gate conductor 192 and the first gate conductor 142 have different potential lead-out lines so as to be controlled separately.

[0089] In this embodiment, the introduction of the second gate conductor 192 further increases the channel density, improves the gate control capability, and reduces the channel resistance, thereby reducing the conduction loss of the device.

[0090] In addition, the provision of the second gate conductor 192 helps to enhance the depletion capability of the field plate structure 130, so that in high voltage applications, the breakdown voltage (BV) of the device is significantly improved, achieving overall performance optimization without sacrificing other parameters or adding special process steps.

[0091] Figure 15 A schematic top view of the structure of a semiconductor device according to a third embodiment of the present disclosure is shown.

[0092] The semiconductor device of the third embodiment of the present disclosure is substantially the same as that of the first embodiment, and similarities are not repeated here, and reference may be made to the relevant description.

[0093] The difference is that, in this embodiment, the first gate structure 140 in the cell forms a closed regular polygonal structure, while the source conductive layer 150 is a circular ring structure.

[0094] The above-mentioned embodiments of the present disclosure can reduce the reverse recovery charge of the device through Schottky contact without sacrificing the area of ​​MOSFET or IGBT and adding special process steps. At the same time, it also improves the breakdown voltage, reduces the on-resistance, optimizes the capacitance parameters, and is compatible with existing processes.

[0095] In the above description, the technical details of patterning and etching of each layer are not described in detail. However, those skilled in the art will understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, those skilled in the art may also design methods that are not identical to the methods described above to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage.

[0096] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A semiconductor device comprising a plurality of cells formed based on a semiconductor layer, at least one of the cells comprising: a first gate structure extending inward from a surface of the semiconductor layer, the first gate structure surrounding a platform region of the semiconductor layer; a field plate structure, located in the platform region and extending inward from the surface of the semiconductor layer; a well region, located in the epitaxial layer region of the platform region, extending inward from the surface of the semiconductor layer, wherein the depth of the well region is less than the depth of the first gate structure, and the sidewalls of the well region are in contact with the sidewalls of the first gate structure and the field plate structure; a source region located in the well region, wherein a depth of the source region is less than a depth of the well region, and a sidewall of the source region is in contact with sidewalls of the first gate structure and the field plate structure; a source conductive layer, located in the platform region and at least partially located on the surface of the semiconductor layer; Wherein, the source conductive layer partially covers the source region and partially covers the epitaxial layer.

2. The semiconductor device according to claim 1, wherein The source conductive layer is connected to the source region to form an ohmic contact, and the source conductive layer is connected to the epitaxial layer to form a Schottky contact.

3. The semiconductor device according to claim 1, wherein In at least one of the cells, the first gate structure surrounds the field plate structure.

4. The semiconductor device according to claim 3, wherein In at least one of the cells, the first gate structure forms a closed regular polygonal structure, and the source conductive layer is conformal to the first gate structure. Alternatively, the first gate structure forms a closed regular polygonal structure, and the source conductive layer is a circular ring structure. The semiconductor device according to claim 1 , wherein In at least one of the cells, the well region is in a cross or M shape, and the center of the well region corresponds to the position of the field plate structure. The semiconductor device according to claim 1 , wherein: An extension depth of the field plate structure in the semiconductor layer is greater than an extension depth of the first gate structure in the semiconductor layer.

7. The semiconductor device according to any one of claims 1 to 6, wherein: The semiconductor layer has a gate trench and a field plate trench, each extending from the surface of the semiconductor layer toward the inside. The first gate structure includes: a first gate dielectric layer, covering an inner surface of the gate trench; and a first gate conductor, located in the gate trench and separated from the semiconductor layer by the first gate dielectric layer; The field plate structure includes: a field plate dielectric layer, covering the inner surface of the field plate trench; and A field plate conductor is located in the field plate trench and is separated from the semiconductor layer by the field plate dielectric layer.

8. The semiconductor device according to claim 7, wherein The thickness of the first gate dielectric layer is smaller than the thickness of the field plate dielectric layer.

9. The semiconductor device according to claim 7, further comprising: The second gate conductor is located in the field plate trench, extends in the field plate dielectric layer along the thickness direction of the semiconductor layer, and is separated from the field plate conductor and the semiconductor layer respectively.

10. The semiconductor device according to claim 9, wherein The second gate conductor extends deeper than the well region.

11. The semiconductor device according to claim 7, wherein The at least one cell further comprises: a field plate conductive plug, at least partially located above the surface of the semiconductor layer and connected to the field plate conductor; and A source wiring layer is located above the epitaxial layer and is respectively connected to the plurality of source conductive layers and the field plate conductive plugs. 12 . A method for manufacturing a semiconductor device, for forming the semiconductor device according to claim 1 .

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