Composite substrate and preparation method thereof, semiconductor device and chip

Abstract

The invention provides a composite substrate and a preparation method thereof, a semiconductor device and a chip, relates to the technical field of semiconductor chips, and aims to solve the problem that the on resistance of the composite substrate is relatively high due to relatively high bonding interface resistance after a plurality of substrates are bonded together. The composite substrate comprises a first substrate, a functional layer and a second substrate which are sequentially stacked, the first substrate and the second substrate are connected through the functional layer; wherein the resistivity of the material of the functional layer is less than or equal to 1 * 10 <-4 > omega.cm.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor chips, and in particular to a composite substrate and a preparation method thereof, a semiconductor device, and a chip. Background Art

[0002] With the continuous development of semiconductor technology, composite substrate bonding technology has been widely used in new energy fields such as power devices, photovoltaics, and solar cells. Composite substrate bonding technology involves bonding multiple substrates together to form a composite substrate. Under the influence of external energy, atoms at the composite substrate interface achieve vertical interconnection through van der Waals forces, molecular forces, and even atomic forces, shortening the connection distance between substrates and reducing heat generation, power consumption, and latency.

[0003] However, in the prior art, after multiple substrates are bonded together, the bonding interface resistance is high, which makes the on-resistance of the composite substrate high, thereby causing a certain impact on the electrical performance of the chip. Summary of the Invention

[0004] The embodiments of the present disclosure provide a composite substrate and a preparation method thereof, a semiconductor device, and a chip, aiming to solve the problem that after multiple substrates are bonded together, the bonding interface resistance is high, resulting in high on-resistance of the substrate.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions: In one aspect, a composite substrate is provided, comprising: a first substrate, a functional layer, and a second substrate stacked in sequence, wherein the first substrate and the second substrate are connected via the functional layer.

[0006] The resistivity of the material of the functional layer is less than or equal to 1×10 -4 Ω·cm.

[0007] In the composite substrate provided by the above embodiment of the present disclosure, the functional layer not only connects the first substrate and the second substrate, but also serves as a bridge connecting the first substrate and the second substrate. By setting the resistivity of the material of the functional layer to be less than or equal to 1×10 -4 Ω·cm, this resistivity range is relatively low, which helps to reduce the resistance of the bonding interface between the first substrate, the second substrate and the functional layer, and helps to reduce the bonding interface resistance and the on-resistance of the entire composite substrate.

[0008] In some embodiments, the material of the functional layer includes: a conductive oxide.

[0009] In some embodiments, the conductive oxide includes at least one of palladium cobalt oxide, tin-doped indium oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, tungsten-doped indium oxide, lanthanum nickelate, and strontium ruthenate.

[0010] In some embodiments, the thickness of the functional layer ranges from 1 nm to 2000 nm.

[0011] In some embodiments, the resistivity of the interface between the first substrate and / or the second substrate and the functional layer is in the range of 1×10 -4 Ω·cm~4×10 -6 Ω·cm.

[0012] In some embodiments, there are multiple functional layers, and at least two of the multiple functional layers are made of different materials.

[0013] In some embodiments, the material of the first substrate and / or the second substrate includes at least one of a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, a diamond substrate, a gallium oxide substrate, an aluminum nitride substrate, and an indium phosphide substrate.

[0014] In another aspect, the present disclosure provides a method for preparing a composite substrate. The method for preparing the composite substrate comprises: A functional layer is formed on one side of the first substrate.

[0015] The functional layer and the second substrate are bonded to form an initial composite substrate.

[0016] The initial composite substrate is heat-treated to obtain a composite substrate.

[0017] It can be understood that the beneficial effects achieved by the method for preparing the composite substrate provided by the above embodiment of the present disclosure can be referred to the beneficial effects of the composite substrate described above, and will not be repeated here.

[0018] In some embodiments, forming a functional layer on one side of the first substrate includes forming a plurality of functional layers on one side of the first substrate.

[0019] In some embodiments, bonding the functional layer and the second substrate to form an initial composite substrate includes: Another functional layer is formed on the second substrate.

[0020] The functional layer is bonded to another functional layer on the second substrate to form an initial composite substrate.

[0021] In some embodiments, forming a functional layer on one side of a first substrate includes: A target material of the functional layer is deposited onto the first substrate by using a magnetron sputtering method.

[0022] In some embodiments, the gas pressure range of the magnetron sputtering method is 1 Pa ~ 10 Pa.

[0023] In some embodiments, the power of the magnetron sputtering method ranges from 100W to 5000W.

[0024] In some embodiments, the temperature range of the magnetron sputtering method is 20°C to 300°C.

[0025] In some embodiments, before bonding the functional layer to the second substrate, the method includes: The surface of the functional layer and the surface of the second substrate close to the functional layer are activated.

[0026] In some embodiments, the functional layer and the second substrate are bonded with a bonding pressure ranging from 500N to 5000N.

[0027] In some embodiments, the initial composite substrate is subjected to a heat treatment at a temperature ranging from 200° C. to 1000° C.

[0028] In yet another aspect, the present disclosure provides a semiconductor device comprising a composite substrate.

[0029] It can be understood that the beneficial effects that can be achieved by the semiconductor device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the composite substrate described above, and will not be repeated here.

[0030] In another aspect, the present disclosure provides a chip comprising: a semiconductor device.

[0031] It can be understood that the beneficial effects that can be achieved by the chip provided by the above embodiments of the present disclosure can refer to the beneficial effects of the composite substrate described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0033] Figure 1 is a schematic structural diagram of a chip according to some embodiments of the present disclosure; Figure 2 is a schematic structural diagram of a composite substrate according to some embodiments of the present disclosure; Figure 3 is a schematic structural diagram of a composite substrate according to some further embodiments of the present disclosure; Figure 4 is a schematic structural diagram of a composite substrate according to some further embodiments of the present disclosure; Figure 5This is a flow chart of a method for preparing a composite substrate according to some embodiments of the present disclosure; Figure 6 1 is a structural diagram corresponding to each step in a method for preparing a composite substrate according to Example 1 of the present disclosure; Figure 7 1 is a structural diagram corresponding to each step in a method for preparing a composite substrate according to Example 2 of the present disclosure; Figure 8 This is a structural diagram corresponding to each step in a method for preparing a composite substrate according to Example 3 of the present disclosure. DETAILED DESCRIPTION

[0034] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0035] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplary" or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0036] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0037] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0038] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0039] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0040] As used herein, the term "substrate" refers to a material onto which subsequent layers of material may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0041] The following are the technical terms used in the embodiments of the present application: Semiconductor: A semiconductor is a material with electrical conductivity between that of a conductor and an insulator at room temperature. Semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor free of impurities and defects, with equal concentrations of electrons and holes, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an extrinsic semiconductor. Impurities added to an impurity semiconductor can provide a certain concentration of carriers (such as holes or electrons. Impurity semiconductors doped with electron-providing impurities (such as pentavalent phosphorus) are also called electron-type semiconductors or N (negative) semiconductors, while impurity semiconductors doped with hole-providing impurities (such as trivalent boron) are also called hole-type semiconductors or P (positive) semiconductors). This improves the conductivity of the intrinsic semiconductor. Generally, a higher carrier concentration results in a lower resistivity and better conductivity. In the embodiments of this application, this type of impurity semiconductor is also referred to as a conductive semiconductor. For example, conductive silicon carbide material is doped with impurities such as nitrogen (N), boron (B), aluminum (Al), etc. Furthermore, when the impurities introduced into the impurity semiconductor are capable of impurity compensation for the impurity semiconductor, the donor electrons are just sufficient to fill the acceptor energy levels, but are unable to provide electrons and holes to the conduction and valence bands, resulting in a wide-bandgap semiconductor material with a resistivity similar to that of an insulator. For example, in the embodiments of the present application, doping a silicon carbide material with a transition metal achieves impurity compensation for the silicon carbide material, thereby increasing the resistivity of the silicon carbide material. This type of impurity semiconductor is also referred to as a semi-insulating semiconductor or semi-insulator, or has semi-insulating properties.

[0042] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0043] In addition, in this application, directional terms such as "upper" and "lower" are defined relative to the orientation of the components in the drawings. It should be understood that these directional terms are relative concepts. They are used for relative description and clarification, and they can change accordingly according to changes in the orientation of the components in the drawings.

[0044] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0045] The technical solutions of this application can be applied to electronic devices, including various types of user equipment or terminal devices, such as computers, mobile phones, tablet computers, wearable devices, and in-vehicle devices. These electronic devices can also be network devices such as base stations. The electronic devices can also be devices such as power amplifiers used in these electronic devices. The embodiments of this application do not impose any particular restrictions on the specific form of these electronic devices.

[0046] The embodiment of the present disclosure provides a chip 100. Figure 1 As shown, the chip 100 includes: a semiconductor device 10 .

[0047] It is understood that the chip 100 is a part of an electronic device and a carrier of an integrated circuit. The semiconductor device 10 has a conductivity between that of a conductor and an insulator and can be used to manufacture rectifiers, diodes, transistors, integrated circuits, and the like.

[0048] An embodiment of the present disclosure provides a semiconductor device 10. The semiconductor device 10 includes a substrate 1.

[0049] It can be understood that in the semiconductor device 10, the substrate 1 is the basis of the entire semiconductor device 10, carrying other film layers. These film layers are precisely manufactured on the substrate 1 through different process steps, such as epitaxial growth, ion implantation, photolithography and etching, to form a semiconductor device 10 with specific functions.

[0050] With the continuous development of semiconductor technology, composite substrate 1A bonding technology has been widely used. That is, multiple substrates 1 are bonded together through bonding technology to form a composite substrate 1A. Under the action of external energy, the atoms at the interface of the composite substrate 1A realize vertical interconnection of multiple substrates 1 through van der Waals force, molecular force and even atomic force, shortening the connection distance between substrates 1 and reducing heat generation, power consumption and delay.

[0051] However, in the prior art, after multiple substrates 1 are bonded together, the bonding interface resistance is relatively high, which results in a relatively high on-resistance of the composite substrate 1A, thereby affecting the electrical performance of the chip 100 to a certain extent.

[0052] The embodiment of the present disclosure provides a composite substrate 1A. Figure 2 As shown, the composite substrate 1A includes: a first substrate 11 , a functional layer 13 , and a second substrate 12 stacked in sequence. The first substrate 11 and the second substrate 12 are connected via the functional layer 13 .

[0053] The resistivity of the material of the functional layer 13 is less than or equal to 1×10 -4 Ω·cm.

[0054] For example, the resistivity of the material of the functional layer 13 may be 1×10 -4 Ω·cm、0.5×10 -4 Ω·cm、1×10 -5 Ω·cm、0.5×10 -5 Ω·cm、1×10 -6 Ω·cm or 0.5×10 -6 Ω·cm, etc., are not limited here.

[0055] It can be understood that the functional layer 13 not only connects the first substrate 11 and the second substrate 12, but also serves as a bridge connecting the first substrate 11 and the second substrate 12. By setting the resistivity of the material of the functional layer 13 to be less than or equal to 1×10 -4 Ω·cm, this resistivity range is relatively low, which helps to reduce the resistance of the bonding interface between the first substrate 11, the second substrate 12 and the functional layer 13, and helps to reduce the bonding interface resistance and the on-resistance of the entire composite substrate 1A.

[0056] In some embodiments, the material of the functional layer 13 includes conductive oxide.

[0057] It can be understood that the conductive oxide has a high charge transfer capability, which helps to effectively transfer charges between the first substrate 11, the second substrate 12 and the functional layer 13, thereby reducing the on-resistance; and the conductive oxide as the material of the functional layer 13 can improve the solid-solid contact interface between the first substrate 11, the second substrate 12 and the functional layer 13, which helps to reduce the interface resistance and reduce the interface barrier, thereby reducing the on-resistance of the composite substrate 1A.

[0058] In some embodiments, the conductive oxide includes at least one of palladium cobalt oxide, tin-doped indium oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, tungsten-doped indium oxide, lanthanum nickelate, and strontium ruthenate.

[0059] Among them, palladium cobalt oxide has a lower resistivity and higher stability.

[0060] Among them, fluorine-doped tin oxide (FTO) is made of tin oxide and fluorine elements. The addition of fluorine can significantly reduce the resistivity of tin oxide while maintaining its excellent transparency.

[0061] Among them, aluminum-doped zinc oxide (AZO) is the abbreviation of aluminum-doped zinc oxide transparent conductive glass, and the resistivity of aluminum-doped zinc oxide is low.

[0062] Among them, tungsten-doped indium oxide is doped to increase the number of free carriers, thereby making the resistivity of tungsten-doped indium oxide lower.

[0063] Among them, lanthanum nickelate can be crystallized more perfectly by adjusting the increase in temperature, thereby reducing the resistivity.

[0064] Among them, under certain conditions, the electrons in strontium ruthenate form Cooper pairs and are not scattered by the lattice, so that the resistivity can be reduced to zero.

[0065] Therefore, by using at least one conductive oxide selected from palladium cobalt oxide, tin-doped indium oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, tungsten-doped indium oxide, lanthanum nickelate and strontium ruthenate as the material of the functional layer 13, the resistance of the bonding interface between the first substrate 11, the second substrate 12 and the functional layer 13 can be further reduced, the interface barrier can be reduced, and thus the on-resistance of the composite substrate 1A can be reduced.

[0066] In some embodiments, the thickness of the functional layer 13 ranges from 1 nm to 2000 nm.

[0067] For example, the thickness of the functional layer 13 may be 1 nm, 100 nm, 300 nm, 500 nm, 700 nm, 1000 nm, 1200 nm, 1400 nm, 1600 nm, 1800 nm or 2000 nm, etc., which is not limited here.

[0068] It can be understood that by setting the thickness of the functional layer 13 within the range of 1nm~2000nm, good contact can be formed between the functional layer 13 and the first substrate 11 and the second substrate 12, reducing the gaps and defects at the interface, thereby reducing the interface barrier, and further reducing the resistance and interface barrier of the bonding interface, which helps to reduce the on-resistance of the entire composite substrate 1A.

[0069] In some embodiments, the combined resistivity of the interface between the first substrate 11 and / or the second substrate 12 and the functional layer 13 is in the range of 1×10 -4 Ω·cm~4×10 -6 Ω·cm.

[0070] For example, the resistivity of the interface between the first substrate 11 and the functional layer 13 may be 1×10 -4 Ω·cm、1×10 -5 Ω·cm、1×10 -6 Ω·cm、2×10 -6 Ω·cm、3×10 -6 Ω·cm or 4×10 -6 Ω·cm, etc., are not limited here.

[0071] For example, the resistivity of the interface between the second substrate 12 and the functional layer 13 may be 1×10 -4 Ω·cm、1×10 -5 Ω·cm、1×10 -6 Ω·cm、2×10 -6 Ω·cm、3×10 -6 Ω·cm or 4×10 -6 Ω·cm, etc., are not limited here.

[0072] It can be understood that by setting the first substrate 11 and / or the second substrate 12, the resistivity of the interface between the functional layer 13 is 1×10 -4 Ω·cm~4×10 -6 The resistivity of the bonding interface is within the range of Ω·cm, that is, the resistivity of the bonding interface is low, which can effectively reduce the obstacles encountered by the current when passing through these interfaces, thereby reducing the on-resistance of the entire composite substrate 1A.

[0073] In some embodiments, as Figure 3 and Figure 4 As shown, there are multiple functional layers 13. At least two of the multiple functional layers 13 are made of different materials.

[0074] It can be understood that the provision of multiple functional layers 13, with at least two functional layers 13 made of different materials, can further optimize the on-resistance of the entire composite substrate 1A; and the combination of different materials may have different electrical properties, or the materials of different functional layers 13 may have different physical and chemical properties, which enables the composite substrate 1A to adapt to different application scenarios and broaden the scope of use of the composite substrate 1A.

[0075] In some embodiments, the first substrate 11 and / or the second substrate 12 includes at least one of a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, a diamond substrate, a gallium oxide substrate, an aluminum nitride substrate, and an indium phosphide substrate.

[0076] As can be understood, silicon substrates have good electrical conductivity and thermal stability. Silicon carbide substrates have high thermal conductivity, high hardness, and chemical stability. Gallium nitride substrates have advantages such as a wide bandgap and a high electron saturation mobility rate. Gallium arsenide substrates have characteristics such as a direct bandgap and high electron mobility. Diamond substrates have extremely high thermal conductivity and hardness. Gallium oxide substrates have characteristics such as a wide bandgap and a high breakdown electric field. Aluminum nitride substrates have characteristics such as high thermal conductivity, good mechanical properties, and chemical stability. Indium phosphide substrates have characteristics such as a direct bandgap and high electron mobility. In practical applications, the first substrate 11 and / or the second substrate 12 can each have unique physical and chemical properties, adapted to different application scenarios, thereby broadening the scope of use of the composite substrate 1A.

[0077] In some implementations, existing bonding processes for composite substrate 1A primarily include adhesive bonding, direct bonding, metal bonding, and mixed metal-dielectric bonding. Direct bonding technology is widely applicable because it is applicable to materials with various crystal orientations, has a wide temperature range, offers high throughput per unit time, and generally guarantees a certain bond strength.

[0078] Plasma activated bonding technology is the primary method for direct bonding. During the plasma activated bonding process, the substrates are primarily connected to each other through van der Waals forces and hydrogen bonds in the hydroxyl groups to achieve adhesion. Finally, heat treatment is used to remove water molecules to form covalent bonds, achieving stable bonding. However, due to the low hydroxyl content on the surface of the first substrate 11 or the second substrate 12 before bonding, it is difficult to provide sufficient hydroxyl groups for subsequent covalent bonding, making debonding prone to occur. Furthermore, due to the residual pores and poor density of the oxide layer on the surface of the first substrate 11 or the second substrate 12, water molecules that fail to escape in time during the subsequent annealing process will combine with these pores to form bubbles, seriously affecting the bonding quality of the composite substrate 1A.

[0079] Hybrid metal dielectric bonding utilizes direct surface bonding without bumps. Compared to traditional liquid phase welding, it significantly increases interconnect density and reduces interconnect loss, making it a core technology for achieving three-dimensional heterogeneous integration. While surface activated bonding can be achieved at room temperature, the activation process requires a relatively high temperature, placing stringent demands on the bonding equipment. Furthermore, hot pressing, while requiring low surface flatness, requires high temperatures and pressures, resulting in low efficiency.

[0080] Based on this, an embodiment of the present disclosure provides a method for preparing a composite substrate 1A. Figure 5 As shown, the method for preparing the composite substrate 1A includes: S1 to S3.

[0081] S1 : forming a functional layer 13 on one side of a first substrate 11 .

[0082] Exemplarily, the method for forming the functional layer 13 may be any one of magnetron sputtering, plasma enhanced chemical vapor deposition, sol-gel method and atomic layer deposition.

[0083] S2: Bonding the functional layer 13 and the second substrate 12 to form an initial composite substrate.

[0084] S3: Heat-treating the initial composite substrate to obtain composite substrate 1A.

[0085] For example, the heat treatment may be performed in a N2 atmosphere, and the heat treatment time may range from 1 hour to 2 hours.

[0086] It can be understood that S1 allows the functional layer 13 to be attached to the first substrate 11. The functional layer 13 helps reduce the resistance of the bonding interface between the first substrate 11, the second substrate 12, and the functional layer 13, thereby helping to reduce the bonding interface resistance and the on-resistance of the entire composite substrate 1A. S2 allows the first substrate 11, the second substrate 12, and the functional layer 13 to be stacked together in sequence to form a stable initial composite substrate structure. S3 allows the bonding structure to be further consolidated through heat treatment, so that the hydrophilic bonding between the first substrate 11 and the second substrate 12 on the initial composite substrate forms more covalent bonds.

[0087] Exemplarily, before forming the functional layer 13 on one side of the first substrate 11, S1 can first clean the first substrate 11 and the second substrate 12, and perform the first cleaning and the second cleaning on the first substrate 11 and the second substrate 12 in sequence to reduce the residues on the first substrate 11 and the second substrate 12, thereby improving the uneven defect problem of the first substrate 11 and the second substrate 12, improving the vacuum adsorption force of the bonding machine chuck on the back of the first substrate 11 and the second substrate 12, and improving the distortion of the bonding between the first substrate 11 and the second substrate 12. During the first cleaning, the cleaning liquid used includes any one or more combinations of hydrofluoric acid, nitric acid, phosphoric acid and sulfuric acid, and the specific type can be selected accordingly according to the different residues; during the second cleaning, the cleaning liquid used includes any one or more combinations of hydrofluoric acid, nitric acid, hydrochloric acid, hydrogen peroxide and ammonia water; the first cleaning is mainly to remove substances such as polysilicon and nitride remaining on the first substrate 11 and the second substrate 12, while the second cleaning is mainly to remove substances generated during the first cleaning process and metal ions that cannot be removed by the first cleaning.

[0088] The present disclosure uses hydrophilic bonding in mixed metal dielectric bonding. The bonding conditions of hydrophilic bonding are mild and bonding can be performed in an atmospheric environment. Its bonding mechanism is to utilize the dehydration condensation (Si-OH+Si-OH→Si-O-Si+H2O) between the hydrophilic groups on the surface of the dielectric material of the first substrate 11 or the second substrate 12 to form a covalent bond at the bonding interface to achieve bonding, and the bonding between the metal pads is achieved through annealing diffusion.

[0089] For the composite substrate 1A having the multi-layer functional layer 13, In some embodiments, combined Figure 7 , S1 forms a functional layer 13 on one side of the first substrate 11, including: A multi-layer functional layer 13 is formed on one side of the first substrate 11 .

[0090] It can be understood that the above method can prepare a composite substrate 1A having multiple functional layers 13 . There is no limitation on the material of each of the multiple functional layers 13 , and the material can be selected according to actual needs.

[0091] In some embodiments, combined Figure 8 , S2 bonds the functional layer 13 to the second substrate 12 to form an initial composite substrate, including: Another functional layer 13 is formed on the second substrate 12 .

[0092] The functional layer 13 is bonded to another functional layer 13 on the second substrate 12 to form an initial composite substrate.

[0093] It can be understood that the above method can prepare a composite substrate 1A having multiple functional layers 13 . There is no limitation on the material of each of the multiple functional layers 13 , and the material can be selected according to actual needs.

[0094] In some embodiments, S1 forms a functional layer 13 on one side of the first substrate 11, including: A target material of the functional layer 13 is deposited on the first substrate 11 by magnetron sputtering.

[0095] Exemplarily, the gas pressure range of the magnetron sputtering method is 1Pa~10Pa.

[0096] For example, the gas pressure of the magnetron sputtering method can be 1 Pa, 2 Pa, 4 Pa, 6 Pa, 8 Pa or 10 Pa, etc., which is not limited here.

[0097] Exemplarily, the power range of the magnetron sputtering method is 100W~5000W.

[0098] For example, the power of the magnetron sputtering method can be 100W, 200W, 300W, 400W or 500W, etc., which is not limited here.

[0099] Exemplarily, the temperature range of the magnetron sputtering method is 20°C to 300°C.

[0100] For example, the temperature of the magnetron sputtering method can be 20° C., 50° C., 100° C., 150° C., 200° C., 250° C., or 300° C., etc., which is not limited here.

[0101] For example, PdCoO2 is deposited as the material of the functional layer 13 by magnetron sputtering, and the thickness of the functional layer 13 ranges from 1 nm to 2000 nm. Pure Pd and pure Co targets, or Pd-Co alloy targets (atomic ratio, Pd:Co=1:1) or PdCoO2 targets are used, and the vacuum is pre-evacuated to <5×10 -4 Pa; argon as carrier gas, flow rate 10sccm~500sccm; oxygen flow rate 1sccm~50sccm; total gas pressure 1Pa~10Pa, DC / RF power supply power 100W~5000W; temperature range 20℃~300℃. Immediately after sputtering, anneal in Ar / O2 or N2 / O2 mixture (such as 95% Ar + 5% O2) for 30 minutes, annealing temperature range 300℃~1000℃, in order to improve crystallinity and stoichiometric ratio and avoid cracking caused by thermal stress during natural cooling.

[0102] In some implementations, from the surface structure of the mixed metal dielectric bonding, most of the bonding area is composed of dielectric material. Therefore, the mechanical strength of the bonding interface strongly depends on the bonding quality of the dielectric material. Improving the hydrophilicity of the dielectric material surface can increase the number of covalent bonds after the dielectric material is bonded, thereby improving the bonding quality.

[0103] Therefore, in some embodiments, before bonding the functional layer 13 and the second substrate 12, the following steps are included: The surface of the functional layer 13 and the surface of the second substrate 12 close to the functional layer 13 are activated.

[0104] It is understood that the activation treatment can improve the hydrophilicity of the surface of the functional layer 13 and the second substrate 12, and promote the formation of chemical bonds. The surface to be bonded of the first substrate 11 and the surface to be bonded of the second substrate 12 are subjected to plasma treatment, and the plasma can be at least one of N2 plasma, O2 plasma and Ar plasma.

[0105] For example, surface activation treatment conditions can be: power of 10W to 5000W. Higher power can damage the surface smoothness of the sample, while lower power can result in incomplete activation. Pressure of 2Pa to 80Pa. Higher pressure can damage the sample surface, while lower pressure can be difficult to implement. Time of 1 minute to 10 minutes. Longer activation times can damage the surface and increase the surface roughness of the material, while shorter activation times may not remove adsorbed contaminants.

[0106] In some embodiments, S2 bonds the functional layer 13 to the second substrate 12 with a bonding pressure ranging from 500N to 5000N.

[0107] Illustratively, the bonding pressure may be 500N, 1000N, 2000N, 3000N, 4000N, or 5000N, etc., which is not limited here.

[0108] It can be understood that the bonding pressure is in the range of 500N~5000N, which helps to ensure close contact at the bonding interface between the first substrate 11, the second substrate 12 and the functional layer 13, promotes the formation of chemical bonds, helps to achieve higher strength bonding at lower pressure, and improves the bonding quality and stability of the composite substrate 1A.

[0109] In some embodiments, S3 performs a heat treatment on the initial composite substrate, and the temperature range of the heat treatment is 200° C. to 1000° C.

[0110] For example, the temperature of the heat treatment may be 200° C., 300° C., 4000° C., 500° C., 600° C., 700° C., 800° C., 900° C., or 1000° C., etc., but is not limited thereto.

[0111] It can be understood that setting the heat treatment temperature within the range of 200°C to 1000°C helps to improve the intermolecular interaction and bonding strength between the first substrate 11 and the second substrate 12 on the initial composite substrate, further allowing the hydrophilic bonds between the first substrate 11 and the second substrate 12 on the initial composite substrate to form more covalent bonds, thereby achieving higher strength bonding and improving the bonding quality and stability of the composite substrate 1A.

[0112] Here, the composite substrate 1A can also be a composite wafer formed by bonding a first wafer and a second wafer together. All descriptions of the composite substrate 1A in this disclosure can be equivalently replaced with the composite wafer. The first substrate 11 and the second substrate 12 can also be equivalently replaced with the first wafer and the second wafer. It should be noted that the composite substrate 1A or composite wafer provided in this disclosure can be applied to the chip 100, or the composite substrate 1A or composite wafer can be directly formed on the chip 100.

[0113] Example 1 Embodiment 1 provides a composite substrate 1A. Figure 6 The preparation method of the composite substrate 1A includes: 1D~5D.

[0114] 1D: providing a first substrate 11, which is a 6-inch polycrystalline diamond substrate, and cleaning the first substrate 11 twice in sequence.

[0115] 2D: The functional layer 13 is deposited on the surface of the first substrate 11 by magnetron sputtering. The material of the functional layer 13 is PdCoO2 with a thickness ranging from 1nm to 2000nm. Pure Pd and pure Co targets, or Pd-Co alloy targets (atomic ratio, Pd:Co=1:1) or PdCoO2 targets are used. The vacuum is pre-evacuated to <5×10 -4 Pa; argon as carrier gas, flow rate 10 sccm to 500 sccm; oxygen flow rate 1 sccm to 50 sccm; total gas pressure 1 Pa to 10 Pa; DC / RF power supply power 100 W to 5000 W; temperature range 20°C to 300°C. Immediately after sputtering, annealing is performed in an Ar / O2 or N2 / O2 mixture (e.g., 95% Ar + 5% O2) for 30 minutes at a temperature range of 300°C to 1000°C. Plasma treatment is performed on the surface of the functional layer 13.

[0116] 3D: Provide a second substrate 12, which is a 6-inch gallium nitride substrate, and perform two cleanings on the second substrate 12. Perform plasma treatment on the surface of the second substrate 12 to be bonded.

[0117] 4D: After aligning the surfaces of the first substrate 11 and the functional layer 13 with the bonding interface of the second substrate 12, a pressure of 500N to 5000N is applied to contact the bonding interface areas of the first substrate 11, the functional layer 13 and the second substrate 12 to form an initial composite substrate.

[0118] 5D: The initial composite substrate is annealed at a temperature of 200°C to 1000°C in a N2 atmosphere for 1 hour to 2 hours to obtain a composite substrate 1A.

[0119] Example 2 Embodiment 2 provides a composite substrate 1A. Figure 7 The preparation method of the composite substrate 1A includes: 1B~5B.

[0120] 1B: providing a first substrate 11, which is a 6-inch polycrystalline diamond substrate, and cleaning the first substrate 11 twice in sequence.

[0121] 2B: Three functional layers 13 are deposited on the surface of the first substrate 11 by magnetron sputtering. The material of the functional layer 13 is PdCoO2 with a thickness ranging from 1 nm to 2000 nm. Pure Pd and pure Co targets, or Pd-Co alloy targets (atomic ratio, Pd:Co=1:1) or PdCoO2 targets are used. The vacuum is pre-evacuated to <5×10 -4 Pa; argon as carrier gas, flow rate 10 sccm to 500 sccm; oxygen flow rate 1 sccm to 50 sccm; total gas pressure 1 Pa to 10 Pa; DC / RF power supply power 100 W to 5000 W; temperature range 20°C to 300°C. Immediately after sputtering, annealing is performed in an Ar / O2 or N2 / O2 mixture (e.g., 95% Ar + 5% O2) for 30 minutes at a temperature range of 300°C to 1000°C. Plasma treatment is performed on the surface of the functional layer 13.

[0122] 3B: Provide a second substrate 12, which is a 6-inch GaN substrate, and perform two cleanings on the second substrate 12. Perform plasma treatment on the surface of the second substrate 12 to be bonded.

[0123] 4B: After aligning the surfaces of the first substrate 11 and the functional layer 13 with the bonding interface of the second substrate 12, a pressure of 500N to 5000N is applied to bring the bonding interface regions of the first substrate 11, the functional layer 13 and the second substrate 12 into contact, forming an initial composite substrate.

[0124] 5B: The initial composite substrate is annealed at a temperature of 200° C. to 1000° C. in a N 2 atmosphere for 1 h to 2 h to obtain a composite substrate 1A.

[0125] Example 3 Embodiment 3 provides a composite substrate 1A. Figure 8 The preparation method of the composite substrate 1A includes: 1C to 6C.

[0126] 1C: providing a first substrate 11, which is a 6-inch polycrystalline diamond substrate, and cleaning the first substrate 11 twice in sequence.

[0127] 2C: The material of the single-layer functional layer 13 is PdCoO2, which has a thickness ranging from 1 nm to 2000 nm, deposited on the surface of the first substrate 11 by magnetron sputtering. Pure Pd and pure Co targets, or Pd-Co alloy targets (atomic ratio, Pd:Co=1:1) or PdCoO2 targets are used. The vacuum is pre-evacuated to <5×10 -4 Pa; argon as carrier gas, flow rate 10 sccm to 500 sccm; oxygen flow rate 1 sccm to 50 sccm; total gas pressure 1 Pa to 10 Pa; DC / RF power supply power 100 W to 5000 W; temperature range 20°C to 300°C. Immediately after sputtering, annealing is performed in an Ar / O2 or N2 / O2 mixture (e.g., 95% Ar + 5% O2) for 30 minutes at a temperature range of 300°C to 1000°C. Plasma treatment is performed on the surface of the functional layer 13.

[0128] 3C: providing a second substrate 12, which is a 6-inch GaN substrate, and cleaning the second substrate 12 twice in sequence.

[0129] 4C: A single functional layer 13 is deposited on the surface of the second substrate 12 by magnetron sputtering. The material of the functional layer 13 is PdCoO2 with a thickness ranging from 1 nm to 2000 nm. Pure Pd and pure Co targets, or Pd-Co alloy targets (atomic ratio, Pd:Co=1:1) or PdCoO2 targets are used. The vacuum is pre-evacuated to <5×10 -4 Pa; argon as carrier gas, flow rate 10 sccm to 500 sccm; oxygen flow rate 1 sccm to 50 sccm; total gas pressure 1 Pa to 10 Pa; DC / RF power supply power 100 W to 5000 W; temperature range 20°C to 300°C. Immediately after sputtering, annealing is performed in an Ar / O2 or N2 / O2 mixture (e.g., 95% Ar + 5% O2) for 30 minutes at a temperature range of 300°C to 1000°C. Plasma treatment is performed on the surface of the functional layer 13.

[0130] 5C: After aligning the surfaces of the first substrate 11 and the functional layer 13 with the bonding interface of the second substrate 12, a pressure of 500N to 5000N is applied to contact the bonding interface areas of the first substrate 11, the functional layer 13 and the second substrate 12 to form an initial composite substrate.

[0131] 6C: The initial composite substrate is annealed at a temperature of 200° C. to 1000° C. in a N 2 atmosphere for 1 h to 2 h to obtain a composite substrate 1A.

[0132] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention are intended to be covered by the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope of protection of the claims.

Claims

1. A composite substrate, characterized in that include: A first substrate, a functional layer, and a second substrate are stacked in sequence; the first substrate and the second substrate are connected via the functional layer; The resistivity of the material of the functional layer is less than or equal to 1×10 -4 Ω·cm.

2. The composite substrate according to claim 1, wherein The material of the functional layer includes conductive oxide.

3. The composite substrate according to claim 2, wherein: The conductive oxide includes at least one of palladium cobalt oxide, tin-doped indium oxide, fluorine-doped tin oxide, aluminum-doped zinc oxide, tungsten-doped indium oxide, lanthanum nickelate and strontium ruthenate.

4. The composite substrate according to claim 1, wherein The thickness of the functional layer ranges from 1 nm to 2000 nm.

5. The composite substrate according to claim 1, wherein The resistivity of the interface between the first substrate and / or the second substrate and the functional layer is in the range of 1×10 -4 Ω·cm~4×10 -6 Ω·cm.

6. The composite substrate according to claim 1, wherein There are multiple functional layers, and at least two of the multiple functional layers are made of different materials.

7. The composite substrate according to claim 1, wherein The first substrate and / or the second substrate includes at least one of a silicon substrate, a silicon carbide substrate, a gallium nitride substrate, a gallium arsenide substrate, a diamond substrate, a gallium oxide substrate, an aluminum nitride substrate, and an indium phosphide substrate.

8. A method for preparing a composite substrate, characterized in that: include: forming a functional layer on one side of a first substrate; bonding the functional layer to a second substrate to form an initial composite substrate; The initial composite substrate is subjected to heat treatment to obtain the composite substrate.

9. The method for preparing a composite substrate according to claim 8, wherein: The forming of a functional layer on one side of the first substrate comprises: A plurality of functional layers are formed on one side of the first substrate.

10. The method for preparing a composite substrate according to claim 8, wherein: Bonding the functional layer and the second substrate to form an initial composite substrate includes: forming another functional layer on the second substrate; The functional layer and the other functional layer on the second substrate are bonded to form an initial composite substrate.

11. The method for preparing a composite substrate according to claim 8, wherein: The forming of a functional layer on one side of the first substrate comprises: A target material of the functional layer is deposited on the first substrate by using a magnetron sputtering method.

12. The method for preparing a composite substrate according to claim 11, wherein: The gas pressure range of the magnetron sputtering method is 1Pa~10Pa; and / or, the power range is 100W~5000W; and / or, the temperature range is 20°C~300°C.

13. The method for preparing a composite substrate according to claim 8, wherein: Before bonding the functional layer and the second substrate, the method includes: An activation treatment is performed on the surface of the functional layer and the surface of the second substrate close to the functional layer.

14. The method for preparing a composite substrate according to claim 8, wherein: The functional layer and the second substrate are bonded together with a bonding pressure ranging from 500N to 5000N.

15. The method for preparing a composite substrate according to claim 8, wherein: The initial composite substrate is subjected to heat treatment at a temperature ranging from 200° C. to 1000° C.

16. A semiconductor device, characterized in that: include: The composite substrate according to any one of claims 1 to 7.

17. A chip, characterized in that: include: The semiconductor device according to claim 16.

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