A chip exception detection method, device, equipment and storage medium

Abstract

This application provides a method, apparatus, device, and storage medium for detecting chip anomalies. The method includes: acquiring the basic structure and layering information of the original design layout of the chip to be tested; performing a first calculation logic setting and color characterization on contact holes according to the connection characteristics of the basic structure and a pre-configured observation mode to obtain contact hole layer images; performing a second calculation logic setting and color characterization on each metal layer based on the connection relationship between the contact hole layer, metal layer, and via layer and the contact hole layer image to obtain images of each metal layer; selecting any metal layer as the metal layer to be tested and scanning it using a scanning electron microscope to obtain an actual voltage contrast image; performing image recognition between the metal layer image as a theoretical voltage contrast image and the actual voltage contrast image to obtain a comparison area image; and performing color comparison on the comparison area image to determine anomaly points. The method of this application improves the efficiency of chip anomaly point location.

Description

Technical Field

[0001] This application relates to the field of chip failure analysis, and in particular to a method, apparatus, device and storage medium for detecting chip anomalies. Background Technology

[0002] During integrated circuit manufacturing, short circuits can occur inside the chip due to process defects, equipment errors, or even human error. Such abnormal short circuits can cause serious problems such as increased chip power consumption, malfunctions, and data loss. Timely detection of defects during integrated circuit manufacturing is crucial for improving yield rates; therefore, chip failure analysis is becoming increasingly important. Chip failure analysis helps integrated circuit designers identify design flaws, process parameter mismatches, or improper design and operation.

[0003] In existing technologies, electron microscopes are typically used to inspect chip structures. For example, the most commonly used electron microscope is the Scanning Electron Microscope (SEM), which examines the chip structure layer by layer. Due to the potential differences between different regions on the sample surface after irradiation by the incident electron beam, voltage contrast (VC) is formed, resulting in SEM images where high potentials are dark and low potentials are bright. However, there are currently no reference documents that can represent the voltage contrast of each layer in a layout under SEM. The most commonly used Graphic Data System (GDS) files only show the shape of each layer and the connection relationships between upper and lower layers, and cannot intuitively represent the actual voltage contrast of a single layer under SEM. Therefore, manual interpretation of the SEM image is required to locate anomalies. Currently, there are generally two methods for manually identifying outliers in SEM images. One method is to manually deduce the theoretical voltage contrast of the basic structure of the layout based on the structural connection relationship shown in the layout and the SEM voltage contrast imaging principle, and then compare it with the actual image to determine outliers. The other method is to manually find structures on the layout with completely consistent connection relationships, and then compare the voltage contrast imaging results of the two areas under SEM to determine outliers.

[0004] Existing judgment methods usually require manual deduction and comparison. It is difficult to quickly judge the structure of a large area by visual observation alone, and it is also difficult to infer the voltage contrast of complex back-layer structures. Therefore, a lot of time and effort is required for analysis and judgment, resulting in low efficiency in locating anomalies. Summary of the Invention

[0005] This application provides a method, apparatus, device, and storage medium for detecting chip anomalies, in order to solve the problem of low efficiency in locating anomaly points based on electron microscope images in the prior art.

[0006] Firstly, this application provides a method for detecting chip anomalies, comprising:

[0007] Obtain the original design layout of the chip to be tested; and perform layout analysis processing based on the original design layout to obtain the basic structure and layout layer information in the original design layout;

[0008] Extract the connection features of the basic structure in the original design layout, and based on the connection features, use a pre-configured observation mode to perform a first calculation logic setting and color characterization processing on the contact holes at the first preset position in the original design layout;

[0009] Based on the first calculation logic and the represented color of the contact hole at the first preset position, voltage contrast calculation is performed to obtain the contact hole layer image;

[0010] The connection relationships between the contact hole layer, the M metal layers, and the via layer in the layout layer information of the original design layout are extracted respectively. Based on the connection relationships, the contact hole layer image is used to perform a second calculation logic setting and color characterization processing on each of the M metal layers to obtain an image of each metal layer. The layout layer information includes M metal layers, where M is a positive integer.

[0011] Select any one of the M metal layers as the metal layer to be detected, and use an electron microscope to scan the metal layer to be detected to obtain an actual voltage contrast image; and perform shape feature extraction processing on the actual voltage contrast image to obtain a feature pattern.

[0012] The image of the metal layer to be detected is used as the theoretical voltage contrast image. Based on the feature pattern, image recognition processing is performed on the actual voltage contrast image and the theoretical voltage contrast image respectively, so as to obtain the first comparison region image from the actual voltage contrast image and the second comparison region image from the theoretical voltage contrast image respectively.

[0013] Color contrast technology is used to perform color comparison processing on the first comparison area image and the second comparison area image to determine whether there are any abnormal points in the chip to be detected.

[0014] Optionally, in the method described above, when the pre-configured observation mode is the first observation mode, the step of performing a first calculation logic setting and color characterization processing on the contact holes at the first preset position in the original design layout according to the connection characteristics and using the pre-configured observation mode includes:

[0015] When it is determined that the contact hole falling on the gate in the original design layout is the first contact hole and the surface of the first contact hole is a high-potential basic structure, the calculation logic of the first contact hole is set to the connection feature between the first contact hole and the gate structure as having a connection, and the first contact hole is characterized by a first preset color.

[0016] When it is determined that the contact hole falling on the P-type shallowly doped active region in the N-well in the original design layout is the second contact hole and the surface of the second contact hole is a low-potential basic structure, the calculation logic of the second contact hole is set as follows: the connection feature between the second contact hole and the gate structure is not connected; the connection feature between the second contact hole and the active region and the P-type source / drain implantation is connected; and the connection feature between the second contact hole and the N-well or deep N-well is connected. The second contact hole is then characterized by a second preset color.

[0017] When it is determined that the contact hole falling on the N-type shallowly doped active region in the P-well in the original design layout is the third contact hole and the surface of the third contact hole is a basic structure with a medium potential, the calculation logic of the third contact hole is set as follows: the connection feature between the third contact hole and the gate structure is set as no connection; the connection feature between the third contact hole and the active region and the N-type source / drain injection is set as a connection; and the connection feature between the third contact hole and the P-well is set as a connection. The third contact hole is then characterized with a third preset color.

[0018] Optionally, in the method described above, when the pre-configured observation mode is the second observation mode, the step of performing a first calculation logic setting and color characterization processing on the contact hole at the first preset position in the original design layout according to the connection feature and using the pre-configured observation mode includes:

[0019] When it is determined that the contact hole falling on the gate in the original design layout is the first contact hole and the surface of the first contact hole is a high-potential basic structure, the calculation logic of the first contact hole is set to the connection feature between the first contact hole and the gate structure as having a connection, and the first contact hole is characterized by a second preset color.

[0020] When it is determined that the contact hole falling on the P-type shallowly doped active region in the N-well in the original design layout is the second contact hole and the surface of the second contact hole is a low-potential basic structure, the calculation logic of the second contact hole is set as follows: the connection feature between the second contact hole and the gate structure is not connected; the connection feature between the second contact hole and the active region and the P-type source / drain implantation is connected; and the connection feature between the second contact hole and the N-well or deep N-well is connected. The second contact hole is then characterized by a third preset color.

[0021] When it is determined that the contact hole falling on the N-type shallowly doped active region in the P-well in the original design layout is the third contact hole and the surface of the third contact hole is a basic structure with a medium potential, the calculation logic of the third contact hole is set as follows: the connection feature between the third contact hole and the gate structure is set as no connection; the connection feature between the third contact hole and the active region and the P-type source / drain injection is set as a connection; and the connection feature between the third contact hole and the N-well or deep N-well is set as a connection. The third contact hole is then characterized by a first preset color.

[0022] Optionally, in the method described above, the step of extracting the connection relationships between the contact hole layer, the M metal layers, and the via layer in the layout layer information of the original design layout, and based on the connection relationships, performing a second calculation logic setting and color characterization processing on each of the M metal layers in the contact hole layer image to obtain an image of each metal layer, includes:

[0023] Extract the connection relationship between the contact hole layer and the first metal layer from the layout layer information in the original design layout; and perform a second calculation logic setting and color characterization processing on the first metal layer according to the connection relationship and the contact hole layer image, so as to generate an image of the first metal layer according to the characterized color.

[0024] Extract the connection relationship between the Nth metal layer and the Nth via layer from the layout layer information in the original design layout; perform color characterization processing on the Nth via layer according to the connection relationship to obtain the Nth via layer image; extract the connection relationship between the Nth via layer and the (N+1)th metal layer, and perform the second calculation logic setting and color characterization processing on the (N+1)th metal layer according to the Nth via layer image to generate the (N+1)th metal layer image according to the characterized color; increment N by 1 and repeat the above steps until the Mth metal layer image in the layout layer information of the original design layout is generated;

[0025] Where N is a positive integer, and is initially 1.

[0026] Optionally, in the method described above, the step of performing a second calculation logic setting and color characterization processing on the first metal layer based on the connection relationship and the contact hole layer image to generate a first metal layer image based on the characterized color includes:

[0027] If the image of the contact hole layer that is connected to the second preset position in the metal layer is characterized by the first preset color, then the image color of the second preset position in the first metal layer is characterized by the first preset color.

[0028] If at least one of the characteristic colors of the contact hole layer image corresponding to the second preset position in the metal layer is a third preset color, and there is no second preset color, then the image color of the second preset position in the first metal layer is characterized as the third preset color.

[0029] If at least one of the characteristic colors of the contact hole layer image corresponding to the second preset position in the metal layer is determined to be the second preset color, then the image color of the second preset position in the first metal layer is characterized as the second preset color.

[0030] Optionally, in the method described above, the step of using color contrast technology to perform color contrast processing on the first comparison region image and the second comparison region image to determine whether there are abnormal points in the chip to be detected includes:

[0031] Obtain the pixels of the first comparison region image and the second comparison region image, as well as the pixel values ​​corresponding to the pixels;

[0032] The pixel values ​​corresponding to the pixels in the first and second comparison regions are obtained and then subtracted to obtain the pixel difference value.

[0033] The pixel difference value is compared with a preset threshold to identify abnormal pixels whose pixel difference value is greater than the preset threshold.

[0034] Based on the abnormal pixels, the abnormal points corresponding to the abnormal pixels are marked.

[0035] Secondly, this application provides a chip anomaly detection device, comprising:

[0036] The acquisition module is used to acquire the original design layout of the chip to be tested; and to perform layout analysis processing based on the original design layout to obtain the basic structure and layout layer information in the original design layout.

[0037] The processing module is used to extract the connection features of the basic structure in the original design layout, and based on the connection features, to perform a first calculation logic setting and color characterization processing on the contact holes at the first preset position in the original design layout using a pre-configured observation mode.

[0038] The processing module is further configured to perform voltage contrast calculation processing based on the first calculation logic and the color represented by the contact hole at the first preset position, and obtain a contact hole layer image.

[0039] The processing module is further configured to extract the connection relationships between the contact hole layer, the M metal layers, and the via layer in the layout layer information of the original design layout, and based on the connection relationships, perform a second calculation logic setting and color characterization processing on each of the M metal layers in the contact hole layer image to obtain an image of each metal layer; wherein, the layout layer information includes M metal layers; M is a positive integer;

[0040] The processing module is further configured to select any one of the M metal layers as the metal layer to be detected, and to scan the metal layer to be detected using an electron microscope to obtain an actual voltage contrast image; and to perform shape feature extraction processing on the actual voltage contrast image to obtain a feature pattern.

[0041] The processing module is further configured to use the image of the metal layer to be detected as a theoretical voltage contrast image, and to perform image recognition processing on the actual voltage contrast image and the theoretical voltage contrast image respectively according to the feature pattern, so as to obtain a first comparison region image from the actual voltage contrast image and a second comparison region image from the theoretical voltage contrast image respectively.

[0042] The processing module is further configured to perform color comparison processing on the first comparison area image and the second comparison area image using color comparison technology to determine whether there are any abnormal points in the chip to be detected.

[0043] Thirdly, this application provides an electronic device, including: a processor, and a memory communicatively connected to the processor;

[0044] The memory stores computer-executed instructions;

[0045] The processor executes computer execution instructions stored in the memory to implement the chip anomaly detection method described in any of the above embodiments.

[0046] Fourthly, this application provides a computer-readable storage medium storing computer-executable instructions, which, when executed by a processor, are used to implement the chip anomaly detection method described in any of the above embodiments.

[0047] This application provides a method, apparatus, device, and storage medium for detecting chip anomalies. The method involves acquiring the original design layout of the chip to be detected; performing layout analysis processing on the original design layout to obtain the basic structure and layout layer information; setting first calculation logic and color representation processing for contact holes based on the connection features of the extracted basic structure and a pre-configured observation mode; performing voltage contrast calculation processing on the contact holes in the contact hole layer based on the set first calculation logic and represented colors to obtain a contact hole layer image; and setting second calculation logic and color representation processing for each of the M metal layers based on the connection relationships between the contact hole layer, M metal layers, and via layers in the extracted layout layer information, as well as the contact hole layer image. The process involves feature processing to obtain an image of each metal layer; arbitrarily selecting one metal layer from the M metal layers as the metal layer to be detected, scanning it with an electron microscope to obtain an actual voltage contrast image; extracting shape features from the actual voltage contrast image to obtain a feature pattern; using the metal layer image corresponding to the metal layer to be detected as the theoretical voltage contrast image, and performing image recognition processing on both the actual voltage contrast image and the theoretical voltage contrast image based on the feature pattern, thereby obtaining a first comparison region image from the actual voltage contrast image and a second comparison region image from the theoretical voltage contrast image; and using color contrast technology to perform color contrast processing on the first and second comparison region images to determine whether there are any abnormal points in the chip to be detected. Compared to existing technologies that require manual calculation and derivation of the theoretical voltage contrast of a specific structure based on the voltage contrast imaging principle and the connection relationship between the basic structure of the layout, followed by visual comparison with the voltage contrast image actually generated by an electron microscope to determine anomalies, the method of this application uses the original layout structure and a pre-configured observation mode. It performs a first calculation logic setting and color characterization processing on the contact holes in the original design layout of the chip under test, and obtains the contact hole layer image based on the connection characteristics of the basic structure in the original design layout. Then, based on the connection relationship between the contact hole layer, M metal layers, and via layers, and the contact hole layer image, a second calculation logic setting and color characterization processing are performed to obtain an image of each metal layer as a theoretical voltage contrast image. During the anomaly determination process, feature patterns are obtained through feature extraction to perform image recognition processing on the actual voltage contrast image and the theoretical voltage contrast image, obtaining the corresponding first and second comparison areas. Color contrast technology is used to perform color comparison processing on the first and second comparison area images to determine whether there are anomalies in the chip under test. This invention enables rapid acquisition of theoretical voltage contrast images of the chip under test, as well as rapid identification and judgment of anomalies during the comparison of theoretical and actual voltage contrast images. The method in this application reduces the consumption of manpower and material resources and improves the efficiency of chip anomaly identification. Attached Figure Description

[0048] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0049] Figure 1 A schematic flowchart of an embodiment of a chip anomaly detection method provided in this application;

[0050] Figure 2 A schematic flowchart of another embodiment of the chip anomaly detection method provided in this application;

[0051] Figure 3 A schematic flowchart of another embodiment of the chip anomaly detection method provided in this application;

[0052] Figure 4 A schematic flowchart of another embodiment of the chip anomaly detection method provided in this application;

[0053] Figure 5 A schematic flowchart of another embodiment of the chip anomaly detection method provided in this application;

[0054] Figure 6 A schematic diagram of the structure of one embodiment of the chip anomaly detection device provided in this application;

[0055] Figure 7 This is a schematic diagram of the structure of one embodiment of an electronic device provided in this application.

[0056] The accompanying drawings have illustrated specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to specific embodiments. Detailed Implementation

[0057] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0058] With technological advancements, intelligent products are proliferating. From computers and smartphones to automotive electronics and artificial intelligence, they are now ubiquitous in our lives. Semiconductor chips, as the core component of intelligent products, are crucial for their rapid development. As demands for product quality and reliability continue to rise, failure analysis is becoming increasingly important. Chip failure analysis helps integrated circuit designers identify design flaws, mismatched process parameters, or improper design and operation.

[0059] In chip failure analysis, the most common and basic method is to use an electron microscope to examine the chip structure layer by layer for anomalies. For example, a scanning electron microscope (SEM) is used to scan the chip and generate voltage contrast images. Anomalies are then visually identified by comparison. Alternatively, the theoretical voltage contrast of a specific structure can be manually derived by combining the SEM voltage contrast imaging principle with the structural connections shown in the layout. This theoretical voltage contrast is then visually compared with the actual images to identify anomalies. Another method is to find structures with completely identical connections on the layout and visually compare the voltage imaging results of the two areas under SEM to identify anomalies.

[0060] However, current judgment methods mostly rely on manual derivation and comparison. Simply relying on visual observation not only makes it difficult to quickly assess the structure of large areas, but also makes it difficult to accurately infer the voltage contrast of complex downstream structures. Therefore, this method requires a significant amount of time and effort for analysis and judgment, thus reducing the efficiency of locating anomalies.

[0061] In order to solve the above-mentioned technical problems, the inventive concept of this application is: how to realize automatic identification and judgment of abnormal points, thereby improving the efficiency of locating abnormal points.

[0062] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will now be described with reference to the accompanying drawings.

[0063] Figure 1 This is a schematic flowchart of an embodiment of a chip anomaly detection method provided in this application. Figure 1 As shown, the method includes:

[0064] Step 101: Obtain the original design layout of the chip to be tested; and perform layout analysis processing based on the original design layout to obtain the basic structure and layout layer information in the original design layout.

[0065] In this embodiment, the original design layout of the chip under test is imported using EDA tools and analyzed to identify the basic structures in the original design layout, such as active areas (AA), gates (Poly), contact holes (CT), etc.; as well as the layer information in the original design layout, such as contact hole (CT) layers, metal layers, via layers, etc.

[0066] Step 102: Extract the connection features of the basic structure in the original design layout, and based on the connection features, use a pre-configured observation mode to perform the first calculation logic setting and color characterization processing on the contact holes at the first preset position in the original design layout.

[0067] In this embodiment, for example, the pre-configured observation mode is a pre-configured observation mode based on the SEM voltage contrast imaging principle; the connection features of the basic structure are identified and extracted in the original design layout, the pre-configured observation mode is adopted, the first calculation logic setting corresponding to the contact hole at the first preset position is set according to the extracted connection features, and the calculation is performed according to the calculation logic and the contact hole is color-characterized to obtain the characterization color corresponding to the contact hole.

[0068] Step 103: Based on the first calculation logic and the color represented by the contact hole at the first preset position, perform voltage contrast calculation to obtain the contact hole layer image.

[0069] In this embodiment, logical operations are performed and color characterization is performed based on the first calculation logic set for the contact hole at the first preset position, thereby obtaining the characterization color corresponding to the contact hole at the first preset position in the contact hole layer, and voltage contrast calculation processing is performed to obtain the contact hole layer image.

[0070] Step 104: Extract the connection relationships between the contact hole layer, the M metal layers, and the via layer in the layout layer information of the original design layout. Based on the connection relationships and the contact hole layer image, perform the second calculation logic setting and color characterization processing on each of the M metal layers to obtain the image of each metal layer.

[0071] The layout layer information includes M metal layers; M is a positive integer.

[0072] In this embodiment, the connection relationships between the contact hole layer, the M metal layers, and the via layer are identified and extracted from the layout layer information in the original design layout. For example, the connection relationship between the contact hole layer and the first metal layer, the connection relationship between the first metal layer and the first via layer, the connection relationship between the first via layer and the second metal layer, etc. Based on the above connection relationships and the obtained contact hole layer image, a second calculation logic corresponding to each of the M metal layers is set and black, white, and gray are used for color representation, thereby obtaining the metal layer image corresponding to each metal layer.

[0073] Step 105: Select any one of the M metal layers as the metal layer to be detected, and use an electron microscope to scan the metal layer to be detected to obtain actual voltage contrast images; and perform shape feature extraction processing on the actual voltage contrast images to obtain feature patterns.

[0074] In this embodiment, for example, the second metal layer is selected as the metal layer to be detected; and a scanning electron microscope (SEM) is used to scan the second metal layer of the chip to be detected, thereby generating an actual scanned image of the second metal layer as an actual voltage contrast image; and by performing shape feature extraction processing on the actual voltage contrast image, feature patterns corresponding to specific structures are extracted.

[0075] Step 106: Use the image of the metal layer to be detected as the theoretical voltage contrast image, and perform image recognition processing on the actual voltage contrast image and the theoretical voltage contrast image according to the feature pattern, so as to obtain the first comparison area image from the actual voltage contrast image and the second comparison area image from the theoretical voltage contrast image.

[0076] In this embodiment, for example, the second metal layer is selected as the metal layer to be detected; then the metal layer image corresponding to the second metal layer is obtained as the theoretical voltage contrast image, and according to the feature pattern of the specific structure, image recognition is performed on the actual voltage contrast image and the theoretical voltage contrast image to obtain the first comparison area image and the second comparison area image with the same feature pattern and the same position.

[0077] Step 107: Use color contrast technology to perform color contrast processing on the first comparison area image and the second comparison area image to determine whether there are any abnormal points in the chip to be detected.

[0078] In this embodiment, based on the first comparison region image in the actual voltage contrast image and the second comparison region image in the theoretical voltage contrast image, color contrast technology is used to extract the color features of the same position in the two comparison regions and compare them, thereby obtaining whether there is a color difference in the same position in the first comparison region image and the second comparison region image, and thus confirming whether there are abnormal points in the chip to be detected.

[0079] In this embodiment, the original design layout of the chip to be tested is obtained; layout analysis is performed on the original design layout to obtain the basic structure and layout layer information in the original design layout; then, based on the connection features of the extracted basic structure and the pre-configured observation mode, the contact holes in the contact hole layer are subjected to a first calculation logic setting and color characterization processing to obtain the contact hole layer image; based on the extracted connection relationship between the contact hole layer, M metal layers and via layers, and the contact hole layer image, a second calculation logic setting and color characterization processing are performed on each metal layer to obtain the image of each metal layer; arbitrarily select one metal layer as the metal layer to be tested, and... The metal layer to be tested is scanned using an electron microscope to obtain an actual voltage contrast image. Shape feature extraction is then performed on the actual voltage contrast image to obtain a feature pattern. The metal layer image corresponding to the metal layer to be tested is used as the theoretical voltage contrast image. Based on the feature pattern, image recognition processing is performed on both the actual voltage contrast image and the theoretical voltage contrast image to obtain a first comparison region image from the actual voltage contrast image and a second comparison region image from the theoretical voltage contrast image. Color contrast technology is used to perform color comparison processing on the first and second comparison region images to determine whether there are any abnormalities in the chip to be tested. Compared to existing technologies that require manual calculation and derivation of the theoretical voltage contrast of a specific structure based on the voltage contrast imaging principle of an electron microscope and the connection relationships between the basic structures of the layout, followed by visual comparison with the actual voltage contrast image generated by the electron microscope to determine anomalies, the method of this application uses the original layout structure and a pre-configured observation mode to perform a first calculation logic setting and color characterization processing on the contact holes in the original design layout of the chip to be tested, and obtains the contact hole layer image based on the connection characteristics of the basic structure in the original design layout; then, based on the connection relationships between the contact hole layer, M metal layers and via layers, and the contact hole layer image, a second calculation logic setting and color characterization processing are performed to obtain the image of each metal layer as a theoretical voltage contrast image; in the process of determining anomalies, feature patterns are obtained through feature extraction to perform image recognition processing on the actual voltage contrast image and the theoretical voltage contrast image to obtain the corresponding first comparison area and second comparison area; color contrast technology is used to perform color comparison processing on the images of the first and second comparison areas to determine whether there are anomalies in the chip to be tested. This system enables rapid acquisition of theoretical voltage contrast images of the chip under test, as well as rapid identification and judgment of anomalies during the comparison of theoretical and actual voltage contrast images. It reduces the consumption of manpower and resources and improves the efficiency of chip anomaly identification.

[0080] Figure 2 This is a schematic flowchart of another embodiment of the chip anomaly detection method provided in this application. Figure 2 As shown, based on the above embodiments, when the pre-configured observation mode is the first observation mode, a specific implementation of step 102, "based on the connection characteristics, using the pre-configured observation mode, to perform first calculation logic settings and color characterization processing on the contact holes at the first preset position in the original design layout," includes:

[0081] Step 201: When it is determined that the contact hole falling on the gate in the original design layout is the first contact hole and the surface of the first contact hole is a high-potential basic structure, the calculation logic of the first contact hole is set to the connection feature between the first contact hole and the gate structure as having a connection, and the first contact hole is characterized by a first preset color.

[0082] In this embodiment, for example, in the low voltage observation mode, if the first contact hole falls on the gate in the original design layout, the surface of the first contact hole is considered to be a high-potential basic structure, usually in a floating state, and the corresponding calculation logic is set to the connection feature between the first contact hole (CT) and the gate (Poly) structure as having a connection; at this time, black is used to characterize the first contact hole.

[0083] Step 202: When it is determined that the contact hole falling on the P-type shallowly doped active region in the N-well in the original design layout is the second contact hole and the surface of the second contact hole is a low-potential basic structure, the calculation logic of the second contact hole is set as follows: the connection feature between the second contact hole and the gate structure is not connected; the connection feature between the second contact hole and the active region and the P-type source / drain injection is connected; and the connection feature between the second contact hole and the N-well or deep N-well is connected. The second contact hole is then characterized with a second preset color.

[0084] In this embodiment, if the second contact hole falls on the P-type shallowly doped active region in the N-well of the original design layout, the surface of the second contact hole is considered to be a low-potential basic structure, usually located in the active region, and forms a forward-conducting PN junction with the substrate. The calculation logic of the second contact hole is set to the connection feature between the second contact hole (CT) and the gate (Poly) as non-connection, while the connection feature between the second contact hole (CT) and the active region (AA), the P-type source / drain implantation (SDP), and the N-well or deep N-well is considered to be connected. At this time, white is used to characterize the second contact hole.

[0085] Step 203: When the contact hole on the N-type shallowly doped active region in the P-well in the original design layout is determined to be the third contact hole and the surface of the third contact hole is a basic structure with a medium potential, the calculation logic of the third contact hole is set as follows: the connection feature between the third contact hole and the gate structure is not connected; the connection feature between the third contact hole and the active region and the N-type source / drain injection is connected; and the connection feature between the third contact hole and the P-well is connected. The third contact hole is then characterized with a third preset color.

[0086] In this embodiment, if the third contact hole falls on the N-type lightly doped active region in the P-well of the original design layout, the surface of the third contact hole is considered to be a basic structure with a medium potential, usually located in the active region, and there is a reverse PN junction between it and the substrate. The calculation logic of the third contact hole is set to the connection feature of the third contact hole (CT) and the gate (Poly) as not connected, while the connection feature of the third contact hole (CT) with the active region (AA), N-type source-drain injection (SDN) and P-well (PW) is connected. At this time, gray is used to characterize the third contact hole.

[0087] In this embodiment, if it is determined that the first contact hole falls on the gate in the original design layout and the surface is a high-potential basic structure, the calculation logic for the first contact hole is set to indicate that the connection between the first contact hole and the gate structure is present, and it is characterized by a first preset color. If it is determined that the second contact hole falls on the P-type shallowly doped active region in the N-well of the original design layout and the surface is a low-potential basic structure, the calculation logic for the second contact hole is set and it is characterized by a second preset color. If it is determined that the third contact hole falls on the N-type shallowly doped active region in the P-well of the original design layout and the surface is a medium-potential basic structure, the calculation logic for the third contact hole is set and it is characterized by a third preset color. Compared with the prior art, the method of this application, when the pre-configured observation mode is the first observation mode, uses the pre-configured observation mode combined with the connection characteristics of the basic structure to determine the calculation logic corresponding to the contact hole and perform color characterization processing, which reduces the observation time, improves the observation efficiency, and avoids misjudgment caused by human observation.

[0088] Furthermore, based on the above embodiments, when the pre-configured observation mode is the second observation mode, a specific implementation of step 102, "based on the connection characteristics, using the pre-configured observation mode, performing a first calculation logic setting and color characterization processing on the contact holes at the first preset position in the original design layout," may further include:

[0089] When it is determined that the contact hole falling on the gate in the original design layout is the first contact hole and the surface of the first contact hole is a high-potential basic structure, the calculation logic of the first contact hole is set to the connection feature between the first contact hole and the gate structure as having a connection, and the first contact hole is characterized by a second preset color.

[0090] In this embodiment, for example, in the high-voltage observation mode, if the first contact hole falls on the gate in the original design layout, the surface of the first contact hole is identified as a basic structure with a high potential, usually in a floating state. The connection feature between the first contact hole (CT) and the gate (Poly) structure in the corresponding computational logic is set to be connected. At this time, white is used to characterize the first contact hole.

[0091] When the contact hole on the P-type shallowly doped active region in the N-well in the original design layout is determined to be the second contact hole and the surface of the second contact hole is a low-potential basic structure, the calculation logic of the second contact hole is set as follows: the connection feature between the second contact hole and the gate structure is set to be non-existent; the connection feature between the second contact hole and the active region and the P-type source / drain implantation is set to be present; and the connection feature between the second contact hole and the N-well or deep N-well is set to be present. The second contact hole is then characterized with a third preset color.

[0092] In this embodiment, if the second contact hole falls on the P-type shallowly doped active region in the N-well of the original design layout, the surface of the second contact hole is considered to be a low-potential basic structure, usually located in the active region, and forms a forward-conducting PN junction with the substrate. The calculation logic of the second contact hole is set to the connection feature of the second contact hole (CT) and the gate (Poly) as non-connected, while the connection feature of the second contact hole (CT) with the active region (AA), the P-type source-drain implantation (SDP), and the N-well or deep N-well is respectively considered to be connected. At this time, gray is used to characterize the second contact hole.

[0093] When the contact hole on the N-type shallowly doped active region in the P-well in the original design layout is determined to be the third contact hole and the surface of the third contact hole is a basic structure with a medium potential, the calculation logic of the third contact hole is set as follows: the connection feature between the third contact hole and the gate structure is set to be non-existent; the connection feature between the third contact hole and the active region and the P-type source / drain injection is set to be present; and the connection feature between the third contact hole and the N-well or deep N-well is set to be present. The third contact hole is then characterized with a first preset color.

[0094] In this embodiment, if the third contact hole falls on the N-type lightly doped active region in the P-well of the original design layout, the surface of the third contact hole is considered to be a basic structure with a medium potential, usually located in the active region, and there is a reverse PN junction between it and the substrate. The calculation logic of the third contact hole is set to the connection feature of the third contact hole (CT) and the gate (Poly) as not connected, while the connection feature of the third contact hole (CT) with the active region (AA), N-type source-drain injection (SDN) and P-well (PW) is connected. At this time, black is used to characterize the third contact hole.

[0095] In this embodiment, if it is determined that the first contact hole falls on the gate in the original design layout and the surface is a high-potential basic structure, the calculation logic for the first contact hole is set to indicate that the connection between the first contact hole and the gate structure is present, and it is characterized by a second preset color. If it is determined that the second contact hole falls on the P-type shallowly doped active region in the N-well of the original design layout and the surface is a low-potential basic structure, the calculation logic for the second contact hole is set and it is characterized by a third preset color. If it is determined that the third contact hole falls on the N-type shallowly doped active region in the P-well of the original design layout and the surface is a medium-potential basic structure, the calculation logic for the third contact hole is set and it is characterized by a first preset color. Compared with the prior art, the method of this application, when the pre-configured observation mode is the second observation mode, uses the pre-configured observation mode combined with the connection characteristics of the basic structure to determine the calculation logic corresponding to the contact hole and perform color characterization processing, which reduces the observation time, improves the observation efficiency, and avoids misjudgment caused by human observation.

[0096] Figure 3 This is a schematic flowchart of another embodiment of the chip anomaly detection method provided in this application. Figure 3 As shown, based on the above embodiments, a specific implementation of step 104, "extracting the connection relationships between the contact hole layer, the M metal layers, and the via layer in the layout layer information of the original design layout, and based on the connection relationships and the contact hole layer image, performing second calculation logic settings and color characterization processing on each of the M metal layers to obtain an image of each metal layer," includes:

[0097] Step 301: Extract the connection relationship between the contact hole layer and the first metal layer from the layout layer information in the original design layout; and based on the connection relationship and the contact hole layer image, perform the second calculation logic setting and color characterization processing on the first metal layer to generate the first metal layer image based on the characterized color.

[0098] In this embodiment, the connection relationship between the contact hole layer and the first metal layer is extracted from the layout layer information in the obtained original design layout. Combined with the obtained contact hole layer image, the first metal layer is subjected to a second calculation logic setting and color characterization processing, so as to characterize the color corresponding to the pattern at the corresponding position of the first metal layer according to the characterization color of each contact hole in the contact hole layer image, so as to obtain the image of the first metal layer.

[0099] Step 302: Extract the connection relationship between the Nth metal layer and the Nth via layer from the layout layer information in the original design layout; perform color characterization processing on the Nth via layer according to the connection relationship to obtain the Nth via layer image; extract the connection relationship between the Nth via layer and the N+1th metal layer, and perform second calculation logic setting and color characterization processing on the N+1th metal layer according to the Nth via layer image to generate the N+1th metal layer image according to the characterized color; increment N by 1 and repeat the steps until the Mth metal layer image in the layout layer information in the original design layout is generated.

[0100] Where N is a positive integer, and is initially 1.

[0101] In this embodiment, for example, the connection relationship between the first metal layer and the first via layer is extracted from the original design layout; combined with the obtained image of the first metal layer, the vias in the first via layer are color-coded; the color of the via in the first via layer is consistent with the color of the corresponding position in the lower first metal layer it contacts, thereby obtaining the image of the first via layer; then, the connection relationship between the first via layer and the second metal layer is extracted from the original design layout, and based on the image of the first via layer, the second metal layer is subjected to a second calculation logic setting and color-coding, and an image of the second metal layer is generated. This process is repeated to derive the image of the Mth metal layer corresponding to the Mth metal layer.

[0102] In this embodiment, by combining the connection relationship between the contact hole layer and the first metal layer in the obtained original design layout with the contact hole layer image, the first metal layer is subjected to a second calculation logic setting and color characterization processing to obtain the first metal layer image; then, by combining the connection relationship between the Nth metal layer and the Nth via layer in the obtained original design layout, the Nth via layer image is obtained through color characterization processing; based on the obtained Nth via layer image, and combining the obtained connection relationship between the Nth via layer and the N+1th metal layer, the N+1th metal layer is subjected to a second calculation logic setting and color characterization processing to obtain the N+1th metal layer image; the above steps are repeated until the Mth metal layer image in the original design layout is generated. Compared with the prior art, the method of this application obtains the image of each of the M metal layers by combining the connection relationship between the contact hole layer and the first metal layer, the Nth metal layer and the Nth via layer, and the connection relationship between the Nth via layer and the N+1th metal layer, along with the second calculation logic setting and color characterization processing, and by deriving layer by layer according to the connection relationship between the layers. This method can efficiently generate the image of each metal layer, avoid the tedious layer-by-layer analysis and processing, and improve the efficiency and accuracy of the analysis.

[0103] Figure 4 This is a schematic flowchart of another embodiment of the chip anomaly detection method provided in this application. Figure 4 As shown, based on the above embodiments, a specific implementation of step 301, "based on the connection relationship and the contact hole layer image, performing a second calculation logic setting and color characterization processing on the first metal layer to generate an image of the first metal layer according to the characterized color," includes:

[0104] Step 401: Determine that the representation color of the second preset position corresponding to the contact hole layer image that has a connection relationship with the second preset position in the metal layer is the first preset color. Then, the image color of the second preset position in the first metal layer is represented by the first preset color.

[0105] In this embodiment, for example, for the second preset position in the first metal layer, the characterization color of the corresponding second preset position in the contact hole layer image is obtained based on the connection relationship between the first metal layer and the contact hole layer and the contact hole layer image. If the characterization colors of the corresponding second preset positions in the contact hole layer image are all black, then the image color of the second preset position in the first metal layer is black.

[0106] Step 402: If the image of the contact hole layer that is connected to the second preset position in the metal layer has at least one of the representation colors of the second preset position that is a third preset color, and there is no second preset color, then the image color of the second preset position in the first metal layer is represented by the third preset color.

[0107] In this embodiment, for example, for the obtained second preset position in the first metal layer, the characterization color of the corresponding second preset position in the contact hole layer image is obtained according to the connection relationship between the first metal layer and the contact hole layer and the contact hole layer image. If at least one of the characterization colors of the corresponding second preset position in the contact hole layer image is gray and no white is present, then the image color of the second preset position in the first metal layer is gray.

[0108] Step 403: If at least one of the characterization colors of the contact hole layer image corresponding to the second preset position in the metal layer is determined to be the second preset color, then the image color of the second preset position in the first metal layer is characterized as the second preset color.

[0109] In this embodiment, for example, for the obtained second preset position in the first metal layer, the characterization color of the corresponding second preset position in the contact hole layer image is obtained according to the connection relationship between the first metal layer and the contact hole layer and the contact hole layer image. If at least one of the characterization colors of the corresponding second preset position in the contact hole layer image is white, then the image color of the second preset position in the first metal layer is white.

[0110] In this embodiment, based on the connection relationship between the first metal layer and the contact hole layer, and the contact hole layer image, the first metal layer undergoes a second calculation logic setting and color characterization processing. If the characterization color of the contact hole layer image corresponding to the second preset position in the metal layer that is connected to the second preset position in the metal layer is determined to be a first preset color, then the image color of the second preset position in the first metal layer is characterized as the first preset color. If at least one characterization color is a third preset color, and no second preset color exists, then the image color of the second preset position in the first metal layer is characterized as the third preset color. If at least one characterization color is a second preset color, then the image color of the second preset position in the first metal layer is characterized as the second preset color. Compared to the prior art, the method of this application, based on the connection relationship between the first metal layer and the contact hole layer, and the generated contact hole layer image, performs color characterization according to the pre-configured second calculation logic to obtain the metal layer image corresponding to the first metal layer, thereby improving the accuracy of color characterization and reducing the possibility of misjudgment and omission when judging abnormal points in subsequent comparison processes.

[0111] Figure 5 This is a schematic flowchart of another embodiment of the chip anomaly detection method provided in this application. Figure 5 As shown, based on the above embodiments, a specific implementation of step 107, "using color contrast technology to perform color contrast processing on the first comparison region image and the second comparison region image to determine whether there are abnormal points in the chip to be detected," includes:

[0112] Step 501: Obtain the pixels of the first comparison region image and the second comparison region image, as well as the pixel values ​​corresponding to the pixels.

[0113] In this embodiment, the pixel point (i.e., position information) and the pixel value (i.e., color information) at each position are extracted from the first comparison region image and the second comparison region image.

[0114] Step 502: Obtain the pixel values ​​corresponding to the pixels in the first comparison region image and the second comparison region image, and perform subtraction to obtain the pixel difference value.

[0115] In this embodiment, pixels at the same position are selected from the first and second comparison region images, respectively. For each selected pixel, the corresponding pixel value in the first and second comparison region images is obtained. For each selected pixel, the pixel difference value corresponding to the first comparison region image is subtracted from the pixel value corresponding to the first comparison region image.

[0116] Step 503: Compare the pixel difference value with a preset threshold to obtain abnormal pixels whose pixel difference value is greater than the preset threshold.

[0117] In this embodiment, for example, an appropriate contrast parameter can be set as a preset threshold based on the imaging characteristics of the voltage contrast image and the possible features of abnormal points; the pixel difference value is compared with the preset threshold. If the pixel difference value is less than or equal to the preset threshold, the pixel is determined to be a normal pixel; if the pixel difference value is greater than the preset threshold, the pixel is determined to be an abnormal pixel.

[0118] Step 504: Mark the abnormal points corresponding to the abnormal pixels.

[0119] In this embodiment, abnormal pixels are obtained, and the abnormal points corresponding to the abnormal pixels are marked using a labeling method and displayed in the image.

[0120] In this embodiment, pixels and corresponding pixel values ​​of a first and a second comparison region image are acquired. The pixel values ​​corresponding to the pixels in the first and second comparison region images are then subtracted to obtain a pixel difference value. This pixel difference value is compared with a preset threshold to identify abnormal pixels whose difference value exceeds the threshold, and these abnormal pixels are then marked. Compared to existing technologies, this method uses color contrast technology to determine and mark abnormal points by comparing the pixel value difference between each pixel in the two comparison region images with a preset threshold. This enables rapid identification and automatic location of abnormal points, allowing analysts to quickly identify abnormal areas, reducing the time required for manual visual identification, and improving the efficiency of abnormal point determination.

[0121] Figure 6 This is a schematic diagram of one embodiment of a chip anomaly detection device provided in this application. Figure 6 As shown, the device 70 includes: an acquisition module 71 and a processing module 72.

[0122] The acquisition module 71 is used to acquire the original design layout of the chip to be tested; and to perform layout analysis processing based on the original design layout to obtain the basic structure and layout layer information in the original design layout.

[0123] The processing module 72 is used to extract the connection features of the basic structure in the original design layout, and based on the connection features, adopt a pre-configured observation mode to perform the first calculation logic setting and color characterization processing on the contact holes at the first preset position in the original design layout.

[0124] The processing module 72 is also used to perform voltage contrast calculation processing based on the first calculation logic and the color represented by the contact hole at the first preset position, and to obtain the contact hole layer image.

[0125] The processing module 72 is also used to extract the connection relationships between the contact hole layer, the M metal layers and the via layer in the layout layer information of the original design layout, and based on the connection relationships and the contact hole layer image, to perform a second calculation logic setting and color characterization processing on each of the M metal layers to obtain an image of each metal layer; wherein, the layout layer information includes M metal layers; M is a positive integer;

[0126] The processing module 72 is also used to select any one of the M metal layers as the metal layer to be detected, and to use an electron microscope to scan the metal layer to be detected to obtain actual voltage contrast images respectively; and to perform shape feature extraction processing on the actual voltage contrast images to obtain feature patterns.

[0127] The processing module 72 is further configured to use the image of the metal layer to be detected as a theoretical voltage contrast image, and to perform image recognition processing on the actual voltage contrast image and the theoretical voltage contrast image respectively according to the feature pattern, so as to obtain the first comparison area image from the actual voltage contrast image and the second comparison area image from the theoretical voltage contrast image respectively.

[0128] The processing module 72 is also used to perform color comparison processing on the first comparison area image and the second comparison area image using color comparison technology to determine whether there are any abnormal points in the chip to be detected.

[0129] The chip anomaly detection and processing device provided in this application embodiment can execute the technical solution shown in the above method embodiment. Its implementation principle and beneficial effects are similar, and will not be described again here.

[0130] Figure 7 This is a schematic diagram of the structure of one embodiment of an electronic device provided in this application. Figure 7 A schematic diagram of the structure of an embodiment of an electronic device provided in this application is shown below. Figure 7 As shown, the electronic device 80 may include a processor 81 and a memory 82.

[0131] The processor 81 is communicatively connected to the memory 82, which stores computer execution instructions. The processor 81 is configured to execute the technical solutions in any of the foregoing method embodiments by executing the computer execution instructions stored in the memory 82.

[0132] Optionally, the memory 82 can be either standalone or integrated with the processor 81. Optionally, when the memory 82 is a device independent of the processor 81, the electronic device 80 may further include a bus for connecting the aforementioned devices.

[0133] The electronic device is used to execute the technical solutions in any of the foregoing method embodiments. Its implementation principle and technical effect are similar, and will not be described again here.

[0134] This application also provides a computer-readable storage medium storing computer-executable instructions. When these instructions are executed by a processor, they are used to implement the above-described method. The implementation principle and technical effects are similar and will not be repeated here.

[0135] Specifically, the computer-readable storage medium may include various media capable of storing computer-executable instructions, such as USB flash drives, portable hard drives, read-only memory (ROM), RAM, disks, or optical discs. Specifically, the computer-readable storage medium stores computer-executable instructions, which, when executed by a computer, cause the technical solution shown in the above method embodiments to be executed. The specific implementation methods and technical effects are similar and will not be repeated here.

[0136] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0137] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0138] It should be understood that the above-described device embodiments are merely illustrative, and the device of this application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units, modules, or components may be combined, or integrated into another system, or some features may be ignored or not executed.

[0139] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this application can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.

[0140] When an integrated unit / module is implemented in hardware, the hardware can be digital circuits, analog circuits, etc. The physical implementation of the hardware structure includes, but is not limited to, transistors, etc. Unless otherwise specified, the processor can be any suitable hardware processor, such as a CPU, GPU, FPGA, DSP, and ASIC, etc. Unless otherwise specified, the storage unit can be any suitable Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Enhanced Dynamic Random Access Memory (EDRAM), High-Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), etc.

[0141] If the integrated unit / module is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a memory and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned memory includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0142] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0143] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0144] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A method for detecting chip anomalies, characterized in that, include: Obtain the original design layout of the chip to be tested; The original design layout is then analyzed to obtain its basic structure and layout layering information. Extract the connection features of the basic structure in the original design layout, and based on the connection features, use a pre-configured observation mode to perform a first calculation logic setting and color characterization processing on the contact holes at the first preset position in the original design layout; Based on the first calculation logic and the represented color of the contact hole at the first preset position, voltage contrast calculation is performed to obtain the contact hole layer image; The connection relationships between the contact hole layer, the M metal layers, and the via layer in the layout layer information of the original design layout are extracted respectively. Based on the connection relationships, the contact hole layer image is used to perform a second calculation logic setting and color characterization processing on each of the M metal layers to obtain an image of each metal layer. The layout layer information includes M metal layers, where M is a positive integer. Select any one of the M metal layers as the metal layer to be detected, and use an electron microscope to scan the metal layer to be detected to obtain an actual voltage contrast image; and perform shape feature extraction processing on the actual voltage contrast image to obtain a feature pattern. The image of the metal layer to be detected is used as the theoretical voltage contrast image. Based on the feature pattern, image recognition processing is performed on the actual voltage contrast image and the theoretical voltage contrast image respectively, so as to obtain the first comparison region image from the actual voltage contrast image and the second comparison region image from the theoretical voltage contrast image respectively. Color contrast technology is used to perform color comparison processing on the first comparison area image and the second comparison area image to determine whether there are any abnormal points in the chip to be detected.

2. The method according to claim 1, characterized in that, When the pre-configured observation mode is the first observation mode, the step of performing a first calculation logic setting and color characterization processing on the contact holes at the first preset position in the original design layout according to the connection characteristics and using the pre-configured observation mode includes: When it is determined that the contact hole falling on the gate in the original design layout is the first contact hole and the surface of the first contact hole is a high-potential basic structure, the calculation logic of the first contact hole is set to the connection feature between the first contact hole and the gate structure as having a connection, and the first contact hole is characterized by a first preset color. When it is determined that the contact hole falling on the P-type shallowly doped active region in the N-well in the original design layout is the second contact hole and the surface of the second contact hole is a low-potential basic structure, the calculation logic of the second contact hole is set as follows: the connection feature between the second contact hole and the gate structure is not connected; the connection feature between the second contact hole and the active region and the P-type source / drain implantation is connected; and the connection feature between the second contact hole and the N-well or deep N-well is connected. The second contact hole is then characterized by a second preset color. When it is determined that the contact hole falling on the N-type shallowly doped active region in the P-well in the original design layout is the third contact hole and the surface of the third contact hole is a basic structure with a medium potential, the calculation logic of the third contact hole is set as follows: the connection feature between the third contact hole and the gate structure is set as no connection; the connection feature between the third contact hole and the active region and the N-type source / drain injection is set as a connection; and the connection feature between the third contact hole and the P-well is set as a connection. The third contact hole is then characterized with a third preset color.

3. The method according to claim 1, characterized in that, When the pre-configured observation mode is the second observation mode, the step of performing a first calculation logic setting and color characterization processing on the contact holes at the first preset position in the original design layout according to the connection characteristics and using the pre-configured observation mode includes: When it is determined that the contact hole falling on the gate in the original design layout is the first contact hole and the surface of the first contact hole is a high-potential basic structure, the calculation logic of the first contact hole is set to the connection feature between the first contact hole and the gate structure as having a connection, and the first contact hole is characterized by a second preset color. When it is determined that the contact hole falling on the P-type shallowly doped active region in the N-well in the original design layout is the second contact hole and the surface of the second contact hole is a low-potential basic structure, the calculation logic of the second contact hole is set as follows: the connection feature between the second contact hole and the gate structure is not connected; the connection feature between the second contact hole and the active region and the P-type source / drain implantation is connected; and the connection feature between the second contact hole and the N-well or deep N-well is connected. The second contact hole is then characterized by a third preset color. When it is determined that the contact hole falling on the N-type shallowly doped active region in the P-well in the original design layout is the third contact hole and the surface of the third contact hole is a basic structure with a medium potential, the calculation logic of the third contact hole is set as follows: the connection feature between the third contact hole and the gate structure is set as no connection; the connection feature between the third contact hole and the active region and the P-type source / drain injection is set as a connection; and the connection feature between the third contact hole and the N-well or deep N-well is set as a connection. The third contact hole is then characterized by a first preset color.

4. The method according to any one of claims 1 to 3, characterized in that, The process involves extracting the connection relationships between the contact hole layer, the M metal layers, and the via layer in the layout layer information of the original design layout, and based on these connection relationships, performing a second calculation logic setting and color characterization processing on each of the M metal layers in the contact hole layer image to obtain an image of each metal layer, including: Extract the connection relationship between the contact hole layer and the first metal layer from the layout layer information in the original design layout; and perform a second calculation logic setting and color characterization processing on the first metal layer according to the connection relationship and the contact hole layer image, so as to generate an image of the first metal layer according to the characterized color. Extract the connection relationship between the Nth metal layer and the Nth via layer from the layout layer information in the original design layout; perform color characterization processing on the Nth via layer according to the connection relationship to obtain the Nth via layer image; extract the connection relationship between the Nth via layer and the (N+1)th metal layer, and perform the second calculation logic setting and color characterization processing on the (N+1)th metal layer according to the Nth via layer image to generate the (N+1)th metal layer image according to the characterized color; increment N by 1 and repeat the above steps until the Mth metal layer image in the layout layer information of the original design layout is generated; Where N is a positive integer, and is initially 1.

5. The method according to claim 4, characterized in that, The step of performing a second calculation logic setting and color characterization processing on the first metal layer based on the connection relationship and the contact hole layer image, to generate an image of the first metal layer based on the characterized color, includes: If the image of the contact hole layer that is connected to the second preset position in the metal layer is characterized by the first preset color, then the image color of the second preset position in the first metal layer is characterized by the first preset color. If at least one of the characteristic colors of the contact hole layer image corresponding to the second preset position in the metal layer is a third preset color, and there is no second preset color, then the image color of the second preset position in the first metal layer is characterized as the third preset color. If at least one of the characteristic colors of the contact hole layer image corresponding to the second preset position in the metal layer is determined to be the second preset color, then the image color of the second preset position in the first metal layer is characterized as the second preset color.

6. The method according to claim 5, characterized in that, The step of using color contrast technology to perform color comparison processing on the first and second comparison region images to determine whether the chip to be detected has any abnormalities includes: Obtain the pixels of the first comparison region image and the second comparison region image, as well as the pixel values ​​corresponding to the pixels; The pixel values ​​corresponding to the pixels in the first and second comparison regions are obtained and then subtracted to obtain the pixel difference value. The pixel difference value is compared with a preset threshold to identify abnormal pixels whose pixel difference value is greater than the preset threshold. Based on the abnormal pixels, the abnormal points corresponding to the abnormal pixels are marked.

7. A chip anomaly detection device, characterized in that, include: The acquisition module is used to acquire the original design layout of the chip under test; The original design layout is then analyzed to obtain its basic structure and layout layering information. The processing module is used to extract the connection features of the basic structure in the original design layout, and based on the connection features, to perform a first calculation logic setting and color characterization processing on the contact holes at the first preset position in the original design layout using a pre-configured observation mode. The processing module is further configured to perform voltage contrast calculation processing based on the first calculation logic and the color represented by the contact hole at the first preset position, and obtain a contact hole layer image. The processing module is further configured to extract the connection relationships between the contact hole layer, the M metal layers, and the via layer in the layout layer information of the original design layout, and based on the connection relationships, perform a second calculation logic setting and color characterization processing on each of the M metal layers in the contact hole layer image to obtain an image of each metal layer; wherein, the layout layer information includes M metal layers; M is a positive integer; The processing module is further configured to select any one of the M metal layers as the metal layer to be detected, and to scan the metal layer to be detected using an electron microscope to obtain an actual voltage contrast image; and to perform shape feature extraction processing on the actual voltage contrast image to obtain a feature pattern. The processing module is further configured to use the image of the metal layer to be detected as a theoretical voltage contrast image, and to perform image recognition processing on the actual voltage contrast image and the theoretical voltage contrast image respectively according to the feature pattern, so as to obtain a first comparison region image from the actual voltage contrast image and a second comparison region image from the theoretical voltage contrast image respectively. The processing module is further configured to perform color comparison processing on the first comparison area image and the second comparison area image using color comparison technology to determine whether there are any abnormal points in the chip to be detected.

8. An electronic device, characterized in that, include: A processor, and a memory communicatively connected to the processor; The memory stores computer-executed instructions; The processor executes computer execution instructions stored in the memory to implement the method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, are used to implement the method as described in any one of claims 1 to 6.

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