Circuit diagram-to-netlist generation method based on deep learning, generation system and product

Abstract

The invention relates to a circuit diagram-to-netlist generation method and system based on deep learning and a product. The circuit diagram-to-netlist generation method comprises the following steps: S1, identifying devices in a circuit diagram through a YOLOv8 model to obtain position information and category of each device; identifying a straight line segment in the circuit diagram through a probabilistic Hough transform algorithm to obtain a starting point coordinate, an end point coordinate and an orientation corresponding to the straight line segment; and S2, generating corresponding text description information according to the position information, the category, the starting point coordinate, the end point coordinate and the orientation. According to the method, by effectively integrating multi-modal information and combining image and text data, comprehensive understanding of a circuit diagram is provided, the recognition accuracy and robustness are improved, even if a single component has a recognition error, the influence of noise on the whole model can still be reduced through final information fusion, and the recognition accuracy and robustness are improved. Therefore, misjudgment and missed judgment in recognition are reduced, and the recognition accuracy of the element and the connection relation is remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of circuit design technology, and in particular to a method, system, and product for generating a circuit diagram into a netlist based on deep learning. Background Art

[0002] Advances in deep learning technology have not only improved the accuracy and efficiency of image recognition but also opened up new possibilities for intelligent circuit design and analysis tools. By combining the strengths of CNN and Transformer models, researchers have developed more intelligent and efficient circuit recognition and analysis systems to meet the complex demands of modern electronic design. Identifying and analyzing electronic components and their connections is a critical task in electronic design automation (EDA) and circuit design. Existing circuit recognition and analysis technologies primarily rely on single-modal information processing. This approach can suffer from reduced recognition accuracy when processing complex circuit diagrams due to a lack of multimodal information fusion. In complex circuit environments, single-modal information processing may not fully capture all information in the circuit diagram. Individual components may suffer from noise interference in the original data, leading to performance degradation. Furthermore, the dataset may be heavily reliant on a single piece of data, lacking generalization capabilities. Furthermore, when combining information from images, text, and other data sources, the fragmented nature of each step hinders information utilization. This lack of multimodal information fusion can lead to misidentifications and missed detections, primarily manifesting as misidentifications of single-modal information that can impact subsequent work. Summary of the Invention

[0003] Based on this, it is necessary to provide a circuit diagram to netlist generation method, generation system and product based on deep learning to address the problem that existing circuit identification and analysis technologies mainly rely on single-mode information processing, which may cause incorrect identification or misjudgment when processing complex circuit diagrams.

[0004] In a first aspect, the present invention proposes a method for generating a circuit diagram into a netlist based on deep learning, which comprises the following steps:

[0005] S1. Use the YOLOv8 model to identify the devices in the circuit diagram and obtain the location information and category of each device. Use the probabilistic Hough transform algorithm to identify the straight line segments in the circuit diagram and obtain the corresponding starting coordinates, end coordinates, and orientation of the straight line segments.

[0006] S2. Generate corresponding text description information based on the location information, category, starting point coordinates, end point coordinates, and orientation; extract all text description information through the word feature extraction model to generate word vectors; and extract the features of the circuit diagram through the image feature extraction model to generate image vectors.

[0007] S3. Concatenate word vectors and image vectors to obtain multimodal features; fuse multimodal features through the Distilbert model to obtain fused features; cluster the fused features through the HDBSCAN model to determine the positional relationship between each device and the straight line segment, and then generate a netlist.

[0008] In a second aspect, the present invention further proposes a deep learning-based circuit diagram to netlist generation system, which uses the deep learning-based circuit diagram to netlist generation method of the first aspect. The circuit diagram to netlist generation system includes a recognition module, a feature processing module, a fusion module, and a clustering module.

[0009] Among them, the recognition module is used to identify the circuit diagram and obtain the location information, category and confidence of each device, as well as the starting point coordinates, end point coordinates and direction corresponding to the straight line segment.

[0010] The feature processing module is used to generate corresponding text description information from location information, category and confidence, starting point coordinates, end point coordinates and orientation, and to segment and encode all text description information to generate word vectors; it is also used to extract features of circuit diagrams to generate image vectors.

[0011] The fusion module is used to concatenate word vectors and image vectors to obtain multimodal features; it is also used to deeply fuse multimodal features to obtain fused features.

[0012] The clustering module is used to dynamically generate two key parameters and form clusters, and perform cluster analysis on the fusion features; it is also used to generate a netlist based on the cluster analysis results.

[0013] In a third aspect, the present invention further proposes a software program product comprising program instructions, which, when run on an electronic device, enables the electronic device to execute the steps of the circuit diagram to netlist generation method based on deep learning in the first aspect.

[0014] The beneficial effects of the present invention are:

[0015] 1. The present invention provides a comprehensive understanding of circuit diagrams by effectively integrating multimodal information and combining image and text data. It can more effectively combine images and text to improve recognition accuracy and robustness. Even if a single component has recognition errors (such as the Hough transform identifying extra straight lines or misidentifying straight lines), the final information fusion can still reduce the impact of these noises on the overall model, thereby reducing misjudgments and missed judgments in recognition and significantly improving the recognition accuracy of components and connection relationships.

[0016] 2. The present invention can automatically generate the netlist of the electronic circuit, reducing manual intervention and eliminating the need for special operations on the data, such as tedious operations such as denoising and dotting, thereby significantly improving the degree of automation of circuit identification and analysis.

[0017] 3. The present invention can maintain high performance in complex circuit environments and can adapt to a variety of application scenarios. The present invention adopts an integrated structure and can predict any input circuit diagram, that is, no special processing of the original circuit diagram is required, and its generalization ability is strong. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 Flowchart of the circuit diagram to netlist generation method based on deep learning;

[0020] Figure 2 Schematic diagram of the inference when identifying devices for the YOLOv8 model;

[0021] Figure 3 This is a schematic diagram of the effect of the probabilistic Hough transform algorithm when identifying straight line segments;

[0022] Figure 4 Flowchart for training the HDBSCAN model. DETAILED DESCRIPTION

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0024] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0025] This invention combines the YOLOv8 model, the probabilistic Hough transform algorithm, the BERT model, the ViT model, and the Distilbert model in the circuit identification and analysis process. The identification information from the YOLOv8 model and the probabilistic Hough transform algorithm is converted into text. The output of the ViT model is used as image information. The text and image information are then fed into the Distilbert model for attention calculation. Finally, the fused features are fed into the HDBSCAN model for clustering, thereby forming the final netlist.

[0026] The specific processing process is introduced below:

[0027] like Figure 1 As shown, this embodiment provides a method for generating a circuit diagram to a netlist based on deep learning, which includes the following steps:

[0028] S1. Identification of information in circuit diagrams, including: (1) Identification of components in circuit diagrams; (2) Identification of straight line segments in circuit diagrams. The following describes these two aspects separately:

[0029] (1) Identification of components in circuit diagrams: The YOLOv8 model uses a convolutional neural network to identify components in circuit diagrams and obtain the location information, category, and confidence level of each component, such as Figure 2 As shown in the figure, the confidence prediction results are filtered using the common method of the YOLOv8 model, with a general confidence threshold of 0.35 and an IOU threshold of 0.45.

[0030] (2) Identification of straight line segments in circuit diagrams: Figure 3 As shown, in order to obtain a higher quality straight line detection effect, the probabilistic Hough Transform algorithm is used to identify the straight line segments in the circuit diagram to obtain the starting point coordinates, end point coordinates and direction of the straight line segments. The method for obtaining the direction of the straight line segment includes the following steps:

[0031] (2.1) The starting coordinates of a line segment are A(x1, y1), and the ending coordinates are B(x2, y2). Calculate the slope k of the line segment based on the starting and ending coordinates.

[0032] (2.2) Determine the direction of the straight line segment based on k. When the deviation of the straight line segment is within the threshold, the straight line segment is still considered to belong to the current closest direction. For example, when y1 = y2, or |y1 - y2| < 2, the straight line segment is identified as horizontal. When x1 = x2, or |x1 - x2| < 2, the straight line segment is identified as vertical. In Python, the following method can be used for processing:

[0033]

[0034] This reduces the errors caused by image recognition.

[0035] S2. First, the location information, category, confidence, starting point coordinates, end point coordinates and orientation are used to generate corresponding text description information. The common part of the text description information is predefined, and the following is the predefined code description of the PMOS device and port:

[0036]

[0037]

[0038] The following are the predefined line segment descriptions:

[0039] line_text=f"Line{index}:The coordinates of the connection lines isfrom[{x1},{y1}]to[{x2},{y2}],and the direction of the line is{direction}"

[0040] Specifically, we predefine the device text template and the line segment text template. When the YOLOv8 model and the probabilistic Hough transform algorithm generate results, they are automatically populated with the device's location information, category, and confidence level. The following is a partial description generated when the YOLOv8 model detects a PMOS device and port:

[0041] The node 7of Source terminal is located within the bounding boxdefined by coordinates from[152,133]to[209,206],belonging to the class ofPMOS,and is typically positioned at the top of the box with a symbol of arrowpointing inwards

[0042] The start and end coordinates and orientation of the line segment are filled into the corresponding parts of the line segment text template. The following is the description generated when the probabilistic Hough transform algorithm detects a line segment (the description shown here is the description of the vertical line):

[0043] Line 4:The coordinates of the connection lines is from[482,154]to[482,59],and the direction of the line is vertical

[0044] This generates the corresponding text description information for subsequent processing. Furthermore, to simplify device port identification, all device ports are described in a strict order. To unify all power supply VDD or ground terminals GND, multiple targets are described only once when describing these two devices, but all their location information is included. For example, GND and VDD are recorded with only one label, with VDD being 0 and GND being 1 in the description, but the two devices will still be described multiple times with their location information.

[0045] Then all the text description information is extracted through the word feature extraction model to generate a word vector. The features of the circuit diagram are extracted through the image feature extraction model to generate a picture vector. In this embodiment, the word feature extraction model can adopt the BERT model. The picture feature extraction model can adopt the ViT (Vision Transformer) model. Among them, all the text description information is segmented and encoded by the BERT model to generate a word vector including all the text description information, which can capture the semantics and contextual information of the text and be used for subsequent fusion with the feature information of the image. The circuit diagram is evenly divided into 196 small blocks of 14*14 specifications using the ViT model. Each small block corresponds to a 768-dimensional picture vector. These picture vectors are used for subsequent processing.

[0046] S3. Add the corresponding modal flag 0 or 1 and the corresponding position information to the word vector and image vector, respectively, and concatenate the word vector and image vector. That is, concatenate 1 word vector and 196 image vectors to obtain a multimodal feature with a length of 197. At the same time, to unify the multimodal features and the input length of the cross-modal attention layer in the Distilbert model, the end of the multimodal features is padded and the corresponding Attention-Mask mechanism is set to ensure that the attention mechanism in the Distilbert model can focus on key information and block out the padded information. Finally, the multimodal features are input into the Distilbert model for processing to obtain fused features.

[0047] Then, the HDBSCAN model is used to generate the connection relationship in the netlist based on the fusion features. The HDBSCAN model constructs a mutual accessibility graph of sample points and combines the minimum spanning tree principle to adaptively discover clusters of points with different density distributions. This feature makes it particularly suitable for identifying connection nodes with irregular distribution characteristics in circuit diagrams. Specifically, when the fusion features are input into the HDBSCAN model to generate the netlist, the fusion features are first input into the MLP to dynamically generate the key parameter size. min , Key parameter 2 samples min . Among them: size min Indicates the minimum cluster size (the minimum number of points required to form a cluster, i.e. the minimum scale). min Indicates the minimum number of samples (the radius of a point is based on the distance to its nearest neighbor, such as samples min is 3, then take the third neighbor as the basis). Then the size generated min 、samples min Together with the fused features, these are input into the HDBSCAN model for clustering, ensuring that ports within the same cluster are connected together. The first 197 output results are described and the final netlist is generated. Since the BERT model only outputs one word vector for subsequent interaction with the 196 image vectors, the clustering results only need to focus on the first 197 results. Subsequent regions are filled in and therefore do not need to be considered. The following is a description of clustering, using PMOS as an example:

[0048]

[0049]

[0050] The final generated netlist description is as follows:

[0051] {'ckt_netlist':[{'component_type':'PMOS','port_connection':{'Drain':'0','Gate':'0','Source':'4'}},{'component_type':'PMOS','port_connection':{'Drain':'0','Gate':'4','Source':'2'}},{'component_type':'NMOS','port_connection':{'Drain':'0','Gate':'3','Source':'1'}},{'component_type':'PMOS','port_connection':{'Drain':'4','Gate':'2','Source':'4'}},{'component_type':'NMOS','port_connection':{'Drain':'3','Gate':'2','Source':'3'}},{'component_type':'NMOS','port_connection':{'Drain':'2','Gate':'2','Source':'2'}},{'component_type':'NMOS','port_connection':{'Drain':'0','Gate':'4','Source':'2'}},{'component_type':'NMOS','port_connection':{'Drain':'4','Gate':'3','Source':'2'}},{'component_type':'Res','port_connection':{'Neg':'1','Pos':'3'}},{'component_type':'Res','port_connection':{'Neg':'0','Pos':'4'}},{'component_type':'Cap','port_connection':{'Neg':'4','Pos':'3'}}],'ckt_type':'SISO-Amplifier'}

[0052] To this end, the present invention combines technologies such as the YOLOv8 model, the probabilistic Hough transform algorithm, the BERT model, the ViT model, and the Distilbert model, and automatically generates the netlist of electronic circuits through the HDBSCAN clustering algorithm. Through this innovative combination of technologies, the present invention not only improves the speed and accuracy of circuit identification, but also reduces the need for manual intervention, promoting the automation process of circuit design and analysis.

[0053] On the other hand, it should be noted that, with the exception of the HDBSCAN model, all other models used in the deep learning-based circuit diagram-to-netlist generation method are pre-trained models from existing technologies. To obtain a higher-quality YOLOv8 model, the YOLOv8 model itself is augmented with data and fine-tuned based on the official pre-trained weights. Specifically, the fine-tuning process includes the following steps: first, images containing interference items, such as three-terminal resistors and capacitors, are removed. Then, 2,000 simulated circuit diagrams are divided into a training set and a validation set in a ratio of 7:3 as training samples. Finally, the final YOLOv8 model is obtained through 300 rounds of training.

[0054] For the HDBSCAN model, the traditional graph edit distance is not differentiable (the traditional method involves abstract operations such as insertion and deletion that are difficult to represent), and it is difficult to directly use it for training deep learning networks. Therefore, the total loss value GED and policy gradient are used to train the HDBSCAN model. In general, GED is converted into a computable form and combined with the policy gradient method to optimize the learning network of two key parameters in the HDBSCAN model. In this embodiment, the training method of the HDBSCAN model includes the following steps:

[0055] S11. Set the device type processing order in the circuit diagram, such as ['net', 'pmos', 'nmos', 'res', 'cap', 'ind', 'diode', 'vsource', 'isource', 'pnp', 'npn', 'diso', 'dido', 'siso']. These predefined types will be mapped to the corresponding numerical indexes 0, 1, 2, 3, ..., 14.

[0056] S12. Predict the number of device type t, count1(t), and compare it with the actual number of device type t, count2(t). Calculate the loss of device type t, type_diff(t). The calculation formula is:

[0057] type_diff(t)=count1(t)-count2(t) / (count1(t)+count2(t)).

[0058] At the same time, in order to prevent negative numbers, the absolute value of the numerator is taken to ensure that type_diff(t) is a positive number.

[0059] When processing large and small circuits (large and small are divided based on the number of certain node types), the absolute difference tends to penalize the large circuit. For example, if count1(t) = 100 and count2(t) = 101 for a large circuit, its absolute difference is 1. For a small circuit, count1(t) = 1 and count2(t) = 2, its absolute difference is also 1. However, the relative difference of the small circuit is greater, making it more fair. This approach ensures fair treatment of different circuits.

[0060] S13, accumulate type_diff(1), type_diff(2), ..., type_diff(T) of T device types, t∈[1,T]. And convert it into tensor form. Since the accumulated value will increase, it will make the network difficult to train (such as gradient explosion). Finally, the accumulated value is normalized to ensure stability, and the total loss value GED is obtained, as shown in the following example: Figure 4 As shown, this avoids gradient explosion.

[0061] Regarding policy gradients, due to the non-differentiability of the HDBSCAN model, its clustering process involves discrete decisions (such as whether a point is a core point or a noise point). These decisions are non-differentiable, and the gradient cannot be propagated from the loss all the way back to the network. Therefore, it is necessary to convert this into a reinforcement learning problem and use policy gradients to address the non-differentiability of the HDBSCAN model. This includes the following steps:

[0062] S14. Obtain the two key parameters of the HDBSCAN model through torch.sigmoid(raw_params[0][0]) and torch.sigmoid(raw_params[0][1]) and convert them into probability form. Then use torch.log form to calculate the corresponding logarithmic probability: log size min 、log samples min .

[0063] S15. Take the negative of GED as the reward value, and define reward = -loss.detach(), that is, the lower the GED loss, the greater the reward value. By combining reward with log size min 、log samples min Calculate the policy gradient pg; its calculation formula is:

[0064] pg=reward*(log size min+log samples min )

[0065] S16. Calculate the gradient of pg through policy_gradient.backward() and update the HDBSCAN model network parameters through the optimizer. Codes such as torch.sigmoid(raw_params[0][0]), torch.sigmoid(raw_params[0][1]), torch.log, and policy_gradient.backward() all represent corresponding functions, commands, or tools called in PyTorch.

[0066] In order to verify the superiority of the dynamic parameter generation of the present invention in the HDBSCAN model, a set of comparative experiments was designed. The control ratio uses fixed parameters, while the present invention dynamically generates parameters based on DistilBERT+MLP. These two methods run the HDBSCAN algorithm to detect circuit connection relationships. Its evaluation criteria are measured using graph editing distance: first, a heterogeneous graph is constructed to create different types of nodes for different types of devices (PMOS, NMOS, resistors, etc.), different types of edges for different connection relationships (gate, source, drain, etc.), and special node types for network nodes (Net). Then, the heterogeneous graph is converted into a comparable multigraph (MultiGraph) structure. Then check whether the predicted netlist and the standard netlist are isomorphic. If they are isomorphic, then GED=0. If they are not isomorphic, calculate the number of editing operations required to convert one graph into another. Editing operations include: node addition, deletion, and replacement, edge addition, deletion, and replacement, and other operations. Accumulate the GED values ​​of all test samples: K_total=Σ(GED_i), and then use the following formula:

[0067]

[0068] The final scores are calculated as shown in Table 1.

[0069] Table 1: Scores of comparative examples and the present invention.

[0070]

[0071]

[0072] Table 1 shows that, by comparison, the dynamic parameter generation method of the present invention, which adaptively adjusts the parameter netlist connection relationships based on the local characteristics of the circuit diagram, improves accuracy by 0.68%. The HDBSCAN algorithm, which uses fixed parameters, cannot adapt to the different regional characteristics of both simple and complex circuit diagrams. In densely populated areas, connection points are incorrectly segmented. In sparsely populated areas, valid connection points are missed. HDBSCAN's parameters are very sensitive.

[0073] On the other hand, a comparative experiment was conducted on the applicability of the DBSCAN algorithm in circuit diagram analysis, as shown in Table 2.

[0074] Table 2: Scores of the DBSCAN algorithm and the present invention.

[0075]

[0076] Table 2 shows that the accuracy of the proposed method is 4.36% higher than that of the DBSCAN algorithm. The results show that DBSCAN has a serious "single cluster trap" problem when processing complex circuit diagrams. For example, in the following case:

[0077] {'ckt_netlist':[{'component_type':'PMOS','port_connection':{'Drain':'0','Gate':'0','Source':'0'}},{'component_type':'PMOS','port_connection':{'Drain':'0','Gate':'0','Source':'0'}},{'component_type':'NMOS','port_connection':{'Drain':'0','Gate':'0','Source':'0'}},{'component_type':'PMOS','port_connection':{'Drain':'0','Gate':'0','Source':'0'}},{'component_type':'NMOS','port_connection':{'Drain':'0','Gate':'0','Source':'0'}},{'component_type':'NMOS','port_connection':{'Drain':'0','Gate':'0','Source':'0'}},{'component_type':'NMOS','port_connection':{'Drain':'0','Gate':'0','Source':'0'}},{'component_type':'NMOS','port_connection':{'Drain':'0','Gate':'0','Source':'0'}},{'component_type':'Res','port_connection':{'Neg':'0','Pos':'0'}},{'component_type':'Res','port_connection':{'Neg':'0','Pos':'0'}},{'component_type':'Cap','port_connection':{'Neg':'0','Pos':'0'}}],'ckt_type':'SISO-Amplifier'}

[0078] When a circuit diagram contains connection points with varying density distributions, the DBSCAN algorithm tends to incorrectly cluster all endpoints into a single network node. This issue occurred very frequently in the test set, causing some netlist generation to fail completely. This is because the DBSCAN algorithm uses a globally consistent density threshold, which is unable to cope with the multi-scale density variations common in circuit diagrams.

[0079] In another embodiment, a deep learning-based circuit diagram to netlist generation system is proposed, which uses the deep learning-based circuit diagram to netlist generation method described above. The circuit diagram to netlist generation system includes: an identification module, a feature processing module, a fusion module, and a clustering module.

[0080] Among them, the recognition module is used to identify the circuit diagram and obtain the location information, category and confidence of each device, as well as the starting point coordinates, end point coordinates and orientation corresponding to the straight line segment. The feature processing module is used to generate corresponding text description information based on the location information, category and confidence, starting point coordinates, end point coordinates and orientation, and to segment and encode all text description information to generate word vectors. The feature processing module is also used to extract the features of the circuit diagram to generate image vectors. The fusion module is used to splice the word vectors and image vectors to obtain multimodal features. The fusion module is also used to deeply fuse the multimodal features to obtain fused features. The clustering module is used to dynamically generate two key parameters and form clusters, and perform cluster analysis on the fused features. The clustering module is also used to generate a netlist based on the clustering analysis results.

[0081] In another embodiment, a software program product is provided, which includes program instructions that, when executed on an electronic device, cause the electronic device to execute the steps of the deep learning-based circuit diagram to netlist generation method described above.

[0082] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0083] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A method for generating a circuit diagram to a netlist based on deep learning, characterized in that: It includes the following steps: S1. Use the YOLOv8 model to identify the components in the circuit diagram and obtain the location information and category of each component; The straight line segments in the circuit diagram are identified by the probabilistic Hough transform algorithm, and the starting point coordinates, end point coordinates and direction of the straight line segments are obtained; S2. Generate corresponding text description information based on the location information, category, starting point coordinates, end point coordinates and orientation; Extract all text description information through the word feature extraction model to generate word vectors; Extract the features of the circuit diagram through the image feature extraction model to generate an image vector; S3. Concatenate word vectors and image vectors to obtain multimodal features. The multimodal features are fused through the Distilbert model to obtain the fusion features; The fused features are clustered using the HDBSCAN model to determine the positional relationship between each device and the straight line segment, and then a netlist is generated.

2. The method for generating a circuit diagram to a netlist based on deep learning according to claim 1, characterized in that: In S1, the method for obtaining the direction of the straight line segment includes the following steps: Calculate the slope k of the straight line segment based on the starting and ending coordinates of the straight line segment; The direction of the straight line segment is determined according to k: when y1=y2, or |y1-y2|<2, the straight line segment is identified as horizontal; when x1=x2, or |x1-x2|<2, the straight line segment is identified as vertical; where x1 and y1 are the horizontal and vertical coordinates of the starting point, respectively; and x2 and y2 are the horizontal and vertical coordinates of the end point, respectively.

3. The method for generating a circuit diagram to a netlist based on deep learning according to claim 1, characterized in that: In S2, the method for generating corresponding text description information includes the following steps: Predefined device text templates and line segment text templates; The device's location information and category are filled into the corresponding part of the device text template; the starting coordinates, end coordinates and orientation of the straight line segment are filled into the corresponding part of the straight line segment text template to generate corresponding text description information.

4. The method for generating a circuit diagram to a netlist based on deep learning according to claim 3, wherein: When multiple power or ground terminals are identified, a corresponding text description information including location information of all power or ground terminals is generated.

5. The method for generating a circuit diagram to a netlist based on deep learning according to claim 1, wherein: In S2, the image feature extraction model is the ViT model; The ViT model's method for extracting circuit diagram features includes: dividing the circuit diagram into 196 small blocks; and mapping each small block into a 768-dimensional image vector.

6. The method for generating a circuit diagram to a netlist based on deep learning according to claim 1, characterized in that: In S3, the end of the multimodal features is padded to unify the input length; Set the corresponding Attention-Mask mechanism on the padded multimodal features; After setting the Attention-Mask mechanism, the multimodal features are input into the Distilbert model for fusion to obtain the fused features.

7. The method for generating a circuit diagram to a netlist based on deep learning according to claim 1, wherein: In S3, the key parameter in the HDBSCAN model is size min 、Key parameter 2 samples min It is obtained by dynamically generating based on fusion features; among them, size min Indicates the minimum cluster size s; samples min Indicates the minimum number of samples; size min 、samples min It is generated dynamically by inputting the fused features into the MLP.

8. The method for generating a circuit diagram to a netlist based on deep learning according to claim 1, characterized in that: The training method of the HDBSCAN model includes the following steps: S11, setting the device type processing order in the circuit diagram; S12. Predict the number of device type t, count1(t), and compare it with the actual number of device type t, count2(t). Calculate the loss of device type t, type_diff(t). The calculation formula is: type_diff(t)=count1(t)-count2(t) / (count1(t)+count2(t)); S13, accumulate type_diff(1), type_diff(2), ..., type_diff(T) of T types of devices, and normalize the accumulated values ​​to obtain the total loss value GED; t∈[1,T]; S14, size is converted to min 、samples min Convert to probability form and calculate its logarithm to get the corresponding logarithmic probability log size min 、log samples min ; S15. Take the negative of GED as the reward value and combine it with log size min 、log samples min Calculate the policy gradient pg; its calculation formula is: pg=reward*(log size min +log samples min ); S16. Calculate the gradient of pg through the gradient function and update the HDBSCAN model network parameters through the optimizer.

9. A circuit diagram to netlist generation system based on deep learning, characterized in that: It uses the circuit diagram to netlist generation method based on deep learning as described in any one of claims 1 to 8; It includes: The recognition module is used to identify the circuit diagram and obtain the location information, category and confidence level of each component, as well as the starting point coordinates, end point coordinates and orientation of the line segment; The feature processing module is used to generate corresponding text description information from location information, category and confidence, starting point coordinates, end point coordinates and orientation, and to segment and encode all text description information to generate word vectors. It is also used to extract features of circuit diagrams to generate image vectors. The fusion module is used to concatenate word vectors and image vectors to obtain multimodal features. It is also used to deeply fuse multimodal features to obtain fused features. The clustering module is used to dynamically generate two key parameters and form clusters, and perform cluster analysis on the fusion features; it is also used to generate a netlist based on the cluster analysis results.

10. A software program product, characterized in that The software program product includes program instructions, which, when run on an electronic device, enable the electronic device to perform the steps of the circuit diagram to netlist generation method based on deep learning as described in any one of claims 1 to 8.

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