Method and system for programming radio frequency circuit based on artificial intelligence collaborative design

Abstract

The invention relates to the technical field of intellectualization and industrial software, in particular to a radio frequency circuit programming method and system based on artificial intelligence collaborative design, and the method comprises the steps: generating an initial schematic diagram and codes; training a circuit generation model; predicting candidate code snippets; simulating and screening the accepted fragments; displaying the accepted fragment and counting the operation frequency; adjusting the model based on the operation; performing loop iteration to target generation, and training a circuit generation model by using preprocessed data through close combination of a design index, an initial circuit schematic diagram and a structured code so as to realize intelligent prediction of a radio frequency circuit code snippet; high-quality code snippets are dynamically screened in combination with performance simulation results, and then a self-adaptive feedback mechanism is formed based on dragging frequency and parameter modification frequency data in user interaction. The problems of low design efficiency and high error rate caused by weak generalization ability of a circuit design result due to model static training and lack of performance closed-loop verification are effectively solved.

Description

Technical Field

[0001] The present invention relates to the field of intelligent and industrial software technology, and in particular to a method and system for collaboratively designing and programming radio frequency circuits based on artificial intelligence. Background Art

[0002] With the rapid development of high-frequency and high-speed applications such as 5G communications, satellite navigation, and the Internet of Things, RF circuits are becoming increasingly important in system integration, and the design complexity and precision requirements are significantly increasing. At the same time, chip R&D cycles are constantly shrinking, posing greater challenges to circuit design efficiency and repeatability. Traditional design methods that rely on manual experience are gradually showing problems such as low efficiency, high error rate, and limited optimization space when faced with a huge design space, multi-dimensional performance constraints, and frequent iteration requirements. Therefore, there is an urgent need for a new technical path that can improve the level of design intelligence, enhance design reliability, and scalability to support the continuous evolution of RF systems towards high performance, low power consumption, and miniaturization.

[0003] Patent document with publication number CN113239651A discloses an artificial intelligence implementation method and system for circuit design, which includes: obtaining a circuit design topology diagram of a historical stage, the circuit design topology diagram consisting of multiple sub-circuit topology diagrams; building a convolutional neural network for training the circuit design topology diagram; constructing a sample database, the sample database including the functional parameters of the sub-circuit, the name of each circuit element in the sub-circuit topology, and the connection relationship between each circuit element; inputting the sample database into the convolutional neural network for training to obtain a first feature model; inputting the circuit topology diagram in the design into the first feature model to obtain circuit feature parameters; and comparing the circuit feature parameters with expected parameters to obtain corresponding judgment results.

[0004] It can be seen that the artificial intelligence implementation method and system for circuit design have the following problems: the method is only trained based on the circuit topology diagram, and cannot effectively combine circuit performance or simulation data to improve the judgment accuracy; the method lacks a dynamic feedback mechanism and cannot adjust the model parameters or optimization strategy according to the actual performance in the design process; the method uses a convolutional neural network to process circuit structure information, and it is difficult to handle non-Euclidean graph structures and complex dependencies in circuit design; the functional parameters of this method are mainly used for classification training, and are not used to generate design suggestions or specific circuit structures, and the functional utilization rate is low; the judgment result of this method is only a static output of whether it is qualified or not, and lacks guidance on the direction of circuit modification or optimization suggestions; the sample database constructed by this method is a static structure and cannot be continuously expanded and optimized as the design data accumulates. Summary of the Invention

[0005] To this end, the present invention provides a method and system for collaboratively designing and programming radio frequency circuits based on artificial intelligence, which is used to overcome the problems in the prior art of low design efficiency and high error rate due to weak generalization ability of circuit design results caused by static model training and lack of performance closed-loop verification by introducing a model iteration mechanism that integrates multi-dimensional acquisition and circuit performance simulation.

[0006] To achieve the above objectives, the present invention provides, on the one hand, a method for collaboratively designing and programming radio frequency circuits based on artificial intelligence, comprising: Step S1: generating an initial circuit schematic and a structured code corresponding to the design indicators in real time according to the design indicators of the radio frequency circuit received on the visual interface; Step S2: inputting the pre-processed initial circuit schematic, the structured code, and the design indicators into a preset artificial intelligence framework to train and obtain a circuit generation model; Step S3: Based on the design indicators input in real time, calling the circuit generation model to perform prediction and generate a number of candidate code snippets; Step S4: performing performance simulation on each of the candidate code snippets using a preset simulation engine, and selecting a number of code snippets to be accepted from all candidate code snippets based on the simulation results and a preset expected threshold; Step S5: displaying all the code snippets to be accepted on a visual interface, and determining a number of predicted snippets from all the code snippets to be accepted based on the real-time dragging frequency and the real-time parameter modification frequency of each code snippet to be accepted; Step S6: adjusting the circuit generation model based on the proportion of the predicted segments in all code segments to be accepted and the preference index of each predicted segment; Step S7, continuing to execute steps S3 to S6 based on the adjusted circuit generation model until a target circuit is generated; In step S6, the preference index is determined based on the real-time dragging frequency and the real-time parameter modification frequency in a past preset update period.

[0007] Furthermore, in step S4, the preset expected threshold is the optimal value among several reference performance values ​​obtained by using the preset simulation engine to perform simulation calculations on each of the initial circuit schematics within the past preset threshold setting period.

[0008] Further, when the radio frequency circuit is a filter, in step S4, the expected threshold value includes an S parameter threshold value; The S parameter threshold is an optimal S parameter obtained by using a CAE simulation engine to simulate and calculate each of the initial circuit schematics within the preset threshold setting period in the past.

[0009] Further, when the radio frequency circuit is a four-channel clock driver, in step S4, the expected threshold includes a timing parameter threshold; The timing parameter thresholds are maximum clock jitter, maximum propagation delay, and maximum output skew obtained by simulating and calculating each of the initial circuit schematics within the past preset threshold setting period using an EDA simulation engine.

[0010] Furthermore, the step S2 includes: Step S21: Obtain radio frequency circuit design cases within a preset historical period in the past, and extract their structured code snippets as training samples; Step S22: performing random masking processing on the structured code in the training sample at a preset masking ratio to obtain a preprocessed code; Step S23: inputting the preprocessed code, its corresponding initial circuit schematic, and design specifications into the preset artificial intelligence architecture to predict the masked code content and obtain a prediction result; Step S24: Compare the prediction result with the original structured code snippet to calculate the prediction loss value, and update the model parameters of the real-time preset artificial intelligence architecture through the back propagation algorithm; Step S25: When the predicted loss value does not decrease within consecutive preset training rounds, the training is terminated to obtain the circuit generation model.

[0011] Furthermore, in step S3, a preset prediction failure threshold is set. When the number of consecutive predictions exceeds the preset prediction failure threshold and the candidate code snippet that meets the preset expected threshold is still not screened out, a prompt for manual intervention in writing is issued.

[0012] Furthermore, the preset artificial intelligence architecture is a Transformer-based encoder-decoder architecture, including: An encoder, composed of a stack of multiple encoder layers, for encoding the input sequence of the structured code and the design indicator into a fixed-length vector through word embedding, position encoding, and a multi-head attention mechanism; The decoder is composed of multiple decoder layers stacked together to gradually generate the subsequent candidate code fragments by combining the encoder output and the sequence of generated structured codes through input embedding, position encoding, masked multi-head attention mechanism and softmax layer.

[0013] Furthermore, the step S5 includes: Step S51: Within each preset statistical period, the number of drags and parameter modifications of each code segment to be accepted is counted to obtain a number of real-time drag frequencies and a number of real-time parameter modification frequencies; Step S52: performing weighted synthesis on the real-time dragging frequency and the real-time parameter modification frequency according to a preset preference weight, and calculating a preference score for each of the code snippets to be accepted; Step S53: sort all the code snippets to be accepted from high to low according to the preference scores, and select several code snippets to be accepted with the highest scores as the predicted snippets according to a preset score threshold.

[0014] Furthermore, step S6 includes: Step S61: within each of the preset update cycles, calculating the proportion of the selected predicted segments in all the code segments to be accepted, and obtaining a proportion coefficient of each predicted segment; Step S62: weighting and synthesizing the proportion coefficient of each predicted segment and its corresponding preference index according to a preset fusion weight to calculate a comprehensive impact factor of each predicted segment; Step S63: construct a model parameter update gradient based on the comprehensive influencing factor and the preset learning rate, and perform one or more gradient descent iterations on the circuit generation model to adjust the model parameters to obtain the adjusted circuit generation model.

[0015] On the other hand, the present invention also provides a system for collaboratively designing and programming radio frequency circuits based on artificial intelligence, comprising: A first generation module is used to generate an initial circuit schematic and a structured code corresponding to the design indicators in real time according to the design indicators of the radio frequency circuit received in the visual interface; a training module connected to the first generation module, configured to input the preprocessed initial circuit schematic, the structured code, and the design indicators into a preset artificial intelligence architecture to train and obtain a circuit generation model; a prediction module connected to the training module, configured to call the circuit generation model to perform prediction and generate a plurality of candidate code snippets based on the design indicators input in real time; a screening module, connected to the prediction module, configured to perform performance simulation on each of the candidate code snippets using a preset simulation engine, and screen out a number of code snippets to be accepted from all candidate code snippets based on the simulation results and a preset expected threshold; a determination module connected to the screening module, configured to display all the code snippets to be accepted on a visual interface, and determine a number of predicted snippets from all the code snippets to be accepted based on the real-time dragging frequency and the real-time parameter modification frequency of each code snippet to be accepted; an adjustment module, connected to the determination module and the training module respectively, for adjusting the circuit generation model based on a proportion of the predicted segments in all the code segments to be accepted and a preference index of each of the predicted segments; The second generation module is connected to the prediction module, the screening module, the determination module and the adjustment module respectively, and is used for continuously optimizing based on the dynamic update result of the circuit generation model until a target circuit is generated.

[0016] Compared with the existing technology, the beneficial effect of the present invention lies in that, by closely combining design indicators with the initial circuit schematic and structured code, the circuit generation model is trained using preprocessed data to achieve intelligent prediction of RF circuit code snippets; high-quality code snippets are dynamically screened based on performance simulation results, and then based on the drag frequency and parameter modification frequency data in user interaction, design preferences are accurately identified, and model parameters are further adjusted to form an adaptive feedback mechanism. The various parameters interact with each other to ensure that the model can not only generate code that meets the design indicators, but also continuously optimize the prediction effect according to actual usage, improve design efficiency and the matching degree of circuit performance, promote the intelligence and personalization of the RF circuit design process, and effectively solve the problem of weak generalization ability of circuit design results due to static model training and lack of performance closed-loop verification, resulting in low design efficiency and high error rate.

[0017] Furthermore, by adopting a Transformer-based encoder-decoder architecture, the model can fully understand the semantic relationship between structured code sequences and design indicators. The encoder converts the input sequence into a context-aware high-dimensional representation through word embedding and positional encoding, and uses a multi-head attention mechanism to effectively focus on different features, thereby enhancing the ability to express the input information. The decoder combines this high-dimensional representation with the existing code sequence, uses a masking mechanism to control the generation path, and outputs the next code fragment with the best probability in the softmax layer. This architecture can improve the model's ability to model complex circuit semantics and the accuracy of code fragment generation, thereby providing high-quality candidates for subsequent simulation screening and optimization, improving overall design efficiency and the engineering applicability of the generated results.

[0018] Furthermore, by introducing structured code snippets based on historical RF circuit design cases during the model training phase, and combining them with a random masking mechanism for self-supervised learning, the model's ability to recognize and complete circuit semantic patterns is effectively enhanced. Specifically, the setting of the mask ratio ensures that the model faces sufficient information loss challenges while retaining the necessary context, thereby guiding it to learn the mapping relationship between key structural features and local function expressions; and the predicted loss value, as a measure of the model's learning effect, combined with a continuous round of descent monitoring mechanism, can dynamically control the training convergence process to avoid overfitting or insufficient training. By continuously optimizing the model parameters through backpropagation, the constructed circuit generation model has stronger generalization capabilities and structural completion accuracy in practical applications. When faced with new design tasks, it can quickly generate candidate code snippets that meet engineering rules and design intents, thereby improving collaborative design efficiency and model quality from the source.

[0019] Furthermore, by setting a preset prediction failure threshold, the prediction performance of the circuit generation model can be effectively monitored. When the number of consecutive predictions exceeds the threshold and still no candidate code fragment that meets the preset expected threshold is generated, the system will promptly trigger a manual intervention prompt to ensure that the design process will not stagnate due to model prediction failure. This mechanism not only ensures the continuity and accuracy of the design, but also promotes human-computer collaboration and improves overall design efficiency and reliability.

[0020] Furthermore, by dynamically setting a preset expected threshold based on the historical optimal performance value, high-precision screening of the performance of candidate code snippets can be achieved in step S4. By taking all the initial circuit schematic simulation results within the past preset threshold setting period as the basis, the optimal reference performance is extracted as the current judgment basis, thereby logically establishing a closed-loop path of "historical performance accumulation-optimal value extraction-current screening optimization", which can effectively improve the matching degree between the simulation results and the target design requirements, avoid excessive screening or misacceptance caused by traditional static threshold setting, and the dynamic update mechanism can continuously optimize the parameter judgment criteria as the design progresses, thereby improving the model's adaptability and evolution efficiency.

[0021] Furthermore, by introducing S-parameter thresholds calculated using a CAE simulation engine as the desired standard in application scenarios where RF circuits are filters, it is possible to fully utilize the simulation data of multiple initial circuit schematics within the historical preset threshold setting period to extract the S-parameters that perform best under the target indicators as a performance reference. By generating dynamic thresholds driven by data, not only does this avoid the subjective bias caused by human experience, but it also reflects the responsiveness and stability of different topologies in actual applications by aggregating historical optimal solutions, thereby improving the accuracy and robustness of screening code snippets for acceptance. Furthermore, this S-parameter threshold forms a closed-loop feedback relationship with design dimensions such as filter structure, material parameters, and frequency range, providing a quantifiable and traceable performance benchmark for subsequent iterative model optimization and circuit generation, strengthening the coupling mechanism between circuit performance and intelligent recommendations, and thus achieving a more engineering-practical collaborative design optimization process.

[0022] Furthermore, by introducing timing parameter thresholds derived from an EDA simulation engine as expected standards in the design scenario of a four-channel RF circuit clock driver, the high dependence of this type of circuit on clock accuracy and signal integrity can be fully reflected. Specifically, maximum clock jitter, maximum propagation delay, and maximum output skew are key indicators for measuring driver stability and synchronization performance. The three are highly coupled: clock jitter directly affects edge stability, propagation delay affects the consistency of the clock distribution path, and output skew reflects the symmetry control effect between output ports. By simulating and extracting a large number of initial schematics within the preset threshold setting cycle, a dynamic optimization threshold system is automatically constructed, enabling the circuit generation model to use the performance lower bound verified in engineering practice as the target constraint, thereby improving the timing correctness and system integration of candidate code snippets. At the same time, a closed-loop deduction from schematic structure to key performance indicators is achieved, significantly enhancing the model's structure-performance mapping capabilities for timing-related circuits, enabling more reliable and controllable automated collaborative design.

[0023] Furthermore, by carefully counting the number of drags and parameter modifications of the accepted code snippets, and calculating the preference scores based on preset preference weights, the actual usage preferences and adjustment needs of each code snippet can be objectively reflected; then, high-scoring code snippets are sorted and screened out as predicted snippets based on the preference scores, effectively improving the pertinence and accuracy of subsequent model training, thereby continuously optimizing the matching degree of circuit design and promoting a more efficient design process that meets actual needs.

[0024] Furthermore, by statistically analyzing the proportion of predicted snippets among all code snippets to be accepted, combining the preference index corresponding to each predicted snippet, and performing a weighted calculation according to preset fusion weights, a comprehensive impact factor is obtained. Based on this impact factor and a preset learning rate, the parameters of the circuit generation model are dynamically adjusted. This process effectively reflects user preferences and usage frequency, promotes continuous model optimization, and improves the accuracy and adaptability of code generation, thereby making the generated RF circuit design more in line with actual needs and improving overall design efficiency and quality.

[0025] Furthermore, through modular construction, intelligent generation and iterative optimization of RF circuits can be achieved. The modules work together to not only realize structured circuit generation driven by design indicators, but also perform dynamic screening and adaptive model updates based on simulation feedback and user behavior, thereby achieving effective identification and continuous optimization of candidate code fragments, greatly improving the intelligence level of circuit design, generation efficiency, and the controllability and reliability of design results. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a flow chart of the method for collaboratively designing and programming radio frequency circuits based on artificial intelligence in this embodiment; Figure 2 This is a flow chart of step S2 of this embodiment; Figure 3 This is a flow chart of step S5 of this embodiment; Figure 4 This is a flowchart of step S6 of this embodiment. DETAILED DESCRIPTION

[0027] In order to make the objects and advantages of the present invention more clearly understood, the present invention is further described below in conjunction with embodiments; it should be understood that the specific embodiments described herein are merely used to explain the present invention and are not intended to limit the present invention.

[0028] The preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only used to explain the technical principles of the present invention and are not intended to limit the scope of protection of the present invention.

[0029] See also Figure 1 As shown, it is a flow chart of the method for collaboratively designing and programming radio frequency circuits based on artificial intelligence in this embodiment. On the one hand, this embodiment provides a method for collaboratively designing and programming radio frequency circuits based on artificial intelligence, including: Step S1: generating an initial circuit schematic and a structured code corresponding to the design indicators in real time according to the design indicators of the radio frequency circuit received on the visual interface; Step S2: inputting the pre-processed initial circuit schematic, the structured code, and the design indicators into a preset artificial intelligence framework to train and obtain a circuit generation model; Step S3: Based on the design indicators input in real time, calling the circuit generation model to perform prediction and generate a number of candidate code snippets; Step S4: performing performance simulation on each of the candidate code snippets using a preset simulation engine, and selecting a number of code snippets to be accepted from all candidate code snippets based on the simulation results and a preset expected threshold; Step S5: displaying all the code snippets to be accepted on a visual interface, and determining a number of predicted snippets from all the code snippets to be accepted based on the real-time dragging frequency and the real-time parameter modification frequency of each code snippet to be accepted; Step S6: adjusting the circuit generation model based on the proportion of the predicted segments in all code segments to be accepted and the preference index of each predicted segment; Step S7, continuing to execute steps S3 to S6 based on the adjusted circuit generation model until a target circuit is generated; In step S6, the preference index is determined based on the real-time dragging frequency and the real-time parameter modification frequency in a past preset update period.

[0030] In this embodiment, the design index is a set of quantitative performance parameters input by the designer in the visual interface, which is used to guide the generation of the initial circuit schematic and structured code and serve as a benchmark for subsequent screening; the specific content of the index varies depending on the circuit type: when the RF circuit is a filter, the design index preferably includes but is not limited to the S parameters of the center frequency (such as 2.4GHz±50MHz), passband insertion loss (≤1.5dB), passband return loss (≥15dB) and out-of-band suppression (≥30dB); when the RF circuit is a four-way When designing clock drivers, emphasis is placed on timing performance indicators, including maximum clock jitter (≤100fs), maximum propagation delay (≤200ps), and maximum output skew (≤50ps). To match this, the preset simulation engine is an electromagnetic / time domain or frequency domain performance evaluation module integrated in the system. Its selection depends on the trade-off between simulation accuracy and response speed. It is preferred to use a CAE S-parameter simulation engine based on the fast multipole algorithm or an EDA simulation tool that supports parasitic parameter extraction and transient analysis. These can complete high-precision (0.01dB or picosecond level) parallel simulation of candidate solutions in batches, thereby providing a reliable historical optimal threshold for screening and model iteration.

[0031] The preset update period refers to the time window in which the model triggers parameter updates after executing several prediction-simulation-screening operations. Its length depends on factors such as the number of candidate code snippets, simulation time, designer interaction frequency, and system computing resources. It can usually be set to trigger every 1 to 5 minutes. In this embodiment, the preset update period is preferably set to every 3 minutes to take into account both the real-time design response and the stability of model convergence. While ensuring smooth human-computer collaborative interaction, it can timely absorb the latest preference data and accelerate the self-adaptation of the circuit generation model towards the optimal direction.

[0032] In this embodiment, in step S1, a visual interface receives design specifications for an RF circuit (such as the center frequency, bandwidth, insertion loss of a filter, or jitter and delay of a clock driver), and generates a corresponding initial circuit schematic and structured code in real time. Subsequently, in step S2, the schematic, code, and design specifications are input into a preset artificial intelligence architecture for training to obtain a circuit generation model that can predict circuit segments in real time. In step S3, the model outputs multiple candidate code segments in real time. In step S4, the system invokes a preset simulation engine to perform performance simulation on each candidate segment and, based on a dynamically updated desired threshold, selects a number of candidate code segments to be accepted that meet the requirements. In step S5, these segments are displayed side by side on the interface, and the designer generates behavioral data by dragging and dropping and fine-tuning parameters. Prioritized predicted segments are determined based on dragging and modification frequencies. In step S6, an impact factor is calculated based on the proportion and preference index of the predicted segments, and the circuit generation model is adjusted online based on a preset learning rate. Finally, in step S7, the closed-loop process of prediction-simulation-screening-feedback-update is repeated until a target circuit that meets all design specifications is generated, thereby achieving efficient and adaptive RF circuit design that is collaborative between AI and human experts.

[0033] By closely integrating design metrics with the initial circuit schematic and structured code, and utilizing preprocessed data to train a circuit generation model, the system achieves intelligent prediction of RF circuit code snippets. High-quality code snippets are dynamically screened based on performance simulation results. Based on user interaction with drag frequency and parameter modification frequency data, the system accurately identifies design preferences and further adjusts model parameters, forming an adaptive feedback mechanism. The interaction of these parameters ensures that the model not only generates code that meets design metrics but also continuously optimizes predictions based on actual usage, improving design efficiency and matching circuit performance. This promotes intelligent and personalized RF circuit design, effectively addressing the issues of low design efficiency and high error rates caused by weak generalization of circuit design results due to static model training and a lack of closed-loop performance verification.

[0034] Specifically, in step S2, the preset artificial intelligence architecture is a Transformer-based encoder-decoder architecture, including: An encoder, composed of a stack of multiple encoder layers, for encoding the input sequence of the structured code and the design indicator into a fixed-length vector through word embedding, position encoding, and a multi-head attention mechanism; The decoder is composed of multiple decoder layers stacked together to gradually generate the subsequent candidate code fragments by combining the encoder output and the sequence of generated structured codes through input embedding, position encoding, masked multi-head attention mechanism and softmax layer.

[0035] See also Figure 2 As shown, it is a flow chart of step S2 of this embodiment. In this embodiment, step S2 includes: Step S21: Obtain radio frequency circuit design cases within a preset historical period in the past, and extract their structured code snippets as training samples; Step S22: performing random masking processing on the structured code in the training sample at a preset masking ratio to obtain a preprocessed code; Step S23: inputting the preprocessed code, its corresponding initial circuit schematic, and design specifications into the preset artificial intelligence architecture to predict the masked code content and obtain a prediction result; Step S24: Compare the prediction result with the original structured code snippet to calculate the prediction loss value, and update the model parameters of the real-time preset artificial intelligence architecture through the back propagation algorithm; Step S25: When the predicted loss value does not decrease within consecutive preset training rounds, the training is terminated to obtain the circuit generation model.

[0036] The preset historical period refers to the historical time range used to collect RF circuit design cases, which depends on the target model's requirements for sample diversity and novelty. It is usually set between 1 month and 12 months. In this embodiment, it is preset to 6 months, which can ensure that the training data is both representative and timely, thereby improving the model's generalization ability.

[0037] The preset masking ratio refers to the masking range ratio when random masking is performed on structured codes. It depends on the need to exercise context understanding ability during model training. It is usually set between 10% and 30%. In this embodiment, it is set to 20%, which can improve the prediction accuracy of the model while maintaining semantic integrity.

[0038] The preset training rounds refer to the upper limit of the number of iterations that the circuit generation model performs to traverse the entire sample during the training phase. This number depends on the model complexity and the convergence speed of the loss function. It is usually set between 50 and 500 rounds. In this embodiment, it is set to 200 rounds, which can ensure sufficient learning while avoiding overfitting.

[0039] By introducing structured code snippets based on historical RF circuit design cases during the model training phase and combining them with a random masking mechanism for self-supervised learning, the model's ability to recognize and complete circuit semantic patterns is effectively enhanced. Specifically, the setting of the mask ratio ensures that the model faces sufficient information loss challenges while retaining the necessary context, thereby guiding it to learn the mapping relationship between key structural features and local function expressions; and the predicted loss value, as a measure of the model's learning effect, combined with a continuous round of descent monitoring mechanism, can dynamically control the training convergence process to avoid overfitting or insufficient training. By continuously optimizing the model parameters through backpropagation, the constructed circuit generation model has stronger generalization capabilities and structural completion accuracy in practical applications. When faced with new design tasks, it can quickly generate candidate code snippets that meet engineering rules and design intents, thereby improving collaborative design efficiency and model quality from the source.

[0040] Specifically, in step S3, a preset prediction failure threshold is also set. When the number of consecutive predictions exceeds the preset prediction failure threshold and the candidate code snippet that meets the preset expected threshold is still not screened out, a prompt for manual intervention in writing is issued.

[0041] The preset prediction failure threshold refers to the maximum allowed number of times that continuous predictions fail to generate code snippets that meet the preset expected threshold. It depends on the circuit complexity and model stability and is usually set between 10 and 50 times. In this embodiment, it is set to 30 times, which can effectively balance the timing of automatic prediction and manual intervention, and ensure the continuity and accuracy of the design process.

[0042] By setting a preset prediction failure threshold, the prediction performance of the circuit generation model can be effectively monitored. When the number of consecutive predictions exceeds the threshold and a candidate code fragment that meets the preset expected threshold is still not generated, the system promptly triggers a manual intervention prompt to ensure that the design process does not stagnate due to model prediction failure. This mechanism not only ensures the continuity and accuracy of the design, but also promotes human-computer collaboration and improves overall design efficiency and reliability.

[0043] Specifically, in step S3, a visual collaborative interface is provided to simultaneously display the candidate code snippets and the real-time code written by human intervention.

[0044] By introducing a visual collaborative interface, automatically generated candidate code snippets can be displayed side by side with manually written code in real time, allowing intuitive comparison and selection of the optimal solution, thereby improving the flexibility and interactivity of the design; the interface supports instant modification and feedback of the code, promoting the deep integration of artificial intelligence, thereby significantly improving overall design efficiency and accuracy.

[0045] Specifically, in step S4, the preset expected threshold is the optimal value among several reference performance values ​​obtained by using the preset simulation engine to perform simulation calculations on each of the initial circuit schematics within the past preset threshold setting period.

[0046] The preset threshold setting period refers to the historical time period used to update the performance evaluation threshold. It depends on the computational time of the circuit simulation, the real-time requirements of the design task, and the complexity of the circuit type. It is usually set between 1 and 72 hours. In this embodiment, it is set to 24 hours. This fully extracts representative performance reference values, ensuring the stability and foresight of the selected desired thresholds, effectively improving the effectiveness of the model in guiding actual designs and the accuracy of simulation screening.

[0047] By dynamically setting a preset expected threshold based on the historical optimal performance value, high-precision screening of the performance of candidate code snippets can be achieved in step S4. By taking all the initial circuit schematic simulation results within the past preset threshold setting period as the basis, the optimal reference performance is extracted as the current judgment basis, thereby logically establishing a closed-loop path of "historical performance accumulation-optimal value extraction-current screening optimization", which can effectively improve the matching degree between the simulation results and the target design requirements, avoid excessive screening or misacceptance caused by traditional static threshold setting. In addition, the dynamic update mechanism can continuously optimize the parameter judgment criteria as the design progresses, thereby improving the model's adaptability and evolution efficiency.

[0048] Specifically, when the radio frequency circuit is a filter, in step S4, the expected threshold value includes an S parameter threshold value; The S parameter threshold is an optimal S parameter obtained by using a CAE simulation engine to simulate and calculate each of the initial circuit schematics within the preset threshold setting period in the past.

[0049] By introducing S-parameter thresholds calculated using a CAE simulation engine as the desired standard in RF circuit filter applications, the simulation data of multiple initial circuit schematics within the historical preset threshold setting period can be fully utilized to extract the S-parameters that perform best under the target indicators as a performance reference. By generating dynamic thresholds driven by data, not only does it avoid the subjective bias caused by human experience, but it also reflects the responsiveness and stability of different topologies in actual applications by aggregating historical optimal solutions, thereby improving the accuracy and robustness of the code snippets to be screened for acceptance. Furthermore, this S-parameter threshold forms a closed-loop feedback relationship with design dimensions such as filter structure, material parameters, and frequency range, providing a quantifiable and traceable performance benchmark for subsequent iterative model optimization and circuit generation, strengthening the coupling mechanism between circuit performance and intelligent recommendations, and thus achieving a more engineering-practical collaborative design optimization process.

[0050] Specifically, when the radio frequency circuit is a four-channel clock driver, in step S4, the expected threshold includes a timing parameter threshold; The timing parameter thresholds are maximum clock jitter, maximum propagation delay, and maximum output skew obtained by simulating and calculating each of the initial circuit schematics within the past preset threshold setting period using an EDA simulation engine.

[0051] By introducing timing parameter thresholds derived from an EDA simulation engine as expected standards in the design scenario of a four-channel RF circuit clock driver, the high dependence of this type of circuit on clock accuracy and signal integrity can be fully reflected. Specifically, maximum clock jitter, maximum propagation delay, and maximum output skew, as key indicators for measuring driver stability and synchronization performance, are highly coupled: clock jitter directly affects edge stability, propagation delay affects the consistency of the clock distribution path, and output skew reflects the symmetry control effect between output ports. By simulating and extracting a large number of initial schematics within the preset threshold setting period, a dynamic optimization threshold system is automatically constructed, enabling the circuit generation model to use the performance lower bound verified in engineering practice as the target constraint, thereby improving the timing correctness and system integration of candidate code snippets. At the same time, a closed-loop deduction from schematic structure to key performance indicators is achieved, significantly enhancing the model's structure-performance mapping capabilities for timing-related circuits, enabling more reliable and controllable automated collaborative design.

[0052] See also Figure 3 As shown, it is a flow chart of step S5 of this embodiment. In this embodiment, step S5 includes: Step S51: Within each preset statistical period, the number of drags and parameter modifications of each code segment to be accepted is counted to obtain a number of real-time drag frequencies and a number of real-time parameter modification frequencies; Step S52: The real-time dragging frequency and the real-time parameter modification frequency are weighted and synthesized according to preset preference weights to calculate the preference score of each code snippet to be accepted, Qi=wd×fi1+wm×fi2, where Qi is the preference score of the i-th code snippet to be accepted, fi1 is the real-time dragging frequency of the i-th code snippet to be accepted, fi2 is the real-time parameter modification frequency of the i-th code snippet to be accepted, wd and wm are the preset preference weights of the real-time dragging frequency and the real-time parameter modification frequency, respectively, and wd+wm=1 is satisfied; Step S53: sort all the code snippets to be accepted from high to low according to their preference scores, and select a number of code snippets to be accepted with the highest scores whose preference scores are greater than a preset score threshold as the predicted snippets.

[0053] The preset preference weight is a coefficient used to balance the impact of real-time dragging frequency and real-time parameter modification frequency on the preference score. It depends on the importance ratio of the two in the specific application scenario. It is usually set between 0 and 1 and the sum of the two weights is 1. In this embodiment, the preset preference weight of the real-time dragging frequency is set to 0.6, and the preset preference weight of the real-time parameter modification frequency is set to 0.4, which can effectively reflect the user's operation preferences and improve the accuracy of the candidate code snippet screening.

[0054] The preset score threshold is the minimum score standard for screening high-preference code snippets. It depends on the system's requirements for the quality and quantity of candidate snippets and is usually set between 0 and 1. In this embodiment, it is set to 0.75, which can effectively filter low-quality code and improve the overall performance of predicted snippets and user satisfaction.

[0055] By carefully counting the number of times the code snippets are dragged and the number of times the parameters are modified, and calculating the preference score based on the preset preference weights, the actual usage preference and adjustment needs of each code snippet can be objectively reflected; then, the high-scoring code snippets are sorted and screened out as prediction snippets based on the preference scores, which effectively improves the pertinence and accuracy of subsequent model training, thereby continuously optimizing the matching degree of circuit design and promoting a more efficient design process that meets actual needs.

[0056] See also Figure 4 As shown, it is a flow chart of step S6 of this embodiment. In this embodiment, step S6 includes: Step S61: within each of the preset update cycles, calculating the proportion of the selected predicted segments in all the code segments to be accepted, and obtaining a proportion coefficient of each predicted segment; Step S62: The proportion coefficient of each predicted segment and its corresponding preference index are weighted and synthesized according to a preset fusion weight to calculate the comprehensive influence factor of each predicted segment, Yi = α × Pi + (1-α) × Qi', where Yi is the i-th comprehensive influence factor, α is the weight ratio of the control proportion coefficient and the preference score in the comprehensive influence factor, Pi is the proportion coefficient of the i-th predicted segment in all the code segments to be accepted, and Qi' is the preference index of the i-th predicted segment; Step S63: construct a model parameter update gradient based on the comprehensive influencing factor and the preset learning rate, and perform one or more gradient descent iterations on the circuit generation model to adjust the model parameters to obtain the adjusted circuit generation model.

[0057] By statistically analyzing the proportion of predicted snippets among all code snippets to be accepted, combining the preference index corresponding to each predicted snippet, and performing a weighted calculation based on preset fusion weights, a comprehensive impact factor is obtained. Based on this impact factor and the preset learning rate, the parameters of the circuit generation model are dynamically adjusted. This process effectively reflects user preferences and usage frequency, promotes continuous model optimization, and improves the accuracy and adaptability of code generation, thereby making the generated RF circuit design more in line with actual needs and improving overall design efficiency and quality.

[0058] On the other hand, this embodiment also provides a system for collaboratively designing and programming radio frequency circuits based on artificial intelligence, including: A first generation module is used to generate an initial circuit schematic and a structured code corresponding to the design indicators in real time according to the design indicators of the radio frequency circuit received in the visual interface; a training module connected to the first generation module, configured to input the preprocessed initial circuit schematic, the structured code, and the design indicators into a preset artificial intelligence architecture to train and obtain a circuit generation model; a prediction module connected to the training module, configured to call the circuit generation model to perform prediction and generate a plurality of candidate code snippets based on the design indicators input in real time; a screening module, connected to the prediction module, configured to perform performance simulation on each of the candidate code snippets using a preset simulation engine, and screen out a number of code snippets to be accepted from all candidate code snippets based on the simulation results and a preset expected threshold; a determination module connected to the screening module, configured to display all the code snippets to be accepted on a visual interface, and determine a number of predicted snippets from all the code snippets to be accepted based on the real-time dragging frequency and the real-time parameter modification frequency of each code snippet to be accepted; an adjustment module, connected to the determination module and the training module respectively, for adjusting the circuit generation model based on a proportion of the predicted segments in all the code segments to be accepted and a preference index of each of the predicted segments; The second generation module is connected to the prediction module, the screening module, the determination module and the adjustment module respectively, and is used for continuously optimizing based on the dynamic update result of the circuit generation model until a target circuit is generated.

[0059] Through modular construction, intelligent generation and iterative optimization of RF circuits are achieved. The modules work together to not only realize structured circuit generation driven by design indicators, but also perform dynamic screening and adaptive model updates based on simulation feedback and user behavior, thereby achieving effective identification and continuous optimization of candidate code fragments, greatly improving the intelligence level of circuit design, generation efficiency, and the controllability and reliability of design results.

[0060] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for collaboratively designing and programming radio frequency circuits based on artificial intelligence, characterized in that: include: Step S1: generating an initial circuit schematic and a structured code corresponding to the design indicators in real time according to the design indicators of the radio frequency circuit received on the visual interface; Step S2: inputting the pre-processed initial circuit schematic, the structured code, and the design indicators into a preset artificial intelligence framework to train and obtain a circuit generation model; Step S3: Based on the design indicators input in real time, calling the circuit generation model to perform prediction and generate a number of candidate code snippets; Step S4: performing performance simulation on each of the candidate code snippets using a preset simulation engine, and selecting a number of code snippets to be accepted from all candidate code snippets based on the simulation results and a preset expected threshold; Step S5: displaying all the code snippets to be accepted on a visual interface, and determining a number of predicted snippets from all the code snippets to be accepted based on the real-time dragging frequency and the real-time parameter modification frequency of each code snippet to be accepted; Step S6: adjusting the circuit generation model based on the proportion of the predicted segments in all code segments to be accepted and the preference index of each predicted segment; Step S7, continuing to execute steps S3 to S6 based on the adjusted circuit generation model until a target circuit is generated; In step S6, the preference index is determined based on the real-time dragging frequency and the real-time parameter modification frequency in a past preset update period.

2. The method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to claim 1, characterized in that: In step S4, the preset expected threshold is the optimal value among several reference performance values ​​obtained by using the preset simulation engine to perform simulation calculations on each of the initial circuit schematics within a past preset threshold setting period.

3. The method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to claim 1, characterized in that: When the radio frequency circuit is a filter, in step S4, the expected threshold value includes an S parameter threshold value; The S parameter threshold is an optimal S parameter obtained by using a CAE simulation engine to simulate and calculate each of the initial circuit schematics within the preset threshold setting period in the past.

4. The method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to claim 1, characterized in that: When the radio frequency circuit is a four-channel clock driver, in step S4, the expected threshold includes a timing parameter threshold; The timing parameter thresholds are maximum clock jitter, maximum propagation delay, and maximum output skew obtained by simulating and calculating each of the initial circuit schematics within the past preset threshold setting period using an EDA simulation engine.

5. The method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to claim 1, characterized in that: The step S2 comprises: Step S21: Obtain radio frequency circuit design cases within a preset historical period in the past, and extract their structured code snippets as training samples; Step S22: performing random masking processing on the structured code in the training sample at a preset masking ratio to obtain a preprocessed code; Step S23: inputting the preprocessed code, its corresponding initial circuit schematic, and design specifications into the preset artificial intelligence architecture to predict the masked code content and obtain a prediction result; Step S24: Compare the prediction result with the original structured code snippet to calculate the prediction loss value, and update the model parameters of the real-time preset artificial intelligence architecture through the back propagation algorithm; Step S25: When the predicted loss value does not decrease within consecutive preset training rounds, the training is terminated to obtain the circuit generation model.

6. The method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to claim 1, characterized in that: In step S3, a preset prediction failure threshold is also set. When the number of consecutive predictions exceeds the preset prediction failure threshold and the candidate code snippet that meets the preset expected threshold is still not screened out, a prompt for manual intervention in writing is issued.

7. The method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to claim 1, wherein in step S2, The preset artificial intelligence architecture is a Transformer-based encoder-decoder architecture, including: An encoder, composed of a stack of multiple encoder layers, for encoding the input sequence of the structured code and the design indicator into a fixed-length vector through word embedding, position encoding, and a multi-head attention mechanism; The decoder is composed of multiple decoder layers stacked together to gradually generate the subsequent candidate code fragments by combining the encoder output and the sequence of generated structured codes through input embedding, position encoding, masked multi-head attention mechanism and softmax layer.

8. The method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to claim 1, characterized in that: The step S5 comprises: Step S51: Within each preset statistical period, the number of drags and parameter modifications of each code segment to be accepted is counted to obtain a number of real-time drag frequencies and a number of real-time parameter modification frequencies; Step S52: performing weighted synthesis on the real-time dragging frequency and the real-time parameter modification frequency according to a preset preference weight, and calculating a preference score for each of the code snippets to be accepted; Step S53: sort all the code snippets to be accepted from high to low according to the preference scores, and select several code snippets to be accepted with the highest scores as the predicted snippets according to a preset score threshold.

9. The method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to claim 1, characterized in that: The step S6 comprises: Step S61: within each of the preset update cycles, calculating the proportion of the selected predicted segments in all the code segments to be accepted, and obtaining a proportion coefficient of each predicted segment; Step S62: weighting and synthesizing the proportion coefficient of each predicted segment and its corresponding preference index according to a preset fusion weight to calculate a comprehensive impact factor of each predicted segment; Step S63: construct a model parameter update gradient based on the comprehensive influencing factor and the preset learning rate, and perform one or more gradient descent iterations on the circuit generation model to adjust the model parameters to obtain the adjusted circuit generation model.

10. A system for collaboratively designing and programming radio frequency circuits based on artificial intelligence, constructed based on the method for collaboratively designing and programming radio frequency circuits based on artificial intelligence according to any one of claims 1 to 9, characterized in that: include: A first generation module is used to generate an initial circuit schematic and a structured code corresponding to the design indicators in real time according to the design indicators of the radio frequency circuit received in the visual interface; a training module connected to the first generation module, configured to input the preprocessed initial circuit schematic, the structured code, and the design indicators into a preset artificial intelligence architecture to train and obtain a circuit generation model; a prediction module connected to the training module, configured to call the circuit generation model to perform prediction and generate a plurality of candidate code snippets based on the design indicators input in real time; a screening module, connected to the prediction module, configured to perform performance simulation on each of the candidate code snippets using a preset simulation engine, and screen out a number of code snippets to be accepted from all candidate code snippets based on the simulation results and a preset expected threshold; a determination module connected to the screening module, configured to display all the code snippets to be accepted on a visual interface, and determine a number of predicted snippets from all the code snippets to be accepted based on the real-time dragging frequency and the real-time parameter modification frequency of each code snippet to be accepted; an adjustment module, connected to the determination module and the training module respectively, for adjusting the circuit generation model based on a proportion of the predicted segments in all the code segments to be accepted and a preference index of each of the predicted segments; The second generation module is connected to the prediction module, the screening module, the determination module and the adjustment module respectively, and is used for continuously optimizing based on the dynamic update result of the circuit generation model until a target circuit is generated.

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