Picture frame rate adjusting method and device of display screen, equipment and storage medium

Abstract

The invention provides a picture frame rate adjusting method and device of a display screen, equipment and a storage medium, and the method comprises the steps: carrying out the prediction processing of a vertical flyback window through detecting the time interval change of adjacent scanning lines in a display controller, and obtaining the prediction time of the vertical flyback window; performing atomic locking processing on the multi-stage frame buffer according to the vertical flyback window prediction time to obtain a buffer switching control signal; and performing rendering completion degree analysis processing on the GPU rendering pipeline according to the buffer switching control signal, obtaining a rendering completion degree evaluation result, reconstructing a multi-stage buffer synchronization strategy according to the rendering completion degree evaluation result, and adjusting the frame rate of the display screen based on the reconstructed synchronization strategy. By accurately predicting the vertical flyback window opportunity and implementing atomic buffer region locking, accurate synchronization of frame buffer region switching and the position of a display scanner is ensured, the problem of single-frame flicker caused by improper buffer region switching opportunity is effectively solved, and the visual continuity of professional display application is improved.

Description

Technical Field

[0001] The present invention relates to the field of data processing technology, and in particular to a method, device, equipment and storage medium for adjusting the frame rate of a display screen. Background Art

[0002] In high-end graphics workstations and professional display systems, display controllers typically use a multi-level frame buffer architecture, including a foreground buffer, a back buffer, and a standby buffer. After the GPU completes rendering a frame, the system must promote the back buffer to the foreground buffer for display scanning during the vertical retrace period to achieve seamless image switching and frame rate adjustment.

[0003] However, existing frame rate adjustment methods, when handling variable refresh rate scenarios, suffer from a delay between the execution of buffer switching instructions and the actual position of the display scanner. This leads to momentary inconsistencies in the display data source at critical moments during frame buffer state transitions. This inconsistency manifests as single-frame flickering. Especially during dynamic frame rate adjustment, variations in the timing of the vertical sync window can amplify this buffer switching race condition, severely impacting visual continuity in professional display applications. Summary of the Invention

[0004] The main purpose of the present invention is to solve the technical problem of single frame flickering caused by improper frame buffer switching timing in the existing display screen frame rate adjustment method; A first aspect of the present invention provides a method for adjusting the frame rate of a display screen, the method comprising: By detecting the change in the time interval between adjacent scan lines in the display controller that outputs the signal to the display screen, the vertical retrace window of the display controller is predicted to obtain the predicted time of the vertical retrace window; performing atomic locking processing on a multi-level frame buffer that supplies data to a display screen according to the vertical retrace window prediction time to obtain a buffer switching control signal; Performing rendering completion analysis on the GPU rendering pipeline that renders the display screen image according to the buffer switching control signal to obtain a rendering completion evaluation result; The multi-level buffer synchronization strategy of the display screen is reconstructed according to the rendering completion evaluation result, and the frame rate of the display screen is adjusted based on the reconstructed multi-level buffer synchronization strategy.

[0005] Optionally, in a first implementation of the first aspect of the present invention, the predicting a vertical retrace window of a display controller by detecting a change in a time interval between adjacent scan lines in a display controller that outputs a signal to a display screen to obtain a predicted vertical retrace window time includes: The scanning position monitoring unit continuously samples the hardware counter in the scanning generator of the display controller to obtain the real-time position data of the scanning row number and the scanning column number; Detecting and processing the change in the time interval between adjacent scanning lines according to the real-time position data to obtain current scanning speed data, and updating the scanning speed history data according to the current scanning speed data to obtain scanning speed fluctuation data; Performing preliminary prediction processing on the vertical retrace window start time using a Kalman filter algorithm based on the scanning speed fluctuation data to obtain a preliminary predicted time; The pixel data in the foreground buffer and the backstage buffer of the display controller are compared pixel by pixel, and the safety margin of the preliminary prediction time is dynamically adjusted according to the pixel difference calculation result to obtain the vertical retrace window prediction time.

[0006] Optionally, in a second implementation of the first aspect of the present invention, performing pixel-by-pixel comparison processing on pixel data in the foreground buffer and the backstage buffer of the display controller, and dynamically adjusting the safety margin of the preliminary prediction time based on a pixel difference calculation result to obtain the vertical retrace window prediction time includes: Calculating the RGB component difference of corresponding pixel positions in the foreground buffer and the backstage buffer using a Euclidean distance algorithm to obtain a pixel difference matrix; Performing statistical processing on the distribution density of the image change area according to the pixel difference matrix to obtain regional distribution density data; Classifying high-change areas and low-change areas using a regional clustering algorithm based on the regional distribution density data to obtain a picture change complexity evaluation result; Calculating a buffer switching risk coefficient according to the picture change complexity evaluation result, and determining a safety boundary adjustment parameter through a risk evaluation model according to the risk coefficient; The preliminary prediction time is corrected according to the safety margin adjustment parameter using a time window smoothing algorithm to obtain a vertical retrace window prediction time.

[0007] Optionally, in a third implementation of the first aspect of the present invention, performing atomic locking processing on a multi-level frame buffer that supplies data to a display screen according to the vertical retrace window prediction time to obtain a buffer switching control signal includes: Calculating a pre-lock start timing according to the vertical retrace window prediction time, and freezing the write operation permission of the multi-level frame buffer 2-3 scan lines before the vertical retrace window according to the pre-lock start timing to obtain a pre-lock state signal; Redirecting a write request from the GPU rendering pipeline through a buffer access arbiter according to the pre-lock state signal, transferring a write operation target from a foreground buffer and a backstage buffer to a standby buffer, and obtaining a write operation redirection control signal; According to the write operation redirection control signal, a foreground buffer pointer and a data source address of a display scanner are synchronously updated through an atomic operation instruction to obtain a buffer pointer switching signal; The access rights of the multi-level frame buffer are restored according to the buffer pointer switching signal, the target buffer allocation state of the rendering pipeline is updated, and a buffer switching control signal is obtained.

[0008] Optionally, in a fourth implementation of the first aspect of the present invention, performing rendering completion analysis on the GPU rendering pipeline that renders the display screen image according to the buffer switching control signal to obtain a rendering completion evaluation result includes: triggering monitoring of workload status of a vertex processing unit, a pixel processing unit, and a rasterization unit in a GPU rendering pipeline according to the buffer switching control signal to obtain real-time load data of each unit; Performing statistical analysis on the instruction queue depth and cache hit rate of the GPU rendering pipeline based on the real-time load data, and quantifying the rendering progress of the current frame in combination with pipeline stage delay calculation to obtain a rendering progress percentage; According to the rendering progress percentage combined with real-time sampling data of GPU memory bandwidth occupancy and texture fill rate, a rendering performance bottleneck position is identified and processed by a weighted average algorithm to obtain a performance bottleneck analysis result; The expected completion time of the current frame is predicted based on the performance bottleneck analysis results combined with historical rendering time statistics to obtain a rendering completion evaluation result.

[0009] Optionally, in a fifth implementation of the first aspect of the present invention, reconstructing the multi-level buffer synchronization strategy of the display screen according to the rendering completion evaluation result, and adjusting the display screen frame rate based on the reconstructed multi-level buffer synchronization strategy includes: Calculating the matching degree between the current frame rate and the GPU rendering capability according to the rendering completion evaluation result to obtain a frame rate adjustment coefficient; Calculate the number configuration and switching timing parameters of the multi-level buffer according to the frame rate adjustment coefficient to obtain the buffer configuration parameters; Reconstructing the buffer allocation strategy through a dynamic programming algorithm according to the buffer configuration parameters and adjusting the pixel clock frequency and scan line timing parameters of the display controller according to the reconstructed multi-level buffer synchronization strategy to obtain a frame rate control parameter; The vertical synchronization signal frequency of the display screen is updated through hardware register configuration according to the frame rate control parameters, and the frame rate of the display screen is adjusted and controlled.

[0010] Optionally, in a sixth implementation of the first aspect of the present invention, the buffer allocation strategy is reconstructed using a dynamic programming algorithm based on the buffer configuration parameters, and the pixel clock frequency and scan line timing parameters of the display controller are adjusted based on the reconstructed multi-level buffer synchronization strategy to obtain the frame rate control parameters, including: Establishing a buffer state transfer matrix according to the buffer configuration parameters, and performing optimization calculation processing on the buffer switching path through a dynamic programming algorithm according to the buffer state transfer matrix to obtain an optimal buffer switching sequence; reallocating the read and write priorities and access permissions of the multi-level buffers according to the optimal buffer switching sequence to obtain a reconstructed multi-level buffer synchronization strategy; Calculating a pixel clock division coefficient of a display controller according to the reconstructed multi-level buffer synchronization strategy, and adjusting the pixel clock frequency using a clock frequency modulation algorithm according to the pixel clock division coefficient to obtain an adjusted pixel clock frequency; The horizontal synchronization interval and the vertical synchronization interval of the scan line are calculated according to the adjusted pixel clock frequency, and the scan line timing parameters are adjusted according to the horizontal synchronization interval and the vertical synchronization interval through a timing parameter optimization algorithm to obtain a frame rate control parameter.

[0011] A second aspect of the present invention provides a device for adjusting the frame rate of a display screen, the device comprising: A timing prediction module is used to predict the vertical retrace window of the display controller by detecting the change in the time interval between adjacent scan lines in the display controller that outputs signals to the display screen, and obtain the predicted time of the vertical retrace window; a buffer locking module, configured to atomically lock the multi-stage frame buffer supplying data to the display screen according to the vertical retrace window prediction time, and obtain a buffer switching control signal; A rendering analysis module is used to perform rendering completion analysis on the GPU rendering pipeline that renders the display screen image according to the buffer switching control signal to obtain a rendering completion evaluation result; A strategy reconstruction module is used to reconstruct the multi-level buffer synchronization strategy of the display screen according to the rendering completion evaluation result, and adjust the display screen frame rate based on the reconstructed multi-level buffer synchronization strategy.

[0012] A third aspect of the present invention provides a device for adjusting the frame rate of a display screen, comprising: a memory and at least one processor, wherein the memory stores instructions, and the memory and the at least one processor are interconnected via a line; the at least one processor calls the instructions in the memory so that the device for adjusting the frame rate of the display screen executes the steps of the above-mentioned method for adjusting the frame rate of the display screen.

[0013] A fourth aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions that, when executed on a computer, enable the computer to execute the steps of the above-mentioned method for adjusting the frame rate of a display screen.

[0014] The above-mentioned display screen frame rate adjustment method, device, equipment, and storage medium predict the vertical retrace window by detecting the change in the time interval between adjacent scan lines in the display controller to obtain the vertical retrace window prediction time; atomically lock the multi-level frame buffer according to the vertical retrace window prediction time to obtain a buffer switching control signal; analyze the rendering completion of the GPU rendering pipeline according to the buffer switching control signal, obtain and reconstruct the multi-level buffer synchronization strategy based on the rendering completion evaluation result, and adjust the display screen frame rate based on the reconstructed synchronization strategy. By accurately predicting the vertical retrace window timing and implementing atomic buffer locking, the present invention ensures the precise synchronization of frame buffer switching and display scanner position, effectively solving the problem of single-frame flickering caused by improper buffer switching timing and improving the visual continuity of professional display applications.

[0015] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or understood by practicing the present invention. The purposes and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0016] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of a first embodiment of a method for adjusting the frame rate of a display screen according to an embodiment of the present invention; Figure 2 Schematic diagram of an embodiment of a device for adjusting the frame rate of a display screen according to an embodiment of the present invention; Figure 3 FIG. 1 is a schematic diagram of an embodiment of a device for adjusting the frame rate of a display screen according to an embodiment of the present invention. DETAILED DESCRIPTION

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0019] The terms "including," "having," and any variations thereof, as used in the embodiments of the present invention are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to the process, method, product, or device.

[0020] To facilitate understanding of this embodiment, a method for adjusting the frame rate of a display screen disclosed in an embodiment of the present invention is first described in detail. Figure 1 As shown, this method includes the following steps: 101. Predicting a vertical retrace window of a display controller by detecting a change in a time interval between adjacent scan lines in a display controller that outputs a signal to a display screen, thereby obtaining a predicted vertical retrace window time. In one embodiment of the present invention, the method of predicting the vertical retrace window of the display controller by detecting the change in the time interval of adjacent scan lines in the display controller that outputs a signal to the display screen to obtain the predicted time of the vertical retrace window includes: continuously sampling the hardware counter in the scan generator of the display controller through a scan position monitoring unit to obtain real-time position data of the scan row number and the scan column number; detecting the change in the time interval of adjacent scan lines based on the real-time position data to obtain current scan speed data, and updating the scan speed history data based on the current scan speed data to obtain scan speed fluctuation data; performing preliminary prediction processing on the start time of the vertical retrace window through a Kalman filtering algorithm based on the scan speed fluctuation data to obtain preliminary prediction time; performing pixel-by-pixel comparison processing on the pixel data of the foreground buffer and the background buffer of the display controller, and dynamically adjusting the safety boundary of the preliminary prediction time based on the pixel difference calculation result to obtain the predicted time of the vertical retrace window.

[0021] Specifically, in professional display systems, the display controller uses a scan generator to generate regular scan signals to control the display's pixel updates. Hardware counters within the scan generator record the precise coordinates of the current scan position in real time. The scan position monitoring unit, a dedicated hardware module, monitors these hardware counters through a high-frequency continuous sampling mechanism. The sampling frequency is typically set to several dozen times the display refresh rate, ensuring that even subtle changes in the scan position are captured. During the sampling process, the monitoring unit synchronously reads the values ​​of the horizontal scan counter and the vertical scan counter, which correspond to the column and row coordinates of the current scan point on the screen, respectively. The scan row number indicates the number of the screen row currently being scanned, starting from row 0 at the top of the screen and incrementing to the maximum row number at the bottom, before returning to row 0 to begin the next scan cycle. The scan column number indicates the specific pixel position within the current scan row, starting from column 0 at the beginning of the row and incrementing to the maximum column number at the end. By continuously collecting this real-time position data, the system can construct a complete scan trajectory map. This data not only reflects the current operating status of the display controller but, more importantly, provides a precise data source for subsequent time interval analysis.

[0022] Specifically, based on the real-time position data, the system calculates the time intervals between adjacent scan lines to assess the current scan speed. The detection processing module continuously monitors changes in the vertical scan counter. When it detects a jump from line N to line N+1, it records the precise timestamp of this jump. By calculating the time difference between two consecutive line jumps, the scan time for a single scan line is calculated. Current scan speed data is obtained by statistically analyzing the scan times of several recent scan lines. Specifically, the calculation method is to take the weighted average of the inverses of these time intervals to obtain a scan speed value in lines per second. The system also maintains a historical scan speed database, recording scan speed trends over a specific time window. As new scan speed data is generated, the historical database is updated according to a time-weighted strategy, assigning higher weights to newer data and gradually decreasing the weights of older data. By comparing the current scan speed data with the historical average, the system calculates scan speed fluctuation data, which reflects the stability of the display controller's operating status. Fluctuations in scan speed are mainly caused by factors such as hardware temperature changes, power supply fluctuations, and load changes. Although these fluctuations are small in magnitude, they have an important impact on accurate timing prediction.

[0023] Specifically, scan speed fluctuation data serves as an input parameter for the Kalman filter algorithm, which is used to scientifically predict the start time of the vertical retrace window. The Kalman filter algorithm is a recursive digital filter particularly well-suited for state estimation in noisy dynamic systems. It can effectively handle random scan speed fluctuations in display timing prediction. The algorithm first establishes a state-space model of the scanning process, using parameters such as the current scan position, scan speed, and acceleration as state variables. The state transition equations describe the temporal evolution of these variables. At the beginning of the prediction process, the algorithm uses the state estimate from the previous moment and the state transition model to calculate the current state prediction. The prediction is then refined by incorporating the scan speed fluctuation data as observations. Through recursive iteration, the algorithm continuously optimizes the accuracy of the state estimate, ultimately outputting a preliminary prediction for the start time of the vertical retrace window. The vertical retrace window is the period between the completion of the display scan and the start of the first row of pixels. During this time window, the display controller does not output valid pixel data, making it the optimal time to perform frame buffer switching operations. The preliminary prediction time is obtained through the output of the Kalman filter algorithm, but since the algorithm is based on the statistical characteristics of the scanning speed, further dynamic adjustment is required to cope with complex situations in actual applications.

[0024] Specifically, to further improve prediction accuracy and ensure buffer switching safety, the system performs pixel-level difference analysis on the display controller's foreground and back buffers. The foreground buffer stores the currently displayed image data, while the back buffer contains the new image data to be switched. The degree of pixel difference between the two directly affects the risk level of buffer switching. This pixel-by-pixel comparison process iterates through each pixel position in the buffers, reads the corresponding RGB color component values, and calculates the color difference between pixels at the same position in the two buffers. Pixel difference is calculated using the Euclidean distance formula, which squares and square-roots the difference between the three RGB color components to produce a scalar value quantifying the visual difference between the two pixels. When the image content changes significantly, the pixel difference is generally higher. In this case, even slight errors in the buffer switching timing are more likely to cause users to notice flicker, so a more conservative safety margin setting is required. Conversely, when the image content changes less, even slight errors in the switching timing have a relatively small impact on the visual effect. In this case, the safety margin can be appropriately reduced to improve system responsiveness. The safety margin adjustment process dynamically determines the amount of time offset to add or subtract from the initial prediction time based on the pixel disparity calculation results. A high disparity corresponds to a larger safety margin, while a low disparity corresponds to a smaller safety margin. By combining the initial prediction time with the dynamically calculated safety margin, a precisely adjusted vertical retrace window prediction time is ultimately obtained.

[0025] Furthermore, the pixel data of the foreground buffer and the backstage buffer of the display controller are compared pixel by pixel, and the safety boundary of the preliminary prediction time is dynamically adjusted according to the pixel difference calculation result to obtain the vertical retrace window prediction time, including: calculating the RGB component difference of the corresponding pixel positions of the foreground buffer and the backstage buffer by the Euclidean distance algorithm to obtain a pixel difference matrix; statistically processing the distribution density of the picture change area according to the pixel difference matrix to obtain regional distribution density data; classifying the high-change area and the low-change area by the regional clustering algorithm according to the regional distribution density data to obtain a picture change complexity assessment result; calculating the buffer switching risk coefficient according to the picture change complexity assessment result, and determining the safety boundary adjustment parameter according to the risk coefficient through the risk assessment model; correcting the preliminary prediction time according to the safety boundary adjustment parameter by the time window smoothing algorithm to obtain the vertical retrace window prediction time.

[0026] Specifically, the system first iterates through each pixel in the foreground and back buffers, reading the red, green, and blue color component values ​​for the corresponding pixel. For any pixel on the screen, the system simultaneously extracts color information from both the foreground and back buffers, recording the intensity values ​​for the red, green, and blue components. The Euclidean distance algorithm first calculates the difference between the corresponding color components in the two buffers: the red component in the back buffer minus the red component in the foreground buffer. The same subtraction operation is used for the green and blue components. Each color component difference is then squared, the three squared values ​​are added together, and the square root of the result is taken to obtain a difference value for that pixel. This value directly reflects the degree of visual difference between the pixels at that location in the two buffers, with larger values ​​indicating more pronounced differences. The system applies this calculation process to every pixel on the screen, scanning row by row, starting from the top-left corner of the screen and processing all pixels in each row until it reaches the bottom-right corner. In its implementation, the system uses multi-threaded parallel computing technology to improve processing speed. The entire screen is divided into several processing blocks, with each processing thread responsible for calculating the disparity of all pixels within a specific area. Once the calculation is complete, the system organizes the disparity values ​​for all pixel positions according to their on-screen coordinates, constructing a two-dimensional data structure that perfectly corresponds to the screen resolution—the pixel disparity matrix. Each position in this matrix stores the disparity calculation result for the corresponding screen pixel. For an 8-bit color system, the maximum difference value for a single component is 255, resulting in a theoretical maximum pixel disparity of approximately 441.

[0027] Specifically, based on the pixel difference matrix, the system performs a distribution density statistical analysis of image change areas. This statistical processing utilizes a sliding window technique, which divides the entire screen into a regular rectangular grid. Each grid is called a statistical block. The block size is dynamically adjusted based on screen resolution and processing accuracy requirements, typically set to a square area of ​​32 or 64 pixels on a side. This size ensures statistical validity without excessively increasing computational burden. For each statistical block, the system performs three different statistical calculations. The first is to calculate the average difference of all pixels within the block, representing the overall intensity of change within the block. The second is to calculate the standard deviation of the pixel differences within the block. The standard deviation reflects the dispersion of change within the block. A larger standard deviation indicates a mix of pixels with significant and minor changes within the block, while a smaller standard deviation indicates a relatively uniform degree of change across all pixels within the block. The third is to count the number of pixels within the block whose difference exceeds a preset threshold. This threshold is typically set at 1.5 times the average difference of all pixels on the entire screen. Pixels exceeding the threshold are considered significantly changed, and the ratio of their number to the total number of pixels in the block is called the pixel density of change. The system calculates a comprehensive change density index for each block by applying a weighted combination of these three statistical indicators. In this weighted combination, average change intensity dominates, receiving a weight of 0.5, change dispersion receives a weight of 0.3, and change pixel density receives a weight of 0.2. The change density indicators for all blocks form the regional distribution density data. This data structure preserves the spatial distribution characteristics of image changes while compressing the original pixel-level data into easily processable regional statistical information.

[0028] Specifically, the regional clustering algorithm automatically classifies and identifies change regions based on regional distribution density data. The algorithm first performs a global statistical analysis of the change density indicators of all blocks, calculating the mean and standard deviation of the global change density. These two statistics reflect the overall level of change and the degree of dispersion of change in the current image. Based on these global statistical results, the system sets two key classification thresholds: a high change threshold equal to the global mean plus one standard deviation, and a low change threshold equal to the global mean minus one standard deviation. Blocks with a change density exceeding the high threshold are directly labeled as high-change blocks, while blocks with a change density below the low threshold are directly labeled as low-change blocks. For blocks with a change density between the two thresholds, the system uses neighborhood analysis to determine the classification. Neighborhood analysis examines the classification of the target block's eight neighboring blocks: blocks above, below, to the left, to the right, and in the four diagonal directions. If the number of high-change blocks among the eight neighboring blocks exceeds the number of low-change blocks, the target block is classified as high-change; otherwise, it is classified as low-change. After the classification is completed, the system uses the connected domain labeling algorithm to identify continuous high-change areas and low-change areas on the screen. The connected domain labeling algorithm uses a depth-first search method, starting from each unmarked high-change block, recursively accessing all adjacent high-change blocks, and marking them as the same connected area. Statistical processing calculates the proportion of the total area of ​​the high-change area to the entire screen area, and at the same time identifies the largest continuous high-change area and calculates its area ratio. The picture change complexity assessment result is obtained through weighted calculation. The total area ratio of the high-change area is assigned a weight of 0.6, and the area ratio of the largest continuous area is assigned a weight of 0.4. The weighted sum is obtained after the value between 0 and 1. The closer the value is to 1, the more complex the picture change.

[0029] Specifically, the buffer switching risk factor is calculated using a segmented mapping strategy, with different calculation methods selected based on the range of image change complexity. When the image change complexity is less than 0.3, it falls into the low complexity range, where the visual impact of the change is relatively small. The risk factor is calculated using a linear relationship: multiplying the complexity value by 0.5. When the complexity is between 0.3 and 0.7, it falls into the medium complexity range, where the visual impact of the change exhibits a nonlinear growth pattern. The risk factor is calculated using a quadratic function, which more accurately reflects the amplifying effect of increasing complexity on risk. When the complexity exceeds 0.7, it falls into the high complexity range, where the marginal impact of further increasing complexity on risk gradually decreases. The risk factor is calculated using a logarithmic function to ensure that the risk factor does not grow indefinitely. The calculated risk factor needs to be converted into specific safety margin adjustment parameters. This conversion process uses a preset mapping table for lookup. The mapping table was established based on extensive experimental data. Low risk corresponds to a time adjustment of 0.1 scan line cycle, medium risk corresponds to 0.3 scan line cycle, and high risk corresponds to 0.5 scan line cycle. A time window smoothing algorithm is used to prevent drastic fluctuations in the safety margin adjustment parameters between consecutive frames. The algorithm maintains a fixed-length circular buffer of 8 to store the safety margin adjustment parameter history for the last eight frames. Smoothing is performed using an exponentially decaying weighted average, assigning a weight of 0.4 to the adjustment parameter for the most recent frame, 0.3 to the previous frame, 0.2 to the previous frame, and 0.1 to the oldest frame. By adding the initial prediction time to the smoothed safety margin adjustment parameter, the system ultimately obtains a precisely corrected vertical retrace window prediction time. This time value, expressed with nanosecond precision, fully meets the stringent timing control requirements of high-frequency display systems.

[0030] 102. Perform atomic locking processing on a multi-level frame buffer that supplies data to a display screen according to the vertical retrace window prediction time to obtain a buffer switching control signal; In one embodiment of the present invention, performing atomic locking processing on the multi-level frame buffers supplying data to the display screen according to the vertical retrace window prediction time to obtain the buffer switching control signal includes: The pre-lock start timing is calculated according to the vertical retrace window prediction time, and the write operation permission of the multi-level frame buffer is frozen at 2-3 scan lines before the vertical retrace window according to the pre-lock start timing to obtain a pre-lock status signal; according to the pre-lock status signal, the write request from the GPU rendering pipeline is redirected through the buffer access arbiter, and the write operation target is transferred from the foreground buffer and the background buffer to the preparation buffer to obtain a write operation redirection control signal; according to the write operation redirection control signal, the foreground buffer pointer and the data source address of the display scanner are synchronously updated through atomic operation instructions to obtain a buffer pointer switching signal; according to the buffer pointer switching signal, the access permission of the multi-level frame buffer is restored, the target buffer allocation status of the rendering pipeline is updated, and a buffer switching control signal is obtained.

[0031] Specifically, the predicted vertical retrace window time, serving as the benchmark for timing control, needs to be converted into a specific pre-lock start timing to control buffer access freeze operations. The pre-lock start timing calculation process first obtains the current display controller's scan parameters, including hardware timing information such as the scan cycle of a single scan line, horizontal retrace time, and total vertical retrace duration. The calculation module subtracts two to three scan line periods from the predicted vertical retrace window time to determine the specific start time for the pre-lock operation. This time advance is set to ensure that all necessary buffer state freeze operations are completed before the vertical retrace window actually arrives, thus avoiding access conflicts at critical moments. The specific number of scan lines is dynamically adjusted based on the current image complexity and rendering load. A three-scan line advance is selected for high complexity, while a two-scan line advance is selected for low complexity. When the pre-lock start timing arrives, the lock control module immediately freezes write access to the multi-level frame buffer. The multi-level frame buffer consists of three independent storage areas: the foreground buffer, the backstage buffer, and the reserve buffer. The foreground buffer stores the currently displayed screen data, the backstage buffer stores the new screen data that will be switched for display, and the reserve buffer serves as a temporary storage area for processing data write operations during the switching process. Freezing processing is achieved by setting specific bits in the buffer access control register, clearing the write enable bits of the foreground and backstage buffers while keeping the read enable bits unchanged, ensuring that the display scanner can still read data from the foreground buffer for display output. The pre-lock status signal is a hardware control signal used to indicate that the current buffer access rights have entered a frozen state. This signal is passed to the buffer access arbitrator and rendering pipeline control module to notify them to adjust subsequent data access strategies.

[0032] Specifically, upon receiving the pre-lock status signal, the buffer access arbiter immediately initiates a write request redirection mechanism. The arbiter is a dedicated hardware module responsible for coordinating access requests to buffer resources from different processing units, ensuring that conflicts do not occur between multiple access sources. Under normal operation, write requests generated by the GPU rendering pipeline are directed to designated buffers based on the current buffer allocation policy, with the foreground and back buffers being the primary write targets. When the pre-lock status is activated, the arbiter reroutes all write requests originally directed to the foreground and back buffers to the reserve buffer. This redirection mechanism is implemented by modifying the arbiter's internal address mapping table, which records the correspondence between logical buffer addresses and physical storage addresses. The arbiter maps the logical addresses of the foreground and back buffers to the physical address space of the reserve buffer. This allows write requests issued by the GPU rendering pipeline to be automatically directed to the reserve buffer after address translation. The redirection operation is transparent; the GPU rendering pipeline remains unaware of the address redirection and continues to send write requests using the original logical addresses. The address translation is performed entirely by the arbiter at the hardware level. The write redirection control signal is a status indicator generated by the arbiter, indicating that all current write requests have been successfully redirected to the reserve buffer. The data contents of the front and back buffers remain stable, and no new write operations will affect their data integrity. This control signal provides a safe execution environment for subsequent atomic operations, ensuring that data inconsistencies do not occur during buffer switching.

[0033] Specifically, the execution of an atomic operation instruction requires the simultaneous update of the foreground buffer pointer and the display scanner data source address within a very short timeframe. Atomic operations are uninterruptible hardware operations that ensure that multiple related register updates are completed within the same clock cycle, avoiding the occurrence of partial updates. The operation first prepares two key address parameters: the new foreground buffer pointer address and the new display scanner data source address. The new foreground buffer pointer points to the physical address of the original back buffer, as the purpose of the switch is to promote the back buffer to the new foreground buffer. The new display scanner data source address also points to the original back buffer, ensuring that the display output reads data from the new buffer. Atomic operation instructions are implemented using a dedicated hardware execution unit capable of simultaneously updating multiple register values ​​within a single clock cycle. The specific update process involves updating the foreground buffer pointer register to point to the original back buffer address, updating the display scanner source address register to the same address value, and simultaneously updating the back buffer pointer register to point to the original foreground buffer address, thus completely swapping the roles of the two buffers. After the operation is complete, the hardware automatically generates a buffer pointer switch signal, which indicates that the buffer's logical role has been switched. The original back buffer is now the new foreground buffer, and the original foreground buffer is now the new back buffer. The buffer pointer switch signal also contains a timestamp, recording the precise moment the switch operation was completed. This timestamp can be used to verify that the switch operation was completed within the predetermined vertical retrace window.

[0034] After the buffer pointer switch is complete, the access permission recovery process is responsible for returning the multi-level frame buffer's access control state to normal operation. The recovery process first checks the validity of the buffer pointer switch signal to confirm that the switch operation was successful and no exceptions occurred. This check verifies the consistency of the foreground buffer pointer and the display scanner's data source address, ensuring that they point to the same physical storage area. Once verified, the recovery module resets the buffer access control registers, restoring the write enable bits of the foreground and back buffers to their normal states, allowing subsequent write operations to access these buffers. Simultaneously, the recovery module also updates the rendering pipeline's target buffer allocation status, informing the GPU rendering pipeline of the current buffer role assignments. The rendering pipeline's target buffer allocation status is a data structure containing multiple fields that records the current roles and availability of the foreground, back, and reserve buffers. The update process marks the new foreground buffer as read-only for reading by the display scanner, marks the new back buffer as writable for writing new image data to the GPU rendering pipeline, and restores the reserve buffer to a standby state, ready for the next switch operation. Upon receiving the updated allocation status information, the rendering pipeline automatically adjusts its output target and writes the newly rendered image data to the newly designated background buffer. The buffer switch control signal, the final output of the entire atomic locking process, contains key information such as the completion status of the switch operation, timestamp information, and the new buffer allocation status. This control signal not only marks the end of the current switch cycle but also provides the necessary input data for rendering completion analysis, ensuring that subsequent performance evaluation can be based on accurate buffer status information.

[0035] 103. Perform rendering completion analysis on the GPU rendering pipeline that renders the display screen image according to the buffer switching control signal to obtain a rendering completion evaluation result; In one embodiment of the present invention, the rendering completion analysis and processing of the GPU rendering pipeline for rendering the display screen image is performed according to the buffer switching control signal to obtain a rendering completion evaluation result, including: triggering the monitoring of the workload status of the vertex processing unit, pixel processing unit and rasterization unit in the GPU rendering pipeline according to the buffer switching control signal to obtain real-time load data of each unit; performing statistical analysis on the instruction queue depth and cache hit rate of the GPU rendering pipeline according to the real-time load data, and quantifying the rendering progress of the current frame in combination with the pipeline stage delay calculation to obtain a rendering progress percentage; identifying the rendering performance bottleneck position through a weighted average algorithm based on the rendering progress percentage in combination with real-time sampling data of the GPU memory bandwidth occupancy rate and texture fill rate to obtain a performance bottleneck analysis result; predicting the expected completion time of the current frame based on the performance bottleneck analysis result in combination with historical rendering time statistics to obtain a rendering completion evaluation result.

[0036] Specifically, the buffer switch control signal activates the GPU rendering pipeline monitoring mechanism. The monitoring module reads the performance counter values ​​of the vertex processing unit, pixel processing unit, and rasterization unit. Vertex processing unit monitoring is achieved by reading the vertex throughput counter and geometry shader execution counter, which record the number of vertices processed and the number of shading instructions executed. The pixel processing unit load is monitored based on the pixel fill counter and texture sample counter. The former counts the number of pixels processed, while the latter records the number of texture accesses. The rasterization unit is monitored using the triangle setup counter and depth test counter, which record the number of rasterized primitives and the number of depth comparison operations, respectively. The monitoring process uses a fixed sampling interval of 1 millisecond. Each sample reads the current value of all counters and calculates the difference with the previous sample. The difference is divided by the sampling interval to obtain the processing rate of each unit. The processing rate is compared with the theoretical peak performance of each unit to calculate the load percentage. The theoretical peak performance of the vertex processing unit is 10 million vertices per second. The current processing rate is divided by the peak performance to obtain the load percentage. The peak fill rate of the pixel processing unit is 4 billion pixels per second, and the peak setup rate of the rasterization unit is 50 million triangles per second. The real-time load data includes the load percentage values ​​of the three processing units, ranging from 0% to 100%. Values ​​exceeding 90% indicate that the unit is close to saturation.

[0037] Specifically, based on real-time load data, the analysis module reads the instruction queue status register of each processing unit to obtain queue depth information. The instruction queue depth of the vertex processing unit is read from the vertex queue count register, with a normal range of 32 to 128 instructions. The queue depth of the pixel processing unit is read from the pixel queue count register; a depth exceeding 256 instructions indicates insufficient processing power. The queue depth of the rasterization unit is read from the primitive queue count register, with a normal range of 16 to 64 instructions. Cache hit rate statistics are calculated by reading the hit counters and access counters of each cache level. The hit rate is calculated by dividing the number of hits by the total number of accesses. The vertex cache hit rate is read from the statistics register of the vertex cache controller, and the pixel cache hit rate is obtained from the texture cache controller. Pipeline stage latency is calculated using an instruction tagging method, recording a timestamp when an instruction enters the queue and calculating the time difference when the instruction completes. Latency statistics are calculated for the geometry processing, rasterization, and pixel shading stages, with each stage maintaining a separate latency accumulator. The current frame's rendering progress is calculated by the ratio of completed operations to total operations, with geometry processing progress accounting for 30%, rasterization progress accounting for 40%, and pixel shading progress accounting for 30%. The progress calculation module reads the completion counters for each stage, divides the number of completed operations by the estimated total, and calculates the progress of each stage. The weighted sum is used to obtain the overall rendering progress percentage.

[0038] Specifically, the rendering progress percentage, along with GPU memory bandwidth utilization and texture fill rate data, is input into a weighted average algorithm for bottleneck identification. Memory bandwidth utilization is calculated using the memory controller's transfer volume counter. The current transfer rate is divided by the theoretical peak bandwidth to obtain the utilization percentage. The texture fill rate is obtained using the texture processing unit's pixel output counter. The actual fill rate is divided by the theoretical peak fill rate to obtain the efficiency percentage. The weighted average algorithm assigns a weight of 0.4 to rendering progress, 0.3 to memory bandwidth utilization, and 0.3 to texture fill rate. The algorithm multiplies each of these three metrics by their corresponding weights and sums them to create a comprehensive score. Bottleneck identification is based on the relative differences between these metrics. When memory bandwidth utilization exceeds 85% and is significantly higher than other metrics, it is identified as a memory bandwidth bottleneck. When texture fill rate is below 60% and significantly lower than other metrics, it is identified as a texture processing bottleneck. When the rendering progress percentage increases slowly and the queue depth continues to increase, it is identified as a processing capacity bottleneck. Performance bottleneck analysis results include a bottleneck type code, severity level, and current performance utilization data.

[0039] Specifically, performance bottleneck analysis results are combined with historical rendering time statistics to predict completion times. The historical statistics database is indexed by bottleneck type, load level, and scene complexity, storing average rendering times under these conditions. The prediction algorithm searches the historical database for matching records based on the current bottleneck type and extracts information about average completion times and time variance. The matching process considers both exact matches of bottleneck types and similar matches of load levels. Records with load level differences within 10% are included in the prediction calculation. The predicted time is calculated based on the current elapsed time and the remaining workload, where the remaining workload is equal to 1 minus the current rendering progress percentage. The algorithm extracts the average time taken to complete similar remaining workloads from the matching historical records and adjusts the time based on the current load status. When the current load is above the historical average, the predicted time is proportionally increased; when the load is below the historical average, the predicted time is reduced accordingly. The rendering completion assessment results include four core data points: the current rendering progress percentage, the estimated remaining completion time, the main performance bottleneck type, and the prediction confidence. The progress percentage reflects the completion level of the current frame, the remaining time indicates the expected completion time, the bottleneck type identifies the current performance limiting factor, and the confidence level indicates the reliability of the prediction result. The evaluation results are output in a structured data format, with numerical precision maintained to two decimal places and time units expressed in milliseconds.

[0040] 104. Reconstruct a multi-level buffer synchronization strategy of the display screen according to the rendering completion evaluation result, and adjust the display screen frame rate based on the reconstructed multi-level buffer synchronization strategy.

[0041] In one embodiment of the present invention, the multi-level buffer synchronization strategy of the display screen is reconstructed according to the rendering completion evaluation result, and the frame rate of the display screen is adjusted based on the reconstructed multi-level buffer synchronization strategy, including: calculating the matching degree between the current frame rate and the GPU rendering capability according to the rendering completion evaluation result to obtain a frame rate adjustment coefficient; calculating the number configuration and switching timing parameters of the multi-level buffer according to the frame rate adjustment coefficient to obtain buffer configuration parameters; reconstructing the buffer allocation strategy through a dynamic programming algorithm according to the buffer configuration parameters and adjusting the pixel clock frequency and scan line timing parameters of the display controller according to the reconstructed multi-level buffer synchronization strategy to obtain frame rate control parameters; updating the vertical synchronization signal frequency of the display screen through hardware register configuration according to the frame rate control parameters to adjust and control the frame rate of the display screen.

[0042] Specifically, the rendering completion assessment results are input into the frame rate matching calculation module. The calculation process first extracts three key data points from the assessment results: the current rendering progress percentage, the estimated remaining completion time, and the main performance bottleneck type. The calculation module determines the estimated total rendering time for the current frame based on the estimated remaining completion time and converts the reciprocal of the estimated total time into a frame rate corresponding to the GPU's actual rendering capabilities. The current display frame rate is obtained by reading the display controller's vertical synchronization counter, which records the period of the vertical synchronization signal. The reciprocal of this period is the current frame rate. The matching calculation divides the GPU's actual rendering frame rate by the current display frame rate to obtain a matching ratio. A ratio equal to 1 indicates a perfect match, greater than 1 indicates excess GPU rendering capacity, and less than 1 indicates insufficient GPU rendering capacity. When the matching ratio is between 0.9 and 1.1, the calculation module assesses the matching as good and sets the frame rate adjustment factor to 1.0, indicating no adjustment is required. When the matching ratio is greater than 1.1, it indicates that the GPU is capable of supporting higher display frame rates. The frame rate adjustment factor is set to the square root of the matching ratio to avoid excessive adjustments. When the matching ratio is less than 0.9, it indicates that the current display frame rate exceeds the GPU processing capability. The frame rate adjustment coefficient is set to the matching ratio multiplied by 0.95, and the target frame rate is appropriately lowered to ensure rendering stability. The performance bottleneck type corrects the adjustment coefficient. When the bottleneck is memory bandwidth limitation, the adjustment coefficient is multiplied by a correction factor of 0.9, because solving the memory bottleneck requires a more conservative frame rate setting. When the bottleneck is texture processing limitation, the adjustment coefficient is multiplied by a correction factor of 0.95. The impact of texture bottleneck on frame rate is relatively small. The effective range of the frame rate adjustment coefficient is limited to between 0.5 and 2.0. Values ​​out of the range will be truncated to the boundary value to avoid excessive frame rate changes affecting display stability.

[0043] Specifically, the frame rate adjustment coefficient is input into the buffer configuration calculation module, which then determines the number of multi-level buffers and switching timing parameters based on the adjustment coefficient. The number of buffers is dynamically determined based on the frame rate adjustment magnitude. When the adjustment coefficient approaches 1.0, a standard three-level buffer configuration is used, consisting of a foreground buffer, a background buffer, and a reserve buffer. When the adjustment coefficient is greater than 1.3, the frame rate needs to be increased. An additional auxiliary buffer is added to form a four-level buffer configuration. The additional buffer is used to alleviate buffer switching pressure at high frame rates. When the adjustment coefficient is less than 0.8, the frame rate needs to be reduced. A double-buffer configuration can be used to save video memory resources, removing the reserve buffer and retaining only the foreground and background buffers. The switching timing parameter calculation determines the buffer switching interval based on the new target frame rate. The target frame rate is equal to the current frame rate multiplied by the frame rate adjustment coefficient. The switching interval is equal to 1 divided by the target frame rate and represents the time difference between buffer switches in seconds. The switching timing also takes into account the length of the vertical retrace window, which is read from the display controller's timing register. Switching operations must occur within the retrace window. When the calculated switching interval is less than three times the retrace window length, the buffer number configuration needs to be adjusted to increase the number of buffers to provide more switching time. The buffer configuration parameters include four core data: the number of buffers, the size allocation of each buffer, the switching time interval, and the switching window length. The buffer size allocation is calculated based on the screen resolution and color depth. The size of each buffer is equal to the screen width multiplied by the height multiplied by the number of bytes per pixel. In the four-level buffer configuration, the main buffer is allocated a standard size, and the auxiliary buffer is allocated 80% of the size to process the rendering results of the simplified scene.

[0044] Specifically, buffer configuration parameters are fed into a dynamic programming algorithm module to reconstruct the buffer allocation strategy. The dynamic programming algorithm models the buffer allocation problem as a multi-stage decision-making process, with each stage corresponding to a buffer allocation decision for a rendering frame. The algorithm first establishes a state transition table, whose state variables include the current set of available buffers, the rendering load level, and display timing constraints. The state transition table records all possible transition paths from the current state to the next state, with each path corresponding to a buffer allocation solution. The algorithm's objective function is set as a weighted combination of minimizing buffer switching latency and maximizing rendering smoothness, with switching latency accounting for 40% and rendering smoothness accounting for 60%. The dynamic programming process begins from the initial state and gradually calculates the optimal decision for each stage, selecting the allocation solution that minimizes the objective function value at each stage. The algorithm considers buffer read-write conflict constraints: only one buffer can be written to at a time, and write operations are prohibited on the currently displayed foreground buffer. The reconstructed allocation strategy dynamically allocates the rendering pipeline's output targets to available buffers, prioritizing large buffers during high load and using smaller buffers to save resources during low load. The allocation strategy also includes a buffer priority queue, which prioritizes buffers based on frequency of use and switching cost. Based on the reconstructed multi-level buffer synchronization strategy, the adjustment module calculates the pixel clock frequency and scan line timing parameters of the display controller. The pixel clock frequency is equal to the screen resolution multiplied by the target frame rate, then multiplied by the scan overhead factor. The scan overhead factor takes into account the proportion of horizontal and vertical retrace time, with a standard value of 1.25. Scan line timing parameters include the horizontal scan period, horizontal retrace time, vertical scan period, and vertical retrace time. The horizontal scan period is equal to the pixel clock period multiplied by the screen width, with the horizontal retrace time set to 20% of the scan period. The vertical scan period is equal to the horizontal scan period multiplied by the screen height, with the vertical retrace time set to 5% of the vertical period.

[0045] Specifically, the frame rate control parameters generated by the adjustment process are input into the hardware register configuration module, which updates the vertical synchronization signal frequency by directly writing to the display controller's configuration registers. The display controller contains three key registers: the pixel clock configuration register, the horizontal timing configuration register, and the vertical timing configuration register. The pixel clock configuration register controls the division ratio of the pixel clock generator. The module converts the new pixel clock frequency into the corresponding division setting value and writes it into the register. The division ratio is calculated based on the display controller's main clock frequency, which is equal to the integer portion of the main clock frequency divided by the target pixel clock frequency. The horizontal timing configuration register contains four fields: the number of horizontal display pixels, the horizontal front porch time, the horizontal synchronization pulse width, and the horizontal back porch time. The module updates the values ​​of these fields based on the new horizontal scan parameters. The vertical timing configuration register contains four fields: the number of vertical display lines, the vertical front porch time, the vertical synchronization pulse width, and the vertical back porch time. The vertical synchronization pulse width directly determines the frequency of the vertical synchronization signal. Register updates utilize atomic writes, ensuring that all relevant registers are updated within the same clock cycle to avoid inconsistent timing parameters. The update is performed during the vertical retrace period to ensure that the display output of the current frame is not affected. After configuration is complete, the display controller automatically generates a vertical synchronization signal according to the new timing parameters. The vertical synchronization frequency is equal to the pixel clock frequency divided by the total number of scanned pixels. Frame rate adjustment control verifies the adjustment effect by monitoring the periodic changes of the vertical synchronization signal. The period measurement module continuously monitors 10 vertical synchronization periods and calculates the average value. The reciprocal of the average period is the actual achieved frame rate. When the deviation between the actual frame rate and the target frame rate is less than 2%, the adjustment control is successful. If the deviation exceeds 5%, the register configuration parameters must be recalculated and the update operation must be performed again.

[0046] Furthermore, the buffer allocation strategy is reconstructed through a dynamic programming algorithm according to the buffer configuration parameters, and the pixel clock frequency and scan line timing parameters of the display controller are adjusted according to the reconstructed multi-level buffer synchronization strategy to obtain the frame rate control parameters, including: establishing a buffer state transfer matrix according to the buffer configuration parameters, optimizing the buffer switching path through a dynamic programming algorithm according to the buffer state transfer matrix, and obtaining an optimal buffer switching sequence; reallocating the read and write priorities and access rights of the multi-level buffer according to the optimal buffer switching sequence to obtain a reconstructed multi-level buffer synchronization strategy; calculating the pixel clock division coefficient of the display controller according to the reconstructed multi-level buffer synchronization strategy, and adjusting the pixel clock frequency through a clock frequency modulation algorithm according to the pixel clock division coefficient to obtain an adjusted pixel clock frequency; calculating the horizontal synchronization interval and vertical synchronization interval of the scan line according to the adjusted pixel clock frequency, and adjusting the scan line timing parameters through a timing parameter optimization algorithm according to the horizontal synchronization interval and vertical synchronization interval to obtain the frame rate control parameters.

[0047] Specifically, buffer configuration parameters are input into the state matrix construction module, which constructs a two-dimensional state transition matrix based on the number of buffers and the switching sequence. The matrix's rows and columns represent the buffer's operating state combinations, including idle, write, read, and switch. Three-level buffering generates 12 state combinations. The construction process enumerates state transition paths and checks access constraints: only one buffer can be written at a time, writes are prohibited while the foreground buffer is reading, and switch operations are restricted to the retrace window. The transition cost is set based on the operation complexity: idle to write has a cost of 1, write to switch has a cost of 2, and switch to read has a cost of 3. Infeasible transitions are marked as infinite. A dynamic programming algorithm reads the state transition matrix and performs optimization calculations using a forward recursive approach, starting from the initial state. The algorithm maintains a decision table that records the minimum cumulative cost and optimal predecessor state for each state. Iterates through each row of the matrix to calculate the cost update for the successor state. The recursion continues for 10 frame periods, and the optimal buffer switching sequence is generated by backtracking the decision table. The sequence includes time steps, buffer identifiers, operation types, and execution timing.

[0048] Specifically, the optimal switching sequence input priority allocation module reallocates read and write priorities and access rights. The allocation is based on the frequency of use and criticality of the buffers in the sequence, and the number of occurrences and operation distribution of each buffer are counted. The foreground buffer is set to priority 1 for read operations, the background buffer is set to priority 2 for write operations, and the standby buffer is temporarily set to priority 3 for writes. The priority of the buffers participating in the switch is temporarily increased during the vertical retrace. The access rights use an 8-bit control word, with bit 0 controlling reads, bit 1 controlling writes, and bit 2 controlling switching. The foreground buffer only opens read permissions, the background buffer only opens write permissions, and the switching state opens all permissions. The reconstructed synchronization strategy includes a role mapping table, a priority scheduling table, and a permission control table. The mapping table records the correspondence between physical buffers and logical roles, the scheduling table arranges access requests by priority, and the control table records the permission settings at each moment.

[0049] Specifically, the reconstructed synchronization strategy input clock calculation module calculates the pixel clock division coefficient based on the switching time interval. The target frame rate is obtained by calculating the inverse of the switching interval. The pixel clock frequency is equal to the total number of screen pixels multiplied by the target frame rate. The total number of pixels includes effective display pixels and retrace virtual pixels. The horizontal total number of pixels is the display width plus the number of retrace pixels, and the vertical total number of pixels is the display height plus the number of retrace lines. The division coefficient is equal to the main clock frequency divided by the target pixel clock frequency, rounded down. The clock modulation algorithm uses fractional division technology to achieve non-integer division ratios, achieving precise frequency by periodically skipping or adding division pulses. The algorithm maintains a cumulative error register to record the division error and performs error compensation when it exceeds a threshold. The adjusted pixel clock is verified by a frequency counter, which measures the number of pulses within the time window to calculate the actual frequency.

[0050] Specifically, the pixel clock frequency input timing calculation module calculates the horizontal and vertical synchronization intervals. The horizontal synchronization interval is the total number of horizontal pixels divided by the pixel clock frequency, while the vertical synchronization interval is the total number of vertical pixels multiplied by the horizontal synchronization interval. The horizontal interval is subdivided into four components: active display, leading edge, synchronization pulse width, and trailing edge, with each component allocated proportionally. The vertical interval uses the same four-segment division scheme. The timing parameter adjustment algorithm reads the display controller constraint registers to obtain hardware parameter ranges and verify whether the calculated parameters meet the constraints. If the constraints are exceeded, the timing segment times are reallocated using scaling to maintain the total interval unchanged. The algorithm searches the timing configuration database for matching standard settings. The database is indexed by resolution and refresh rate and contains verified parameter combinations. The matching algorithm finds the closest configuration based on the pixel clock frequency and target frame rate, extracts the timing allocation ratio, and calculates the parameters. The frame rate control parameters, including the pixel clock division factor, horizontal timing parameters, vertical timing parameters, and synchronization polarity settings, are directly used to configure the display controller registers.

[0051] In this embodiment, the vertical retrace window is predicted by detecting changes in the time interval between adjacent scan lines in the display controller to obtain a predicted vertical retrace window time. Based on the predicted vertical retrace window time, a multi-level frame buffer is atomically locked to obtain a buffer switching control signal. Based on the buffer switching control signal, the GPU rendering pipeline is analyzed for rendering completion, and a multi-level buffer synchronization strategy is reconstructed based on the rendering completion assessment results. The display screen frame rate is then adjusted based on the reconstructed synchronization strategy. By accurately predicting the vertical retrace window timing and implementing atomic buffer locking, this invention ensures precise synchronization between frame buffer switching and the display scanner position, effectively resolving the single-frame flicker problem caused by improper buffer switching timing and improving the visual continuity of professional display applications.

[0052] The above describes the method for adjusting the frame rate of a display screen according to an embodiment of the present invention. The following describes the device for adjusting the frame rate of a display screen according to an embodiment of the present invention. Figure 2 In one embodiment of the present invention, a device for adjusting the frame rate of a display screen includes: A timing prediction module 201 is configured to predict a vertical retrace window of a display controller by detecting a change in the time interval between adjacent scan lines in the display controller that outputs a signal to the display screen, thereby obtaining a predicted vertical retrace window time. a buffer locking module 202 configured to atomically lock the multi-stage frame buffers supplying data to the display screen according to the vertical retrace window prediction time, and obtain a buffer switching control signal; The rendering analysis module 203 is used to perform rendering completion analysis on the GPU rendering pipeline that renders the display screen image according to the buffer switching control signal to obtain a rendering completion evaluation result; The strategy reconstruction module 204 is configured to reconstruct the multi-level buffer synchronization strategy of the display screen according to the rendering completion evaluation result, and adjust the display screen frame rate based on the reconstructed multi-level buffer synchronization strategy.

[0053] In an embodiment of the present invention, the display screen frame rate adjustment device runs the above-mentioned display screen frame rate adjustment method. The display screen frame rate adjustment device predicts the vertical retrace window by detecting the change in the time interval between adjacent scan lines in the display controller to obtain the vertical retrace window prediction time; atomically locks the multi-level frame buffer according to the vertical retrace window prediction time to obtain a buffer switching control signal; performs rendering completion analysis on the GPU rendering pipeline according to the buffer switching control signal to obtain and reconstruct the multi-level buffer synchronization strategy based on the rendering completion evaluation result, and adjusts the display screen frame rate based on the reconstructed synchronization strategy. The present invention ensures the precise synchronization of frame buffer switching and display scanner position by accurately predicting the vertical retrace window timing and implementing atomic buffer locking, effectively solving the single-frame flickering problem caused by improper buffer switching timing and improving the visual continuity of professional display applications.

[0054] above Figure 2 The frame rate adjustment device for the display screen in the embodiment of the present invention is described in detail from the perspective of modular functional entities. The frame rate adjustment device for the display screen in the embodiment of the present invention is described in detail from the perspective of hardware processing.

[0055] Figure 3This is a schematic diagram of the structure of a display screen frame rate adjustment device provided by an embodiment of the present invention. The display screen frame rate adjustment device 300 may vary significantly depending on configuration or performance. It may include one or more central processing units (CPUs) 310 (e.g., one or more processors), memory 320, and one or more storage media 330 (e.g., one or more mass storage devices) storing application programs 333 or data 332. The memory 320 and storage medium 330 may be either transient or persistent storage. The program stored in the storage medium 330 may include one or more modules (not shown), each of which may include a series of instructions for operating on the display screen frame rate adjustment device 300. Furthermore, the processor 310 may be configured to communicate with the storage medium 330, and the display screen frame rate adjustment device 300 may execute the series of instructions stored in the storage medium 330 to implement the steps of the above-described display screen frame rate adjustment method.

[0056] The display screen frame rate adjustment device 300 may further include one or more power supplies 340, one or more wired or wireless network interfaces 350, one or more input and output interfaces 360, and / or one or more operating systems 331, such as Windows Server, Mac OS X, Unix, Linux, FreeBSD, etc. It will be understood by those skilled in the art that Figure 3 The structure of the display screen frame rate adjustment device shown does not constitute a limitation on the display screen frame rate adjustment device provided by the present invention, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0057] The present invention also provides a computer-readable storage medium, which can be a non-volatile computer-readable storage medium or a volatile computer-readable storage medium. The computer-readable storage medium stores instructions, which, when executed on a computer, cause the computer to execute the steps of the method for adjusting the frame rate of the display screen.

[0058] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0059] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0060] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that the technical solutions described in the above embodiments can still be modified, or some of the technical features thereof can be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for adjusting the frame rate of a display screen, characterized in that: The method for adjusting the frame rate of the display screen includes: By detecting the change in the time interval between adjacent scan lines in the display controller that outputs the signal to the display screen, the vertical retrace window of the display controller is predicted to obtain the predicted time of the vertical retrace window; performing atomic locking processing on a multi-level frame buffer that supplies data to a display screen according to the vertical retrace window prediction time to obtain a buffer switching control signal; Performing rendering completion analysis on the GPU rendering pipeline that renders the display screen image according to the buffer switching control signal to obtain a rendering completion evaluation result; The multi-level buffer synchronization strategy of the display screen is reconstructed according to the rendering completion evaluation result, and the frame rate of the display screen is adjusted based on the reconstructed multi-level buffer synchronization strategy.

2. The method for adjusting the frame rate of a display screen according to claim 1, wherein: The method of predicting the vertical retrace window of the display controller by detecting the change in the time interval between adjacent scan lines in the display controller that outputs a signal to the display screen to obtain the predicted time of the vertical retrace window includes: The scanning position monitoring unit continuously samples the hardware counter in the scanning generator of the display controller to obtain the real-time position data of the scanning row number and the scanning column number; Detecting and processing the change in the time interval between adjacent scanning lines according to the real-time position data to obtain current scanning speed data, and updating the scanning speed history data according to the current scanning speed data to obtain scanning speed fluctuation data; Performing preliminary prediction processing on the vertical retrace window start time using a Kalman filter algorithm based on the scanning speed fluctuation data to obtain a preliminary predicted time; The pixel data in the foreground buffer and the backstage buffer of the display controller are compared pixel by pixel, and the safety margin of the preliminary prediction time is dynamically adjusted according to the pixel difference calculation result to obtain the vertical retrace window prediction time.

3. The method for adjusting the frame rate of a display screen according to claim 2, wherein: The pixel data of the foreground buffer and the backstage buffer of the display controller are compared pixel by pixel, and the safety margin of the preliminary prediction time is dynamically adjusted according to the pixel difference calculation result to obtain the vertical retrace window prediction time, which includes: Calculating the RGB component difference of corresponding pixel positions in the foreground buffer and the backstage buffer using a Euclidean distance algorithm to obtain a pixel difference matrix; Performing statistical processing on the distribution density of the image change area according to the pixel difference matrix to obtain regional distribution density data; Classifying high-change areas and low-change areas using a regional clustering algorithm based on the regional distribution density data to obtain a picture change complexity evaluation result; Calculating a buffer switching risk coefficient according to the picture change complexity evaluation result, and determining a safety boundary adjustment parameter through a risk evaluation model according to the risk coefficient; The preliminary prediction time is corrected according to the safety margin adjustment parameter using a time window smoothing algorithm to obtain a vertical retrace window prediction time.

4. The method for adjusting the frame rate of a display screen according to claim 1, wherein: The step of performing atomic locking processing on the multi-level frame buffers supplying data to the display screen according to the vertical retrace window prediction time to obtain a buffer switching control signal comprises: Calculating a pre-lock start timing according to the vertical retrace window prediction time, and freezing the write operation permission of the multi-level frame buffer 2-3 scan lines before the vertical retrace window according to the pre-lock start timing to obtain a pre-lock state signal; Redirecting a write request from the GPU rendering pipeline through a buffer access arbiter according to the pre-lock state signal, transferring a write operation target from a foreground buffer and a backstage buffer to a standby buffer, and obtaining a write operation redirection control signal; According to the write operation redirection control signal, a foreground buffer pointer and a data source address of a display scanner are synchronously updated through an atomic operation instruction to obtain a buffer pointer switching signal; The access rights of the multi-level frame buffer are restored according to the buffer pointer switching signal, the target buffer allocation state of the rendering pipeline is updated, and a buffer switching control signal is obtained.

5. The method for adjusting the frame rate of a display screen according to claim 1, wherein: The performing rendering completion analysis on the GPU rendering pipeline for rendering the display screen image according to the buffer switching control signal to obtain a rendering completion evaluation result includes: triggering monitoring of workload status of a vertex processing unit, a pixel processing unit, and a rasterization unit in a GPU rendering pipeline according to the buffer switching control signal to obtain real-time load data of each unit; Performing statistical analysis on the instruction queue depth and cache hit rate of the GPU rendering pipeline based on the real-time load data, and quantifying the rendering progress of the current frame in combination with pipeline stage delay calculation to obtain a rendering progress percentage; According to the rendering progress percentage combined with real-time sampling data of GPU memory bandwidth occupancy and texture fill rate, a rendering performance bottleneck position is identified and processed by a weighted average algorithm to obtain a performance bottleneck analysis result; The expected completion time of the current frame is predicted based on the performance bottleneck analysis results combined with historical rendering time statistics to obtain a rendering completion evaluation result.

6. The method for adjusting the frame rate of a display screen according to claim 1, wherein: The reconstructing the multi-level buffer synchronization strategy of the display screen according to the rendering completion evaluation result, and adjusting the display screen frame rate based on the reconstructed multi-level buffer synchronization strategy includes: Calculating the matching degree between the current frame rate and the GPU rendering capability according to the rendering completion evaluation result to obtain a frame rate adjustment coefficient; Calculate the number configuration and switching timing parameters of the multi-level buffer according to the frame rate adjustment coefficient to obtain the buffer configuration parameters; Reconstructing the buffer allocation strategy through a dynamic programming algorithm according to the buffer configuration parameters and adjusting the pixel clock frequency and scan line timing parameters of the display controller according to the reconstructed multi-level buffer synchronization strategy to obtain a frame rate control parameter; The vertical synchronization signal frequency of the display screen is updated through hardware register configuration according to the frame rate control parameters, and the frame rate of the display screen is adjusted and controlled.

7. The method for adjusting the frame rate of a display screen according to claim 6, wherein: The buffer allocation strategy is reconstructed by a dynamic programming algorithm according to the buffer configuration parameters and the pixel clock frequency and scan line timing parameters of the display controller are adjusted according to the reconstructed multi-level buffer synchronization strategy to obtain the frame rate control parameters, including: Establishing a buffer state transfer matrix according to the buffer configuration parameters, and performing optimization calculation processing on the buffer switching path through a dynamic programming algorithm according to the buffer state transfer matrix to obtain an optimal buffer switching sequence; reallocating the read and write priorities and access permissions of the multi-level buffers according to the optimal buffer switching sequence to obtain a reconstructed multi-level buffer synchronization strategy; Calculating a pixel clock division coefficient of a display controller according to the reconstructed multi-level buffer synchronization strategy, and adjusting the pixel clock frequency using a clock frequency modulation algorithm according to the pixel clock division coefficient to obtain an adjusted pixel clock frequency; The horizontal synchronization interval and the vertical synchronization interval of the scan line are calculated according to the adjusted pixel clock frequency, and the scan line timing parameters are adjusted according to the horizontal synchronization interval and the vertical synchronization interval through a timing parameter optimization algorithm to obtain a frame rate control parameter.

8. A device for adjusting the frame rate of a display screen, characterized in that: The image frame rate adjustment device of the display screen includes: A timing prediction module is used to predict the vertical retrace window of the display controller by detecting the change in the time interval between adjacent scan lines in the display controller that outputs signals to the display screen, and obtain the predicted time of the vertical retrace window; a buffer locking module, configured to atomically lock the multi-stage frame buffer supplying data to the display screen according to the vertical retrace window prediction time, and obtain a buffer switching control signal; A rendering analysis module is used to perform rendering completion analysis on the GPU rendering pipeline that renders the display screen image according to the buffer switching control signal to obtain a rendering completion evaluation result; A strategy reconstruction module is used to reconstruct the multi-level buffer synchronization strategy of the display screen according to the rendering completion evaluation result, and adjust the display screen frame rate based on the reconstructed multi-level buffer synchronization strategy.

9. A device for adjusting the frame rate of a display screen, characterized in that: The display screen frame rate adjustment device includes: a memory and at least one processor, wherein the memory stores instructions; The at least one processor calls the instructions in the memory to enable the display screen frame rate adjustment device to perform the steps of the display screen frame rate adjustment method according to any one of claims 1 to 7.

10. A computer-readable storage medium having instructions stored thereon, characterized in that: When the instructions are executed by the processor, the steps of the method for adjusting the frame rate of a display screen as described in any one of claims 1 to 7 are implemented.

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