Circulating isolator structure with enhanced capacitance

Abstract

According to the capacitance-enhanced circular isolator structure provided by the invention, common-ground electric connection is realized by forming a ground metal boss structure, the distance between a grounding metal and a multi-path impedance adding structure is remarkably reduced, the ground capacitance of the multi-path impedance adding structure is remarkably improved, and meanwhile, bandwidth expansion is realized through capacitance-inductance cooperative tuning; a second-order LC matching network is adopted in three radio frequency ports, a slotting part of a matching capacitor can enable a matching inductor and the matching capacitor to share space to a certain extent, so that the size of the matching network is effectively reduced, a first-order LC matching network is adopted in an absorption port, impedance matching of the absorption port is realized under the condition that only a single resistor is added, and the impedance matching performance of the absorption port is improved. The size of the matching network can be reduced while a good absorption effect is achieved, and the size of the non-reciprocal central junction structure can be reduced; in addition, the first non-reciprocal central junction structure and the second non-reciprocal central junction structure are subjected to conjugate matching by adopting an L-C-L type matching network, so that good isolation performance is realized.

Description

Technical Field

[0001] The present invention relates to the field of microwave integrated devices, and in particular to a capacitance-enhanced ring isolator structure. Background Art

[0002] In wireless communications and radar systems, ring isolators, as core passive components, perform critical functions such as signal channel isolation, impedance matching, antenna multiplexing, and co-channel duplexing. Compared to RF switches, ring isolators utilize gyromagnetic materials to generate non-reciprocal transmission under an applied bias magnetic field, enabling unidirectional electromagnetic wave propagation along a circular path. This effectively suppresses signal crosstalk between transmit and receive channels. They achieve natural isolation without the need for dynamic control circuitry, preventing the load-pull effect on the power amplifier (PA) caused by impedance mismatch, significantly improving system stability and performance.

[0003] Currently, common ring isolators are mainly waveguide and microstrip types. Waveguide ring isolators operate based on a metal waveguide cavity and ferrite loading structure, leveraging the nonreciprocal transmission characteristics of TE-mode electromagnetic waves to achieve isolation. Their advantages lie in low insertion loss and high power capacity, but due to the physical size limitations of the waveguide structure in the millimeter-wave frequency band, they struggle to meet the miniaturization, lightweight, and planar integration requirements of modern communication equipment. Microstrip ring isolators employ a planar design, achieving nonreciprocal transmission through electromagnetic coupling between microstrip lines and a ferrite substrate. Their compact planar layout makes them easier to integrate with low-temperature co-fired ceramic modules, making them a popular choice for miniaturized transceiver components.

[0004] However, microstrip ring isolators are mostly made by co-firing ferrite and high-dielectric ceramics, which has many defects and the microstrip line precision is not high. At the same time, the vertical through-holes produced based on this process require mechanical drilling or laser ablation, which is a relatively difficult process and the rough surface of the through-holes will introduce additional losses in high-frequency signal transmission. In addition, existing silicon-based ferrite circulators usually use a planar substrate design. Due to the low dielectric constant of the silicon-based material, the size of the ring isolator is difficult to compress, which cannot meet the needs of miniaturization and integration.

[0005] Therefore, a new type of ring isolator design is urgently needed to improve line accuracy without introducing additional losses while taking into account a smaller size design to adapt to the needs of miniaturization and integration, thereby meeting the needs of communication systems and millimeter-wave radar systems for high-performance, highly integrated RF front-end modules.

[0006] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of this application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are explained in the background technology part of this application. Summary of the Invention

[0007] In view of the above shortcomings of the prior art, the object of the present invention is to provide a capacitance-enhanced ring isolator structure to solve the problems of the prior art microstrip ring isolator, such as the large number of defects, low microstrip line precision, difficulty in forming vertical through holes, and difficulty in reducing the size of the ring isolator due to the low dielectric constant of silicon-based materials.

[0008] To achieve the above object, the present invention provides a capacitance-enhanced ring isolator structure, which comprises, from bottom to top, the following:

[0009] A kovar metal layer and a first conductive layer disposed on the kovar metal layer;

[0010] a first silicon substrate, wherein a first metal layer is provided on a front surface of the first silicon substrate, a second metal layer is provided on a back surface of the first silicon substrate, the second metal layer is electrically connected to the first conductive layer, and a ground metal boss structure is formed on the back surface of the first silicon substrate, the ground metal boss including a cavity and a third metal layer provided inside the cavity;

[0011] a first through hole, wherein the first through hole is provided in the first silicon substrate on one side of the ground metal boss, and two ends of the first through hole are respectively connected to the first metal layer and the second metal layer;

[0012] a resistance layer, wherein the resistance layer is located on the front surface of the first silicon substrate and the resistance layer and the first through hole are located on the same side of the ground metal boss;

[0013] a second through hole, the second through hole being coaxially arranged with the ground metal boss and being used to accommodate a ferrite substrate, one end of the ferrite substrate being in contact with the Kovar metal layer, and the other end of the ferrite substrate being in contact with the fourth metal layer;

[0014] a second silicon substrate, wherein a fourth metal layer is provided on the back surface of the second silicon substrate, the fourth metal layer and the second metal layer are bonded to each other, and a first circulator and a second circulator are formed in cascade on the back surface of the second silicon substrate;

[0015] A permanent magnet is provided on the front surface of the second silicon substrate, and an insulating spacer is provided between the permanent magnet and the second silicon substrate.

[0016] Optionally, the ground metal boss includes a first ground metal boss and a second ground metal boss, the first ground metal boss is located below the first circulator and is coaxially arranged with the first circulator, and the second ground metal boss is located below the second circulator and is coaxially arranged with the second circulator.

[0017] Optionally, the first metal boss and the second metal boss each include a central ring and lugs distributed circumferentially along the central ring.

[0018] Optionally, the first circulator includes a first non-reciprocal center junction structure, the second circulator includes a second non-reciprocal center junction structure, and the first non-reciprocal center junction structure and the second non-reciprocal center junction are connected via a fifth matching network.

[0019] Optionally, the first non-reciprocal central junction structure includes a first multi-channel impedance structure, a first RF port, a first matching network matched with the first RF port, and a second RF port and a second matching network matched with the second RF port, and the first RF port and the second RF port are symmetrically distributed about the first multi-channel impedance structure.

[0020] Optionally, the second non-reciprocal central junction structure includes a second multi-channel impedance structure, a third RF port, a third matching network matched with the third RF port, and an absorption port of an integrated resistor, and an electrical connection is formed between the absorption port of the integrated resistor and the resistance layer.

[0021] Optionally, the first matching network includes a first-stage matching inductor, a second-stage matching inductor, a first-stage matching capacitor and a second-stage matching capacitor. The first matching network, the second matching network and the third matching network have the same structure and the first matching network and the second matching network are symmetrically distributed about the first multi-path impedance structure.

[0022] Optionally, the first multi-channel resistant structure and the second multi-channel resistant structure both include a central disk and a first microstrip line group, a first microstrip line group and a third microstrip line group connected to the central disk, wherein the central disk is located directly above the central circular ring, and the first microstrip line group, the second microstrip line group and the third microstrip line group are located directly above the ear piece and are evenly distributed along the circumference.

[0023] Optionally, the first microstrip line group, the second microstrip line group and the third microstrip line group each include 3 to 5 microstrip lines, and the microstrip lines are distributed in parallel; and the first microstrip line group, the second microstrip line group and the third microstrip line group include the same number of microstrip lines.

[0024] Optionally, a diameter of the first through hole ranges from 20 to 60 μm, and a connection metal is formed in the first through hole.

[0025] As described above, the present invention provides a capacitance-enhanced ring isolator structure, which has the following beneficial effects:

[0026] The present invention forms a ground metal boss structure and a third metal layer electrically connected to the first metal layer in the first silicon substrate, thereby reducing the spacing between the first multi-path impedance structure and the second multi-path impedance structure, significantly improving the capacitance of the multi-path impedance structure to ground, thereby greatly reducing the size of the non-reciprocal center junction structure, and at the same time achieving bandwidth expansion through capacitor-inductor cooperative tuning; the first matching network to the third matching network adopts a second-order LC matching network, and the matching capacitor slot portion allows the matching inductor and the matching capacitor to share space to a certain extent, effectively reducing the size of the first matching network to the third matching network, and the absorption port adopts a first-order LC matching network. The matching network is combined with the tuning of the resistor parasitic parameters to achieve impedance matching of the absorption port under the condition of adding only a single resistor, which can achieve good absorption effect while reducing the size of the matching circuit; in addition, the first non-reciprocal center junction structure and the second non-reciprocal center junction structure adopt an LCL-type matching network for conjugate matching, thereby achieving good isolation performance. Compared with the traditional multi-channel impedance structure, the structure of the present invention can achieve a significant reduction in size, while reducing the requirements for the surface roughness of the ferrite substrate, which helps to improve the product assembly yield and improve product consistency. It has good application prospects in satellite communications, radar, electronic countermeasures and other fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic cross-sectional structure diagram of a capacitance-enhanced ring isolator structure according to an embodiment of the present invention.

[0028] Figure 2 Shown is a schematic top view of the first circulator and the second circulator in an embodiment of the present invention.

[0029] Figure 3 Shown is a schematic top view of the structure of a metal boss according to an embodiment of the present invention.

[0030] Figures 4 to 6 Shown is an S-parameter simulation data diagram of a capacitance-enhanced ring isolator structure according to an embodiment of the present invention.

[0031] Component number description

[0032] 10. Kovar metal layer; 11. First conductive layer; 12. First silicon substrate; 13. Second metal layer; 14. First metal layer; 15. Ground metal boss; 151. Cavity; 152. Third metal layer; 153. First ground metal boss; 1531. Ear piece; 1532. Center ring; 154. Second ground metal boss; 16. First through hole; 17. Resistor layer; 18. Fourth metal layer; 19. Second silicon substrate; 201. Second through hole; 20. Ferrite substrate; 21. Insulation pad 22. Permanent magnet; 23. First circulator; 230. Second-stage matching capacitor; 231. First microstrip line group; 232. Second microstrip line group; 233. Third microstrip line group; 234. Center disk; 235. Second RF port; 236. First RF port; 237. First-stage matching inductor; 238. First-stage matching capacitor; 239. Second-stage matching inductor; 24. Second circulator; 241. Third RF port; 242. Absorption port; 243. Fourth matching network. DETAILED DESCRIPTION

[0033] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] For example, when describing the embodiments of the present invention, schematic diagrams illustrating device structures may be partially enlarged for ease of explanation. These schematic diagrams are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0035] For convenience of description, spatially relative terms such as "under," "below," "below," "below," "above," and "upper" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0036] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0037] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0038] like Figure 1 As shown, the present invention provides a capacitance-enhanced ring isolator structure, which includes, from bottom to top:

[0039] A kovar metal layer 10 and a first conductive layer 11 disposed on the kovar metal layer 10;

[0040] A first silicon substrate 12, wherein a first metal layer 14 is provided on the front surface of the first silicon substrate 12, and a second metal layer 13 is provided on the back surface of the first silicon substrate 12, wherein the second metal layer 13 is electrically connected to the first conductive layer 11, and a ground metal boss 15 structure is formed on the back surface of the first silicon substrate 12, wherein the ground metal boss 15 includes a cavity 151 and a third metal layer 152 disposed inside the cavity 151;

[0041] a first through hole 16 , wherein the first through hole 16 is provided in the first silicon substrate 12 on one side of the ground metal boss 15 , and two ends of the first through hole 16 are respectively connected to the first metal layer 14 and the second metal layer 13 ;

[0042] a resistance layer 17 , the resistance layer 17 being located on the front surface of the first silicon substrate 12 and the resistance layer 17 and the first through hole 16 being located on the same side of the ground metal boss 15 ;

[0043] a second through hole 201, the second through hole 201 being coaxially arranged with the ground metal boss 15 and being used to accommodate a ferrite substrate 20, one end of the ferrite substrate 20 being in contact with the Kovar metal layer 10, and the other end of the ferrite substrate 20 being in contact with the fourth metal layer 18;

[0044] A second silicon substrate 19, a fourth metal layer 18 is provided on the back side of the second silicon substrate 19, the fourth metal layer 18 and the second metal layer 13 are bonded to each other, and a first circulator 23 and a second circulator 24 are formed in cascade on the back side of the second silicon substrate 19;

[0045] A permanent magnet 22 is provided on the front surface of the second silicon substrate 19 , and an insulating spacer 21 is provided between the permanent magnet 22 and the second silicon substrate 19 .

[0046] In one embodiment, Figure 1As shown, the material forming the Kovar metal layer 10 is an Fe-Ni-Co alloy, which is generally composed of Fe (54% wet), Ni (29% wet), Co (17% wet), and trace amounts of other components such as Si and Mn. The thickness of the Kovar metal layer 10 is 50 to 300 μm, for example, it can be 50 μm, 150 μm, 250 μm or 300 μm. The specific thickness of the Kovar metal layer 10 can be set according to the size of the ring isolator structure required in practice, and is not limited here.

[0047] In one embodiment, Figure 1 As shown, a first conductive layer 11 is formed above the Kovar metal layer 10. The materials forming the first conductive layer 11 include but are not limited to metal solder and conductive glue. The first conductive layer 11 and the Kovar metal layer 10 have good electrical and thermal conductivity and a low thermal expansion coefficient. The thickness of the first conductive layer 11 is 10 to 50 μm, for example, it can be 10 μm, 30 μm or 50 μm, which is not limited here.

[0048] In some embodiments, as Figure 1 As shown, the front and back sides of the first silicon substrate 12 are respectively provided with a first metal layer 14 and a second metal layer 13. The material forming the first silicon substrate 12 is high-resistance silicon. The materials of the first metal layer 14 and the second metal layer 13 include, but are not limited to, gold, copper, or tungsten. The second metal layer 13 and the first conductive layer 11 can be welded together by gold-tin sintering to form an electrical connection. The thickness of the first silicon substrate 12 is 80 to 400 μm, for example, 80 μm, 250 μm, or 400 μm, the thickness of the first metal layer 14 is 2 to 20 μm, and the thickness of the second metal layer 13 is 2 to 20 μm, for example, 2 μm, 10 μm, or 20 μm, without limitation here. The second metal layer 13 and the first silicon substrate 12 are etched from the back side of the first silicon substrate 12 to form a cavity 151, and the cavity 151 is used to fill the gyromagnetic sheet (i.e., the ferrite substrate 20). A third metal layer 152 is also formed on the inner side of the cavity 151. The material forming the third metal layer 152 includes but is not limited to gold, copper or tungsten, and the third metal layer 152 and the second metal layer 13 are welded together by gold-tin sintering to form an electrical connection, wherein the cavity 151 and the third metal layer 152 inside it constitute a ground metal boss 15 structure, and since the third metal layer 152, the second metal layer 13 and the first conductive layer 11 are electrically connected to the common ground, the distance between the grounding metal and the multi-path impedance structure is significantly reduced, thereby significantly improving the capacitance of the multi-path impedance structure to ground.

[0049] In some embodiments, as Figure 1As shown, a first through hole 16 is formed in the first silicon substrate 12. The first through hole 16 is located on one side of the ground metal boss 15 structure, for example, on the left or right side of the ground metal boss 15 structure. This is not limited here, but it should be noted that the position of the first through hole 16 should be on the same side as the position of the resistor layer 17. The diameter of the first through hole 16 ranges from 20 to 60 μm. Since the two ends of the first through hole 16 are respectively connected to the first metal layer 14 and the second metal layer 13, a connecting metal layer is also formed in the first through hole 16. The material forming the connecting metal layer includes but is not limited to copper, gold, or other metals. In addition, a resistor layer 17 is also formed on the front surface of the first silicon substrate 12. The material forming the resistor layer 17 includes but is not limited to TaN, NiCr, and TiW. The thickness of the resistor layer 17 is 15 to 50 nm. The two ends of the resistor layer 17 are respectively connected to the circuit structures of the first circulator 23 and the second circulator 24 formed in the first metal layer 14.

[0050] like Figure 1 As shown, a photolithography process is performed on the front surface of the first silicon substrate 12 to form a second through hole 201, wherein the second through hole 201 is coaxially arranged with the ground metal boss 15 structure and the second through hole 201 is connected to the cavity 151 of the ground metal boss 15, for accommodating the ferrite substrate 20, and one end of the ferrite substrate 20 is arranged in contact with the kovar metal layer 10.

[0051] In some embodiments, as Figure 1 As shown, a second silicon substrate 19 and a fourth metal layer 18 provided on the back side of the second silicon substrate 19 are provided at the other end of the ferrite substrate 20. The fourth metal layer 18 is bonded to the second metal layer 13 and is also connected to the other end of the ferrite substrate 20. Optionally, the material forming the second silicon substrate 19 is high-resistance silicon, and the material forming the fourth metal layer 18 includes but is not limited to gold, copper, or tungsten. The thickness of the second silicon substrate 19 is 80 to 400 μm, for example, 80 μm, 250 μm, or 400 μm, and the thickness of the fourth metal layer 18 is 2 to 20 μm, for example, 2 μm, 10 μm, or 20 μm, which are not limited here.

[0052] In one embodiment, a cascaded first circulator 23 and a second circulator 24 are also formed in the fourth metal layer 18 and the third metal layer 152, and the first circulator 23 includes a first non-reciprocal center junction structure, and the second circulator 24 includes a second non-reciprocal center junction structure, and the first non-reciprocal center junction structure and the second non-reciprocal center junction are connected through a fifth matching network.

[0053] As an example, the first metal boss 153 and the second metal boss 154 each include a central ring 1532 and lugs 1531 distributed circumferentially along the central ring 1532 .

[0054] Specifically, such as Figure 2 and Figure 3 As shown, the ground metal boss 15 includes a first ground metal boss 153 and a second ground metal boss 154, wherein the first ground metal boss 153 is located below the first circulator 23 and is coaxially arranged with the first circulator 23, and the second ground metal boss 154 is located below the second circulator 24 and is coaxially arranged with the second circulator 24, and the first ground metal boss 153 and the second ground metal boss 154 both include a central ring 1532 and ears 1531 distributed circumferentially along the central ring 1532, wherein a microstrip line group is formed on the ear 1531, and a cascaded first circulator 23 and second circulator 24 are formed on the central ring 1532.

[0055] Specifically, the fifth matching network includes an LCL matching network, which can achieve conjugate matching between the first circulator 23 and the second circulator 24 , thereby achieving good signal isolation performance.

[0056] In one embodiment, the first non-reciprocal central junction structure includes a first multi-channel impedance structure, a first RF port 236, a first matching network matched with the first RF port 236, a second RF port 235, and a second matching network matched with the second RF port 235, and the first RF port 236 and the second RF port 235 are symmetrically distributed with respect to the first multi-channel impedance structure. Specifically, Figure 2 As shown, the first matching network includes a second-order LC matching network formed by a first-stage matching inductor 237, a second-stage matching inductor 239, a first-stage matching capacitor 238, and a second-stage matching capacitor 230, and the first-stage matching inductor 237, the second-stage matching inductor 239, the first-stage matching capacitor 238, and the second-stage matching capacitor 230 are interconnected. The first-stage matching inductor 237 and the second-stage matching inductor 239 are implemented by a fine microstrip structure, and the first-stage matching capacitor 238 and the second-stage matching capacitor 230 are implemented by a slotted fan-shaped microstrip structure. The slotted portions of the first-stage matching capacitor 238 and the second-stage matching capacitor 230 allow the first-stage matching inductor 237 and the second-stage matching inductor 239 to share space with the first-stage matching capacitor 238 and the second-stage matching capacitor 230 to a certain extent, thereby effectively reducing the size of the first matching network. In addition, the ground metal boss 15 structure also increases the ground capacitance of the slotted fan-shaped microstrip structure, further reducing the size of the first-stage matching capacitor 238 and the second-stage matching capacitor 230. Figure 2As shown, the structural composition of the second matching network is the same as that of the first matching network, and the first matching network and the second matching network are symmetrically distributed about the first multi-path impedance structure. Based on the same principle, the size of the second matching network can also be effectively reduced.

[0057] In one embodiment, the first multi-channel impedance structure includes a central disk 234 and a first microstrip line group 231, a first microstrip line group 231 and a third microstrip line group 233 connected to the central disk 234. Specifically, Figure 2 and Figure 3 As shown, the central disk 234 is located directly above the central ring 1532, and the first microstrip line group 231, the second microstrip line group 232, and the third microstrip line group 233 are located directly above the ear piece 1531 and are evenly distributed along the circumference. That is, the first microstrip line group 231, the second microstrip line group 232, and the third microstrip line group 233 are distributed at an angle of 120°, and the first microstrip line group 231, the second microstrip line group 232, and the third microstrip line group 233 each include 3 to 5 microstrip lines, and the number of microstrip lines included in the first microstrip line group 231, the second microstrip line group 232, and the third microstrip line group 233 is the same. Preferably, in this embodiment, the first microstrip line group 231, the second microstrip line group 232, and the third microstrip line group 233 each include 3 microstrip lines, and the 3 microstrip lines are distributed parallel to each other.

[0058] In one embodiment, the second non-reciprocal central junction structure includes a second multi-channel impedance structure, a third RF port 241, a third matching network matched with the third RF port 241, an absorbing port 242 of an integrated resistor, and a fourth matching network 243 matched with the absorbing port 242 of the integrated resistor, wherein the fourth matching network 243 is electrically connected to the resistor layer 17. Specifically, as Figure 2As shown, the structure of the third matching network is the same as that of the first matching network, both including a second-order LC matching network formed by a first-stage matching inductor 237, a second-stage matching inductor 239, a first-stage matching capacitor 238, and a second-stage matching capacitor 230, wherein the first-stage matching inductor 237, the second-stage matching inductor 239, the first-stage matching capacitor 238, and the second-stage matching capacitor 230 are interconnected, wherein the first-stage matching inductor 237 and the second-stage matching inductor 239 are implemented by a fine microstrip structure, and the first-stage matching capacitor 238 and the second-stage matching capacitor 230 are implemented by a slotted fan-shaped microstrip structure. The slotted portions of the first-stage matching capacitor 238 and the second-stage matching capacitor 230 allow the first-stage matching inductor 237 and the second-stage matching inductor 239 to share space with the first-stage matching capacitor 238 and the second-stage matching capacitor 230 to a certain extent, thereby effectively reducing the size of the third matching network.

[0059] like Figure 2 As shown, a fourth matching network 243 matching the absorption port 242 of the integrated resistor is provided at the absorption port 242 of the integrated resistor. The fourth matching network 243 uses a first-order LC matching network to adjust the impedance to a specific point, and then uses the parasitic parameters of the resistor layer 17 itself to achieve matching, thereby achieving good absorption of the isolated signal while reducing the size of the fourth matching network 243.

[0060] In one embodiment, a permanent magnet 22 is disposed on the front surface of the second silicon substrate 19, with an insulating spacer 21 disposed between the permanent magnet 22 and the second silicon substrate 19. The permanent magnet 22, the insulating spacer 21, and the ferrite substrate 20 are vertically coaxially arranged. The insulating spacer 21 has a thickness of 50 to 400 μm. The permanent magnet 22 is made of samarium cobalt and has a thickness of 400 to 3000 μm. The permanent magnet 22 provides a constant bias magnetic field, thereby achieving a signal loop effect, ultimately enabling low-loss signal transmission.

[0061] like Figures 4 to 6 As shown, it shows the S parameter simulation results obtained after the three-dimensional electromagnetic simulation of the capacitance enhanced ring isolator structure of the present invention, Figure 4 It can be seen that within the 8.8-10.5 GHz frequency band, the insertion loss is less than 0.7 dB, the isolation is better than 30 dB, and the return loss is better than 20 dB.

[0062] In summary, the present invention realizes common ground electrical connection by forming a ground metal boss structure and a third metal layer electrically connected to the first metal layer in the first silicon substrate, significantly reduces the distance between the ground metal and the multi-path impedance structure, significantly improves the capacitance of the multi-path impedance structure to ground, and at the same time realizes bandwidth expansion through capacitor-inductor cooperative tuning; the first matching network to the third matching network adopts a second-order LC matching network, wherein the first-stage matching inductor and the second-stage matching inductor are realized by a fine microstrip structure, and the first-stage matching capacitor and the second-stage matching capacitor are realized by a slotted fan-shaped microstrip structure, and the slotted parts of the first-stage matching capacitor and the second-stage matching capacitor can make the first-stage matching inductor and the second-stage matching inductor share a certain degree of space with the first-stage matching capacitor and the second-stage matching capacitor, thereby effectively reducing the size of the first matching network. In addition The ground metal boss structure also increases the ground capacitance of the slotted fan-shaped microstrip structure, effectively reducing the size of the first matching network to the third matching network, and the absorption port adopts a first-order LC matching network combined with resistor parasitic parameter tuning to achieve impedance matching of the absorption port under the condition of only adding a single resistor, while achieving good absorption effect. At the same time, it can also reduce the size of the matching network, thereby helping to reduce the size of the non-reciprocal center junction structure; in addition, the first non-reciprocal center junction structure and the second non-reciprocal center junction structure adopt an LCL-type matching network for conjugate matching, thereby achieving good isolation performance, and the structure of the present invention can reduce the requirements for the surface roughness of the ferrite substrate compared to the traditional multi-channel impedance structure, which helps to improve the product assembly yield and improve product consistency. It has good application prospects in satellite communications, radar, electronic countermeasures and other fields.

[0063] Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0064] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A capacitance-enhanced ring isolator structure, characterized in that: The ring isolator structure includes, from bottom to top: A kovar metal layer and a first conductive layer disposed on the kovar metal layer; a first silicon substrate, wherein a first metal layer is provided on a front surface of the first silicon substrate, a second metal layer is provided on a back surface of the first silicon substrate, the second metal layer is electrically connected to the first conductive layer, and a ground metal boss structure is formed on the back surface of the first silicon substrate, the ground metal boss including a cavity and a third metal layer provided inside the cavity; a first through hole, wherein the first through hole is provided in the first silicon substrate on one side of the ground metal boss, and two ends of the first through hole are respectively connected to the first metal layer and the second metal layer; a resistance layer, wherein the resistance layer is located on the front surface of the first silicon substrate and the resistance layer and the first through hole are located on the same side of the ground metal boss; a second through hole, the second through hole being coaxially arranged with the ground metal boss and being used to accommodate a ferrite substrate, one end of the ferrite substrate being in contact with the Kovar metal layer, and the other end of the ferrite substrate being in contact with the fourth metal layer; a second silicon substrate, wherein a fourth metal layer is provided on the back surface of the second silicon substrate, the fourth metal layer and the second metal layer are bonded to each other, and a first circulator and a second circulator are formed in cascade on the back surface of the second silicon substrate; A permanent magnet is provided on the front surface of the second silicon substrate, and an insulating spacer is provided between the permanent magnet and the second silicon substrate.

2. The capacitance-enhanced ring isolator structure according to claim 1, characterized in that: The ground metal boss includes a first ground metal boss and a second ground metal boss. The first ground metal boss is located below the first circulator and is coaxially arranged with the first circulator. The second ground metal boss is located below the second circulator and is coaxially arranged with the second circulator.

3. The capacitance-enhanced ring isolator structure according to claim 2, characterized in that: The first metal boss and the second metal boss each include a central ring and lugs distributed circumferentially along the central ring.

4. The capacitance-enhanced ring isolator structure according to claim 3, characterized in that: The first circulator includes a first non-reciprocal center junction structure, the second circulator includes a second non-reciprocal center junction structure, and the first non-reciprocal center junction structure and the second non-reciprocal center junction are connected via a fifth matching network.

5. The capacitance-enhanced ring isolator structure according to claim 4, characterized in that: The first non-reciprocal central junction structure includes a first multi-channel impedance structure, a first RF port, a first matching network matched with the first RF port, and a second RF port, and a second matching network matched with the second RF port, and the first RF port and the second RF port are symmetrically distributed about the first multi-channel impedance structure.

6. The capacitance-enhanced ring isolator structure according to claim 5, characterized in that: The second non-reciprocal central junction structure includes a second multi-channel impedance structure, a third RF port, a third matching network matched with the third RF port, and an absorption port of an integrated resistor, and an electrical connection is formed between the absorption port of the integrated resistor and the resistance layer.

7. The capacitance-enhanced ring isolator structure according to claim 6, characterized in that: The first matching network includes a first-stage matching inductor, a second-stage matching inductor, a first-stage matching capacitor, and a second-stage matching capacitor. The first matching network, the second matching network, and the third matching network have the same structure, and the first matching network and the second matching network are symmetrically distributed about the first multi-path impedance structure.

8. The capacitance-enhanced ring isolator structure according to claim 7, characterized in that: The first multi-channel resistant structure and the second multi-channel resistant structure both include a central disk and a first microstrip line group, a first microstrip line group and a third microstrip line group connected to the central disk, wherein the central disk is located directly above the central circular ring, and the first microstrip line group, the second microstrip line group and the third microstrip line group are located directly above the ear piece and are evenly distributed along the circumference.

9. The capacitance-enhanced ring isolator structure according to claim 8, characterized in that: The first microstrip line group, the second microstrip line group and the third microstrip line group each include 3 to 5 microstrip lines, which are distributed in parallel; and the first microstrip line group, the second microstrip line group and the third microstrip line group include the same number of microstrip lines.

10. The capacitance-enhanced ring isolator structure according to claim 1, wherein: The diameter of the first through hole is in the range of 20 to 60 μm, and a connection metal is formed in the first through hole.

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