Silicon carbide power device, preparation method thereof and chip

Abstract

The invention belongs to the technical field of power devices, and provides a silicon carbide power device, a preparation method thereof and a chip, a plurality of P-type floating islands are arranged between an N-type drift region and a top epitaxial region, so that the clamping effect on saturation current can be increased, the short-circuit characteristic is strengthened, and the performance of the device is improved. Meanwhile, the self-depletion effect of the P-type floating island is beneficial to reducing capacitance between the first electrode layer and the grid electrode in the device, the switching characteristic of the device is improved, and the trade-off relationship between breakdown voltage and on-resistance can be effectively balanced under the condition of a relatively shallow P-type well region and a relatively deep doped current expansion region, so that the performance of the device is improved. On-resistance of the device is optimized on the premise that breakdown voltage is not affected, and the requirement of high-power application for device performance is met.

Description

Technical Field

[0001] The present application belongs to the technical field of power devices, and in particular relates to a silicon carbide power device, a preparation method thereof, and a chip. Background Art

[0002] Silicon carbide (SiC), a third-generation semiconductor material, offers advantages such as a wide bandgap, high critical breakdown electric field, and high saturation drift velocity, making SiC power devices uniquely suited for high-voltage, high-power, and high-frequency applications. However, existing SiC planar MOS device structures still face room for improvement in the trade-off between on-resistance and breakdown voltage. To increase device integration density and performance, researchers have proposed various improvements, such as employing buried gate structures and optimizing channel distribution.

[0003] However, existing SiC MOS devices still face challenges in short-circuit performance and reliability. In particular, under high current conditions, the devices are prone to thermal failure, impacting their long-term stability. Furthermore, conventional SiC MOS device structures struggle to achieve both low on-resistance (Ron) and high breakdown voltage (BV), limiting their adoption in high-power applications. Therefore, developing a novel SiC planar MOS structure that optimizes on-resistance and improves short-circuit withstand capability without compromising the device's withstand voltage performance is crucial. Summary of the Invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide a silicon carbide power device and a preparation method and chip thereof, which can optimize the on-resistance and improve the short-circuit tolerance without affecting the voltage resistance performance of the device.

[0005] According to a first aspect of an embodiment of the present application, a silicon carbide power device is provided, comprising: a silicon carbide substrate, a first electrode layer, an N-type drift region, a P-type floating island, a top epitaxial region, a current extension region, an N-type heavily doped region, a P-type well region, a P-type heavily doped region, a gate dielectric layer, a gate layer, and a second electrode layer; The first electrode layer is located on the back side of the silicon carbide substrate, the N-type drift region is located on the front side of the silicon carbide substrate, and a plurality of P-type floating islands are provided between the N-type drift region and the top epitaxial region; The current extension region, the P-type well region, and the P-type heavily doped region are located on the top epitaxial region, and the P-type heavily doped region and the P-type well region are provided on both sides of the current extension region, the P-type well region is located between the P-type heavily doped region and the current extension region, the depth of the current extension region is greater than the depth of the P-type well region, the doping concentration of the P-type well region is less than the doping concentration of the P-type heavily doped region, and the doping concentration of the current extension region is greater than the doping concentration of the top epitaxial region; The N-type heavily doped region is formed on the horizontal portion of the P-type well region, the gate dielectric layer is located on the N-type heavily doped region, the P-type well region, and the current extension region, and the gate dielectric layer wraps the gate layer, and the second electrode layer covers the gate dielectric layer and contacts the N-type heavily doped region and the P-type heavily doped region.

[0006] In some embodiments, the gate dielectric layer includes multiple gate layers, the multiple gate layers are isolated by the gate dielectric layer, and at least two gate layers are arranged opposite to the vertical portions of the P-type well region on both sides of the current extension region.

[0007] In some embodiments, a P-type shallowly doped region is provided between the current extension region and the gate dielectric layer. The P-type shallowly doped region contacts the gate dielectric layer and is located in a groove of the current extension region.

[0008] In some embodiments, the current extension region is a concave structure, and a portion of the protruding structure of the gate dielectric layer is filled in the groove of the current extension region.

[0009] In some embodiments, the top epitaxial region is a concave structure, and the top epitaxial region and the N-type drift region have different doping concentrations.

[0010] In some embodiments, the width of the P-type floating island is equal to or greater than the width of the current extension region; at least one of the P-type floating islands is arranged opposite to the current extension region, and at least two of the P-type floating islands are arranged opposite to the P-type heavily doped regions on both sides of the current extension region.

[0011] In some embodiments, the silicon carbide substrate is P-type doped, and an N-type buffer layer is further provided between the silicon carbide substrate and the N-type drift region.

[0012] A second aspect of the present application further provides a method for preparing a silicon carbide power device, the method comprising: forming an N-type drift region on a silicon carbide substrate, and performing P-type ion implantation on a plurality of regions on the N-type drift region to form a plurality of P-type floating islands; Performing secondary epitaxy to form a top epitaxial region, and etching the top epitaxial region so that the top epitaxial region has a concave structure; A current extension region, an N-type heavily doped region, a P-type well region, and a P-type heavily doped region are formed using a self-aligned process; wherein the current extension region, the P-type well region, and the P-type heavily doped region are located on the top epitaxial region, and the P-type heavily doped region and the P-type well region are provided on both sides of the current extension region, and the P-type well region is located between the P-type heavily doped region and the current extension region; forming a gate dielectric layer on the N-type heavily doped region, the P-type well region, and the current extension region, and forming a gate layer by a polysilicon deposition process so that the gate dielectric layer wraps the gate layer; A first electrode layer is formed on the back side of the silicon carbide substrate, and a second electrode layer is formed on the gate dielectric layer, the N-type heavily doped region, and the P-type heavily doped region.

[0013] In some embodiments, forming an N-type drift region on a silicon carbide substrate includes: An N-type buffer layer is formed on a silicon carbide substrate, and an N-type drift region is formed on the N-type buffer layer.

[0014] A third aspect of an embodiment of the present application further provides a chip, which includes a silicon carbide power device as described in any one of the above items.

[0015] The beneficial effects of the embodiments of the present application are as follows: by arranging multiple P-type floating islands between the N-type drift region and the top epitaxial region, the clamping effect on the saturation current can be increased, and the short-circuit characteristics can be enhanced. At the same time, the self-depletion effect of the P-type floating island is beneficial to reducing the capacitance between the first electrode layer and the gate in the device, thereby improving the switching characteristics of the device. Moreover, in the case of a shallower P-type well region and a deeper doped current extension region, the trade-off relationship between the breakdown voltage and the on-resistance can be effectively balanced, so that the device optimizes the on-resistance without affecting the breakdown voltage, thereby meeting the device performance requirements of high-power applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic structural diagram of a silicon carbide power device provided in an embodiment of the present application; Figure 2 This is a schematic structural diagram of a silicon carbide power device provided in an embodiment of the present application; Figure 3 This is a schematic structural diagram of a silicon carbide power device provided in an embodiment of the present application; Figure 4 This is a schematic structural diagram of a silicon carbide power device provided in an embodiment of the present application; Figure 5 This is a schematic structural diagram of a silicon carbide power device provided in an embodiment of the present application; Figure 6 This is a schematic structural diagram of a silicon carbide power device provided in an embodiment of the present application; Figure 7 This is a schematic structural diagram of a silicon carbide power device provided in an embodiment of the present application; Figure 8 This is a flow chart of a method for preparing a silicon carbide power device provided in an embodiment of the present application; Figure 9This is a structural schematic diagram of some steps in a method for preparing a silicon carbide power device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0018] Existing SiC MOS devices still face challenges in short-circuit performance and reliability. In particular, under high current conditions, the devices are prone to thermal failure, impacting their long-term stability. Furthermore, conventional SiC MOS device structures struggle to achieve both low on-resistance (Ron) and high breakdown voltage (BV), limiting their adoption in high-power applications. Therefore, developing a novel SiC planar MOS structure that optimizes on-resistance and improves short-circuit withstand capability without compromising the device's withstand voltage performance is crucial.

[0019] In order to solve the above technical problems, the present invention provides a silicon carbide power device. Figure 1 As shown, the silicon carbide power device in this embodiment includes: a silicon carbide substrate 110, a first electrode layer 510, an N-type drift region 120, a P-type floating island 210, a top epitaxial region 130, a current extension region 310, an N-type heavily doped region 340, a P-type well region 320, a P-type heavily doped region 330, a gate dielectric layer 410, a gate layer 420 and a second electrode layer 520.

[0020] The first electrode layer 510 is located on the back side of the silicon carbide substrate 110, the N-type drift region 120 is located on the front side of the silicon carbide substrate 110, and a plurality of P-type floating islands 210 are provided between the N-type drift region 120 and the top epitaxial region 130; the current extension region 310, the P-type well region 320 and the P-type heavily doped region 330 are located on the top epitaxial region 130, and the P-type heavily doped region 330 and the P-type well region 320 are provided on both sides of the current extension region 310, the P-type well region 320 is located between the P-type heavily doped region 330 and the current extension region 310, and the current extension region 310 is provided with a plurality of P-type floating islands 210; the current extension region 310, the P-type well region 320 and the P-type heavily doped region 330 are provided on both sides of the current extension region 310, and the P-type well region 320 is located between the P-type heavily doped region 330 and the current extension region 310. The depth of the current extension region 310 is greater than the depth of the P-type well region 320. The P-type well region 320 is an L-shaped structure, and the vertical part of the P-type well region 320 is in contact with the current extension region 310; the N-type heavily doped region 340 is formed on the horizontal part of the P-type well region 320, and the gate dielectric layer 410 is located on the N-type heavily doped region, the P-type well region 320, and the current extension region 310, and the gate dielectric layer 410 wraps the gate layer 420, and the second electrode layer 520 covers the gate dielectric layer 410 and is in contact with the N-type heavily doped region 340 and the P-type heavily doped region 330.

[0021] In this embodiment, the P-type well region 320 is shallowly doped, while the current extension region 310 is N-type doped and deeply doped. The doping concentration of the P-type well region 320 is lower than that of the heavily doped P-type region 330, while the doping concentration of the current extension region 310 is higher than that of the top epitaxial region 130. The provision of multiple P-type floating islands 210 between the N-type drift region 120 and the top epitaxial region 130 enhances the clamping effect on the saturation current and strengthens the short-circuit characteristics. Simultaneously, the self-depletion effect of the P-type floating islands 210 helps reduce the capacitance between the first electrode layer 510 (drain) and the gate within the device, thereby improving the switching characteristics of the device. Furthermore, the depth of the current extension region 310 exceeds that of the P-type well region 320. This effectively balances the trade-off between breakdown voltage and on-resistance in the case of a shallow P-type well region 320 and a heavily doped current extension region 310, optimizing the on-resistance without compromising breakdown voltage, thus meeting the performance requirements of high-power applications. The structural design in this embodiment not only reduces the device area by 8-10% while maintaining the same on-resistance specification, thereby reducing chip costs, but also improves the device's withstand voltage, conduction, and short-circuit performance through an optimized design, significantly enhancing the overall performance of the SiC planar MOS device.

[0022] In some embodiments, the depth of the P-type well region 320 is less than the depth of the current extension region 310, the upper surface of the P-type well region 320 is flush with the upper surface of the current extension region 310, the thickness of the current extension region 310 is at least five-sixths of the thickness of the P-type well region 320, and the thickness of the P-type well region 320 is 0.6-0.7um.

[0023] In some embodiments, the P-type well region 320 is an L-shaped structure, the gate layer 420 is a U-shaped structure, the vertical portion of the P-type well region 320 contacting the first side of the current expansion region 310 is opposite to the first end of the gate layer 420, the vertical portion of the P-type well region 320 contacting the second side of the current expansion region 310 is opposite to the second end of the gate layer 420, and the width of the vertical portion of the P-type well region 320 is smaller than the width of the two ends of the gate layer 420.

[0024] In some embodiments, multiple P-type floating islands 210 between the N-type drift region 120 and the top epitaxial region 130 are arranged in an array in a cross section. The P-type floating islands 210 are located at the junction of the N-type drift region 120 and the top epitaxial region 130. The N-type drift region 120 has multiple grooves at the junction for setting the P-type floating islands 210. In addition, a portion of the P-type floating islands 210 are arranged opposite to the P-type heavily doped region 330, another portion of the P-type floating islands 210 are arranged opposite to the P-type well region 320, and another portion of the P-type floating islands 210 are arranged opposite to the current extension region 310. In this way, the clamping effect on the saturation current can be increased, and the short-circuit characteristics can be enhanced. At the same time, the self-depletion effect of the P-type floating islands 210 is beneficial to reducing the capacitance between the first electrode layer 510 (drain) and the gate in the device, thereby improving the switching characteristics of the device.

[0025] In some embodiments, the thickness of the multiple P-type floating islands 210 between the N-type drift region 120 and the top epitaxial region 130 is related to their positions. The thickness of the P-type floating islands 210 arranged opposite to the P-type heavily doped region 330 is greater than the thickness of the P-type floating islands 210 arranged opposite to the P-type well region 320. The thickness of the P-type floating islands 210 arranged opposite to the P-type well region 320 is greater than the thickness of the P-type floating islands 210 arranged opposite to the current extension region 310. In this way, the clamping effect on the saturation current can be adjusted according to the current density of the current flowing between the first electrode layer 510 and the second electrode layer 520, thereby enhancing the short-circuit characteristics and helping to reduce the thickness of the P-type well region 320. The self-depletion effect of the P-type floating islands 210 is beneficial to reducing the capacitance between the first electrode layer 510 (drain) and the gate in the device, thereby improving the switching characteristics of the device.

[0026] In some embodiments, the widths of the multiple P-type floating islands 210 between the N-type drift region 120 and the top epitaxial region 130 are related to their positions. The widths of some of the P-type floating islands 210 arranged opposite to the P-type heavily doped region 330 are greater than the widths of some of the P-type floating islands 210 arranged opposite to the P-type well region 320. The widths of some of the P-type floating islands 210 arranged opposite to the P-type well region 320 are greater than the widths of some of the P-type floating islands 210 arranged opposite to the current extension region 310. In this way, the clamping effect on the saturation current can be adjusted according to the current density of the current flowing between the first electrode layer 510 and the second electrode layer 520, thereby enhancing the short-circuit characteristics and helping to reduce the thickness of the P-type well region 320. The self-depletion effect of the P-type floating islands 210 is beneficial to reducing the capacitance between the first electrode layer 510 (drain) and the gate in the device, thereby improving the switching characteristics of the device.

[0027] In some embodiments, the areas of the multiple P-type floating islands 210 between the N-type drift region 120 and the top epitaxial region 130 are related to their positions. The areas of some P-type floating islands 210 arranged opposite to the P-type heavily doped region 330 are larger than the areas of some P-type floating islands 210 arranged opposite to the P-type well region 320. The areas of some P-type floating islands 210 arranged opposite to the P-type well region 320 are larger than the areas of some P-type floating islands 210 arranged opposite to the current extension region 310. In this way, the clamping effect on the saturation current can be adjusted according to the current density of the current flowing between the first electrode layer 510 and the second electrode layer 520, thereby enhancing the short-circuit characteristics and helping to reduce the thickness of the P-type well region 320. The self-depletion effect of the P-type floating islands 210 is beneficial to reducing the capacitance between the first electrode layer 510 (drain) and the gate in the device, thereby improving the switching characteristics of the device.

[0028] In some embodiments, the ion implantation dose of the P-type well region 320 is 5-13E12 / cm 2 .

[0029] In some embodiments, the junction depth of the P-type well region 320 is in the range of 0.6-0.7 μm.

[0030] In some embodiments, the ion implantation dose of the N-type heavily doped region 340 is 2-8E15 / cm 2 .

[0031] In some embodiments, N-type heavily doped regions 340 are provided on both sides of the current extension region 310 . The junction depth of the N-type heavily doped regions 340 is 0.3-0.4 μm. The N-type heavily doped regions 340 are used to form a good ohmic contact with the second electrode layer 520 .

[0032] In some embodiments, the ion implantation dose of the current extension region 310 is 1E13-1E14 / cm 2 .

[0033] In some embodiments, the junction depth of the current extension region 310 is 0.8-1.0 μm, and the junction depth of the current extension region 310 exceeds the junction depth of the P-type well region 320, which can optimize the BV-Ron trade-off relationship, so that the device optimizes the on-resistance (Ron) without affecting the breakdown voltage (BV). When the junction depth of the current extension region 310 is 0.8-1.0 μm, and the junction depth of the current extension region 310 exceeds the junction depth of the P-type well region 320 by approximately 0.2-0.3 μm, the on-resistance (Ron) is reduced by 10%, which has a better BV-Ron trade-off relationship and meets the device performance requirements of high-power applications.

[0034] In some embodiments, the doping depth of the current extension region 310 is greater than the doping depth of the P-type well region 320, so that the top epitaxial region 130 has a groove structure, which is opposite to the gate layer 420. At this time, the thickness of the current extension region 310 is greater than the thickness of the P-type well region 320, and the difference between the thickness of the current extension region 310 and the thickness of the P-type well region 320 is 0.2-0.3um.

[0035] In some embodiments, the second electrode layer 520 may be a source layer, and the first electrode layer 510 may be a source layer.

[0036] In some embodiments, the lower surface of the N-type heavily doped region 340 is flush with the upper surface of the P-type heavily doped region 330, and the thickness of the N-type heavily doped region 340 is 0.3-0.4 μm. A shallow trench of 0.3-0.4 μm is formed by source etching, which increases the contact area between the second electrode layer 520 and the N-type heavily doped region 340, effectively reducing contact resistance, facilitating cell size reduction, and further reducing the device's specific on-resistance.

[0037] In some embodiments, the junction depth of the P-type heavily doped region 330 is 1.0-1.1 μm, exceeding the thickness of the P-type well region 320 by 0.6-0.8 μm, for optimizing electric field distribution and forming a good grounding.

[0038] In some embodiments, a P-type well region 320 is provided on both adjacent sides of the current extension region 310. The P-type well region 320 has an L-shaped structure. An N-type heavily doped region 340 is formed on the horizontal portion of the P-type well region 320. Furthermore, the P-type heavily doped region 330 is in contact with the P-type well region 320, and the thickness of the P-type heavily doped region 330 is greater than the thickness of the horizontal portion of the P-type well region 320. By etching a shallow trench structure at the source, the implantation depth of the P-type heavily doped region 330 can be made deeper. The P-type heavily doped region 330 is located directly below the shallow source trench and has the same width as the trench. The P-type heavily doped region 330 is 0.3-0.4 μm deeper than a conventional MOS, meaning that its depth exceeds the depth of the horizontal portion of the P-type well region 320 by at least 0.6-0.8 μm. This optimizes the device's withstand voltage performance and significantly improves its reliability and stability.

[0039] In some embodiments, a plurality of P-type floating islands 210 can be formed on the N-type drift region 120 by P-type ion implantation. The plurality of P-type floating islands 210 are arranged in parallel, which can increase the clamping effect on the saturation current and enhance the short-circuit characteristics. At the same time, the self-depletion effect of the floating island is equivalent to connecting a depletion region capacitor in series between the gate and the drain, thereby reducing the total Cgd of the device and improving the switching characteristics of the device.

[0040] In some embodiments, among the plurality of P-type floating islands 210 , the spacing between adjacent P-type floating islands 210 is the same.

[0041] In some embodiments, the width of the P-type floating island 210 is 0.6-1 um, and the thickness of the P-type floating island 210 is 0.4-0.6 um.

[0042] In some embodiments, the gate layer 420 is a convex structure, and the gate dielectric layer 410 has a protruding structure opposite to the gate layer 420. The protruding structure extends deep into the current extension region 310, so that the insulating layer between the gate and drain of the device becomes thicker and Cgd is reduced. In this way, the thickness of the middle gate dielectric can be thickened to withstand high electric fields, thereby enhancing the reliability of the gate dielectric layer 410 and strengthening the switching characteristics of the device.

[0043] In some embodiments, the gate dielectric layer 410 is silicon oxide.

[0044] In some embodiments, see Figure 2 As shown, the gate dielectric layer 410 includes multiple gate layers 420 , which are isolated by the gate dielectric layer 410 , and at least two gate layers 420 are arranged opposite to the vertical portions of the P-type well region 320 on both sides of the current extension region 310 .

[0045] In this embodiment, if Figure 2 As shown, the gate dielectric layer 410 includes a gate layer 421 and a gate layer 422. The gate layer 421 is arranged relative to the vertical portion of the P-type well region 320 on the first side of the current extension region 310, and the gate layer 422 is arranged relative to the vertical portion of the P-type well region 320 on the second side of the current extension region 310. By optimizing the doping concentration and depth of each region and adopting a special gate structure design, the on-resistance and breakdown voltage of the device are effectively balanced, thereby improving the short-circuit tolerance and switching performance of the device.

[0046] In some embodiments, see Figure 3 As shown, a P-type shallowly doped region 430 is provided between the current extension region 310 and the gate dielectric layer 410 . The P-type shallowly doped region 430 contacts the gate dielectric layer 410 and is located in the groove of the current extension region 310 .

[0047] In this embodiment, the gate dielectric layer 410 can be protected by providing the P-type shallowly doped region 430 .

[0048] In some embodiments, see Figure 4 As shown, the current extension region 310 is a concave structure, and a portion of the protruding structure of the gate dielectric layer 410 is filled in the groove of the current extension region 310 .

[0049] In this embodiment, the raised structure of the gate dielectric layer 410 is opposite to the middle of the gate, and can be formed by etching the silicon carbide material downward along the middle of the gate to form a shallow groove and filling it with dielectric material. By forming a partial raised structure in the direction of the gate dielectric layer 410 toward the current extension region 310, it is beneficial to protect the gate dielectric layer 410.

[0050] In some embodiments, see Figure 5 As shown, the top epitaxial region 130 is a concave structure, and the top epitaxial region 130 and the N-type drift region 120 have different doping concentrations.

[0051] In this embodiment, the top epitaxial region 130 and the N-type drift region 120 have the same doping type, the thickness of the top epitaxial region 130 is approximately 1.5-2.5 μm, the doping concentration of the top epitaxial region 130 is less than the doping concentration of the current extension region 310, and the doping concentration of the top epitaxial region 130 is greater than the doping concentration of the N-type drift region 120. In this way, the Ron-BV trade-off relationship can be further optimized.

[0052] In some embodiments, as Figure 5 As shown, the groove of the gate layer 420 is opposite to the groove of the current extension region 310 .

[0053] In some embodiments, see Figure 6 As shown, multiple P-type floating islands 210 include a P-type floating island 211, a P-type floating island 212, and a P-type floating island 213. The P-type floating island 211 is arranged opposite to the P-type heavily doped region 330 on the first side of the current extension region 310, the P-type floating island 212 is arranged opposite to the P-type heavily doped region 330 on the second side of the current extension region 310, and the P-type floating island 213 is arranged opposite to the current extension region 310.

[0054] In some embodiments, see Figure 6 As shown, the width of the P-type floating island 210 is equal to or greater than the width of the current extension region 310; at least one P-type floating island 210 is arranged opposite to the current extension region 310, and at least two P-type floating islands 210 are arranged opposite to the P-type heavily doped regions 330 on both sides of the current extension region 310.

[0055] In some embodiments, participating Figure 7 As shown, the silicon carbide substrate 110 is P-type doped, and an N-type buffer layer 121 is further provided between the silicon carbide substrate 110 and the N-type drift region 120 .

[0056] In this embodiment, the second electrode layer 520 may be an emitter, and the first electrode layer 510 may be a collector, thereby forming an IGBT structure with a P-type substrate.

[0057] The present invention also provides a method for preparing a silicon carbide power device. Figure 8As shown, the preparation method includes: steps S100 to S500.

[0058] In step S100 , an N-type drift region 120 is formed on a silicon carbide substrate 110 , and P-type ion implantation is performed on a plurality of regions on the N-type drift region 120 to form a plurality of P-type floating islands 210 .

[0059] In this embodiment, an N-type drift region 120 may be formed on the silicon carbide substrate 110 by an epitaxial process, such as Figure 9 Schematic structure (a) in FIG, and then P-type ion implantation is performed on multiple regions on the N-type drift region 120 to form multiple P-type floating islands 210, as shown in FIG. Figure 9 Schematic structure of (b).

[0060] In some embodiments, the doping concentration of the silicon carbide substrate 110 is greater than the doping concentration of the N-type drift region 120 .

[0061] In step S200 , secondary epitaxial growth is performed to form a top epitaxial region 130 , and the top epitaxial region 130 is etched so that the top epitaxial region 130 has a concave structure.

[0062] In this embodiment, through another epitaxial process, the top epitaxial region 130 covering the plurality of P-type floating islands 210 is formed. Figure 9 As shown in the schematic structure (c) in FIG, the top epitaxial region 130 is etched into a shallow source trench to form a micro-trench in the middle of the JFET, as shown in FIG. Figure 9 The schematic structure is shown in (d).

[0063] In step S300 , a current extension region 310 , an N-type heavily doped region 340 , a P-type well region 320 , and a P-type heavily doped region 330 are formed by a self-aligned process.

[0064] In this embodiment, multiple ion implantations are performed by a self-aligned process, such as Figure 9 As shown in the schematic structure (e) in FIG, the current extension region 310, the P-type well region 320 and the P-type heavily doped region 330 are located on the top epitaxial region 130, and the P-type heavily doped region 330 and the P-type well region 320 are provided on both sides of the current extension region 310, and the P-type well region 320 is located between the P-type heavily doped region 330 and the current extension region 310.

[0065] In step S400 , a gate dielectric layer 410 is formed on the N-type heavily doped region, the P-type well region 320 , and the current extension region 310 , and a gate layer 420 is formed by a polysilicon deposition process so that the gate dielectric layer 410 wraps the gate layer 420 .

[0066] In this embodiment, a gate dielectric layer covering the N-type heavily doped region, the P-type well region 320, and the current extension region 310 may be formed by a thermal oxidation process, such as Figure 9 As shown in the schematic structure (f) in FIG, a gate layer 420 is formed by chemical vapor deposition, and then a thermal oxidation process and an etching process are performed again to obtain a gate dielectric layer 410 wrapping the gate layer 420, as shown in FIG. Figure 9 The schematic structure is shown in (g).

[0067] In step S500, a first electrode layer 510 is formed on the back side of the silicon carbide substrate 110, and a second electrode layer 520 is formed on the gate dielectric layer 410, the N-type heavily doped region 340, and the P-type heavily doped region 330. Figure 9 The schematic structure is shown in (h).

[0068] In some embodiments, in step S100 , forming an N-type drift region 120 on the silicon carbide substrate 110 includes forming an N-type buffer layer 121 on the silicon carbide substrate 110 and forming the N-type drift region 120 on the N-type buffer layer 121 .

[0069] In this embodiment, if the silicon carbide substrate 110 is P-type doped, an N-type buffer layer can be formed on the silicon carbide substrate 110 by epitaxy. At this time, the second electrode layer 520 can be an emitter and the first electrode layer 510 can be a collector, thereby forming an IGBT structure with a P-type substrate.

[0070] An embodiment of the present application further provides a chip, comprising the silicon carbide power device as described in any one of the above items.

[0071] In this embodiment, the chip includes a chip substrate, on which one or more silicon carbide power devices are disposed.

[0072] In some embodiments, the silicon carbide power device may be any one of a silicon carbide MOSFET, a silicon carbide triode, and a silicon carbide IGBT.

[0073] The silicon carbide device described in any of the above embodiments can be applied to any high-voltage power device produced based on SiC materials, including but not limited to silicon carbide MOSFET, silicon carbide diode, silicon carbide IGBT, etc.

[0074] In a specific application embodiment, other related semiconductor devices may be integrated on the chip substrate to form an integrated circuit together with the preparation method of the silicon carbide power device.

[0075] In a specific application embodiment, the chip may be a switch chip or a driver chip.

[0076] In this embodiment, by providing a plurality of P-type floating islands between the N-type drift region and the top epitaxial region, the clamping effect on the saturation current can be increased, and the short-circuit characteristics can be enhanced. At the same time, the self-depletion effect of the P-type floating island is beneficial to reducing the capacitance between the first electrode layer 510 and the gate in the device, thereby improving the switching characteristics of the device. Moreover, the trade-off relationship between the breakdown voltage and the on-resistance can be effectively balanced in the case of a shallower P-type well region and a deeper doped current extension region, so that the device optimizes the on-resistance without affecting the breakdown voltage, thereby meeting the device performance requirements of high-power applications.

[0077] Those skilled in the art will clearly understand that for the sake of convenience and brevity, the division of the above-mentioned doping regions and devices is only used as an example for illustration. In actual applications, the above-mentioned functions can be distributed and completed by different doping regions and devices as needed, that is, the internal structure of the device is divided into different doping regions to complete all or part of the functions described above. The doping regions and devices in the embodiments can be integrated into a single unit, each unit can exist physically separately, or two or more units can be integrated into a single unit.

[0078] In addition, the specific names of the doping regions and devices are only for the convenience of distinguishing each other and are not used to limit the scope of protection of this application.

[0079] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0080] In addition, each doping region in each embodiment of the present application may be integrated into one unit, each unit may exist physically separately, or two or more units may be integrated into one unit.

[0081] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A silicon carbide power device, characterized in that: The silicon carbide power device comprises: a silicon carbide substrate, a first electrode layer, an N-type drift region, a P-type floating island, a top epitaxial region, a current extension region, an N-type heavily doped region, a P-type well region, a P-type heavily doped region, a gate dielectric layer, a gate layer and a second electrode layer; The first electrode layer is located on the back side of the silicon carbide substrate, the N-type drift region is located on the front side of the silicon carbide substrate, and a plurality of P-type floating islands are provided between the N-type drift region and the top epitaxial region; The current extension region, the P-type well region, and the P-type heavily doped region are located on the top epitaxial region, and the P-type heavily doped region and the P-type well region are provided on both sides of the current extension region, the P-type well region is located between the P-type heavily doped region and the current extension region, the depth of the current extension region is greater than the depth of the P-type well region, the doping concentration of the P-type well region is less than the doping concentration of the P-type heavily doped region, and the doping concentration of the current extension region is greater than the doping concentration of the top epitaxial region; The N-type heavily doped region is formed on the horizontal portion of the P-type well region, the gate dielectric layer is located on the N-type heavily doped region, the P-type well region, and the current extension region, and the gate dielectric layer wraps the gate layer, and the second electrode layer covers the gate dielectric layer and contacts the N-type heavily doped region and the P-type heavily doped region.

2. The silicon carbide power device according to claim 1, wherein: The gate dielectric layer includes a plurality of gate layers, the plurality of gate layers are isolated by the gate dielectric layer, and at least two gate layers are arranged opposite to the vertical portions of the P-type well region on both sides of the current extension region.

3. The silicon carbide power device according to claim 1, wherein: A P-type shallowly doped region is provided between the current extension region and the gate dielectric layer. The P-type shallowly doped region contacts the gate dielectric layer and is located in the groove of the current extension region.

4. The silicon carbide power device according to claim 1, wherein: The current extension region is a concave structure, and a portion of the protruding structure of the gate dielectric layer is filled in the groove of the current extension region.

5. The silicon carbide power device according to claim 1, wherein: The top epitaxial region is a concave structure, and the top epitaxial region and the N-type drift region have different doping concentrations.

6. The silicon carbide power device according to claim 1, wherein: The width of the P-type floating island is equal to or greater than the width of the current extension region; at least one of the P-type floating islands is arranged opposite to the current extension region, and at least two of the P-type floating islands are arranged opposite to the P-type heavily doped regions on both sides of the current extension region.

7. The silicon carbide power device according to claim 1, wherein: The silicon carbide substrate is P-type doped, and an N-type buffer layer is provided between the silicon carbide substrate and the N-type drift region.

8. A method for preparing a silicon carbide power device, characterized in that: The preparation method comprises: forming an N-type drift region on a silicon carbide substrate, and performing P-type ion implantation on a plurality of regions on the N-type drift region to form a plurality of P-type floating islands; Performing secondary epitaxy to form a top epitaxial region, and etching the top epitaxial region so that the top epitaxial region has a concave structure; A current extension region, an N-type heavily doped region, a P-type well region, and a P-type heavily doped region are formed using a self-aligned process; wherein the current extension region, the P-type well region, and the P-type heavily doped region are located on the top epitaxial region, and the P-type heavily doped region and the P-type well region are provided on both sides of the current extension region, and the P-type well region is located between the P-type heavily doped region and the current extension region; forming a gate dielectric layer on the N-type heavily doped region, the P-type well region, and the current extension region, and forming a gate layer by a polysilicon deposition process so that the gate dielectric layer wraps the gate layer; A first electrode layer is formed on the back side of the silicon carbide substrate, and a second electrode layer is formed on the gate dielectric layer, the N-type heavily doped region, and the P-type heavily doped region.

9. The preparation method according to claim 8, wherein The forming of an N-type drift region on a silicon carbide substrate comprises: An N-type buffer layer is formed on a silicon carbide substrate, and an N-type drift region is formed on the N-type buffer layer.

10. A chip, characterized in that: The chip includes the silicon carbide power device according to any one of claims 1 to 7.

Images