Heterojunction battery and preparation method and application thereof

Abstract

The invention provides a heterojunction cell and a preparation method and application thereof, and belongs to the technical field of photovoltaic.The preparation method comprises the steps that first intrinsic amorphous layers are deposited on the surface and the side face of one side of a substrate, and a second intrinsic amorphous layer and an N-type doped microcrystalline silicon layer are sequentially deposited on the surface and the side face of the other side of the substrate; depositing a P-type doped microcrystalline silicon layer on the surface of the first intrinsic amorphous layer and the side surface of the substrate, wherein the P-type doped microcrystalline silicon layer is overlapped with the N-type doped microcrystalline silicon layer on the side surface of the substrate; preparing a back TCO film layer and a front TCO film layer; preparing metal electrodes on the surfaces of the back TCO film layer and the front TCO film layer respectively; the deposition temperature of the P-type doped microcrystalline silicon layer is less than 160 DEG C and greater than or equal to 130 DEG C. Through low-temperature deposition of the P-type doped microcrystalline silicon layer, the problems that the efficiency of the heterojunction cell is reduced and the power of the assembly is reduced after lamination are avoided, so that the efficiency, the thermal stability and the power of the assembly of the heterojunction cell are effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of photovoltaics and relates to a heterojunction battery and a preparation method and application thereof. Background Art

[0002] With the increasing demand for renewable energy, solar photovoltaic cells have become an important energy source. Among solar photovoltaic cells, heterojunction cells have attracted widespread attention due to their high open-circuit voltage, simple preparation process, good light stability, low temperature coefficient, and high conversion efficiency compared to other crystalline silicon cells.

[0003] However, when heterojunction cells are fabricated into modules, they undergo adhesive film lamination. The typical module lamination process temperature is between 110-150°C, and the total lamination time is 10-20 minutes. High temperatures and long lamination times can lead to a decrease in heterojunction cell efficiency. This is because heat-induced hydrogen diffusion in the microcrystalline doping layer alters the effective doping structure within the microcrystalline layer. This reduction in cell efficiency ultimately reduces module power.

[0004] Based on the above research, it is necessary to provide a method for preparing a heterojunction battery, which can enable the heterojunction battery to resist thermal attenuation and ensure component power. Summary of the Invention

[0005] The purpose of the present invention is to provide a heterojunction battery and its preparation method and application. The preparation method avoids the problem of decreased efficiency and reduced component power of heterojunction batteries after lamination by depositing a P-type doped microcrystalline silicon layer at low temperature, thereby effectively improving the efficiency, thermal stability and component power of heterojunction batteries.

[0006] In order to achieve the purpose of the invention, the present invention adopts the following technical solutions:

[0007] In a first aspect, the present invention provides a method for preparing a heterojunction battery, the method comprising the following steps:

[0008] A first intrinsic amorphous layer is deposited on the surface and side of one side of the substrate, and a second intrinsic amorphous layer and an N-type doped microcrystalline silicon layer are deposited in sequence on the surface and side of the other side. Then, a P-type doped microcrystalline silicon layer is deposited on the surface of the first intrinsic amorphous layer and the side of the substrate. The P-type doped microcrystalline silicon layer overlaps with the N-type doped microcrystalline silicon layer on the side of the substrate.

[0009] A back transparent conductive oxide film layer (TCO film layer) is prepared on a portion of the surface of the P-type doped microcrystalline silicon layer.

[0010] A front TCO film layer is prepared on the surface and side surfaces of the N-type doped microcrystalline silicon layer.

[0011] Metal electrodes are respectively prepared on the surfaces of the back TCO film layer and the front TCO film layer.

[0012] The deposition temperature of the P-type doped microcrystalline silicon layer is less than 160° C. and greater than or equal to 130° C.

[0013] In some embodiments, the deposition temperature of the P-type doped microcrystalline silicon layer is less than 160° C. and greater than or equal to 140° C.

[0014] In some embodiments, before depositing the P-type doped microcrystalline silicon layer, a third intrinsic layer is first deposited on the surface of the first intrinsic amorphous layer and the side of the substrate, and the third intrinsic layer is located between the P-type doped microcrystalline silicon layer and the N-type doped microcrystalline silicon layer on the side of the substrate.

[0015] In some embodiments, the ratio of the dopant flow rate to the silane flow rate during the deposition of the P-type doped microcrystalline silicon layer is 0.4% to 1.6%, preferably 0.7% to 0.9%.

[0016] In some embodiments, the dopant for depositing the P-type doped microcrystalline silicon layer includes borane, and the gas actually introduced is a mixture of borane and hydrogen, with a borane concentration of 2%.

[0017] In some embodiments, the method of depositing the P-type doped microcrystalline silicon layer includes plasma enhanced chemical vapor deposition (PECVD).

[0018] In some embodiments, the gas pressure for depositing the P-type doped microcrystalline silicon layer is 3.5 torr to 6 torr, and the power is 2.9 kW / m 2 ~5.2kW / m 2 , the deposition thickness is 15nm~35nm.

[0019] In some embodiments, the method of depositing the N-type doped microcrystalline silicon layer comprises PECVD.

[0020] In some embodiments, the N-type doped microcrystalline silicon layer is deposited at a temperature of 160° C. to 220° C., and has a thickness of 15 nm to 30 nm.

[0021] In some embodiments, the method of depositing the first intrinsic amorphous layer includes PECVD, the deposition temperature is 180° C. to 230° C., and the deposition thickness is 4 nm to 10 nm.

[0022] In some embodiments, the method of depositing the second intrinsic amorphous layer includes PECVD, the deposition temperature is 180° C. to 230° C., and the deposition thickness is 4 nm to 10 nm.

[0023] In some embodiments, the method of depositing the third intrinsic layer includes PECVD, the deposition temperature is 180° C. to 230° C., and the thickness of the deposited film is 0.5 nm to 5 nm.

[0024] In some embodiments, the method of preparing the backside TCO film layer and the frontside TCO film layer comprises physical vapor deposition (PVD).

[0025] In some embodiments, the back TCO film layer includes an oxide conductive film containing In and / or an oxide conductive film not containing In, and the thickness of the back TCO film layer is 50 nm to 150 nm.

[0026] In some embodiments, the front TCO film layer includes an oxide conductive film containing In and / or an oxide conductive film not containing In, and the thickness of the front TCO film layer is 50 nm to 150 nm.

[0027] In some embodiments, the method for preparing the metal electrode includes printing the metal electrode slurry, followed by drying and curing.

[0028] In a second aspect, the present invention provides a method for preparing a heterojunction battery, the method comprising the following steps:

[0029] A first intrinsic amorphous layer is deposited on the surface and side of one side of the substrate, and a second intrinsic amorphous layer and an N-type doped microcrystalline silicon layer are deposited in sequence on the surface and side of the other side. Then, a P-type doped microcrystalline silicon layer is deposited on the surface of the first intrinsic amorphous layer and the side of the substrate. The P-type doped microcrystalline silicon layer overlaps with the N-type doped microcrystalline silicon layer on the side of the substrate.

[0030] A back TCO film layer is prepared on a portion of the surface of the P-type doped microcrystalline silicon layer.

[0031] A front TCO film layer is prepared on the surface and side surfaces of the N-type doped microcrystalline silicon layer.

[0032] Metal electrodes are respectively prepared on the surfaces of the back TCO film layer and the front TCO film layer.

[0033] The chamber temperature for depositing the P-type doped microcrystalline silicon layer is 145° C. to 205° C.

[0034] In some embodiments, the difference between the chamber temperature during the deposition of the P-type doped microcrystalline silicon layer and the deposition temperature during the deposition of the P-type doped microcrystalline silicon layer is 15° C. to 45° C.

[0035] In a third aspect, the present invention provides a heterojunction battery, wherein the heterojunction battery is prepared using the preparation method described in the first aspect or the second aspect;

[0036] The heterojunction battery includes a substrate, a first intrinsic amorphous layer arranged on the surface and side of one side of the substrate, and a second intrinsic amorphous layer arranged on the surface and side of the other side of the substrate. The first intrinsic amorphous layer is further provided with a P-type doped microcrystalline silicon layer, a back TCO film layer and a metal electrode in sequence on the side away from the substrate, and the second intrinsic amorphous layer is further provided with an N-type doped microcrystalline silicon layer, a front TCO film layer and a metal electrode in sequence on the side away from the substrate.

[0037] In a fourth aspect, the present invention provides a solar module, comprising the heterojunction cell as described in the third aspect.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] The present invention reduces the temperature during deposition of the P-type doped microcrystalline silicon layer, thereby preventing H diffusion in the P-type doped microcrystalline silicon layer during hot pressing during the preparation of heterojunction cells, thereby changing the effective doping structure in the microcrystalline layer and causing a decrease in heterojunction cell efficiency and component power. This effectively improves the efficiency and thermal stability of the heterojunction cell and the power performance of the component. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 The figure is a flow chart of the preparation method in one embodiment of the present invention.

[0041] Figure 2 This is a schematic structural diagram of the heterojunction battery described in Example 1 of the present invention.

[0042] Figure 3 This is a schematic structural diagram of the heterojunction battery described in Example 4 of the present invention.

[0043] Among them, 10-second metal electrode, 11-front TCO film layer, 12-N-type doped microcrystalline silicon layer, 13-second intrinsic amorphous layer, 14-substrate, 15-first intrinsic amorphous layer, 16-P-type doped microcrystalline silicon layer, 17-back TCO film layer, 18-first metal electrode, 19-third intrinsic layer. DETAILED DESCRIPTION

[0044] The technical solution of the present invention is further described below by way of specific embodiments. It should be understood by those skilled in the art that the embodiments are merely to help understand the present invention and should not be regarded as specific limitations of the present invention.

[0045] In the first aspect, the present invention provides a method for preparing a heterojunction battery, the flow chart of the preparation method is as follows Figure 1 As shown, the preparation method comprises the following steps:

[0046] S100: depositing a first intrinsic amorphous layer on the surface and side of one side of the substrate, depositing a second intrinsic amorphous layer and an N-type doped microcrystalline silicon layer on the surface and side of the other side in sequence, and then depositing a P-type doped microcrystalline silicon layer on the surface of the first intrinsic amorphous layer and the side of the substrate, the P-type doped microcrystalline silicon layer overlapping with the N-type doped microcrystalline silicon layer on the side of the substrate.

[0047] S200: preparing a back TCO film layer on a portion of the surface of the P-type doped microcrystalline silicon layer.

[0048] S300: Preparing a front TCO film layer on the surface and side surfaces of the N-type doped microcrystalline silicon layer.

[0049] S400: preparing metal electrodes on the surfaces of the back TCO film layer and the front TCO film layer respectively.

[0050] Wherein, the deposition temperature of the P-type doped microcrystalline silicon layer in S100 is less than 160° C. and greater than or equal to 130° C.

[0051] The present invention deposits a P-type doped microcrystalline silicon layer at a low temperature below 160°C, which can improve the crystallization rate of the P-type doped microcrystalline silicon layer and reduce the activation energy of the P-type doped microcrystalline silicon layer, thereby reducing the series resistance Rs of the battery and improving FF, ultimately achieving an improvement in battery efficiency. This solves the problem that due to the hot pressing in the component preparation process, H diffusion in the P-type doped microcrystalline silicon layer causes the effective doping structure to change, resulting in a decrease in the efficiency of the heterojunction battery. Therefore, the present invention can improve the efficiency of the heterojunction battery by depositing the P-type doped microcrystalline silicon layer at a low temperature, reduce the influence of thermal attenuation of the heterojunction battery, and avoid power reduction of the component.

[0052] In addition, after the present invention prepares the P-type doped microcrystalline silicon layer, a back TCO film layer is immediately prepared on part of its surface, and then a front TCO film layer is prepared on the surface and side of the N-type doped microcrystalline silicon layer. This sequence can better protect the pn junction on the back and improve the passivation effect. At the same time, due to the influence of water vapor on the front TCO film layer, the carrier concentration of the film layer is reduced and the square resistance is increased. Finally, the front TCO film is plated to better avoid the influence of water vapor and improve the reliability of the heterojunction battery.

[0053] The deposition temperature of the P-type doped microcrystalline silicon layer deposited in S100 of the present invention refers to the coating temperature, which corresponds to the actual temperature of the film carrier. The deposition temperature is <160°C and ≥130°C. For example, it can be 155°C, 150°C, 140°C or 130°C, but is not limited to the listed values. Other unlisted values ​​within the numerical range are also applicable, preferably <160°C and ≥140°C.

[0054] The temperature for depositing the P-type doped microcrystalline silicon layer in the present invention is not easy to be too low. If the deposition temperature is too low, the deposition rate of the microcrystalline layer will decrease, which will cause the thickness of the microcrystalline layer to become thinner, thereby affecting the field passivation effect. In addition, if the deposition temperature is too low, the doping concentration will further increase, resulting in an increase in internal defects in the film layer, and further causing the dark conductivity of the film layer to decrease.

[0055] In a specific embodiment, before depositing the P-type doped microcrystalline silicon layer, a third intrinsic layer is first deposited on the surface of the first intrinsic amorphous layer and the side of the substrate, and the third intrinsic layer is located between the P-type doped microcrystalline silicon layer and the N-type doped microcrystalline silicon layer on the side of the substrate.

[0056] Since the present invention prepares highly doped P-type doped microcrystalline silicon layers and N-type doped microcrystalline silicon layers, which are different from amorphous silicon layers, the P-type doped microcrystalline silicon layers and N-type doped microcrystalline silicon layers have better conductivity. When the P-type doped microcrystalline silicon layers and N-type doped microcrystalline silicon layers overlap on the sides, they are prone to edge leakage. In order to solve the edge leakage problem of the P-type doped microcrystalline silicon layers and the N-type doped microcrystalline silicon layers, the present invention deposits a third intrinsic layer to separate the sides of the P-type doped microcrystalline silicon layers and the N-type doped microcrystalline silicon layers to avoid the formation of tunnel junctions and leakage. Therefore, since the P-type doped layers and N-type doped layers in the prior art are amorphous silicon layers, and the present invention is aimed at highly doped P-type doped microcrystalline silicon layers and N-type doped microcrystalline silicon layers, the present invention further adds a third intrinsic layer to improve the structure and process, thereby improving battery efficiency while avoiding current loss. In addition, depositing an intrinsic layer before the P microcrystal-doped microcrystalline silicon layer can serve as a sublayer, which can further improve the crystallization rate of the P microcrystal-doped layer, thereby reducing the series resistance Rs of the heterojunction battery. At the same time, it can also improve passivation, ultimately achieving an increase in the battery fill factor FF and efficiency EFF.

[0057] In a specific embodiment, the ratio of the dopant flow rate to the silane flow rate for depositing the P-type doped microcrystalline silicon layer is 0.4% to 1.6%, for example, it can be 0.4%, 0.6%, 0.8%, 1.0%, 1.2%, 1.4% or 1.6%, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0058] The low-temperature deposition of the P-type doped microcrystalline silicon layer in the present invention increases the doping amount compared to high-temperature deposition. In order to cooperate with the low-temperature deposition of the P-type doped microcrystalline silicon layer, a specific dopant flow rate is used to increase the dopant content in the P-type doped microcrystalline silicon layer, which can reduce the contact resistivity between the intrinsic amorphous silicon layer and the P-type doped microcrystalline silicon layer, thereby reducing the battery series resistance Rs and improving the battery efficiency; if the dopant flow rate is too low, the boron doping amount will be too low, thereby causing the field passivation to decrease, and at the same time increasing the contact resistivity between the intrinsic amorphous silicon layer and the P-type doped microcrystalline silicon layer; if the dopant flow rate is too high, the boron doping amount will be too high, resulting in disordered structure of the P-type doped microcrystalline silicon layer, thereby reducing the crystallization rate of the microcrystalline doped layer, and ultimately causing the battery Rs to increase and the battery efficiency to decrease.

[0059] In a specific embodiment, the dopant for depositing the P-type doped microcrystalline silicon layer includes borane.

[0060] In a specific embodiment, the method of depositing the P-type doped microcrystalline silicon layer includes PECVD.

[0061] The low-temperature deposition of the P-type doped microcrystalline silicon layer described in the present invention is matched with the PECVD method.

[0062] In a specific embodiment, the gas pressure for depositing the P-type doped microcrystalline silicon layer is 3.5 torr to 6 torr, for example, 3.5 torr, 4.5 torr, 5.5 torr or 6 torr, and the power density is 2.8 kW / m 2 ~5.2kW / m 2 , for example, it can be 2.9kW / m 2 、3.6kW / m 2 4.4kW / m 2 or 5.1kW / m 2 The deposition thickness is 15 nm to 35 nm, for example, 15 nm, 20 nm, 25 nm, 30 nm or 35 nm, but is not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0063] In a specific embodiment, the method of depositing the N-type doped microcrystalline silicon layer includes PECVD.

[0064] In a specific embodiment, the temperature for depositing the N-type doped microcrystalline silicon layer is 160°C to 220°C, for example, it can be 160°C, 180°C, 200°C or 220°C, and the deposition thickness is 15nm to 30nm, for example, it can be 15nm, 20nm, 25nm or 30nm, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0065] In a specific embodiment, the method of depositing the first intrinsic amorphous layer includes PECVD, the deposition temperature is 180°C to 230°C, for example, it can be 180°C, 190°C, 200°C, 210°C or 230°C, and the deposition thickness is 4nm to 10nm, for example, it can be 4nm, 6nm, 8nm or 10nm, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0066] In a specific embodiment, the method of depositing the second intrinsic amorphous layer includes PECVD, the deposition temperature is 180°C to 230°C, for example, it can be 180°C, 190°C, 200°C, 210°C or 230°C, and the deposition thickness is 4nm to 10nm, for example, it can be 4nm, 6nm, 8nm or 10nm, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0067] In one embodiment, the method for depositing the third intrinsic layer includes PECVD, the power frequency used is greater than 14 MHz, for example, 14 MHz, 16 MHz, 18 MHz or 20 MHz, the deposition gas includes silane, hydrogen and carbon dioxide, the deposition temperature is 180°C to 230°C, for example, 180°C, 190°C, 200°C, 210°C or 230°C, the deposition thickness is 0.5 nm to 5 nm, for example, 0.5 nm, 1 nm, 2 nm, 4 nm or 5 nm, the deposition pressure is 0.5 to 1.5 torr, for example, 0.5 torr, 0.7 torr, 0.9 torr, 1.2 torr or 1.5 torr, and the deposition power density is 0.3 kW / m 2 ~0.8kW / m 2 , for example, it can be 0.3kW / m 2 , 0.5kW / m 2 , 0.6kW / m 2 and 0.8kW / m 2 , but not limited to the listed values, other unlisted values ​​within the numerical range are also applicable.

[0068] The deposition temperature of the intrinsic amorphous layer of the present invention is carried out within a specific temperature range and should not be too high, so as to avoid the problem of crystallization of the intrinsic amorphous layer and resulting in chemical passivation failure.

[0069] In a specific embodiment, the method for preparing the back TCO film layer and the front TCO film layer includes PVD.

[0070] In a specific embodiment, the back TCO film layer and the front TCO film layer independently include an In-containing oxide conductive film and / or an In-free oxide conductive film.

[0071] The In-containing oxide conductive film may be any one of ITO, VTTO, HITO or IWO, or a combination of at least two thereof.

[0072] In a specific embodiment, the thickness of the back TCO film layer and the front TCO film layer are independently 50nm to 150nm, for example, 50nm, 70nm, 90nm, 110nm, 130nm or 150nm, but are not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0073] In one embodiment, the method for preparing the metal electrode includes printing the metal electrode slurry, followed by drying and curing.

[0074] In one specific embodiment, the metal electrode paste includes pure silver paste or silver-copper paste.

[0075] In a specific embodiment, the drying temperature is 100°C to 200°C, for example, it can be 100°C, 120°C, 140°C, 160°C, 180°C or 200°C, but is not limited to the listed values. Other values ​​not listed within the numerical range are also applicable.

[0076] In a specific embodiment, the curing temperature is 150°C to 230°C, for example, 150°C, 170°C, 190°C, 210°C or 230°C, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0077] In a second aspect, the present invention provides a method for preparing a heterojunction battery, the method comprising the following steps:

[0078] S1: depositing a first intrinsic amorphous layer on the surface and side of one side of the substrate, depositing a second intrinsic amorphous layer and an N-type doped microcrystalline silicon layer on the surface and side of the other side in sequence, and then depositing a P-type doped microcrystalline silicon layer on the surface of the first intrinsic amorphous layer and the side of the substrate, the P-type doped microcrystalline silicon layer overlapping with the N-type doped microcrystalline silicon layer on the side of the substrate.

[0079] S2: preparing a back TCO film layer on a portion of the surface of the P-type doped microcrystalline silicon layer.

[0080] S3: preparing a front TCO film layer on the surface and side surfaces of the N-type doped microcrystalline silicon layer.

[0081] S4: preparing metal electrodes on the surfaces of the back TCO film layer and the front TCO film layer respectively.

[0082] The temperature of the chamber for depositing the P-type doped microcrystalline silicon layer in S1 is 145° C. to 205° C.

[0083] Since the deposition of the P-type doped microcrystalline silicon layer needs to be carried out in a cavity, a temperature value needs to be set in the cavity, and the temperature monitoring in the cavity is above the heating plate, and the carrier plate for placing the battery cell intermediate is at a certain distance from the heating plate in the cavity, so the cavity temperature is different from the actual deposition temperature. The present invention can monitor the actual deposition temperature of the carrier plate for placing the battery cell intermediate in the first aspect, and control the actual deposition temperature to be less than 160°C and ≥130°C, and can also control the cavity temperature to be 145°C~205°C to achieve temperature control.

[0084] In a specific embodiment, the difference between the chamber temperature during deposition of the P-type doped microcrystalline silicon layer and the deposition temperature during deposition of the P-type doped microcrystalline silicon layer is 15°C to 45°C, for example, it can be 15°C, 20°C, 25°C, 30°C, 35°C, 40°C or 45°C, but is not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0085] There is a certain difference between the chamber temperature and the deposition temperature described in the present invention. Within a certain range, as shown in Table 1 below, when the film layer passes through 5 vacuum chambers, the chamber temperatures of the first chamber, the second chamber, the third chamber, the fourth chamber, and the fifth chamber are all higher than the deposition temperature.

[0086] Table 1

[0087]

[0088] The other conditions of the method for preparing a heterojunction battery in the second aspect are the same as those of the method for preparing a heterojunction battery in the first aspect.

[0089] In a third aspect, the present invention further provides a heterojunction battery, wherein the heterojunction battery is prepared using the preparation method according to the present invention;

[0090] The heterojunction battery includes a substrate, a first intrinsic amorphous layer arranged on the surface and side of one side of the substrate, and a second intrinsic amorphous layer arranged on the surface and side of the other side of the substrate. The first intrinsic amorphous layer is further provided with a P-type doped microcrystalline silicon layer, a back TCO film layer and a metal electrode in sequence on the side away from the substrate, and the second intrinsic amorphous layer is further provided with an N-type doped microcrystalline silicon layer, a front TCO film layer and a metal electrode in sequence on the side away from the substrate.

[0091] In a fourth aspect, the present invention further provides a solar module, which includes the heterojunction cell described in the present invention.

[0092] The solar module of the present invention can ensure low module power attenuation under the lamination temperature of 140-155° C., and can also ensure that the module film has a high degree of cross-linking.

[0093] The technical solution of the present invention is further illustrated below through specific embodiments.

[0094] Example 1

[0095] This embodiment provides a method for preparing a heterojunction battery. The structural diagram of the heterojunction battery is shown in FIG. Figure 2 As shown, it includes a substrate 14, a first intrinsic amorphous layer 15 provided on the surface and side of one side of the substrate 14, and a second intrinsic amorphous layer 13 provided on the surface and side of the other side of the substrate 14. A P-type doped microcrystalline silicon layer 16, a back TCO film layer 17, and a first metal electrode 18 are sequentially provided on the side of the first intrinsic amorphous layer 15 away from the substrate 14. An N-type doped microcrystalline silicon layer 12, a front TCO film layer 11, and a second metal electrode 10 are sequentially provided on the side of the second intrinsic amorphous layer 13 away from the substrate 14. The preparation method includes the following steps:

[0096] (1) A first intrinsic amorphous layer 15 is deposited on the surface and side of one side of the substrate 14 by using the PECVD method, and a second intrinsic amorphous layer 13 and an N-type doped microcrystalline silicon layer 12 are deposited in sequence on the surface and side of the other side by using the PECVD method, and then a P-type doped microcrystalline silicon layer 16 is deposited on the surface and side of the first intrinsic amorphous layer 15 by using the PECVD method.

[0097] The chamber temperature for depositing the P-type doped microcrystalline silicon layer 16 is set at 165° C., corresponding to an actual carrier temperature of 140° C. The borane flow rate during deposition is 1% of the silane flow rate, the gas pressure is 5 Torr, and the power density is 3.6 kW / m 2 , the deposition thickness is 25nm.

[0098] The N-type doped microcrystalline silicon layer 12 is deposited at a temperature of 190° C. and has a thickness of 25 nm.

[0099] The first intrinsic amorphous layer 15 is deposited at a temperature of 210° C. with a thickness of 6 nm. The second intrinsic amorphous layer 13 is deposited at a temperature of 210° C. with a thickness of 6 nm.

[0100] The substrate 14 is a textured N-type silicon wafer.

[0101] (2) A back TCO film layer 17 is prepared on a portion of the surface of the P-type doped microcrystalline silicon layer 16 in step (1) by using a PVD method.

[0102] (3) A front TCO film layer 11 is prepared on the surface and side surfaces of the N-type doped microcrystalline silicon layer 12 in step (1) by using a PVD method.

[0103] The thickness of the back TCO film layer 17 and the front TCO film layer 11 is 100 nm and the material is ITO.

[0104] (4) In step (2), pure silver paste is printed on the surface of the back TCO film layer 17 to prepare the first metal electrode 18, and in step (3), pure silver paste is printed on the surface of the front TCO film layer 11 to prepare the second metal electrode 10, and then the mixture is dried at a temperature of 150° C. and cured at a temperature of 200° C. to obtain the heterojunction battery.

[0105] Example 2

[0106] This embodiment provides a method for preparing a heterojunction battery, the heterojunction battery comprising a substrate, a first intrinsic amorphous layer disposed on the surface and side of one side of the substrate, and a second intrinsic amorphous layer disposed on the surface and side of the other side of the substrate, wherein a P-type doped microcrystalline silicon layer, a back TCO film layer, and a first metal electrode are sequentially disposed on a side of the first intrinsic amorphous layer away from the substrate, and an N-type doped microcrystalline silicon layer, a front TCO film layer, and a second metal electrode are sequentially disposed on a side of the second intrinsic amorphous layer away from the substrate. The preparation method comprises the following steps:

[0107] (1) A first intrinsic amorphous layer is deposited on the surface and side of one side of the substrate by using the PECVD method, and a second intrinsic amorphous layer and an N-type doped microcrystalline silicon layer are deposited in sequence on the surface and side of the other side by using the PECVD method, and then a P-type doped microcrystalline silicon layer is deposited on the surface and side of the first intrinsic amorphous layer by using the PECVD method.

[0108] The chamber temperature for depositing the P-type doped microcrystalline silicon layer is set at 165°C, the corresponding actual carrier temperature is 140°C, the borane / silane doping flow ratio is 1%, the gas pressure is 3.5 torr, and the power density is 5.1 kW / m 2 , the deposition thickness is 35nm.

[0109] The temperature for depositing the N-type doped microcrystalline silicon layer is 180° C., and the deposition thickness is 15 nm.

[0110] The first intrinsic amorphous layer is deposited at a temperature of 180° C. with a thickness of 4 nm. The second intrinsic amorphous layer is deposited at a temperature of 180° C. with a thickness of 4 nm.

[0111] The substrate is a textured N-type silicon wafer.

[0112] (2) A back TCO film layer is prepared on a portion of the surface of the P-type doped microcrystalline silicon layer in step (1) using a PVD method.

[0113] (3) A front TCO film layer is prepared on the surface and side of the N-type doped microcrystalline silicon layer in step (1) using a PVD method.

[0114] The thickness of the back TCO film layer and the front TCO film layer is 150nm, and the material is ITO.

[0115] (4) In step (2), a first metal electrode is prepared by printing a pure silver paste on the surface of the back TCO film layer, and in step (3), a second metal electrode is prepared by printing a pure silver paste on the surface of the front TCO film layer, and then drying at a temperature of 200° C. and curing at a temperature of 230° C. to obtain the heterojunction battery.

[0116] Example 3

[0117] This embodiment provides a method for preparing a heterojunction battery, which includes a substrate, a first intrinsic amorphous layer disposed on the surface and side of one side of the substrate, and a second intrinsic amorphous layer disposed on the surface and side of the other side of the substrate. The first intrinsic amorphous layer is further provided with a P-type doped microcrystalline silicon layer, a back TCO film layer, and a first metal electrode in sequence on the side away from the substrate, and the second intrinsic amorphous layer is further provided with an N-type doped microcrystalline silicon layer, a front TCO film layer, and a second metal electrode in sequence on the side away from the substrate. The preparation method includes the following steps:

[0118] (1) A first intrinsic amorphous layer is deposited on the surface and side of one side of the substrate by using the PECVD method, and a second intrinsic amorphous layer and an N-type doped microcrystalline silicon layer are deposited in sequence on the surface and side of the other side by using the PECVD method, and then a P-type doped microcrystalline silicon layer is deposited on the surface and side of the first intrinsic amorphous layer by using the PECVD method.

[0119] The chamber temperature for depositing the P-type doped microcrystalline silicon layer is set at 165°C, the corresponding actual carrier temperature is 140°C, the borane / silane doping flow ratio is 1%, the gas pressure is 6 Torr, and the power density is 2.9 kW / m 2 , the deposition thickness is 15nm.

[0120] The N-type doped microcrystalline silicon layer is deposited at a temperature of 200° C. and a thickness of 30 nm.

[0121] The first intrinsic amorphous layer is deposited at a temperature of 230° C. with a thickness of 10 nm. The second intrinsic amorphous layer is deposited at a temperature of 230° C. with a thickness of 10 nm.

[0122] The substrate is a textured N-type silicon wafer.

[0123] (2) A back TCO film layer is prepared on a portion of the surface of the P-type doped microcrystalline silicon layer in step (1) using a PVD method.

[0124] (3) A front TCO film layer is prepared on the surface and side of the N-type doped microcrystalline silicon layer in step (1) using a PVD method.

[0125] The thickness of the back TCO film layer and the front TCO film layer is 50 nm, and the material is ITO.

[0126] (4) In step (2), a pure silver paste is printed on the surface of the back TCO film layer to prepare a first metal electrode, and in step (3), a pure silver paste is printed on the surface of the front TCO film layer to prepare a second metal electrode, and then the electrodes are dried at a temperature of 100° C. and cured at a temperature of 150° C. to obtain the heterojunction battery.

[0127] Example 4

[0128] This embodiment provides a method for preparing a heterojunction battery. The structural diagram of the heterojunction battery is shown in FIG. Figure 3 As shown, it includes a substrate 14, a first intrinsic amorphous layer 15 provided on the surface and side of one side of the substrate 14, and a second intrinsic amorphous layer 13 provided on the surface and side of the other side of the substrate 14. The first intrinsic amorphous layer 15 is further provided with a third intrinsic layer 19, a P-type doped microcrystalline silicon layer 16, a back TCO film layer 17 and a first metal electrode 18 in sequence on the side away from the substrate 14. The second intrinsic amorphous layer 13 is further provided with an N-type doped microcrystalline silicon layer 12, a front TCO film layer 11 and a second metal electrode 10 in sequence on the side away from the substrate 14. The preparation method includes the following steps:

[0129] (1) A first intrinsic amorphous layer 15 is deposited on the surface and side of one side of the substrate 14 by using the PECVD method, and a second intrinsic amorphous layer 13 and an N-type doped microcrystalline silicon layer 12 are sequentially deposited on the surface and side of the other side by using the PECVD method. Then, a third intrinsic layer 19 and a P-type doped microcrystalline silicon layer 16 are sequentially deposited on the surface and side of the first intrinsic amorphous layer 15 by using the PECVD method.

[0130] The chamber temperature for depositing the P-type doped microcrystalline silicon layer 16 is set at 165° C., corresponding to an actual carrier temperature of 140° C. The borane flow rate during deposition is 1% of the silane flow rate, the gas pressure is 5 Torr, and the power density is 3.6 kW / m 2 , the deposition thickness is 25nm.

[0131] The N-type doped microcrystalline silicon layer 12 is deposited at a temperature of 190° C. and has a thickness of 25 nm.

[0132] The temperature for depositing the first intrinsic amorphous layer 15 is 210°C, the deposition thickness is 6 nm, the temperature for depositing the second intrinsic amorphous layer 13 is 210°C, the thickness is 6 nm, the temperature for depositing the third intrinsic layer 19 is 210°C, the deposition pressure is 1 Torr, and the deposition power density is 0.7 kW / m 2 , with a thickness of 2nm.

[0133] The substrate 14 is a textured N-type silicon wafer.

[0134] (2) A back TCO film layer 17 is prepared on a portion of the surface of the P-type doped microcrystalline silicon layer 16 in step (1) by using a PVD method.

[0135] (3) A front TCO film layer 11 is prepared on the surface and side surfaces of the N-type doped microcrystalline silicon layer 12 in step (1) by using a PVD method.

[0136] The thickness of the back TCO film layer 17 and the front TCO film layer 11 is 100 nm and the material is ITO.

[0137] (4) In step (2), pure silver paste is printed on the surface of the back TCO film layer 17 to prepare the first metal electrode 18, and in step (3), pure silver paste is printed on the surface of the front TCO film layer 11 to prepare the second metal electrode 10, and then the mixture is dried at a temperature of 150° C. and cured at a temperature of 200° C. to obtain the heterojunction battery.

[0138] Example 5

[0139] This embodiment provides a method for preparing a heterojunction battery. The method for preparing the heterojunction battery is the same as that of Example 1, except that the temperature for depositing the P-type doped microcrystalline silicon layer in step (1) is 150° C.

[0140] Example 6

[0141] This embodiment provides a method for preparing a heterojunction battery. The method for preparing the heterojunction battery is the same as that of Example 1, except that the chamber temperature for depositing the P-type doped microcrystalline silicon layer in step (1) is set to 145°C, and the actual temperature of the corresponding carrier is 130°C.

[0142] Example 7

[0143] This embodiment provides a method for preparing a heterojunction battery. The method for preparing the heterojunction battery is the same as that of Example 1, except that the borane / silane doping flow ratio in step (1) is 0.4%.

[0144] Example 8

[0145] This embodiment provides a method for preparing a heterojunction battery. The method for preparing the heterojunction battery is the same as that of Example 1, except that the borane / silane doping flow rate ratio in step (1) is 1.6%.

[0146] Comparative Example 1

[0147] This comparative example provides a method for preparing a heterojunction battery. The method for preparing the heterojunction battery is the same as Example 1 except that the chamber temperature for depositing the P-type doped microcrystalline silicon layer in step (1) is set to 185°C and the actual temperature of the corresponding carrier is 160°C.

[0148] Comparative Example 2

[0149] This comparative example provides a method for preparing a heterojunction battery. The method for preparing the heterojunction battery is the same as that of Example 1, except that the temperature for depositing the P-type doped microcrystalline silicon layer in step (1) is 120°C.

[0150] Comparative Example 3

[0151] This comparative example provides a method for preparing a heterojunction battery. The method for preparing the heterojunction battery is the same as that in Example 1, except that step (2) firstly prepares a front TCO film layer on the surface of the N-type doped microcrystalline silicon layer by a PVD method, and then prepares a back TCO film layer on the surface of the P-type doped microcrystalline silicon layer by a PVD method.

[0152] The IV performance of the heterojunction cells obtained in the above examples and comparative examples was characterized, wherein the result measured in comparative example 1 was the BSL (baseline), and the results of the remaining examples compared therewith were shown in Table 2:

[0153] Table 2

[0154]

[0155] The thermal stability of the heterojunction cells described in the above examples and comparative examples was characterized by the following method:

[0156] The lamination process and conditions of the components were simulated, and 15 heterojunction cells were taken to test the initial electrical performance parameters of the cells. The tested cells were then placed in a heating chamber and heated at 145°C with nitrogen protective gas for 20 minutes. The cells were then taken out and the electrical performance of the cells was tested after the cells cooled. The relative attenuation values ​​of the battery electrical performance efficiency at different deposition temperatures were obtained by comparing the battery electrical performance parameters before and after heating. Relative attenuation value = (battery thermal attenuation value - battery initial value) / battery initial value × 100%. The test results are shown in Table 3:

[0157] Table 3

[0158]

[0159] The heterojunction cells described in the above examples and comparative examples were prepared into modules, and the power performance of the modules was tested. The result measured in comparative example 1 was the BSL (baseline), and the results of the remaining examples compared with it are shown in Table 4:

[0160] Table 4

[0161]

[0162] In order to compare the effects of the present invention on improving the crystallization rate of the P-type doped microcrystalline silicon layer and improving the activation energy of the microcrystalline doped layer by using the low temperature deposition of the P-type doped microcrystalline silicon layer, the crystallization rate, dark conductivity and activation energy of Comparative Example 1, Example 1 and Example 5 are shown in Table 5:

[0163] Table 5

[0164]

[0165] From Tables 2 to 5 we can see that:

[0166] (1) It can be seen from Examples 1-9 and Comparative Example 1 that the present invention reduces the temperature for depositing the P-type doped microcrystalline silicon layer, can improve the crystallization rate of the P-type doped microcrystalline silicon layer, and at the same time reduce the activation energy of the microcrystalline doped layer, thereby improving the battery efficiency. For example, the efficiency of Example 1 is improved by 0.12% rel compared with Comparative Example 1, and Rs is significantly reduced by 0.20 mΩ. It can be seen from the improvements in Rs and pFF in Table 3 that the thermal stability of the battery is improved, and the Rs attenuation is improved from 0.69 mΩ in Comparative Example 1 to 0.45 mΩ in Example 1, and the pFF attenuation is improved from -0.43% rel in Comparative Example 1 to -0.35% rel in Example 1. As can be seen from Table 4, the component power is also improved at the same time.

[0167] (2) It can be seen from Example 1 and Comparative Example 2 that the temperature of the P-type doped microcrystalline silicon layer deposited by the present invention is not easy to be too low. If it is too low, the deposition rate of the microcrystalline layer will be reduced, resulting in the thinning of the microcrystalline layer thickness, affecting the field passivation effect, and further increasing the borane doping concentration, resulting in an increase in internal defects of the film layer and thus a decrease in the dark conductivity of the film layer, thereby affecting the battery performance; It can be seen from Example 1 and Comparative Example 3 that after the present invention prepares the P-type doped microcrystalline silicon layer, it immediately prepares a back TCO film layer on part of its surface, which can better protect the pn junction on the back, improve passivation and enhance battery efficiency, and at the same time, the final plating of the front TCO film can better avoid the influence of water vapor on the TCO film, thereby improving the reliability of the battery; From Example 1 As can be seen from Example 4, Example 4 also provides a third intrinsic layer, which avoids the problem of leakage due to direct contact between the P-type doped microcrystalline silicon layer and the N-type doped microcrystalline silicon layer at the side, thereby improving the battery efficiency and avoiding current loss; in addition, it can be used as a seed layer to increase the crystallization rate of the P microcrystalline doped layer and thus reduce the series resistance Rs of the battery. At the same time, it can also improve the passivation effect of the battery and thus increase the pFF, ultimately achieving an improvement in the battery EFF; as can be seen from Example 1 and Examples 5-6, when the deposition temperature of the present invention changes, the performance will also change, and the deposition temperature is preferably 140°C; as can be seen from Examples 1 and Examples 7-8, the flow rate of the borane dopant of the present invention will affect the boron doping amount, thereby affecting the battery performance.

[0168] In summary, the present invention provides a heterojunction battery and its preparation method and application. The preparation method avoids the problem of decreased efficiency and reduced component power of the heterojunction battery after lamination by depositing a P-type doped microcrystalline silicon layer at low temperature, thereby effectively improving the efficiency, thermal stability and component power of the heterojunction battery.

[0169] The above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention fall within the protection scope and disclosure scope of the present invention.

Claims

1. A method for preparing a heterojunction battery, characterized in that: The preparation method comprises the following steps: Depositing a first intrinsic amorphous layer on one surface and side of the substrate, depositing a second intrinsic amorphous layer and an N-type doped microcrystalline silicon layer on the other surface and side in sequence, and then depositing a P-type doped microcrystalline silicon layer on the surface of the first intrinsic amorphous layer and the side of the substrate, wherein the P-type doped microcrystalline silicon layer overlaps with the N-type doped microcrystalline silicon layer on the side of the substrate; forming a back TCO film layer on a portion of the surface of the P-type doped microcrystalline silicon layer; forming a front TCO film layer on the surface and side of the N-type doped microcrystalline silicon layer; Prepare metal electrodes on the surface of the back TCO film layer and the front TCO film layer respectively; The deposition temperature of the P-type doped microcrystalline silicon layer is less than 160° C. and greater than or equal to 130° C.; The ratio of the dopant flow rate to the silane flow rate for depositing the P-type doped microcrystalline silicon layer is 0.4% to 1.6%.

2. The method for preparing a heterojunction battery according to claim 1, wherein: The deposition temperature of the P-type doped microcrystalline silicon layer is less than 160° C. and greater than or equal to 140° C.

3. The method for preparing a heterojunction battery according to claim 1 or 2, characterized in that: Before depositing the P-type doped microcrystalline silicon layer, a third intrinsic layer is deposited on the surface of the first intrinsic amorphous layer and the side of the substrate. The third intrinsic layer is located between the P-type doped microcrystalline silicon layer and the N-type doped microcrystalline silicon layer on the side of the substrate.

4. The method for preparing a heterojunction battery according to claim 1 or 2, characterized in that: The dopant for depositing the P-type doped microcrystalline silicon layer includes borane.

5. The method for preparing a heterojunction battery according to claim 1 or 2, characterized in that: The method of depositing the P-type doped microcrystalline silicon layer includes PECVD; And / or, the gas pressure for depositing the P-type doped microcrystalline silicon layer is 3.5 torr to 6 torr, and the power density is 2.9 kW / m 2 ~5.2kW / m 2 , the deposition thickness is 15nm~35nm; and / or, the method of depositing the N-type doped microcrystalline silicon layer comprises PECVD; And / or, the temperature for depositing the N-type doped microcrystalline silicon layer is 160° C. to 220° C., and the deposition thickness is 15 nm to 30 nm.

6. The method for preparing a heterojunction battery according to claim 3, wherein: The method of depositing the first intrinsic amorphous layer includes PECVD, the deposition temperature is 180° C. to 230° C., and the deposition thickness is 4 nm to 10 nm; And / or, the method of depositing the second intrinsic amorphous layer comprises PECVD, the deposition temperature is 180° C. to 230° C., and the deposition thickness is 4 nm to 10 nm; And / or, the method for depositing the third intrinsic layer includes PECVD, the deposition temperature is 180° C. to 230° C., and the deposition thickness is 0.5 nm to 5 nm.

7. The method for preparing a heterojunction battery according to claim 1 or 2, characterized in that: The method for preparing the back TCO film layer and the front TCO film layer includes PVD; And / or, the back TCO film layer includes an In-containing oxide conductive film and / or an In-free oxide conductive film, and the thickness of the back TCO film layer is 50 nm to 150 nm; And / or, the front TCO film layer includes an oxide conductive film containing In and / or an oxide conductive film not containing In, and the thickness of the front TCO film layer is 50 nm to 150 nm.

8. The method for preparing a heterojunction battery according to claim 1 or 2, characterized in that: The method for preparing the metal electrode comprises printing the metal electrode slurry, followed by drying and curing.

9. A method for preparing a heterojunction battery, characterized in that: The preparation method comprises the following steps: Depositing a first intrinsic amorphous layer on one surface and side of the substrate, depositing a second intrinsic amorphous layer and an N-type doped microcrystalline silicon layer on the other surface and side in sequence, and then depositing a P-type doped microcrystalline silicon layer on the surface of the first intrinsic amorphous layer and the side of the substrate, wherein the P-type doped microcrystalline silicon layer overlaps with the N-type doped microcrystalline silicon layer on the side of the substrate; forming a back TCO film layer on a portion of the surface of the P-type doped microcrystalline silicon layer; forming a front TCO film layer on the surface and side of the N-type doped microcrystalline silicon layer; Prepare metal electrodes on the surface of the back TCO film layer and the front TCO film layer respectively; The chamber temperature for depositing the P-type doped microcrystalline silicon layer is 145° C. to 205° C.

10. The method for preparing a heterojunction battery according to claim 9, characterized in that: The difference between the chamber temperature during the deposition of the P-type doped microcrystalline silicon layer and the deposition temperature during the deposition of the P-type doped microcrystalline silicon layer is 15° C. to 45° C.

11. A heterojunction battery, characterized in that: The heterojunction battery is prepared by the method for preparing a heterojunction battery according to any one of claims 1 to 8, or is prepared by the method for preparing a heterojunction battery according to claim 9 or 10; The heterojunction battery includes a substrate, a first intrinsic amorphous layer arranged on the surface and side of one side of the substrate, and a second intrinsic amorphous layer arranged on the surface and side of the other side of the substrate. The first intrinsic amorphous layer is further provided with a P-type doped microcrystalline silicon layer, a back TCO film layer and a metal electrode in sequence on the side away from the substrate, and the second intrinsic amorphous layer is further provided with an N-type doped microcrystalline silicon layer, a front TCO film layer and a metal electrode in sequence on the side away from the substrate.

12. A solar module, characterized in that: The solar module comprises the heterojunction cell according to claim 11.

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