Pressure sensor, manufacturing method thereof and pressure sensing assembly

Abstract

A pressure sensor comprises a substrate (100) and at least one capacitive second electrode (12) arranged on the substrate (100), the at least one second electrode (12) is provided with a release hole (121), a cavity (13) is formed between the at least one second electrode (12) and the substrate (100), and the at least one second electrode (12) surrounds the side wall of the cavity (13); the hole sealing layer (30) is arranged on the periphery of the cavity (13), and the hole sealing layer (30) covers the release hole (121) and at least part of the surface, away from the substrate (100), of the at least one second electrode (12). The invention also provides a preparation method of the pressure sensor and a pressure sensing assembly.

Description

Pressure sensor, manufacturing method thereof, and pressure sensing assembly

[0001] This application claims priority to PCT international application No. PCT / CN2023 / 141987, filed on December 26, 2023, entitled “Pressure sensor, method for manufacturing the same, and pressure sensing assembly,” the contents of which should be understood as incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to, but is not limited to, the field of sensor technology, and in particular to a pressure sensor, a manufacturing method thereof, and a pressure sensing assembly. Background Art

[0003] Pressure sensors, devices that convert pressure signals into electrical signals, are widely used in consumer electronics, medical monitoring, industrial control, automotive electronics, aerospace, and other fields. In micro-electromechanical systems (MEMS), pressure sensors can be divided into absolute pressure sensors, gauge pressure sensors, and differential pressure sensors based on the pressure value they output. Absolute pressure sensors output pressure relative to a vacuum, gauge pressure sensors output pressure after deducting atmospheric pressure, and differential pressure sensors output pressure differentials.

[0004] Absolute pressure sensors can be mainly divided into piezoresistive and capacitive types according to the signal conversion form. Among them, the technical principle of capacitive absolute pressure sensors is to use the capacitance effect to convert the pressure signal into a corresponding electrical signal, that is, a capacitor is formed by two parallel and opposite low-resistance films (upper plate and lower plate). Under the action of pressure, the upper plate is deformed, and the change in the relative distance between the upper plate and the lower plate causes the capacitance to change. Summary of the Invention

[0005] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0006] In a first aspect, the present disclosure provides a pressure sensor comprising: a substrate and at least one second electrode of a capacitor disposed on the substrate, the at least one second electrode being provided with a release hole, a cavity being formed between the at least one second electrode and the substrate, the pressure sensor further comprising: a sealing layer;

[0007] The sealing layer is disposed at the periphery of the cavity, and the sealing layer covers the release hole and at least a portion of a surface of the at least one second electrode away from the substrate.

[0008] In an exemplary embodiment, the at least one second electrode is disposed around a sidewall of the cavity;

[0009] The at least one second electrode includes: a first sub-electrode and a second sub-electrode connected to each other, wherein the first sub-electrode and the second sub-electrode are provided in the same layer;

[0010] The orthographic projection of the first sub-electrode on the substrate does not overlap with the orthographic projection of the second sub-electrode on the substrate. The first sub-electrode is arranged along the side wall of the cavity, and the second sub-electrode is arranged on the side of the cavity away from the substrate. The orthographic projection of the cavity on the substrate at least partially overlaps with the orthographic projection range of the second sub-electrode on the substrate.

[0011] In an exemplary embodiment, the substrate includes: a base and a first electrode of at least one capacitor disposed on the base, wherein an orthographic projection of the first electrode of the at least one capacitor on the base at least partially overlaps with an orthographic projection of a second sub-electrode of a second electrode of the at least one capacitor on the base;

[0012] The release hole is located on the second sub-electrode.

[0013] In an exemplary embodiment, the number of the release holes is plural, and the plurality of release holes are arranged;

[0014] Orthographic projections of at least part of the plurality of release holes on the substrate are located in an overlapping region on the substrate between the first electrode and the second electrode of the at least one capacitor.

[0015] In an exemplary embodiment, the number of the release hole is one, the second sub-electrode is divided into a peripheral area and a central area, the peripheral area is arranged around the periphery of the central area, and the release hole is located in the peripheral area of ​​the second sub-electrode;

[0016] The cavity includes: a first cavity, a second cavity, and a channel, the first cavity and the second cavity are connected through the channel, the release hole passes through the second cavity and is connected to the second cavity, an orthographic projection of the first cavity on the substrate and an orthographic projection of the release hole on the substrate do not overlap, and the orthographic projection on the substrate is located in an overlapping area of ​​the first electrode and the second electrode of the at least one capacitor on the substrate;

[0017] The width of the channel is smaller than the width of at least one of the first cavity and the second cavity, and the width of the second cavity is smaller than the width of the first cavity.

[0018] In an exemplary embodiment, the sealing layer includes: a first sealing structure, a second sealing structure, a third sealing structure, a fourth sealing structure, and a fifth sealing structure, wherein the first sealing structure, the third sealing structure, the second sealing structure, the fourth sealing structure, and the fifth sealing structure are sequentially connected;

[0019] The first sealing structure is located on a side of the second electrode away from the substrate;

[0020] The second sealing structure is located on a side of the second electrode close to the substrate;

[0021] The third sealing structure is arranged around the side wall of the release hole;

[0022] The fourth sealing structure is arranged around the side wall of the cavity;

[0023] The fifth sealing structure is located on one side of the substrate, and an orthographic projection of the fifth sealing structure on the substrate at least partially overlaps with an orthographic projection of at least a portion of a surface of the substrate close to the second electrode on the substrate.

[0024] In an exemplary embodiment, the first sealing structure includes: a first sub-sealing structure and a second sub-sealing structure, wherein the first sub-sealing structure is located at the periphery of the second sub-sealing structure and is integrally formed;

[0025] The orthographic projection of the first sub-sealing structure on the substrate at least partially overlaps with the orthographic projection of the second sub-electrode on the substrate, and the orthographic projection of the second sub-sealing structure on the substrate covers the orthographic projection of the third sealing structure on the substrate;

[0026] The thickness of the first sub-sealing structure is uniform, and the second sub-sealing structure is symmetrically arranged relative to the center line of the release hole. The thickness of the second sub-sealing structure gradually increases from the center line of the release hole to the side wall of the release hole, and the center line of the release hole is perpendicular to the substrate.

[0027] In an exemplary embodiment, the second electrode is made of a material including: one of single crystal silicon and polycrystalline silicon, and the sealing layer is made of a material including silicon oxide.

[0028] In an exemplary embodiment, the second sealing structure includes: a third sub-sealing structure and a fourth sub-sealing structure, wherein the third sub-sealing structure is located at the periphery of the fourth sub-sealing structure and is integrally formed;

[0029] The orthographic projection of the third sub-sealing structure on the substrate at least partially overlaps with the orthographic projection of the second sub-electrode on the substrate, and the orthographic projection of the fourth sub-sealing structure on the substrate covers the orthographic projection of the third sealing structure on the substrate;

[0030] The thickness of the third sub-sealing structure is uniform, and the fourth sub-sealing structure is symmetrically arranged along the center line of the release hole. The thickness of the fourth sub-sealing structure gradually increases from the center line of the release hole to the side wall of the release hole.

[0031] In an exemplary embodiment, the thickness of the third sealing structure is uniform, and the third sealing structure fills the release hole completely;

[0032] At least two of the first sub-sealing structure, the third sub-sealing structure, the third sealing structure, the fourth sealing structure, and the fifth sealing structure have the same thickness.

[0033] In an exemplary embodiment, the thickness of the third sealing structure gradually decreases from a direction away from the substrate to a direction close to the substrate, and the third sealing structure is a hollow structure and includes: a first through hole, and the second sealing structure is a hollow structure and includes: a second through hole;

[0034] The thickness of the first sub-sealing structure is greater than the thickness of at least one of the second sealing structure, the third sealing structure, the fourth sealing structure, and the fifth sealing structure;

[0035] The thickness of the third sealing structure away from the substrate is greater than the thickness of at least one of the second sealing structure, the fourth sealing structure and the fifth sealing structure;

[0036] A center line of the first through hole coincides with a center line of the second through hole, and a size of the second through hole is larger than a size of the first through hole.

[0037] In an exemplary embodiment, the second electrode is made of a material including one of single crystal silicon, polycrystalline silicon, and metal, and the sealing layer is made of a material including one of silicon nitride and silicon oxide.

[0038] In an exemplary embodiment, the thickness of the first sub-sealing structure is greater than the pore diameter of the release pore;

[0039] The thickness of the third sealing structure on a side away from the substrate is in a range from 0.25 times to 0.3 times the diameter of the release hole;

[0040] The thickness of the third sealing structure on the side close to the substrate is in a range from 0.05 times to 0.1 times the diameter of the release hole;

[0041] The thickness of at least one of the second sealing structure, the fourth sealing structure, and the fifth sealing structure is in a range from 0.05 to 0.1 times the diameter of the release hole;

[0042] The pore diameter of the release pores is in the range of 0.25 micrometers to 100 micrometers.

[0043] In an exemplary embodiment, the second electrode is made of a material selected from the group consisting of single crystal silicon, polycrystalline silicon, and metal, and the sealing layer is made of a material selected from the group consisting of silicon nitride and tetraethoxysilane.

[0044] In an exemplary embodiment, the thickness of the first sub-sealing structure is greater than 0.9 times the diameter of the release hole;

[0045] The thickness of the third sealing structure on a side away from the substrate is in a range of 0.4 to 0.5 times the diameter of the release hole;

[0046] The thickness of the third sealing structure on a side close to the substrate is in a range from 0.25 times to 0.35 times the diameter of the release hole;

[0047] The thickness of at least one of the second sealing structure, the fourth sealing structure, and the fifth sealing structure is in a range of 0.25 to 0.35 times the diameter of the release hole;

[0048] The pore size of the release pores is in the range of 0.25 μm to 2 μm.

[0049] In an exemplary embodiment, the orthographic projection of the first sealing structure on the substrate is located within the range of the orthographic projection of the cavity on the substrate;

[0050] The size of the first sealing structure is 3 to 5 times the diameter of the release hole.

[0051] In an exemplary embodiment, the method further includes: a sealing layer, the sealing layer being disposed on a side of the sealing layer away from the substrate, and having an orthographic projection on the substrate covering an orthographic projection of the first sealing structure on the substrate;

[0052] The sealing layer is made of a material selected from silicon oxide and silicon nitride. The thickness of the sealing layer is in a range from 1 / 3 to 1 / 2 of the diameter of the release hole.

[0053] In an exemplary embodiment, the orthographic projection of the sealing layer on the substrate is within the range of the orthographic projection of the cavity on the substrate, and the size of the sealing layer is within a range of 4 to 6 times the diameter of the release hole.

[0054] In an exemplary embodiment, the substrate includes: a base, a first electrode of at least one capacitor, and an insulating dielectric layer;

[0055] The first electrode is formed in the substrate and located on the surface of the substrate, and the insulating dielectric layer is located on a side of the substrate close to the second electrode.

[0056] In a second aspect, the present disclosure further provides a pressure sensing assembly, comprising: the above-mentioned pressure sensors arranged in an array.

[0057] In a third aspect, the present disclosure further provides a method for preparing a pressure sensor, which is configured to prepare the above-mentioned pressure sensor, the method comprising:

[0058] forming a substrate;

[0059] forming a sacrificial layer on the substrate;

[0060] At least one second electrode of a capacitor is formed on the sacrificial layer, and the sacrificial layer is removed to form a cavity.

[0061] In an exemplary embodiment, forming a sacrificial layer on the substrate includes:

[0062] Depositing a sacrificial film on the substrate, and processing the sacrificial film through a patterning process to form an initial sacrificial layer, wherein the sacrificial layer is made of at least one of low-temperature glass, phosphosilicate glass, silicon oxide, and silicon nitride;

[0063] The initial sacrificial layer is annealed to form a sacrificial layer.

[0064] In an exemplary embodiment, forming at least one second electrode of a capacitor on the sacrificial layer, removing the sacrificial layer, and forming a sealing layer includes:

[0065] forming at least one second electrode of a capacitor on the sacrificial layer, wherein the second electrode is provided with a release hole;

[0066] placing the substrate with the second electrode formed thereon into an etchant, wherein the etchant removes the sacrificial layer through the release hole to form a cavity;

[0067] A sealing layer is formed on the substrate having the cavity formed therein.

[0068] In an exemplary embodiment, forming a sealing layer on the substrate having the cavity formed therein includes:

[0069] A plasma enhanced chemical vapor deposition process is used to deposit silicon nitride or silicon oxide on the substrate having the cavity formed therein to form a sealing layer;

[0070] Alternatively, silicon nitride or tetraethoxysilane is deposited on the substrate with the cavity formed therein by using a low-pressure chemical vapor deposition process to form a sealing layer.

[0071] In an exemplary embodiment, after forming the sealing layer, the method further includes:

[0072] The sealing layer is etched, and a sealing layer is formed on the sealing layer.

[0073] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0074] Summary of the Figures

[0075] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0076] FIG1 is a schematic structural diagram of a pressure sensor provided by an embodiment of the present disclosure;

[0077] FIG2 is a top view of the second electrode;

[0078] FIG3A is a schematic diagram of a pressure sensor;

[0079] FIG3B is a second schematic diagram of a pressure sensor;

[0080] FIG3C is a third schematic diagram of a pressure sensor;

[0081] FIG4A is a first schematic diagram of another pressure sensor;

[0082] FIG4B is a second schematic diagram of another pressure sensor;

[0083] FIG4C is a third schematic diagram of another pressure sensor;

[0084] FIG5 is a schematic structural diagram of another pressure sensor;

[0085] FIG6 is a schematic diagram of a connection of a pressure sensor;

[0086] FIG7 is a connection diagram of another pressure sensor;

[0087] FIG8 is a schematic structural diagram of a pressure sensor including two capacitors;

[0088] FIG9A is a second structural diagram of a pressure sensor including two capacitors;

[0089] FIG9B is a third structural diagram of a pressure sensor including two capacitors;

[0090] FIG10 is a fourth structural diagram of a pressure sensor including two capacitors;

[0091] FIG11A is a fifth structural diagram of a pressure sensor including two capacitors;

[0092] FIG11B is a sixth structural diagram of a pressure sensor including two capacitors;

[0093] FIG12 is a first schematic diagram of the film layer where the second electrode of the pressure-sensing capacitor is located;

[0094] FIG13 is a second schematic diagram of the film layer where the second electrode of the pressure-sensing capacitor is located;

[0095] FIG14 is a connection diagram of another pressure sensor;

[0096] FIG15 is a first structural diagram of a pressure sensor including four capacitors;

[0097] FIG16A is a second structural diagram of a pressure sensor including four capacitors;

[0098] FIG16B is a third structural diagram of a pressure sensor including four capacitors;

[0099] FIG17 is a fourth structural diagram of a pressure sensor including four capacitors;

[0100] FIG18A is a fifth structural diagram of a pressure sensor including two capacitors;

[0101] FIG18B is a sixth structural diagram of a pressure sensor including two capacitors;

[0102] FIG19 is a top view of a conductive film layer of a pressure sensor including four capacitors;

[0103] FIG20 is a schematic diagram of one of the conductive film layers in FIG19;

[0104] FIG21 is a schematic diagram of another conductive film layer in FIG19;

[0105] FIG22 is a schematic diagram 1 of the film layer where the second electrodes of the two pressure-sensing capacitors are located;

[0106] FIG23 is a second schematic diagram of the film layer where the second electrodes of the two pressure-sensing capacitors are located;

[0107] 24a to 24h are flowcharts of manufacturing the pressure sensor provided in FIG8;

[0108] 25a to 25d are flowcharts of manufacturing the pressure sensor provided in FIG9;

[0109] 26a to 26e are flowcharts of manufacturing the pressure sensor provided in FIG10;

[0110] 27a to 27c are flowcharts of manufacturing the pressure sensor provided in FIG11;

[0111] FIG28 is a cross-sectional view of a pressure sensor provided by another embodiment of the present disclosure;

[0112] FIG29 is another cross-sectional view of a pressure sensor provided by another embodiment of the present disclosure;

[0113] FIG30 is another cross-sectional view of a pressure sensor provided by another embodiment of the present disclosure;

[0114] FIG31 is a top view of a portion of the film layers of FIG28 to FIG30;

[0115] FIG32A is a cross-sectional view of a pressure sensor provided in yet another exemplary embodiment of the present disclosure;

[0116] FIG32B is a cross-sectional view of a pressure sensor provided in yet another exemplary embodiment of the present disclosure;

[0117] FIG33A is a top view of a portion of the membrane layer of the pressure sensor provided in FIG32A;

[0118] FIG33B is a side view of the second electrode in FIG33;

[0119] FIG34 is a schematic diagram of FIG28 after forming a sacrificial layer;

[0120] FIG35 is a schematic diagram of FIG28 after forming the original second electrode;

[0121] FIG36 is a schematic diagram of FIG28 after the sacrificial layer is removed;

[0122] FIG37 is a schematic diagram of FIG28 after forming a sealing layer;

[0123] FIG38 is a schematic diagram of FIG29 or FIG30 after forming a second electrode.

[0124] Details

[0125] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0126] The scale of the drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. The drawings described in this disclosure are only schematic diagrams of the structure, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0127] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0128] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0129] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0130] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0131] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0132] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0133] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0134] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0135] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0136] Absolute pressure sensors require an independently sealed cavity, and the pressure within the cavity is typically low. The manufacturing process for absolute pressure sensors involves forming a lower plate, depositing a sacrificial layer on the lower plate, depositing an upper plate on the sacrificial layer, forming a release hole in the upper plate, etching the sacrificial layer to form a cavity, and then using thin film deposition technology to seal the release hole to form a vacuum reference cavity. The formation of this cavity requires strict control of the sacrificial layer release time and the design of a sufficient number and density of release holes, resulting in low precision control of the pressure sensor's cavity size and poor product consistency.

[0137] Figure 1 is a schematic diagram of the structure of a pressure sensor provided by an embodiment of the present disclosure. As shown in Figure 1, the pressure sensor provided by an embodiment of the present disclosure may include: a substrate 10 and at least one capacitor disposed on substrate 10, wherein one of the at least one capacitor may include: a first electrode 11 and a second electrode 12 disposed oppositely and insulated from each other, with second electrode 12 located on a side of first electrode 11 away from substrate 10, and a cavity 13 disposed between first electrode 11 and second electrode 12.

[0138] As shown in Figure 1, the orthographic projection of the first electrode 11 on the substrate 10 at least partially overlaps with the orthographic projection of the second electrode on the substrate 10, and the orthographic projection of the overlapping area of ​​the first electrode 11 and the second electrode 12 on the substrate at least partially overlaps with the orthographic projection of the cavity 13 on the substrate. That is, the orthographic projection of the first electrode 11 on the substrate 10 at least partially overlaps with the orthographic projection of the cavity 13 on the substrate 10, and the orthographic projection of the second electrode 12 on the substrate 10 at least partially overlaps with the orthographic projection of the cavity 13 on the substrate 10, so that a capacitor is formed between the first electrode 11 and the second electrode 12.

[0139] In the present disclosure, under the action of pressure, the capacitor in the pressure sensor causes the second electrode 12 to deform toward the cavity 13, and the distance between the first electrode 11 and the second electrode 12 becomes smaller. Since the capacitance value is negatively correlated with the distance between the first electrode 11 and the second electrode 12, as the distance between the first electrode 11 and the second electrode 12 becomes smaller, the capacitance value of the pressure sensor becomes larger, and the pressure value can be obtained through the correspondence between the capacitance value and the pressure value.

[0140] In an exemplary embodiment, the cavity 13 may be a sealed cavity, for example, a vacuum cavity.

[0141] In an exemplary embodiment, the cross-section of the cavity 13 may be square, rectangular, circular, or any other shape that meets design requirements, and the present disclosure does not impose any limitation thereto.

[0142] In an exemplary embodiment, as shown in FIG1 , the second electrode 12 is disposed around the cavity 13 to form a sidewall, and is at least partially disposed on the surface of the cavity 13 away from the first electrode. By disposing the second electrode 12 around the cavity 13 to form a sidewall, and at least partially surrounding the surface of the cavity 13 away from the first electrode, the second electrode can be used to define the pattern of the cavity boundary, eliminating the need to control the release time of the sacrificial layer and design a sufficient number and density of release holes. This ensures that the pattern of the cavity boundary is not affected by the release process, thereby improving the cavity size control accuracy and product consistency of the pressure sensor.

[0143] In an exemplary embodiment, as shown in FIG. 1 , the first electrode 11 may be formed within the substrate 10 and positioned on a surface of the substrate 10 .

[0144] In an exemplary embodiment, the substrate 10 may be made of a material including single crystal silicon.

[0145] In an exemplary embodiment, the present disclosure can form a first electrode by implanting ions into a substrate 10. By controlling implantation process parameters, such as power and time, the implantation depth can be controlled, thereby controlling the thickness of the first electrode. For example, the ions can include boron, phosphorus, and arsenic.

[0146] In an exemplary embodiment, the shape of the top view of the first electrode may be a square, a rectangle, a circle, or a pattern that meets design requirements, and the present disclosure does not impose any limitation on this.

[0147] The first electrode disclosed in the present invention is arranged in the substrate, which not only reduces the thickness of the pressure sensor, but also avoids the deposition of a conductive film used to form the first electrode. The first electrode is formed by a patterning process, which simplifies the preparation steps of the pressure sensor and reduces the production cost.

[0148] 1 , the pressure sensor may further include an insulating dielectric layer 20 disposed between the first electrode 11 and the second electrode 12 of the at least one capacitor. The insulating dielectric layer 20 serves as an insulating layer between the first electrode 11 and the second electrode 12.

[0149] In an exemplary embodiment, the insulating dielectric layer 20 may be made of an insulating material that is non-reactive with the etchant of the sacrificial layer. For example, the insulating dielectric layer 20 may be made of silicon nitride or silicon oxide.

[0150] In an exemplary embodiment, the sacrificial layer may be made of silicon oxide, low-temperature glass, polysilicon, or phosphosilicate glass. When the sacrificial layer is made of low-temperature glass or phosphosilicate glass, the etchant for the sacrificial layer may include an aqueous solution of hydrogen fluoride. When the sacrificial layer is made of polysilicon, the etchant for the sacrificial layer may be an aqueous solution of potassium hydroxide or an aqueous solution of tetramethylammonium hydroxide.

[0151] For example, when the insulating dielectric layer is made of silicon nitride, the insulating dielectric layer is etched to form the cavity, and the sacrificial layer may be made of at least one of low-temperature glass, polysilicon, and phosphosilicate glass.

[0152] Figure 2 is a top view of the second electrode. As shown in Figure 2, the second electrode 12 is provided with a release hole array 120. Release hole array 120 includes release holes 121 arranged in an array. The orthographic projection of release hole array 120 on the substrate is within the range of the orthographic projection of the cavity on the substrate.

[0153] In an exemplary embodiment, the top view of the second electrode may be in the shape of a square, a rectangle, a circle, or any other shape that meets design requirements, and this disclosure does not impose any limitation thereto. FIG2 takes a rectangle as an example.

[0154] In an exemplary embodiment, the number of release holes in the release hole array and the distance between the release holes can control the speed of cavity formation, which is specifically determined according to the process of the pressure sensor and is not limited in this disclosure.

[0155] In an exemplary embodiment, the release hole array provided on the second electrode can not only form a cavity but also prevent a decrease in the yield of the pressure sensor caused by an excessively large cross-sectional area of ​​the second electrode.

[0156] 1 and 2 , the orthographic projection of the release hole array 120 on the substrate 10 is within the range of the orthographic projection of the cavity 13 on the substrate 10 . The etchant of the sacrificial layer can be released through the release holes 121 .

[0157] 1 , the pressure sensor may further include a sealing layer 30, which is at least partially located on a side of the second electrode 12 of the at least one capacitor away from the substrate 10. The sealing layer 30 may make the cavity 13 a sealed cavity.

[0158] In an exemplary embodiment, as shown in FIG1 , the orthographic projection of the cavity 13 of at least one capacitor on the substrate 10 is located within the orthographic projection of the sealing layer 30 on the substrate 10, and the sealing layer 30 at least partially fills the release hole 121. For example, the sealing layer 30 may cover the substrate 10.

[0159] In an exemplary embodiment, the sealing layer 30 may be made of a material including at least one of silicon oxide and silicon nitride.

[0160] In an exemplary embodiment, FIG3A is a schematic diagram of a pressure sensor, FIG3B is a schematic diagram of a pressure sensor, FIG4A is a schematic diagram of another pressure sensor, and FIG4B is a schematic diagram of another pressure sensor. As shown in FIG3A, FIG3B, FIG4A, and FIG4B, the boundary of the cavity 13 is in contact with the insulating dielectric layer 20, the second electrode 22, and the sealing layer 30. That is, the insulating dielectric layer 20 serves as the lower boundary of the cavity 13, a portion of the second electrode 12 serves as the side boundary of the cavity 13, and another portion of the second electrode 12 and the sealing layer filled in the release hole serve as the upper boundary of the cavity 13. FIG3A illustrates an example in which the entire area of ​​the release hole is filled with the sealing layer. FIG3B illustrates an example in which a portion of the release hole is filled with the sealing layer. The boundary of the cavity in FIG3A and FIG3B is determined by the shape of the second electrode.

[0161] In an exemplary embodiment, FIG3C is a third schematic diagram of a pressure sensor, and FIG4C is a third schematic diagram of another pressure sensor. As shown in FIG3C and FIG4C , the sealing layer 30 may include: a first sealing structure 30A and a second sealing structure 30B. The first sealing structure 30A and the second sealing structure 30B may be an integral structure. The first sealing structure 30A is located on the side of the second electrode 12 away from the substrate 10 and at least partially fills the release hole. The orthographic projection of the cavity 13 of at least one capacitor on the substrate 10 is located within the orthographic projection of the first sealing structure 30A on the substrate 10; illustratively, the first sealing structure 30A may cover the substrate 10.

[0162] In an exemplary embodiment, as shown in Figures 3C and 4C , second sealing structure 30B is located between second electrode 12 and insulating dielectric layer 20, and cavity 13 is formed within second sealing structure 30B. The boundary of the second sealing structure is defined by second electrode 12, while the boundary of cavity 13 is defined by the boundary of second sealing structure 30B. In other words, the boundary of cavity 13 is defined by second electrode 12.

[0163] In an exemplary embodiment, as shown in FIG1 and FIG3A to FIG3C , the second electrode 12 may include a first sub-electrode 12A and a second sub-electrode 12B. The first sub-electrode 12A and the second sub-electrode 12B are disposed in the same layer and formed using the same patterning process. The orthographic projection of the first sub-electrode 12A on the substrate 10 does not overlap with the orthographic projection of the second sub-electrode 12B on the substrate 10.

[0164] In an exemplary embodiment, as shown in Figures 1 and 3A to 3C, the first sub-electrode 12A is arranged around the side wall of the cavity 13, the second sub-electrode 12B is arranged on the side of the cavity away from the substrate 10, the orthographic projection of the cavity 13 on the substrate 10 and the orthographic projection of the second sub-electrode 12B on the substrate 10 at least partially overlap, and the release hole array is arranged on the second sub-electrode 12B.

[0165] In an exemplary embodiment, the pressure sensor provided in Figures 3A to 3C also includes: a first conductive layer and a second conductive layer, the first conductive layer includes at least: a first electrode of at least one capacitor, the second conductive layer includes at least: a second electrode of at least one capacitor, the first conductive layer is located on a side of the insulating dielectric layer close to the substrate, the second conductive layer is located on a side of the cavity away from the substrate, and the second conductive layer is at least partially in direct contact with the insulating dielectric layer.

[0166] 4A to 4C , the pressure sensor may further include a second dielectric layer 14 , and the second electrode 12 may include a first sub-connection portion 12C and a second sub-connection portion 12D. The second dielectric layer 14 is located on a side of the second electrode 12 close to the substrate 10 .

[0167] In an exemplary embodiment, as shown in Figures 4A to 4C, the orthographic projection of the second dielectric layer 14 on the substrate 10 at least partially overlaps with the orthographic projection of the second electrode 12 on the substrate 10, the second dielectric layer 14 is arranged around the sidewall of the cavity 13, the second electrode 12 is arranged on the side of the cavity 13 away from the substrate 10, the orthographic projection of the first sub-connector 12C on the substrate 10 at least partially overlaps with the orthographic projection of the second dielectric layer 14 on the substrate 10, the orthographic projection of the cavity 13 on the substrate 10 at least partially overlaps with the orthographic projection of the second sub-connector 12D on the substrate 10, and the release hole array is arranged on the second sub-connector 12D.

[0168] In an exemplary embodiment, the pressure sensor provided in Figures 4A to 4C also includes: a first conductive layer, a second conductive layer and a third conductive layer, the first conductive layer includes at least: a first electrode of at least one capacitor, the second conductive layer includes at least: a first sub-electrode of the second electrode of at least one capacitor, the third conductive layer includes at least: a second sub-electrode of the second electrode of at least one capacitor, the first conductive layer is located on a side of the insulating dielectric layer close to the substrate, the second conductive layer is arranged around the cavity to form a sidewall, and is located on a side of the insulating dielectric layer away from the substrate, and the third conductive layer is located on a side of the second conductive layer away from the substrate.

[0169] In an exemplary embodiment, the material of the first electrode 11 may include single crystal silicon doped with ions, and the ions include boron, phosphorus, and arsenic.

[0170] In an exemplary embodiment, the second electrode 12 may be made of a material including low-resistance polysilicon or metal.

[0171] In an exemplary embodiment, as shown in FIG. 3A to FIG. 3C , the pressure sensor may further include: a plurality of pads, the plurality of pads being located on a side of the sealing layer 30 away from the substrate 10 , the plurality of pads being respectively connected to a first electrode and a second electrode of at least one capacitor.

[0172] In an exemplary embodiment, the material of the plurality of pads may include aluminum or gold.

[0173] The provision of the pad layer in the present disclosure can realize the input and detection of the pressure sensor signal without the need to flatten the surface away from the sealing layer 30, thereby greatly reducing the process steps and improving the yield of the pressure sensor.

[0174] In an exemplary embodiment, Figure 5 is a schematic diagram of the structure of another pressure sensor. As shown in Figure 5, the pressure sensor may further include an adhesive layer 50, the adhesive layer including a plurality of adhesive structures. The sealing layer defines a plurality of grooves, the plurality of adhesive structures corresponding one-to-one with the plurality of grooves and one-to-one with the plurality of pads. The adhesive structures are disposed within the corresponding grooves and connected to the corresponding pads and the electrodes to which they are connected.

[0175] In an exemplary embodiment, an orthographic projection of at least one adhesive structure on the substrate coincides with an orthographic projection of a corresponding pad on the substrate.

[0176] In an exemplary embodiment, the adhesion layer 50 may include a conductive film layer, and the resistivity of the material making the adhesion layer may be greater than the resistivity of the material making the pads. The provision of the adhesion layer in the present disclosure can improve the stability of the multiple pads and the connected electrodes, thereby improving the reliability of the pressure sensor.

[0177] In an exemplary embodiment, the adhesion layer may be made of a metal. For example, the adhesion layer may be made of titanium, chromium, or tantalum.

[0178] Figure 6 is a schematic diagram of a pressure sensor connection. In this exemplary embodiment, the at least one capacitor in the pressure sensor includes a pressure-sensing capacitor FC, meaning the pressure sensor includes only one pressure-sensing capacitor. The second electrode in the pressure-sensing capacitor deforms under pressure, and one of the first and second electrodes 11, 12 in the pressure-sensing capacitor is connected to interface K1, while the other of the first and second electrodes 11, 12 in the pressure-sensing capacitor is connected to interface K2.

[0179] In an exemplary embodiment, a DC voltage signal or an AC voltage signal is input to one of the interfaces K1 or K2, and a pressure-sensitive capacitance signal is detected at one of the interfaces K1 or K2. The pressure sensor can obtain a pressure value based on the pressure-sensitive capacitance signal.

[0180] In the exemplary embodiment, Figures 3A to 3C and 4A to 4C illustrate a pressure sensor including a single pressure-sensing capacitor. As shown in Figures 3A to 3C and 4A to 4C, when the pressure sensor includes a single pressure-sensing capacitor, the multiple pads may include a first pad P11 and a second pad P12. First pad P11 is connected to first electrode 11 of the pressure-sensing capacitor, and second pad P12 is connected to second electrode 12 of the pressure-sensing capacitor.

[0181] In an exemplary embodiment, when the first electrode 11 in the pressure-sensing capacitor is connected to the interface K1 and the second electrode 12 in the pressure-sensing capacitor is connected to the interface K2, the first pad P11 serves as the interface K1 and the second pad P12 serves as the interface K2; or when the first electrode 11 in the pressure-sensing capacitor is connected to the interface K2 and the second electrode 12 in the pressure-sensing capacitor is connected to the interface K1, the first pad P11 serves as the interface K2 and the second pad P12 serves as the interface K1.

[0182] Taking into account the inherent large parasitic capacitance of a single pressure-sensing capacitor and its significant influence on packaging stress, the at least one capacitor in the pressure sensor of the present disclosure may further include: at least one pressure-sensing capacitor and at least one reference capacitor. The deformation rate of the second electrode of the reference capacitor under the action of pressure is 0.1% to 0.3% of the deformation rate of the pressure-sensing capacitor under the action of pressure, that is, the second electrode of the pressure-sensing capacitor is deformed under the action of pressure, and the second electrode of the reference capacitor is basically not deformed under the action of pressure. The present disclosure offsets the parasitic capacitance of the pressure-sensing capacitor through the parasitic capacitance of the reference capacitor, which can improve the detection accuracy of the pressure sensor. Exemplarily, the at least one capacitor may include: a pressure-sensing capacitor and a reference capacitor, or the at least one capacitor includes: two pressure-sensing capacitors and two reference capacitors. The present disclosure does not impose any limitation on this.

[0183] In an exemplary embodiment, the number of release holes included in the release hole array of the second electrode of the pressure-sensing capacitor and the number of release holes included in the release hole array of the second electrode of the reference capacitor can be the same, or the number of release holes included in the release hole array of the second electrode of the pressure-sensing capacitor can be greater than the number of release holes included in the release hole array of the second electrode of the reference capacitor.

[0184] In an exemplary embodiment, a first electrode of at least one pressure-sensing capacitor and a first electrode of at least one reference capacitor are disposed on the same layer, and a second electrode of at least one pressure-sensing capacitor and a second electrode of at least one reference capacitor are disposed on the same layer.

[0185] In an exemplary embodiment, the at least one capacitor in the pressure sensor may further include: at least one pressure-sensing capacitor and at least one reference capacitor, which can minimize the size of the pressure sensor while not increasing the number of process steps.

[0186] Figure 7 is a schematic diagram of another pressure sensor connection. As shown in Figure 7, when the at least one capacitor includes a pressure-sensing capacitor FC and a reference capacitor RC, the pressure-sensing capacitor FC and the reference capacitor RC are connected in series. Specifically, the first electrode 21 of the pressure-sensing capacitor FC and the first electrode 31 of the reference capacitor RC are connected to interface K2, the second electrode 22 of the pressure-sensing capacitor FC is connected to interface K1, and the second electrode 32 of the reference capacitor RC is connected to interface K3. A DC voltage signal or an AC voltage signal is input to interfaces K1 and K3, and the pressure-sensing capacitor signal is detected at interfaces K1 and K2. According to the principle of charge conservation, the charge Q of the pressure-sensing capacitor FC and the reference capacitor RC is equal. The voltage output by the pressure-sensing capacitor FC satisfies U = Q / C, where C is the capacitance of the pressure-sensing capacitor FC. Under pressure, the second electrode 22 of the pressure-sensing capacitor FC deforms, while the second electrode 32 of the reference capacitor RC remains substantially unchanged. This increases the capacitance of the pressure-sensing capacitor FC and reduces the voltage between interfaces K1 and K2, which are connected to the pressure-sensing capacitor FC, thereby reflecting the magnitude of the pressure. The pressure sensor includes: a pressure-sensing capacitor and a reference capacitor connected in series, which can make the parasitic capacitance of the reference capacitor and the parasitic capacitance of the pressure-sensing capacitor cancel each other out, and the stress introduced by the sealing layer applied to the reference capacitor and the pressure-sensing capacitor with basically the same processing technology, causing the capacitance changes to cancel each other out, thereby improving the product stability and measurement accuracy of the pressure sensor.

[0187] FIG8 is a schematic diagram of the structure of a pressure sensor including two capacitors, FIG9A is a schematic diagram of the structure of a pressure sensor including two capacitors, FIG9B is a schematic diagram of the structure of a pressure sensor including two capacitors, FIG10 is a schematic diagram of the structure of a pressure sensor including two capacitors, FIG11A is a schematic diagram of the structure of a pressure sensor including two capacitors, and FIG11B is a schematic diagram of the structure of a pressure sensor including two capacitors. As shown in FIG8, FIG9A, FIG9B, FIG10, FIG11A and FIG11B, when there is one pressure-sensing capacitor and one reference capacitor, the plurality of pads include: a first pad P21, a second pad P22 and a third pad P23. The first pad P21 is connected to the second electrode 22 of the pressure-sensing capacitor FC, the second pad P22 is connected to the second electrode 32 of the reference capacitor RC, and the third pad P23 is connected to the first electrode 21 of the pressure-sensing capacitor FC and the first electrode 31 of the reference capacitor RC. Figures 8 and 9A are explained using the structure of the capacitor as Figure 3A as an example, and Figure 9B is explained using the structure of the capacitor as Figure 3C as an example. The structure of the capacitor can also be as shown in Figure 3B. Figures 10 and 11A are explained using the structure of the capacitor as Figure 4A as an example, and Figure 11B is explained using the structure of the capacitor as Figure 4C as an example. The structure of the capacitor can also be as shown in Figure 4B. The present disclosure does not impose any limitations on this.

[0188] In an exemplary embodiment, the first pad 21 serves as the interface K1 , the second pad 22 serves as the interface K3 , and the third pad serves as the interface K2 .

[0189] In an exemplary embodiment, the first electrode 21 of the pressure-sensing capacitor FC and the first electrode 31 of the reference capacitor RC are integrally implanted but spatially isolated. The first electrode 21 of the pressure-sensing capacitor FC and the first electrode 31 of the reference capacitor RC may be connected via a pad metal wire.

[0190] In an exemplary embodiment, sealing layer 30 defines a via hole exposing second electrode 22 of pressure-sensing capacitor FC and a via hole exposing second electrode 32 of reference capacitor RC. First pad P21 is connected to second electrode 22 of pressure-sensing capacitor FC via the via hole exposing second electrode 22 of pressure-sensing capacitor FC, and second pad P22 is connected to second electrode 32 of reference capacitor RC via the via hole exposing second electrode 32 of reference capacitor RC.

[0191] In the exemplary embodiment, vias exposing the first electrode 21 of the pressure-sensing capacitor FC and the first electrode 31 of the reference capacitor RC are formed in the dielectric layer 20 and the sealing layer 30. The third pad P23 is connected to the first electrode 21 of the pressure-sensing capacitor FC and the first electrode 31 of the reference capacitor RC through the vias exposing the first electrode 21 of the pressure-sensing capacitor FC and the first electrode 31 of the reference capacitor RC.

[0192] In order to ensure that the second electrode of the pressure-sensing capacitor deforms under pressure while the second electrode of the reference capacitor remains substantially unchanged under pressure, as shown in Figures 8 and 10, the pressure sensor may further include: a pressure-resistant layer 60, which is located on the side of the plurality of pads away from the substrate 10 and covers the substrate 10. The orthographic projection of at least one reference capacitor on the substrate is within the orthographic projection of the pressure-resistant layer 60 on the substrate 10. The pressure-resistant layer 60 is provided with at least one pressure-sensing hole exposing the sealing layer 30, and the at least one pressure-sensing hole corresponds one-to-one with at least one pressure-sensing capacitor, that is, the pressure-resistant layer in the present disclosure may include a pressure-sensing hole K, the orthographic projection of the pressure-sensing hole K on the substrate 10 at least partially overlapping with the orthographic projection of the second electrode 22 of the pressure-sensing capacitor FC on the substrate 10. The provision of the pressure-sensing hole K in the present disclosure can enable the second electrode 22 of the pressure-sensing capacitor FC to deform under pressure, while the provision of the pressure-resistant layer 60 can ensure that the second electrode 32 of the reference capacitor RC remains substantially unchanged under pressure.

[0193] In an exemplary embodiment, the thickness of the pressure-resistant layer 60 may be greater than the thickness of the cavity of the at least one capacitor.

[0194] In an exemplary embodiment, the material of the stress-resistant layer 60 may include at least one of silicon oxide or silicon nitride.

[0195] In an exemplary embodiment, the pressure sensors provided in Figures 5, 8, and 10 may further include a covering layer 70, wherein the orthographic projection of the covering layer 70 on the substrate covers the orthographic projection of the cavity on the substrate. Figure 5 does not show the covering layer, but Figures 8 and 10 do.

[0196] In an exemplary embodiment, the covering layer 70 can serve as an etching stop layer when forming the pressure-sensitive hole, thereby avoiding damage to the sealing layer when forming the pressure-sensitive hole. The covering layer 70 can also serve as a part of the sealing layer to increase the thickness of the sealing layer, thereby improving the airtightness of the cavity.

[0197] In an exemplary embodiment, the capping layer 70 may be made of a material including polysilicon or metal.

[0198] In an exemplary embodiment, as shown in FIG8 , the pressure-resistant layer 60 further defines a plurality of pad holes that expose a plurality of pads. The plurality of pad holes include a first pad hole V11, a second pad hole V12, and a third pad hole V13. The first pad hole V11 exposes the first pad P21, the second pad hole V12 exposes the second pad P22, and the third pad hole V13 exposes the third pad P23.

[0199] In an exemplary embodiment, Figure 12 is a first schematic diagram of the film layer where the second electrode of the pressure-sensing capacitor is located. As shown in Figure 12, the number of release holes included in the release hole array 220 of the second electrode 22 of the pressure-sensing capacitor FC is the same as the number of release holes included in the release hole array 220 of the second electrode 32 of the reference capacitor RC. For example, the number and arrangement of release holes 221 included in the release hole array of the second electrode 22 of the pressure-sensing capacitor FC is the same as the number and arrangement of release holes 321 included in the release hole array of the second electrode 32 of the reference capacitor RC. Figure 12 is a schematic diagram of the film layer where the second electrode of the pressure-sensing capacitor is located when the pressure sensor includes a pressure-resistant layer.

[0200] In order to achieve deformation of the second electrode of the pressure-sensing capacitor under the action of pressure, while the second electrode of the reference capacitor is basically not deformed under the action of pressure, as shown in Figures 9A, 9B, 11A and 11B, the reference capacitor may further include: a support structure 34, which is arranged between the second electrode 32 of the reference capacitor RC and the insulating dielectric layer 20. The orthographic projection of the support structure 34 on the substrate 10 overlaps with the orthographic projection of the second electrode 32 of the reference capacitor RC on the substrate 10, and the cavity 33 of the reference capacitor RC is arranged around the support structure 34. The present disclosure achieves deformation of the pressure-sensing capacitor FC under the action of pressure, while the reference capacitor RC does not deform under the action of pressure by providing the support structure 34 in the reference capacitor RC and not providing the support structure in the pressure-sensing capacitor FC.

[0201] In an exemplary embodiment, as shown in FIG9A and FIG11A , when the capacitor structure is as shown in FIG3A , FIG3B , FIG4A and FIG4B , the sealing layer is not disposed around the sidewall of the support structure of the reference capacitor.

[0202] In an exemplary embodiment, as shown in FIG. 9B and FIG. 11B , when the capacitor structure is as shown in FIG. 3C or FIG. 4C , the second sealing structure of the sealing layer is disposed around the sidewall of the support structure of the reference capacitor.

[0203] In an exemplary embodiment, the support structure 34 and the cavity of the reference capacitor RC are formed using the same process, and the support structure 34 is a sacrificial layer that is not corroded. The support structure 34 is made of materials including silicon oxide, low-temperature glass, phosphosilicate glass, or polysilicon.

[0204] In an exemplary embodiment, Figure 13 is a second schematic diagram of the film layer where the second electrode of the pressure-sensing capacitor is located. As shown in Figure 13, the number of release holes 221 included in the release hole array 220 of the second electrode 22 of the pressure-sensing capacitor FC is greater than the number of release holes 321 included in the release hole array 220 of the second electrode 32 of the reference capacitor RC. This allows the sacrificial layer in the pressure-sensing capacitor FC to be etched away during the same period of time, while the sacrificial layer in the reference capacitor RC is not completely etched. The unetched portion serves as a support structure 34 to support the second electrode of the reference capacitor RC, ensuring that the reference capacitor RC remains substantially unchanged under pressure. Figure 13 is a schematic diagram of the film layer where the second electrode of the pressure-sensing capacitor is located when the reference capacitor includes a support structure.

[0205] In an exemplary embodiment, in order to achieve deformation of the second electrode of the pressure-sensing capacitor under the action of pressure and the basic non-deformation of the second electrode of the reference capacitor under the action of pressure, when the pressure sensor may include a pressure-resistant layer, the reference capacitor may also include a support structure 34.

[0206] FIG14 is a connection diagram of another pressure sensor. As shown in FIG14 , when the at least one capacitor includes two pressure-sensing capacitors and two reference capacitors, the two pressure-sensing capacitors and the two reference capacitors can be connected in series and parallel to form a Wheatstone bridge. The two pressure-sensing capacitors are a first pressure-sensing capacitor FC1 and a second pressure-sensing capacitor FC2, and the two reference capacitors are a first reference capacitor RC1 and a second reference capacitor RC2. The second electrode 42 of the first pressure-sensing capacitor FC1 and the second electrode 52 of the first reference capacitor RC1 are respectively connected to interface K1. The first electrode 41 of the first pressure-sensing capacitor FC1 and the first electrode 71 of the second reference capacitor RC2 are respectively connected to interface K2. The second electrode 62 of the second pressure-sensing capacitor FC2 and the second electrode 72 of the second reference capacitor RC2 are respectively connected to interface K3. The first electrode 61 of the second pressure-sensing capacitor FC2 and the first electrode 51 of the first reference capacitor RC1 are respectively connected to interface K4. A DC voltage signal or an AC voltage signal is input to interface K1 and interface K3, and the pressure-sensing capacitor signals are detected at interfaces K2 and K4. The signal strength of the pressure-sensitive capacitor signal detected by the pressure sensor including two pressure-sensitive capacitors and two reference capacitors is twice the signal strength of the pressure-sensitive capacitor signal detected by the pressure sensor including one pressure-sensitive capacitor and one reference capacitor, that is, the detection sensitivity of the pressure sensor including two pressure-sensitive capacitors and two reference capacitors is significantly higher than the detection sensitivity of the pressure sensor including one pressure-sensitive capacitor and one reference capacitor. The pressure sensor including two pressure-sensitive capacitors and two reference capacitors has better measurement accuracy and better product stability. Since multiple capacitors are only connected to four interfaces, the difficulty of signal processing is further reduced.

[0207] Figure 15 is a schematic diagram of the structure of a pressure sensor including four capacitors, Figure 16A is a schematic diagram of the structure of a pressure sensor including four capacitors, Figure 16B is a schematic diagram of the structure of a pressure sensor including four capacitors, Figure 17 is a schematic diagram of the structure of a pressure sensor including four capacitors, Figure 18A is a schematic diagram of the structure of a pressure sensor including four capacitors, Figure 18B is a schematic diagram of the structure of a pressure sensor including four capacitors, and Figure 19 is a top view of the conductive film layer of the pressure sensor including four capacitors. Figures 15, 16A, and 16B are cross-sectional views of Figure 19 along the AA direction. As shown in Figures 15, 16A, 16B, and 19, in an exemplary embodiment, when the number of pressure-sensing capacitors is two and the number of reference capacitors is two, the multiple pads include: a first pad P31, a second pad P32, a third pad P33, and a fourth pad P44. The first pad P31 is connected to the second electrode 42 of the first pressure-sensing capacitor FC1 and the second electrode 52 of the first reference capacitor RC1, respectively. The second pad P32 is connected to the second electrode 62 of the second pressure-sensing capacitor FC2 and the second electrode 72 of the second reference capacitor RC2, respectively. The third pad P33 is connected to the first electrode 41 of the first pressure-sensing capacitor FC1 and the first electrode 72 of the second reference capacitor RC2, respectively. The fourth pad P34 is connected to the first electrode 51 of the first reference capacitor RC1 and the first electrode 61 of the second pressure-sensing capacitor FC2, respectively. Figures 15 and 16A are described using the structure of the capacitor as Figure 3A as an example, and Figure 16B is described using the structure of the capacitor as Figure 3C as an example. The structure of the capacitor can also be Figure 3B. Figures 17 and 18A are described using the structure of the capacitor as Figure 4A as an example, and Figure 18B is described using the structure of the capacitor as Figure 4C as an example. The structure of the capacitor can also be Figure 4B. The present disclosure does not impose any limitations on this. In an exemplary embodiment, the second electrodes of the two reference capacitors and the two pressure-sensing capacitors are provided with a release hole array. To simplify FIG. 19 , FIG. 19 does not show the release hole array.

[0208] In an exemplary embodiment, the first pad P31 serves as the interface K1 , the second pad P32 serves as the interface K3 , the third pad P33 serves as the interface K2 , and the fourth pad P34 serves as the interface K4 .

[0209] In an exemplary embodiment, as shown in FIG19 , the first pressure-sensing capacitor FC1, the second reference capacitor RC2, the first reference capacitor RC1, and the second pressure-sensing capacitor FC2 are arranged along a first direction D1. Exemplarily, the first pressure-sensing capacitor FC1, the second reference capacitor RC2, the first reference capacitor RC1, and the second pressure-sensing capacitor FC2 are arranged in sequence along the first direction D1, but this disclosure does not impose any limitation on this.

[0210] In an exemplary embodiment, Figure 20 is a schematic diagram of one of the conductive film layers in Figure 19 . As shown in Figure 20 , the first electrode 41 of the first pressure-sensing capacitor FC1 and the first electrode 71 of the second reference capacitor RC2 are integrally implanted but spatially separated. The first electrode 41 of the first pressure-sensing capacitor FC1 and the first electrode 71 of the second reference capacitor RC2 are connected via a pad metal lead. The first electrode 61 of the second pressure-sensing capacitor FC2 and the first electrode 51 of the first reference capacitor RC1 are integrally implanted but spatially separated. The first electrode 61 of the second pressure-sensing capacitor FC2 and the first electrode 51 of the first reference capacitor RC1 are connected via a pad metal lead.

[0211] In an exemplary embodiment, Figure 21 is a schematic diagram of another conductive film layer in Figure 19. As shown in Figure 21, the second electrode 42 of the first pressure-sensing capacitor FC1, the second electrode 62 of the second pressure-sensing capacitor FC2, the second electrode 52 of the first reference capacitor RC1, and the second electrode 72 of the second reference capacitor RC2 are provided separately.

[0212] In an exemplary embodiment, as shown in Figures 20 and 21, the first and second electrodes of at least one capacitor each include a main portion and a connecting portion. The main portion is rectangular in shape, and the connecting portion is located on one side of the main portion and connected to the main portion. The area of ​​the connecting portion is smaller than that of the main portion. The orthographic projection of the main portion of the first electrode 41 of the first pressure-sensing capacitor FC1 on the substrate at least partially overlaps with the orthographic projection of the main portion of the second electrode 42 of the first pressure-sensing capacitor FC1 on the substrate. The orthographic projection of the main portion of the first electrode 61 of the second pressure-sensing capacitor FC2 on the substrate at least partially overlaps with the orthographic projection of the main portion of the second electrode 62 of the second pressure-sensing capacitor FC2 on the substrate. The orthographic projection of the main portion of the first electrode 51 of the first reference capacitor RC1 on the substrate at least partially overlaps with the orthographic projection of the main portion of the second electrode 52 of the first reference capacitor RC1 on the substrate. The orthographic projection of the main portion of the first electrode 71 of the second reference capacitor RC2 on the substrate at least partially overlaps with the orthographic projection of the main portion of the second electrode 72 of the second reference capacitor RC2 on the substrate.

[0213] In an exemplary embodiment, the sealing layer 30 is provided with a via hole exposing the second electrode 42 of the first pressure-sensing capacitor FC, a via hole exposing the second electrode 62 of the second pressure-sensing capacitor FC2, a via hole exposing the second electrode 52 of the first reference capacitor RC1, and a via hole exposing the second electrode 72 of the second reference capacitor RC2. The first pad P31 is connected to the second electrode 42 of the first pressure-sensing capacitor FC1 through the via hole exposing the second electrode 42 of the first pressure-sensing capacitor FC, and is connected to the second electrode 52 of the first reference capacitor RC1 through the via hole exposing the second electrode 52 of the first reference capacitor RC1. The second pad P32 is connected to the second electrode 62 of the second pressure-sensing capacitor FC2 through the via hole exposing the second electrode 62 of the second pressure-sensing capacitor FC2, and is connected to the second electrode 72 of the second reference capacitor RC2 through the via hole exposing the second electrode 72 of the second reference capacitor RC2.

[0214] In an exemplary embodiment, the sealing layer 30 and the dielectric layer 20 are provided with a via hole exposing the integral structure of the first electrode 41 of the first pressure-sensing capacitor FC1 and the first electrode 72 of the second reference capacitor RC2, and a via hole exposing the integral structure of the first electrode 51 of the first reference capacitor RC1 and the first electrode 61 of the second pressure-sensing capacitor FC2. The third pad P33 is connected to the first electrode 41 of the first pressure-sensing capacitor FC1 and the first electrode 72 of the second reference capacitor RC2 via the integral structure of the via hole exposing the first electrode 41 of the first pressure-sensing capacitor FC1 and the first electrode 72 of the second reference capacitor RC2. The fourth pad P34 is connected to the first electrode 51 of the first reference capacitor RC1 and the first electrode 61 of the second pressure-sensing capacitor FC2 via the integral structure of the via hole exposing the first electrode 41 of the first pressure-sensing capacitor FC1 and the first electrode 72 of the second reference capacitor RC2.

[0215] To ensure that the second electrode 42 of the first pressure-sensing capacitor FC1 and the second electrode 62 of the second pressure-sensing capacitor FC2 deform under pressure, while the second electrode 52 of the first reference capacitor RC1 and the second electrode 72 of the second reference capacitor RC2 remain substantially unchanged under pressure, the pressure sensor may further include a pressure-resistant layer 60, as shown in Figures 15 and 17. The pressure-resistant layer 60 is located on a side of the sealing layer away from the substrate 10 and covers the substrate 10. The pressure-resistant layer 60 is provided with at least one pressure-sensitive hole that exposes the sealing layer 30. As shown in Figures 15 and 17, the at least one pressure-sensitive hole includes a first pressure-sensitive hole K1 and a second pressure-sensitive hole K2. The orthographic projection of the first pressure-sensitive hole K1 on the substrate 10 at least partially overlaps with the orthographic projection of the second electrode 42 of the first pressure-sensing capacitor FC1 on the substrate 10. The orthographic projection of the second pressure-sensitive hole K2 on the substrate 10 at least partially overlaps with the orthographic projection of the second electrode 62 of the second pressure-sensing capacitor FC2 on the substrate 10. The setting of the first pressure-sensing hole K1 and the second pressure-sensing hole K2 in the present disclosure can make the second electrode 42 of the first pressure-sensing capacitor and the second electrode 62 of the second pressure-sensing capacitor deform under the action of pressure, and the setting of the pressure-resistant layer 60 can make the second electrode 52 of the first reference capacitor and the second electrode 72 of the second reference capacitor basically not deformed under the action of pressure.

[0216] In an exemplary embodiment, as shown in FIG15 , the pressure-resistant layer 60 further has a plurality of pad holes that expose a plurality of pads. The plurality of pad holes include a first pad hole V21, a second pad hole V22, a third pad hole V23, and a fourth pad hole V24. The first pad hole V21 exposes the first pad P31, the second pad hole V22 exposes the second pad P32, the third pad hole V23 exposes the third pad P33, and the fourth pad hole V24 exposes the fourth pad P34.

[0217] In an exemplary embodiment, Figure 22 is a schematic diagram of the film layer where the second electrodes of two pressure-sensing capacitors are located. As shown in Figure 22, the number of release holes included in the release hole array of the second electrode of at least one pressure-sensing capacitor is the same as the number of release holes included in the release hole array of the second electrode of at least one reference capacitor. For example, the number and arrangement of release holes 421 included in the release hole array 420 of the second electrode 42 of the first pressure-sensing capacitor FC1 and the release hole array 621 included in the release hole array 620 of the second electrode 62 of the second pressure-sensing capacitor FC2 are the same as the number and arrangement of release holes 521 included in the release hole array 520 of the second electrode 52 of the first reference capacitor RC1 and the release hole array 720 of the second electrode 72 of the second reference capacitor RC2. Figure 22 is a schematic diagram of the film layer where the second electrodes of the pressure-sensing capacitors are located when the pressure sensor includes a pressure-resistant layer.

[0218] In order to achieve deformation of the second electrode of the pressure-sensing capacitor under the action of pressure, while the second electrode of the reference capacitor does not deform substantially under the action of pressure, at least one reference capacitor may include: a support structure. The support structure is arranged between the second electrode of the reference capacitor and the insulating dielectric layer 20. The orthographic projection of the support structure on the substrate 10 overlaps with the orthographic projection of the second electrode of the reference capacitor on the substrate 10, and the cavity of the reference capacitor is arranged around the support structure. For example, as shown in Figures 16A, 16B, 18A and 18B, the first reference capacitor RC1 may further include: a support structure 54, and the second reference capacitor RC2 may further include: a support structure 74, the support structure 54 is arranged between the second electrode 52 of the first reference capacitor RC1 and the insulating dielectric layer 20. The orthographic projection of the support structure 54 on the substrate 10 overlaps with the orthographic projection of the second electrode 52 of the first reference capacitor RC1 on the substrate 10, and the cavity 53 of the first reference capacitor RC1 is arranged around the support structure 54. The support structure 74 is arranged between the second electrode 72 of the second reference capacitor RC2 and the insulating dielectric layer 20. The orthographic projection of the support structure 74 on the substrate 10 overlaps with the orthographic projection of the second electrode 72 of the second reference capacitor RC2 on the substrate 10, and the cavity 73 of the second reference capacitor RC2 is arranged around the support structure 74. In the present disclosure, by providing the support structure 34 in at least one reference capacitor and omitting the support structure in at least one pressure-sensing capacitor, the second electrode of at least one reference capacitor deforms under pressure, while the second electrode of at least one reference capacitor does not deform under pressure.

[0219] In an exemplary embodiment, as shown in FIG16A and FIG18A , when the capacitor structure is as shown in FIG3A , FIG3B , FIG4A and FIG4B , the sealing layer is not disposed around the sidewall of the support structure of the reference capacitor.

[0220] In an exemplary embodiment, as shown in FIG. 16B and FIG. 18B , when the capacitor structure is as shown in FIG. 3C or FIG. 4C , the second sealing structure of the sealing layer is disposed around the sidewall of the support structure of the reference capacitor.

[0221] In an exemplary embodiment, the support structure of at least one reference capacitor and the cavity are formed using the same process, and the support structure is a sacrificial layer that is not corroded. The support structure is made of materials including silicon oxide, low-temperature glass, phosphosilicate glass, or polysilicon.

[0222] In an exemplary embodiment, Figure 23 is a second schematic diagram of the film layer containing the second electrodes of two pressure-sensing capacitors. As shown in Figure 23, the number of release holes included in the release hole array of the second electrode of at least one pressure-sensing capacitor is greater than the number of release holes included in the release hole array of the second electrode of at least one reference capacitor. For example, the number of release holes 421 included in the release hole array 420 of the second electrode 42 of the first pressure-sensing capacitor FC1 and the number of release holes 621 included in the release hole array 620 of the second electrode 62 of the second pressure-sensing capacitor FC2 are greater than the number of release holes 521 included in the release hole array 520 of the second electrode 52 of the first reference capacitor RC1 and the number of release holes 721 included in the release hole array 720 of the second electrode 72 of the second reference capacitor RC2. The release hole array of the second electrode of at least one pressure-sensing capacitor includes a greater number of release holes than the release hole array of the second electrode of at least one reference capacitor. This allows, during the same period of time, the sacrificial layer in the at least one pressure-sensing capacitor to be etched away, while the sacrificial layer in the at least one reference capacitor is not completely etched. The unetched portion serves as a support structure to support the second electrode of the at least one reference capacitor, ensuring that the reference capacitor RC remains substantially unchanged under pressure. Figure 22 is a schematic diagram of the film layer where the second electrode of the pressure-sensing capacitor is located when the at least one reference capacitor includes a support structure.

[0223] In an exemplary embodiment, in order to achieve deformation of the second electrode of at least one pressure-sensing capacitor under the action of pressure, and the basic non-deformation of the second electrode of at least one reference capacitor under the action of pressure, when the pressure sensor may include a pressure-resistant layer, at least one reference capacitor may also include a support structure.

[0224] In an exemplary embodiment, the area of ​​the surface of the cavity in at least one capacitor near the second electrode is within a range of 20 to 100 times the thickness of the cavity. In the present disclosure, the area of ​​the surface of the cavity in at least one capacitor near the second electrode is within a range of 20 to 100 times the thickness of the cavity, which ensures that the capacitor can have a large deformation, thereby ensuring that the pressure sensor has a high sensitivity.

[0225] In an exemplary embodiment, when at least one reference capacitor in the pressure sensor is provided with a supporting structure, since the pressure sensor is relatively thin, the pressure sensor may be touched during transportation, packaging, and testing. An appropriate unstructured blank area is reserved outside the capacitor area to enable transportation and packaging without direct contact with the capacitor.

[0226] The following is an illustrative example of the pressure sensor fabrication process. The "patterning process" referred to in this disclosure includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping for metal, inorganic, or transparent conductive materials. For organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed by any one or more of spray coating, spin coating, and inkjet printing; and etching can be performed by any one or more of dry etching and wet etching, although this disclosure does not limit this. A "thin film" refers to a thin layer of a material deposited on a substrate using deposition, coating, or other processes. If the thin film does not require a patterning process during the entire fabrication process, it can also be referred to as a "layer." If the thin film requires a patterning process during the entire fabrication process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process. In an exemplary embodiment of the present disclosure, "the orthographic projection of the membrane is within the range of the orthographic projection of A" or "the orthographic projection of B includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0227] The method for preparing the pressure sensor provided in FIG8 includes steps S11 to S18 .

[0228] Step S11: providing a substrate 10, coating a photoresist 71 on the substrate 10, and forming opening areas H1 and H2 on the photoresist 71 through a patterning process, as shown in FIG24 a.

[0229] In an exemplary embodiment, the substrate 10 is single crystal silicon.

[0230] Step S12: ions are implanted into the opening areas H1 and H2. The substrates implanted with ions serve as the first electrode 21 of the pressure-sensing capacitor and the first electrode 31 of the reference capacitor, and the photoresist is stripped off, as shown in FIG24 b.

[0231] In an exemplary embodiment, low-temperature, high-concentration ion implantation is performed using an ion implanter, and the implantation dose may be 3E15 to 1E16 per square centimeter.

[0232] Illustratively, the ions may be boron, phosphorus, or arsenic.

[0233] Step S13: An insulating dielectric film and a sacrificial film are sequentially deposited on the substrate on which the first electrode of the pressure-sensing capacitor and the first electrode of the reference capacitor are formed, and the sacrificial film is patterned through a patterning process to form an insulating dielectric layer 20 covering the substrate 10 and a sacrificial layer 72 located on the insulating dielectric layer 20 and at least one capacitor, as shown in FIG24c.

[0234] In an exemplary embodiment, the shape of the sacrificial layer 72 may be a boss structure, and the three-dimensional morphology of the sacrificial layer 72 determines the morphology of the inner wall of the cavity.

[0235] In an exemplary embodiment, the insulating dielectric layer 20 may be made of silicon nitride. The insulating dielectric layer 20 does not react with the etchant of the sacrificial layer.

[0236] In an exemplary embodiment, the sacrificial layer 72 may be made of a material including silicon oxide, low-temperature glass, or phosphosilicate glass.

[0237] Step S14: depositing a first conductive film on the substrate on which the sacrificial layer 72 is formed, and patterning the first conductive film through a patterning process to form the second electrode 22 of the pressure-sensing capacitor and the second electrode 32 of the reference capacitor. The second electrode 22 of the pressure-sensing capacitor is provided with release holes 221 arranged in an array, and the second electrode 32 of the reference capacitor is provided with release holes 321 arranged in an array, as shown in FIG24d.

[0238] In an exemplary embodiment, the material of the first conductive film may include low-resistance polysilicon.

[0239] In an exemplary embodiment, the number and arrangement of the release holes 221 in the second electrode 22 of the pressure-sensing capacitor are the same as the number and arrangement of the release holes 321 in the second electrode 32 of the reference capacitor.

[0240] Step S15: Immerse the substrate on which the second electrode of the pressure-sensing capacitor and the second electrode of the reference capacitor are formed in an etchant, and use the etchant to corrode and release the sacrificial layer to form the cavity 23 of the pressure-sensing capacitor and the cavity 33 of the reference capacitor. Dry the substrate on which the cavity 23 of the pressure-sensing capacitor and the cavity 33 of the reference capacitor are formed, as shown in FIG24e.

[0241] In an exemplary embodiment, since the sacrificial layer is surrounded by low-resistance polysilicon, which is not corroded by the etchant, the substrate on which the second electrode of the pressure-sensing capacitor and the second electrode of the reference capacitor are formed can be immersed in the etchant for a long time, and the sacrificial layer can be completely corroded by shaking to ensure that no cavity remains.

[0242] In an exemplary embodiment, the etchant is an aqueous solution of hydrogen fluoride.

[0243] Step S16: depositing a sealing film on the substrate where the pressure-sensing capacitor cavity 23 and the reference capacitor cavity 33 are formed, and patterning the sealing film through a patterning process to form a sealing layer 30, as shown in FIG24f.

[0244] In an exemplary embodiment, the sealing layer 30 covers the release hole of the second electrode of the pressure-sensing capacitor and the release hole of the second electrode of the reference capacitor, thereby sealing the cavity of the pressure-sensing capacitor and the cavity of the reference capacitor.

[0245] In an exemplary embodiment, the sealing layer 30 includes a plurality of vias, including a first electrode exposure hole EV1, a second electrode exposure hole EV2, and a third electrode exposure hole EV3. The first electrode exposure hole EV1 exposes the second electrode of the pressure-sensing capacitor, the second electrode exposure hole EV2 exposes the second electrode of the reference capacitor, and the dielectric layer within the third electrode exposure hole EV3 is etched to expose the first electrode of the pressure-sensing capacitor and the first electrode of the reference capacitor.

[0246] In an exemplary embodiment, the sealing layer 30 may be formed of a material including at least one of silicon oxide and silicon nitride.

[0247] Step S17: depositing a second conductive film on the substrate with the sealing layer 30 formed thereon, and patterning the second conductive film through a patterning process to form a plurality of pads, as shown in FIG. 24 g .

[0248] In an exemplary embodiment, the plurality of pads include a first pad P21, a second pad P22, and a third pad P23. The first pad P21 is connected to the second electrode of the pressure-sensing capacitor through a first electrode exposure hole, the second pad P22 is connected to the second electrode of the reference capacitor through a second electrode exposure hole, and the third pad P23 is connected to the first electrode of the pressure-sensing capacitor and the first electrode of the reference capacitor through a third electrode exposure hole.

[0249] In an exemplary embodiment, the pad may be made of a metal, such as aluminum or gold, that is, the film layer where the pad is located is a metal conductive layer.

[0250] In an exemplary embodiment, the metal conductive film needs to be annealed after deposition to enable the metal conductive layer to form a good ohmic contact.

[0251] In an exemplary embodiment, an adhesive film may be deposited before depositing the second conductive film on the substrate having the sealing layer 30 formed thereon. The adhesive film and the second conductive film are patterned by a patterning process to form an adhesive layer and a pad layer on the adhesive layer.

[0252] In an exemplary embodiment, the adhesion layer may be a metal conductive layer, and the material of the adhesion layer may be a metal, such as titanium, chromium, or tantalum.

[0253] Step S18: depositing a pressure-resistant film on the substrate with the pad layer formed thereon, and patterning the pressure-resistant film through a patterning process to form a pressure-resistant layer 60 covering the substrate, as shown in FIG24h.

[0254] In an exemplary embodiment, the pressure-resistant layer 60 may include a pressure-resistant hole K and first to third via holes V11 to V13. The pressure-resistant hole K exposes the sealing layer, and its orthographic projection on the substrate at least partially overlaps with the orthographic projection of the second electrode of the pressure-sensitive capacitor on the substrate. The first via hole V11 exposes the first pad, the second via hole V12 exposes the second pad, and the third via hole V13 exposes the third pad.

[0255] The method for preparing the pressure sensor provided in FIG9 includes steps S21 to S27 .

[0256] Step 21 is the same as step S11 , step S22 is the same as step S12 , and step S23 is the same as step S13 .

[0257] Step S24: depositing a first conductive film on the substrate on which the sacrificial layer is formed, and patterning the first conductive film through a patterning process to form a second electrode 22 of the pressure-sensing capacitor and a second electrode 32 of the reference capacitor. The second electrode 22 of the pressure-sensing capacitor is provided with release holes 221 arranged in an array, and the second electrode 32 of the reference capacitor is provided with release holes 321 arranged in an array, as shown in FIG25a.

[0258] In an exemplary embodiment, the material of the first conductive film may include low-resistance polysilicon.

[0259] In an exemplary embodiment, the number of release holes 221 in the second electrode 22 of the pressure-sensing capacitor is greater than the number of release holes 321 in the second electrode 32 of the reference capacitor.

[0260] Step S25: Immerse the substrate on which the second electrode of the pressure-sensing capacitor and the second electrode of the reference capacitor are formed in an etchant, and use the etchant to corrode and release the sacrificial layer to form the cavity 23 of the pressure-sensing capacitor and the cavity 33 and support structure 34 of the reference capacitor. Dry the substrate on which the cavity 23 of the pressure-sensing capacitor and the cavity 33 of the reference capacitor are formed, as shown in FIG25b.

[0261] In an exemplary embodiment, because the sacrificial layer is surrounded by low-resistance polysilicon, which is not corroded by the etchant, the substrate on which the second electrode of the pressure-sensing capacitor and the second electrode of the reference capacitor are formed can be immersed in the etchant within the allowable release time to ensure that the cavity of the pressure-sensing capacitor is not retained. The cavity of the reference capacitor is also provided with a support structure 34. In an exemplary embodiment, the allowable release time can be obtained by calculating the release rate of the release hole array of the second electrode of the pressure-sensing capacitor and the release rate of the release hole array of the second electrode of the reference capacitor, as well as by fiber observation.

[0262] Step S26: depositing a sealing film on the substrate with the cavity of the pressure-sensing capacitor, the cavity of the reference capacitor, and the support structure, and patterning the sealing film through a patterning process to form a sealing layer 30, as shown in FIG25c.

[0263] In an exemplary embodiment, the sealing layer 30 covers the release hole of the second electrode of the pressure-sensing capacitor and the release hole of the second electrode of the reference capacitor, thereby sealing the cavity of the pressure-sensing capacitor and the cavity of the reference capacitor.

[0264] In an exemplary embodiment, the sealing layer 30 includes a plurality of vias, including a first electrode exposure hole EV1, a second electrode exposure hole EV2, and a third electrode exposure hole EV3. The first electrode exposure hole EV1 exposes the second electrode of the pressure-sensing capacitor, the second electrode exposure hole EV2 exposes the second electrode of the reference capacitor, and the dielectric layer within the third electrode exposure hole EV3 is etched to expose the first electrode of the pressure-sensing capacitor and the first electrode of the reference capacitor.

[0265] In an exemplary embodiment, the sealing layer 30 may be formed of a material including at least one of silicon oxide and silicon nitride.

[0266] Step S27 , depositing a second conductive film on the substrate with the sealing layer 30 formed thereon, and patterning the second conductive film through a patterning process to form a pad layer, as shown in FIG. 25 d .

[0267] In an exemplary embodiment, the pad layer includes a first pad P21, a second pad P22, and a third pad P23. The first pad P21 is connected to the second electrode of the pressure-sensing capacitor through a first electrode exposure hole, the second pad P22 is connected to the second electrode of the reference capacitor through a second electrode exposure hole, and the third pad P23 is connected to the first electrode of the pressure-sensing capacitor and the first electrode of the reference capacitor through a third electrode exposure hole.

[0268] In an exemplary embodiment, the pad may be made of a metal, such as aluminum or gold, that is, the film layer where the pad is located is a metal conductive layer.

[0269] In an exemplary embodiment, the metal conductive film needs to be annealed after deposition to enable the metal conductive layer to form a good ohmic contact.

[0270] In an exemplary embodiment, an adhesive film may be deposited before depositing the second conductive film on the substrate having the sealing layer 30 formed thereon. The adhesive film and the second conductive film are patterned by a patterning process to form an adhesive layer and a pad layer on the adhesive layer.

[0271] In an exemplary embodiment, the adhesion layer may be a metal conductive layer, and the material of the adhesion layer may be a metal, such as titanium, chromium, or tantalum.

[0272] The method for preparing the pressure sensor provided in FIG10 includes steps S31 to S37 .

[0273] Step S31 is the same as step S11 , and step S32 is the same as step S12 .

[0274] Step S33, depositing an insulating dielectric film and a sacrificial film on the substrate on which the first electrode 21 of the pressure-sensing capacitor and the first electrode 31 of the reference capacitor are formed, coating the sacrificial film with photoresist, and forming an opening area on the photoresist through a patterning process, injecting ions into the opening area to form an insulating dielectric layer 20 and a sacrificial layer 72, and stripping the photoresist. The sacrificial layer includes a doped area and a non-doped area. After stripping the photoresist, rapid thermal annealing or furnace annealing is performed to activate the ions located in the doped area so that the doped area is conductive, serving as the first sub-electrode 22A of the second electrode of the pressure-sensing capacitor and the first sub-electrode 32A of the second electrode of the reference capacitor, as shown in Figure 26a.

[0275] In an exemplary embodiment, the region where the non-doped region is located is a cavity region of the capacitor, and the height of the non-doped region determines the height of the cavity of the capacitor.

[0276] In an exemplary embodiment, the material forming the sacrificial thin film may include polysilicon.

[0277] In an exemplary embodiment, the insulating dielectric layer 20 may be made of silicon oxide or silicon nitride. The insulating dielectric layer 20 does not react with the etchant of the sacrificial film.

[0278] In an exemplary embodiment, the etchant for the sacrificial thin film in the non-doped region is an aqueous solution of potassium hydroxide or an aqueous solution of tetramethylammonium hydroxide.

[0279] Step S34: depositing a first conductive film on the substrate on which the sacrificial layer 72 is formed, and patterning the first conductive film through a patterning process to form a second sub-electrode 22B of the second electrode of the pressure-sensing capacitor and a second sub-electrode 32B of the second electrode of the reference capacitor. The second sub-electrode 22B of the second electrode of the pressure-sensing capacitor is provided with an array-arranged release hole 221, and the second sub-electrode 32B of the second electrode 32 of the reference capacitor is provided with an array-arranged release hole 321, as shown in FIG26b.

[0280] In an exemplary embodiment, the first conductive film may be made of a material including low-resistance polysilicon or metal. When the first conductive film is made of a metal, the metal may be platinum or chromium.

[0281] In an exemplary embodiment, the number of release holes 221 in the second sub-electrode 22B of the second electrode of the pressure-sensing capacitor is the same as the number of release holes 321 in the second sub-electrode 32B of the second electrode of the reference capacitor.

[0282] Step S35: Immerse the substrate on which the second sub-electrode of the second electrode of the pressure-sensing capacitor and the second sub-electrode of the second electrode of the reference capacitor are formed in an etchant, and use the etchant to corrode and release the non-doped area of ​​the sacrificial layer to form the cavity 23 of the pressure-sensing capacitor and the cavity 33 of the reference capacitor. Dry the substrate on which the cavity 23 of the pressure-sensing capacitor and the cavity 33 of the reference capacitor are formed, as shown in FIG26c.

[0283] In this exemplary embodiment, the etchant in the undoped region of the sacrificial layer etches the doped region of the sacrificial layer at a rate of only 1% to 2% of the rate in the undoped region of the sacrificial layer. When the etchant etches the undoped region of the sacrificial layer, the etching stops automatically when it encounters the doped region of the sacrificial layer, allowing the boundary dimensions of the cavity to be precisely controlled. Therefore, the substrate forming the second sub-electrode of the second electrode of the pressure-sensing capacitor and the second sub-electrode of the second electrode of the reference capacitor can be immersed in the etchant for a long time, and the sacrificial layer can be completely etched away by shaking, ensuring that no cavity remains.

[0284] Step S36 , depositing a sealing film on the substrate where the pressure-sensing capacitor cavity 23 and the reference capacitor cavity 33 are formed, and patterning the sealing film through a patterning process to form a sealing layer 30 , as shown in FIG26 d .

[0285] In an exemplary embodiment, the sealing layer 30 covers the release hole of the second electrode of the pressure-sensing capacitor and the release hole of the second electrode of the reference capacitor, thereby sealing the cavity of the pressure-sensing capacitor and the cavity of the reference capacitor.

[0286] In an exemplary embodiment, the sealing layer 30 may be formed of a material including at least one of silicon oxide and silicon nitride.

[0287] Step S37 : depositing a pressure-resistant film on the substrate with the sealing layer formed thereon, and patterning the pressure-resistant film through a patterning process to form a pressure-resistant layer 60 covering the substrate, as shown in FIG26 e .

[0288] In an exemplary embodiment, the pressure-resistant layer 60 includes a pressure-resistant hole K. The pressure-resistant hole K exposes the sealing layer, and an orthographic projection of the pressure-resistant hole K on the substrate at least partially overlaps with an orthographic projection of the second electrode of the pressure-sensitive capacitor on the substrate.

[0289] The method for preparing the pressure sensor provided in FIG11 includes steps S41 to S46 .

[0290] Step S41 is the same as step S31 , step S42 is the same as step S32 , and step S43 is the same as step S33 .

[0291] Step S44: depositing a first conductive film on the substrate on which the sacrificial layer is formed, and patterning the first conductive film through a patterning process to form a second sub-electrode 22B of the second electrode of the pressure-sensing capacitor and a second sub-electrode 32B of the second electrode of the reference capacitor. The second sub-electrode 22B of the second electrode of the pressure-sensing capacitor is provided with release holes 221 arranged in an array, and the second sub-electrode 32B of the second electrode of the reference capacitor is provided with release holes 321 arranged in an array, as shown in FIG27a.

[0292] In an exemplary embodiment, the material of the first conductive film may include low-resistance polysilicon.

[0293] In an exemplary embodiment, the number of release holes 221 in the second sub-electrode 22B of the second electrode of the pressure-sensing capacitor is greater than the number of release holes 321 in the second sub-electrode 32B of the second electrode of the reference capacitor.

[0294] Step S45: Immerse the second sub-electrode substrate of the second electrode of the pressure-sensing capacitor and the second sub-electrode substrate of the second electrode of the reference capacitor in an etchant, and use the etchant to corrode and release the non-doped area of ​​the sacrificial layer to form the cavity 23 of the pressure-sensing capacitor and the cavity 33 and support structure 34 of the reference capacitor. Dry the substrate on which the cavity 23 of the pressure-sensing capacitor and the cavity 33 of the reference capacitor are formed, as shown in FIG27b.

[0295] In an exemplary embodiment, the substrate on which the second sub-electrode of the second electrode of the pressure-sensing capacitor and the second sub-electrode of the second electrode of the reference capacitor are formed is immersed in an etchant within an allowable release time to ensure that the cavity of the pressure-sensing capacitor is not retained. The cavity of the reference capacitor is also provided with a support structure 34. In an exemplary embodiment, the allowable release time can be obtained by calculating the release rate of the release hole array of the second electrode of the pressure-sensing capacitor and the release rate of the release hole array of the second electrode of the reference capacitor, and observing through a microscope.

[0296] Step S46: depositing a sealing film on the substrate with the cavity of the pressure-sensing capacitor and the cavity of the reference capacitor and the supporting structure, and patterning the sealing film through a patterning process to form a sealing layer 30, as shown in FIG27c.

[0297] In an exemplary embodiment, the sealing layer 30 covers the release hole of the second electrode of the pressure-sensing capacitor and the release hole of the second electrode of the reference capacitor, thereby sealing the cavity of the pressure-sensing capacitor and the cavity of the reference capacitor.

[0298] In an exemplary embodiment, the deposition process may include a plasma enhanced chemical vapor deposition process, a low temperature chemical vapor deposition process, or a physical vapor deposition process, which is not limited in the present disclosure.

[0299] The embodiment of the present disclosure further provides a pressure sensing assembly, comprising: pressure sensors arranged in an array.

[0300] The pressure sensor is the pressure sensor provided in any of the aforementioned embodiments, and the present disclosure does not impose any limitation on this.

[0301] The present disclosure also provides a method for manufacturing a pressure sensor, which is configured to manufacture the pressure sensor provided by any of the aforementioned embodiments. The method for manufacturing the pressure sensor may include:

[0302] Step S100: forming a first electrode of at least one capacitor.

[0303] Step S200: forming a second electrode of at least one capacitor.

[0304] Step S300: forming a cavity between a first electrode and a second electrode of at least one capacitor.

[0305] In an exemplary embodiment, step S100 may include:

[0306] Step S110: providing a substrate.

[0307] Step S120 : implanting ions into a partial area of ​​the substrate to form at least one first electrode of a capacitor.

[0308] In an exemplary embodiment, before step S200, the method for manufacturing a pressure sensor may further include:

[0309] Step S400: forming an insulating dielectric layer on a first electrode of at least one capacitor.

[0310] In an exemplary embodiment, after step S300, the method for manufacturing a pressure sensor may further include:

[0311] Step S500: forming a sealing layer on the second electrode of at least one capacitor by a patterning process.

[0312] In an exemplary embodiment, step S200 may include:

[0313] Step S210 : forming a sacrificial layer on the insulating dielectric layer through a patterning process.

[0314] Step S220 : forming a second electrode of at least one capacitor on the sacrificial layer through a patterning process, wherein a release hole array is provided on the second electrode of the at least one capacitor.

[0315] In an exemplary embodiment, step S300 may include: etching the sacrificial layer through the release hole array using an etchant to form a cavity.

[0316] In an exemplary embodiment, the etchant may include: an aqueous solution of hydrofluoric acid;

[0317] In an exemplary embodiment, step S200 may include:

[0318] Step S230 : forming a sacrificial layer on the insulating dielectric layer through a patterning process.

[0319] Step S240 : implanting ions into a partial region of the sacrificial layer to form a first sub-electrode of a second electrode of at least one capacitor.

[0320] In an exemplary embodiment, the ions include boron, phosphorus, and arsenic, and the implantation dose is in the range of 3E15 per square centimeter to 1E16 per square centimeter.

[0321] Step S250: forming a second sub-electrode of the second electrode on the ion-implanted sacrificial layer by a patterning process, wherein a release hole array is provided on the second sub-electrode, and the orthographic projection of the release hole array on the substrate partially overlaps with the orthographic projection of the non-ion-implanted sacrificial layer on the substrate.

[0322] In an exemplary embodiment, step S300 may include:

[0323] Step S330: using an etchant to etch the sacrificial layer into which ions are not implanted through the release hole array to form a cavity.

[0324] In an exemplary embodiment, the etchant may include an aqueous solution of tetramethylammonium hydroxide or an aqueous solution of potassium hydroxide.

[0325] In an exemplary embodiment, after step S300, the method for manufacturing a pressure sensor may further include:

[0326] Step S600: forming a plurality of pads on the sealing layer through a patterning process.

[0327] In an exemplary embodiment, after step S300, the method for manufacturing a pressure sensor may further include:

[0328] Step S700: forming an adhesion layer and a plurality of pads on the sealing layer by a patterning process in sequence.

[0329] In an exemplary embodiment, when the pressure sensor includes at least one pressure-sensing capacitor and at least one reference capacitor, after step S600 or step S700, the method for manufacturing the pressure sensor further includes forming a pressure-resistant layer on the plurality of pads through a patterning process.

[0330] In an exemplary embodiment, the pressure-resistant layer is provided with at least one pressure-sensitive hole, and the at least one pressure-sensitive hole corresponds one-to-one with at least one pressure-sensitive capacitor, and the orthographic projection of the pressure-sensitive hole on the substrate at least partially overlaps with the orthographic projection of the second electrode of the corresponding pressure-sensitive capacitor on the substrate.

[0331] In an exemplary embodiment, when the pressure sensor includes: at least one pressure-sensitive capacitor and at least one reference capacitor, after step S500, the method for manufacturing the pressure sensor further includes: forming a pressure-resistant layer on the sealing layer through a composition process, the pressure-resistant layer having at least one pressure-sensitive hole, the at least one pressure-sensitive hole corresponding one-to-one to at least one pressure-sensitive capacitor, and the orthographic projection of the pressure-sensitive hole on the substrate at least partially overlaps with the orthographic projection of the second electrode of the corresponding pressure-sensitive capacitor on the substrate.

[0332] In an exemplary embodiment, when the pressure sensor includes: at least one pressure-sensing capacitor and at least one reference capacitor, step S300 may include: forming a cavity between a first electrode and a second electrode of the at least one pressure-sensing capacitor, and forming a cavity and a support structure between a first electrode and a second electrode of the at least one reference capacitor.

[0333] Figure 28 is a cross-sectional view of a pressure sensor according to another embodiment of the present disclosure, Figure 29 is another cross-sectional view of a pressure sensor according to another embodiment of the present disclosure, and Figure 30 is yet another cross-sectional view of a pressure sensor according to another embodiment of the present disclosure. As shown in Figures 28 to 30, the pressure sensor according to another embodiment of the present disclosure may include: a substrate 100 and at least one second electrode 12 of a capacitor disposed on the substrate 100, wherein the at least one second electrode 12 is provided with a release hole 121, and a cavity 13 is formed between the at least one second electrode 12 and the substrate 100.

[0334] As shown in Figures 28 to 30 , the pressure sensor further includes a sealing layer 30 , which is disposed around the cavity 13 and covers at least a portion of the release hole 121 and a surface of the at least one second electrode 12 away from the substrate 100 .

[0335] The sealing layer in the present disclosure can make the cavity a low-pressure cavity, thereby ensuring the long-term stability of the pressure sensor.

[0336] In exemplary embodiments, as shown in FIG. 28 to FIG. 30 , at least one second electrode 12 may be disposed around a sidewall of the cavity 13 .

[0337] In an exemplary embodiment, as shown in Figures 28 to 30 , at least one second electrode 12 includes a first sub-electrode 12A and a second sub-electrode 12B connected to each other, with the first sub-electrode 12A and the second sub-electrode 12B being disposed in the same layer. The orthographic projection of the first sub-electrode 12A on the substrate does not overlap with the orthographic projection of the second sub-electrode 12B on the substrate. The first sub-electrode 12A is disposed along the sidewall of the cavity 13, while the second sub-electrode 12B is disposed on a side of the cavity 13 away from the substrate. The orthographic projection of the cavity 13 on the substrate at least partially overlaps with the orthographic projection of the second sub-electrode 12B on the substrate.

[0338] In an exemplary embodiment, the substrate includes: a base and a first electrode of at least one capacitor disposed on the base, wherein an orthographic projection of the first electrode of the at least one capacitor on the base at least partially overlaps with an orthographic projection of a second sub-electrode of the second electrode of the at least one capacitor on the base.

[0339] In an exemplary embodiment, Fig. 31 is a top view of a portion of the film layers shown in Figs. 28 to 30. As shown in Figs. 28 to 31, the release hole 121 may be located on the second sub-electrode.

[0340] In an exemplary embodiment, as shown in Figure 31, there may be a plurality of release holes 121 arranged in an array. Orthographic projections of at least some of the release holes on the substrate are located in an overlapping region on the substrate between the first electrode and the second electrode of at least one capacitor.

[0341] In an exemplary embodiment, FIG32A is a cross-sectional view of a pressure sensor provided in another exemplary embodiment of the present disclosure, FIG32B is a cross-sectional view of a pressure sensor provided in another exemplary embodiment of the present disclosure, FIG33A is a top view of a portion of the membrane layer of the pressure sensor, and FIG33B is a side view of the second electrode of the pressure sensor. As shown in FIG32A, FIG32B, FIG33A, and FIG33B, there is one release hole 121, and the second sub-electrode is divided into a peripheral area and a central area. The peripheral area is arranged around the periphery of the central area, and the release hole is located in the peripheral area of ​​the second sub-electrode. In an exemplary embodiment, the aperture of the central area of ​​the second sub-electrode can be half the size of the second sub-electrode, that is, the release hole in the present disclosure can be located in the area of ​​the second sub-electrode close to the first sub-electrode. FIG32 is illustrated by taking the sealing layer provided in FIG28 as an example. The sealing layer in FIG32 can also be the sealing layer in FIG29 and FIG30.

[0342] As shown in Figures 33A and 33B , the shape of the release hole 121 can be circular, square, or other shapes, which are not limited in this disclosure. Figures 33A and 33B illustrate the release hole 121 as a circular shape.

[0343] As shown in FIG33A and FIG33B , the cavity includes: a first cavity 131 , a second cavity 132 and a channel 133 , and the first cavity 131 and the second cavity 132 are connected through the channel 133 .

[0344] In an exemplary embodiment, as shown in Figures 33A and 33B , the release hole 121 passes through the second cavity 132 and communicates with the second cavity 132. The orthographic projection of the first cavity 131 on the substrate does not overlap with the orthographic projection of the release hole 121 on the substrate, and the orthographic projections on the substrate are located in the overlapping area of ​​the first electrode and the second electrode of the at least one capacitor on the substrate.

[0345] In an exemplary embodiment, as shown in Figures 33A and 33B, the width of channel 133 is smaller than the width of at least one of first cavity 131 and second cavity 132, and the width of second cavity 132 is smaller than the width of first cavity 131. The width of at least one of the first cavity, second cavity, and channel refers to the width of the at least one of the first cavity, second cavity, and channel along a second direction, where the second direction intersects the arrangement direction of the first cavity, channel, and second cavity and lies in the same plane.

[0346] The arrangement of the cavity in the present disclosure can ensure that the etchant used when forming the cavity can flow inside the cavity, thereby increasing the corrosion rate.

[0347] The pressure sensor provided in Figures 32A, 32B, 33A and 33B does not have a release hole in the portion of the second electrode located above the first cavity, thereby ensuring that the surface of the second electrode is as flat as possible and avoiding the internal stress correspondence of the sealing layer material to the second electrode, thereby improving the reliability of the pressure sensor.

[0348] In an exemplary embodiment, the sealing layer includes: a first sealing structure, a second sealing structure, a third sealing structure, a fourth sealing structure, and a fifth sealing structure, which are sequentially connected. The first sealing structure is located on the side of the second electrode away from the substrate; the second sealing structure is located on the side of the second electrode closer to the substrate; the third sealing structure is disposed around the sidewalls of the release hole; the fourth sealing structure is disposed around the sidewalls of the cavity; and the fifth sealing structure is located on one side of the substrate, with the orthographic projection of the fifth sealing structure on the substrate at least partially overlapping with the orthographic projection of at least a portion of the substrate surface closer to the second electrode on the substrate.

[0349] As shown in Figures 28 to 30, the sealing layer 30 includes: a first sealing structure 31, a second sealing structure 32, a third sealing structure 33, a fourth sealing structure 34 and a fifth sealing structure 35, and the first sealing structure 31, the second sealing structure 32, the third sealing structure 33, the fourth sealing structure 34 and the fifth sealing structure 35 are interconnected.

[0350] In an exemplary embodiment, as shown in FIG. 28 to FIG. 30 , the first sealing structure 31 is located on a side of the second electrode 12 away from the substrate 100 and covers at least a portion of a surface of the second sub-electrode 12B away from the substrate 100 .

[0351] In an exemplary embodiment, as shown in FIG. 28 to FIG. 30 , the second sealing structure 32 is located on a side of the second sub-electrode 12B close to the substrate 100 and covers a surface of the second sub-electrode 12B close to the substrate 100 .

[0352] In an exemplary embodiment, as shown in FIG. 28 to FIG. 30 , the third sealing structure 33 is disposed around the sidewall of the release hole 121 .

[0353] 28 to 30 , the fourth sealing structure 34 is disposed around the sidewall of the cavity. The fourth sealing structure 34 is located on a side of the first sub-electrode 12A close to the substrate 100 and covers the sidewall of the first sub-electrode 12A close to the cavity 13 .

[0354] In an exemplary embodiment, as shown in FIG. 28 to FIG. 30 , the fifth sealing structure 35 is located on one side of the substrate 100 and covers at least a portion of the surface of the substrate 100 close to the second electrode 12 .

[0355] In an exemplary embodiment, as shown in FIG. 28 to FIG. 30 , the first sealing structure 31 includes a first sub-sealing structure 311 and a second sub-sealing structure 312 . The first sub-sealing structure 311 is located outside the second sub-sealing structure 312 and is integrally formed.

[0356] In an exemplary embodiment, as shown in Figures 28 to 30, the orthographic projection of the first sub-sealing structure 311 on the substrate 100 at least partially overlaps with the orthographic projection of the second sub-electrode 12B on the substrate 100, and the orthographic projection of the second sub-sealing structure 312 on the substrate 100 covers the orthographic projection of the third sealing structure 33 on the substrate 100.

[0357] In an exemplary embodiment, as shown in Figures 28 to 30 , the first sub-sealing structure 311 has a uniform thickness, and the second sub-sealing structure 312 is symmetrically arranged with respect to the release hole centerline O. The thickness of the second sub-sealing structure 312 gradually increases from the release hole centerline O to the sidewalls of the release hole 121. The thickness of a structure refers to its length perpendicular to the substrate. A uniform thickness of a structure means that the thickness is the same at any two locations within the structure.

[0358] In an exemplary embodiment, the release hole center line O is a straight line passing through the center point of the release hole and perpendicular to the substrate 100. The center point of the release hole refers to a circular point of a circular projection when the release hole is projected onto the substrate, or a midline of a diagonal line of a rectangular projection when the release hole is projected onto the substrate.

[0359] In an exemplary embodiment, FIG. 28 illustrates an example in which the second electrode 12 is made of a material including single crystal silicon and polycrystalline silicon, and the sealing layer 30 is made of a material including silicon oxide.

[0360] In an exemplary embodiment, as shown in FIG28 , when the second electrode 12 is made of one of single-crystal silicon and polycrystalline silicon, and the sealing layer 30 is made of silicon oxide, the second sealing structure 32 includes a third sub-sealing structure 321 and a fourth sub-sealing structure 322. The third sub-sealing structure 321 is positioned around the fourth sub-sealing structure 322 and is integrally formed. The orthographic projection of the third sub-sealing structure 321 on the substrate 100 at least partially overlaps with the orthographic projection of the second sub-electrode 12B on the substrate 100, and the orthographic projection of the fourth sub-sealing structure 322 on the substrate 100 covers the orthographic projection of the third sealing structure 33 on the substrate 100.

[0361] In an exemplary embodiment, as shown in FIG28 , the material for making the second electrode 12 includes: one of single crystal silicon and polycrystalline silicon, and the material for making the sealing layer 30 includes silicon oxide, the thickness of the third sub-sealing structure 321 is uniform, and the fourth sub-sealing structure 322 is symmetrically arranged with respect to the center line O of the release hole, and the thickness of the fourth sub-sealing structure 322 gradually increases from the center line O of the release hole to the side wall of the release hole 121.

[0362] In an exemplary embodiment, as shown in FIG28 , the material for making the second electrode 12 includes: one of single crystal silicon and polycrystalline silicon, and the material for making the sealing layer 30 includes silicon oxide, the thickness of the third sealing structure 33 is uniform, and the third sealing structure 33 fills the release hole 121 .

[0363] In an exemplary embodiment, as shown in FIG28 , the second electrode 12 is made of a material selected from the group consisting of single crystal silicon and polycrystalline silicon, and the sealing layer 30 is made of a material selected from the group consisting of silicon oxide. Furthermore, the thickness H1 of the first sub-sealing structure 311, the thickness H2 of the third sub-sealing structure, the thickness H3 of the third sealing structure 33, the thickness H4 of the fourth sealing structure 34, and the thickness H5 of the fifth sealing structure 35 are the same.

[0364] In an exemplary embodiment, as shown in FIG28 , the material of the second electrode 12 includes: one of single crystal silicon and polycrystalline silicon, and the material of the sealing layer 30 includes silicon oxide, and the thickness H1 of the first sub-sealing structure 311, the thickness H2 of the third sub-sealing structure, the thickness H3 of the third sealing structure 33, the thickness H4 of the fourth sealing structure 34, and the thickness H5 of the fifth sealing structure 35 are between 0.4 μm and 0.6 μm.

[0365] In an exemplary embodiment, as shown in FIG28 , the material for making the second electrode 12 includes: one of single crystal silicon and polycrystalline silicon, and the material for making the sealing layer 30 includes silicon oxide, and the sum of the thickness L of the second sub-electrode 12B, the thickness H1 of the first sealing structure 31, and the thickness H2 of the second sealing structure 32 is in the range of 2 μm to 3 μm.

[0366] In an exemplary embodiment, as shown in Figures 29 and 30, the thickness of the third sealing structure 33 gradually decreases from the direction away from the substrate 100 to the direction close to the substrate 100, and the third sealing structure 33 is a hollow structure and includes: a first through hole V1, and the second sealing structure 32 is a hollow structure and includes: a second through hole V2.

[0367] In an exemplary embodiment, as shown in Figures 29 and 30 , the thickness H1 of the first sub-sealing structure 311 is greater than the thickness of at least one of the second sealing structure 32, the third sealing structure 33, the fourth sealing structure 34, and the fifth sealing structure 35. In Figures 29 and 30 , the thickness of the second sealing structure 32 is referred to as H2, the thickness of the third sealing structure 33 away from the substrate is referred to as H31, the thickness of the third sealing structure 33 close to the substrate is referred to as H32, the thickness of the fourth sealing structure 34 is referred to as H4, and the thickness of the fifth sealing structure 35 is referred to as H5.

[0368] In an exemplary embodiment, as shown in FIG. 29 and FIG. 30 , a thickness H31 of the third sealing structure 33 away from the substrate 100 is greater than a thickness of at least one of the second sealing structure 32 , the fourth sealing structure 34 , and the fifth sealing structure 35 .

[0369] In an exemplary embodiment, as shown in FIG. 29 and FIG. 30 , a thickness H32 of the third sealing structure 33 on a side close to the substrate 100 is equal to a thickness of at least one of the second sealing structure 32 , the fourth sealing structure 34 , and the fifth sealing structure 35 .

[0370] In an exemplary embodiment, as shown in FIG. 29 and FIG. 30 , a center line of the first through hole V1 coincides with a center line of the second through hole V2 , and a size of the second through hole V2 is larger than a size of the first through hole V1 .

[0371] In an exemplary embodiment, a center line of at least one of the first through hole V1 and the second through hole V2 may be a straight line passing through a center point of at least one of the first through hole V1 and the second through hole V2 and perpendicular to the substrate 100. The center point of the through hole refers to a point of a circular projection when the projection shape of the through hole on the substrate is circular, or a center line of a diagonal line of a rectangular projection when the projection shape of the through hole on the substrate is rectangular.

[0372] In an exemplary embodiment, FIG. 29 illustrates an example in which the second electrode 12 is made of one of single crystal silicon, polycrystalline silicon and metal, and the sealing layer 30 is made of one of silicon nitride and silicon oxide.

[0373] In an exemplary embodiment, as shown in FIG29 , when the material of the second electrode 12 includes: one of single crystal silicon, polycrystalline silicon, and metal, and the material of the sealing layer 30 includes: one of silicon nitride and silicon oxide, the thickness L of the second sub-electrode 12B is in the range of 1 μm to 2 μm;

[0374] In an exemplary embodiment, as shown in FIG29 , when the second electrode 12 is made of one of single-crystal silicon, polycrystalline silicon, and metal, and the sealing layer 30 is made of one of silicon nitride and silicon oxide, the thickness of the first sub-sealing structure is greater than the diameter of the release hole 121. In this disclosure, when the projection of the release hole on the substrate is circular, the diameter of the release hole 121 refers to the diameter of the circular projection; when the projection of the release hole on the substrate is rectangular, the diameter of the release hole 121 refers to the length of the diagonal of the rectangular projection.

[0375] In an exemplary embodiment, as shown in FIG29 , the second electrode 12 is made of one of single crystal silicon, polycrystalline silicon, and metal, and the sealing layer 30 is made of one of silicon nitride and silicon oxide. The thickness H31 of the third sealing structure 33 on the side away from the substrate 100 is in a range of 0.25 to 0.3 times the diameter of the release hole 121.

[0376] In an exemplary embodiment, as shown in FIG29 , when the material of the second electrode 12 includes: one of single crystal silicon, polycrystalline silicon and metal, and the material of the sealing layer 30 includes one of silicon nitride and silicon oxide, the thickness H32 of the third sealing structure 33 on the side close to the substrate 100 is in the range of 0.05 times to 0.1 times the aperture of the release hole 121.

[0377] In an exemplary embodiment, as shown in Figure 29, the material for making the second electrode 12 includes: one of single crystal silicon, polycrystalline silicon and metal, and the material for making the sealing layer 30 includes one of silicon nitride and silicon oxide, and the thickness of at least one structure of the second sealing structure 32, the fourth sealing structure 34 and the fifth sealing structure 35 is in the range of 0.05 times to 0.1 times the aperture of the release hole 121.

[0378] In an exemplary embodiment, in the pressure sensor provided in FIG29 , the pore diameter of the release hole is in the range of 0.25 μm to 100 μm. For example, the pore diameter of the release hole may be in the range of 0.25 μm to 0.35 μm, or in the range of 0.35 μm to 0.5 μm, or in the range of 1 μm to 2 μm.

[0379] In an exemplary embodiment, in the pressure sensor provided in FIG. 29 , when the sealing layer is formed by a plasma enhanced chemical vapor deposition process to seal the release holes, the pore diameter of the release holes may be in the range of 2 μm to 100 μm.

[0380] In an exemplary embodiment, FIG30 illustrates an example in which the second electrode 12 is made of one of single crystal silicon, polycrystalline silicon and metal, and the sealing layer 30 is made of one of silicon nitride and tetraethoxysilane.

[0381] In an exemplary embodiment, as shown in FIG30 , when the material of the second electrode 12 includes: one of single crystal silicon, polycrystalline silicon and metal, and the material of the sealing layer 30 includes: one of silicon nitride and tetraethoxysilane, the thickness H1 of the first sub-sealing structure 311 is greater than 0.9 times the aperture of the release hole 121.

[0382] In an exemplary embodiment, as shown in FIG30 , when the material for making the second electrode 12 includes: one of single crystal silicon, polycrystalline silicon and metal, and the material for making the sealing layer 30 includes: one of silicon nitride and tetraethoxysilane, the thickness H31 of the third sealing structure 33 on the side away from the substrate 100 is in the range of 0.4 times to 0.5 times the aperture of the release hole 121.

[0383] In an exemplary embodiment, as shown in Figure 30, the material for making the second electrode 12 includes: one of single crystal silicon, polycrystalline silicon and metal, and the material for making the sealing layer 30 includes: one of silicon nitride and tetraethoxysilane, and the thickness H32 of the third sealing structure 33 on the side close to the substrate 100 is in the range of 0.25 times to 0.35 times the aperture of the release hole 121.

[0384] In an exemplary embodiment, as shown in FIG30 , when the material of the second electrode 12 includes: one of single crystal silicon, polycrystalline silicon, and metal, and the material of the sealing layer 30 includes: one of silicon nitride and tetraethoxysilane, the thickness of at least one of the second sealing structure 32, the fourth sealing structure 34, and the fifth sealing structure 35 is in a range of 0.25 to 0.35 times the diameter of the release hole 121;

[0385] In an exemplary embodiment, in the pressure sensor provided in FIG30 , the pore size of the release hole may be in the range of 0.25 μm to 2 μm. For example, the pore size of the release hole may be in the range of 0.25 μm to 0.35 μm, or in the range of 0.35 μm to 0.5 μm, or in the range of 0.5 μm to 1 μm, or in the range of 1 μm to 2 μm.

[0386] In an exemplary embodiment, as shown in FIG. 28 to FIG. 30 , an example is given in which the orthographic projection of the first sealing structure on the substrate covers the orthographic projection of the cavity 13 on the substrate.

[0387] In an exemplary embodiment, as shown in FIG. 32A , the orthographic projection of the first sealing structure 31 on the substrate 100 is located within the range of the orthographic projection of the cavity 13 on the substrate 100 .

[0388] In an exemplary embodiment, the size of the first sealing structure 31 is 3 to 5 times the diameter of the release hole 121. The size of the first sealing structure refers to the diameter of a circular projection when the projection of the first sealing structure onto the substrate 100 is circular, and refers to the length of the diagonal of the rectangle when the projection of the first sealing structure onto the substrate 100 is rectangular.

[0389] In an exemplary embodiment, in the pressure sensor provided in FIG. 32A , the pore size of the release hole may be in the range of 0.25 μm to 100 μm, or may be larger than 100 μm.

[0390] In an exemplary embodiment, as shown in Figures 32A and 32B, the pressure sensor may further include: a sealing layer 40, which is arranged on a side of the sealing layer away from the substrate 100, and the orthographic projection of the sealing layer 40 on the substrate 100 covers the orthographic projection of the first sealing structure 33 on the substrate 100.

[0391] In an exemplary embodiment, as shown in FIG. 32A and FIG. 32B , the sealing layer 40 is made of a material including silicon oxide or silicon nitride.

[0392] In an exemplary embodiment, as shown in FIG. 32A and FIG. 32B , the thickness H of the sealing layer 40 is within a range of ⅓ to ½ of the hole diameter of the release hole 121 .

[0393] In an exemplary embodiment, FIG. 32A is described as an example in which the orthographic projection of the sealing layer 40 on the substrate covers the orthographic projection of the second electrode 12 on the substrate.

[0394] In another exemplary embodiment, as shown in FIG32B , the orthographic projection of the sealing layer 40 on the substrate is within the range of the orthographic projection of the cavity 13 on the substrate, and the size of the sealing layer is within a range of 4 to 6 times the diameter of the release hole. The term "size of the sealing layer" refers to the diameter of a circular projection when the projection of the sealing layer on the substrate 100 is circular, and refers to the length of the diagonal of the rectangular projection when the projection of the sealing layer on the substrate 100 is rectangular.

[0395] The arrangement of the sealing layer and the sealing layer in the present disclosure can achieve better sealing effect and cavity sealing without increasing the thickness of the pressure sensor in the direction perpendicular to the substrate, which can make the second electrode easier to deform and the pressure detection accuracy higher.

[0396] In an exemplary embodiment, substrate 100 further includes an insulating dielectric layer. The insulating dielectric layer is located on a side of the substrate proximal to the second electrode. The substrate, at least one first electrode of the capacitor, and the insulating dielectric layer are identical to those described in Figures 1 to 19 and are not further described in this disclosure.

[0397] The embodiment of the present disclosure further provides a pressure sensing assembly. The pressure sensing assembly provided by the embodiment of the present disclosure further includes: the pressure sensors provided by any of the aforementioned embodiments arranged in an array.

[0398] The present disclosure also provides a method for preparing a pressure sensor, which is configured to prepare the pressure sensor of any of the aforementioned embodiments provided in FIG. 28 to FIG. 33B . The method for preparing the pressure sensor may include:

[0399] Step 101: forming a substrate.

[0400] Step 102: forming a sacrificial layer on the substrate.

[0401] Step 103: forming at least one second electrode of a capacitor on the sacrificial layer, removing the sacrificial layer, and forming a sealing layer.

[0402] In an exemplary embodiment, step 101 may include: providing a substrate, implanting ions into a portion of the substrate to form at least one first electrode of a capacitor, and forming an insulating dielectric layer on the substrate forming the at least one first electrode of the capacitor.

[0403] In an exemplary embodiment, step 102 may include: depositing a sacrificial thin film on a substrate, processing the sacrificial thin film through a patterning process to form an initial sacrificial layer, and annealing the initial sacrificial layer to form a sacrificial layer.

[0404] In an exemplary embodiment, the sacrificial layer is made of at least one of low-temperature glass, phosphosilicate glass, silicon oxide, and silicon nitride.

[0405] In an exemplary embodiment, when the sacrificial film is made of silicon oxide, the sacrificial film may be deposited using a plasma enhanced chemical vapor deposition process. When the sacrificial film is made of silicon nitride, the sacrificial film may be deposited using a sub-atmospheric pressure chemical vapor deposition process.

[0406] In an exemplary embodiment, in another exemplary embodiment, annealing the initial sacrificial layer to form the sacrificial layer may include: annealing the initial sacrificial layer using a rapid thermal annealing process to form the sacrificial layer.

[0407] In an exemplary embodiment, when the material of the sealing layer includes one of silicon nitride, silicon oxide, and tetraethoxysilane, step 103 may include the following steps:

[0408] Step 1031 : forming at least one second electrode of a capacitor on the sacrificial layer, wherein the second electrode is provided with a release hole.

[0409] Step 1032: Place the substrate with the second electrode formed thereon into an etchant. The etchant removes the sacrificial layer through the release holes to form a cavity.

[0410] In an exemplary embodiment, the etchant may be an aqueous solution of hydrogen fluoride.

[0411] Step 1033: forming a sealing layer on the substrate with the cavity formed therein.

[0412] In an exemplary embodiment, when the sealing layer is made of a material comprising silicon nitride and silicon oxide, step 1033 may include depositing silicon nitride or silicon oxide on the substrate having the cavity formed therein using a plasma enhanced chemical vapor deposition process to form the sealing layer.

[0413] In an exemplary embodiment, when the sealing layer is made of a material comprising silicon nitride and tetraethoxysilane, step 1033 may include depositing silicon nitride or tetraethoxysilane on the substrate having the cavity formed therein using a low pressure chemical vapor deposition process to form the sealing layer.

[0414] In an exemplary embodiment, the sealing layer is made of silicon oxide, and step 103 may include the following steps:

[0415] Step 1041: forming an original second electrode on the sacrificial layer, wherein the original second electrode is provided with an original release hole.

[0416] In an exemplary embodiment, the pore size of the primary release pores is less than 6 microns.

[0417] Step 1042: Place the substrate with the original second electrode formed thereon into an etchant. The etchant removes the sacrificial layer through the original release hole to form a cavity.

[0418] Step 1043 : forming at least one second electrode of a capacitor and a sealing layer on the substrate having the cavity formed therein.

[0419] In an exemplary embodiment, step 1043 includes placing the substrate having the cavity formed therein into a furnace tube at a third temperature and introducing oxygen therein to oxidize the surface of the original second electrode to form at least one second electrode of the capacitor and a sealing layer. The second electrode is the original, unoxidized second electrode, and the oxidized surface of the original second electrode serves as the sealing layer.

[0420] In an exemplary embodiment, the surface of the oxidized second electrode may expand to form a sealing layer.

[0421] In an exemplary embodiment, the thickness of the second electrode is 2 / 3 of the thickness of the original second electrode, the via hole of the second electrode is called a release hole, and the aperture of the release hole is 5 / 3 of the aperture of the original release hole.

[0422] In an exemplary embodiment, the sealing layer is made of a material selected from the group consisting of silicon nitride and silicon oxide, and the deposition temperature of the sealing layer is lower than 450 degrees Celsius. After the sealing layer is formed, the pressure sensor manufacturing method may further include:

[0423] The sealing layer is etched, and a sealing layer is formed on the sealing layer.

[0424] In an exemplary embodiment, the sealing layer includes a first sealing structure located on a side of the second electrode away from the substrate, and etching the sealing layer may include etching the first sealing structure using a photolithography process or a dry etching process.

[0425] The pressure sensor of the embodiment of the present disclosure is further explained below through the preparation process of the pressure sensor in Figure 28.

[0426] Step S51: forming a substrate 10, depositing a sacrificial film on the substrate 10, processing the sacrificial film through a patterning process to form an initial sacrificial layer, and annealing the initial sacrificial layer to form a sacrificial layer 50. As shown in FIG34, FIG34 is a schematic diagram of FIG28 after the sacrificial layer is formed.

[0427] Step S52: forming at least one original second electrode 60 of a capacitor on the sacrificial layer. As shown in FIG35 , FIG35 is a schematic diagram of FIG28 after forming the original second electrode.

[0428] In an exemplary embodiment, the original second electrode 60 is provided with an original release hole 61 .

[0429] Step S53: Place the substrate with the original second electrode in an etchant, and remove the sacrificial layer through the original release hole to form a cavity 13. As shown in FIG36, FIG36 is a schematic diagram of FIG28 after the sacrificial layer is removed.

[0430] Step S54: Place the substrate with the cavity formed therein into a furnace at a third temperature and introduce oxygen to oxidize the surface of the original second electrode, thereby forming at least one capacitor second electrode 12 and a sealing layer 30. FIG37 is a schematic diagram of FIG28 after the sealing layer is formed.

[0431] The dotted line in Figure 37 indicates the frame of the original second electrode. The oxidized surface of the original second electrode serves as the sealing layer 30, that is, the second electrode is retracted relative to the original second electrode.

[0432] The pressure sensor of the embodiment of the present disclosure is further explained below through the preparation process of the pressure sensor in Figure 29 or 30.

[0433] Step S61: Form a substrate, deposit a sacrificial film on the substrate, pattern the sacrificial film to form an initial sacrificial layer, and anneal the initial sacrificial layer to form a sacrificial layer. The schematic diagrams of Figures 29 and 30 after the sacrificial layer is formed are the same as the schematic diagram of Figure 28 after the sacrificial layer is formed, and are not further described here.

[0434] Step S62: forming at least one second electrode 12 of the capacitor on the sacrificial layer. As shown in FIG38 , FIG38 is a schematic diagram of FIG29 or FIG30 after the second electrode is formed.

[0435] In an exemplary embodiment, the second electrode 12 is provided with a release hole 121 .

[0436] Step S63: Place the substrate with the second electrode in an etchant, which removes the sacrificial layer through the release holes to form a cavity 13. The schematic diagrams of FIG29 or FIG30 after removing the sacrificial layer are the same as the schematic diagram of FIG28 after removing the sacrificial layer, and are not repeated here.

[0437] Step S64: Silicon nitride or silicon oxide is deposited on the substrate with the cavity formed therein by using a plasma enhanced chemical vapor deposition process, or silicon nitride or tetraethoxysilane is deposited on the substrate with the cavity formed therein by using a low pressure chemical vapor deposition process to form a sealing layer, as shown in FIG29 or FIG30.

[0438] The pressure sensor of the embodiment of the present disclosure is further illustrated below through the preparation process of the pressure sensor in Figure 32A or Figure 32B.

[0439] The process in FIG. 32A or FIG. 32B before forming the sealing layer is the same as the process of the pressure sensor provided in FIG. 29 , and will not be described in detail herein.

[0440] The manufacturing process of the pressure sensor of FIG32A or FIG32B further includes:

[0441] Step S71 , etching the first sealing structure of the sealing layer.

[0442] Step S72 : forming a sealing layer on the substrate having the etched first sealing structure formed thereon.

[0443] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0444] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0445] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A pressure sensor, comprising: A substrate and a second electrode of at least one capacitor disposed on the substrate, at least one second electrode being provided with a release hole, a cavity being formed between the at least one second electrode and the substrate, the pressure sensor further comprising: a sealing layer; The sealing layer is disposed around the cavity, and the sealing layer covers at least a part of the release hole and the surface of the at least one second electrode away from the substrate.

2. The pressure sensor according to claim 1, wherein, The at least one second electrode surrounds the side wall of the cavity; The at least one second electrode includes: a first sub-electrode and a second sub-electrode connected to each other, the first sub-electrode and the second sub-electrode being disposed in the same layer; The orthographic projection of the first sub-electrode on the substrate does not overlap with the orthographic projection of the second sub-electrode on the substrate, the first sub-electrode is disposed along the side wall of the cavity, the second sub-electrode is disposed on a side of the cavity away from the substrate, and the orthographic projection of the cavity on the substrate at least partially overlaps with the orthographic projection of the second sub-electrode on the substrate.

3. The pressure sensor according to claim 2, wherein, The substrate includes: a base and a first electrode of at least one capacitor disposed on the base, the orthographic projection of the first electrode of the at least one capacitor on the base at least partially overlaps with the orthographic projection of the second sub-electrode of the second electrode of the at least one capacitor on the base; The release hole is located on the second sub-electrode.

4. The pressure sensor according to claim 3, wherein, The number of the release holes is multiple, and the multiple release holes are arranged; At least a part of the orthographic projections of the multiple release holes on the base is located in the overlapping region of the first electrode and the second electrode of the at least one capacitor on the base.

5. The pressure sensor according to claim 3, wherein, The number of the release holes is one, the second sub-electrode is divided into a peripheral region and a central region, the peripheral region surrounds the periphery of the central region, and the release hole is located in the peripheral region of the second sub-electrode; The cavity includes: a first cavity, a second cavity and a channel, the first cavity and the second cavity are communicated through the channel, the release hole penetrates through the second cavity and is communicated with the second cavity, the orthographic projection of the first cavity on the base and the orthographic projection of the release hole on the base do not have an overlapping region, and the orthographic projection on the base is located in the overlapping region of the first electrode and the second electrode of the at least one capacitor on the base; The width of the channel is smaller than the width of at least one of the first cavity and the second cavity, and the width of the second cavity is smaller than the width of the first cavity.

6. The pressure sensor according to claim 3 or 4, wherein, The sealing layer includes: a first sealing structure, a second sealing structure, a third sealing structure, a fourth sealing structure and a fifth sealing structure, the first sealing structure, the third sealing structure, the second sealing structure, the fourth sealing structure and the fifth sealing structure are communicated in sequence; The first sealing structure is located on a side of the second electrode away from the substrate; The second sealing structure is located on a side of the second electrode close to the substrate; The third sealing structure is disposed around the side wall of the release hole; The fourth sealing structure is disposed around the side wall of the cavity; The fifth hole-sealing structure is located on one side of the substrate, and the orthographic projection of the fifth hole-sealing structure on the substrate overlaps at least partially with the orthographic projection of at least a part of the surface of the substrate close to the second electrode on the substrate.

7. The pressure sensor according to claim 6, wherein, The first hole-sealing structure includes: a first sub-hole-sealing structure and a second sub-hole-sealing structure. The first sub-hole-sealing structure is located on the periphery of the second sub-hole-sealing structure and is integrally formed. The orthographic projection of the first sub-hole-sealing structure on the substrate overlaps at least partially with the orthographic projection of the second electrode on the substrate, and the orthographic projection of the second sub-hole-sealing structure on the substrate covers the orthographic projection of the third hole-sealing structure on the substrate. The thickness of the first sub-hole-sealing structure is uniform. The second sub-hole-sealing structure is symmetrically arranged with respect to the center line of the release hole. From the center line of the release hole to the side wall of the release hole, the thickness of the second sub-hole-sealing structure gradually increases. The center line of the release hole is perpendicular to the substrate.

8. The pressure sensor according to claim 7, wherein, The manufacturing material of the second electrode includes one of monocrystalline silicon and polycrystalline silicon, and the manufacturing material of the hole-sealing layer includes silicon oxide.

9. The pressure sensor according to claim 8, wherein the second hole-sealing structure comprises: A third sub-hole-sealing structure and a fourth sub-hole-sealing structure. The third sub-hole-sealing structure is located on the periphery of the fourth sub-hole-sealing structure and is integrally formed. The orthographic projection of the third sub-hole-sealing structure on the substrate overlaps at least partially with the orthographic projection of the second electrode on the substrate, and the orthographic projection of the fourth sub-hole-sealing structure on the substrate covers the orthographic projection of the third hole-sealing structure on the substrate. The thickness of the third sub-hole-sealing structure is uniform. The fourth sub-hole-sealing structure is symmetrically arranged along the center line of the release hole. From the center line of the release hole to the side wall of the release hole, the thickness of the fourth sub-hole-sealing structure gradually increases.

10. The pressure sensor according to claim 9, wherein, The thickness of the third hole-sealing structure is uniform, and the third hole-sealing structure fills the release hole. The thicknesses of at least two of the first sub-hole-sealing structure, the third sub-hole-sealing structure, the third hole-sealing structure, the fourth hole-sealing structure, and the fifth hole-sealing structure are the same.

11. The pressure sensor according to claim 7, wherein, In the direction from far away from the substrate to close to the substrate, the thickness of the third hole-sealing structure gradually decreases, and the third hole-sealing structure is a hollow structure and includes: a first through hole. The second hole-sealing structure is a hollow structure and includes: a second through hole. The thickness of the first sub-hole-sealing structure is greater than the thickness of at least one of the second hole-sealing structure, the third hole-sealing structure, the fourth hole-sealing structure, and the fifth hole-sealing structure. The thickness of the third hole-sealing structure on the side far away from the substrate is greater than the thickness of at least one of the second hole-sealing structure, the fourth hole-sealing structure, and the fifth hole-sealing structure. The center lines of the first through hole and the second through hole coincide, and the size of the second through hole is greater than the size of the first through hole.

12. The pressure sensor according to claim 11, wherein, The manufacturing material of the second electrode includes one of monocrystalline silicon, polycrystalline silicon, and metal, and the manufacturing material of the hole-sealing layer includes one of silicon nitride and silicon oxide.

13. The pressure sensor according to claim 12, wherein, The thickness of the first sub-hole-sealing structure is greater than the aperture of the release hole. The thickness of the third hole-sealing structure on the side far away from the substrate is in the range of 0.25 times to 0.3 times the aperture of the release hole. The thickness of the third hole-sealing structure near the substrate side is in the range of 0.05 times to 0.1 times the aperture of the release hole; The thickness of at least one of the second hole-sealing structure, the fourth hole-sealing structure, and the fifth hole-sealing structure is in the range of 0.05 times to 0.1 times the aperture of the release hole; The aperture of the release hole is in the range of 0.25 micrometers to 100 micrometers.

14. The pressure sensor according to claim 11, wherein, The material for making the second electrode includes one of single-crystalline silicon, polycrystalline silicon, and metal, and the material for making the hole-sealing layer includes one of silicon nitride and tetraethoxysilane.

15. The pressure sensor according to claim 14, wherein, The thickness of the first sub-hole-sealing structure is greater than 0.9 times the aperture of the release hole; The thickness of the third hole-sealing structure far from the substrate side is in the range of 0.4 times to 0.5 times the aperture of the release hole; The thickness of the third hole-sealing structure near the substrate side is in the range of 0.25 times to 0.35 times the aperture of the release hole; The thickness of at least one of the second hole-sealing structure, the fourth hole-sealing structure, and the fifth hole-sealing structure is in the range of 0.25 times to 0.35 times the aperture of the release hole; The aperture of the release hole is in the range of 0.25 micrometers to 2 micrometers.

16. The pressure sensor according to claim 15, wherein, The orthographic projection of the first hole-sealing structure on the substrate is within the orthographic projection of the cavity on the substrate; The size of the first hole-sealing structure is 3 times to 5 times the aperture of the release hole.

17. The pressure sensor according to claim 16, further comprising: A sealing layer, the sealing layer is arranged on the side of the hole-sealing layer far from the substrate, and the orthographic projection on the substrate covers the orthographic projection of the first hole-sealing structure on the substrate; The material for making the sealing layer includes one of silicon oxide or silicon nitride, and the thickness of the sealing layer is in the range of 1 / 3 to 1 / 2 times the aperture of the release hole.

18. The pressure sensor according to claim 17, wherein, The orthographic projection of the sealing layer on the substrate is within the orthographic projection of the cavity on the substrate, and the size of the sealing layer is in the range of 4 times to 6 times the aperture of the release hole.

19. The pressure sensor according to claim 1, wherein, The substrate includes: a substrate, the first electrode of at least one capacitor, and an insulating dielectric layer; Wherein, the first electrode is formed in the substrate and located on the surface of the substrate, and the insulating dielectric layer is located on the side of the substrate close to the second electrode.

20. A pressure sensing component, comprising: An array of pressure sensors according to any one of claims 1 to 19.

21. A method for manufacturing a pressure sensor, configured to manufacture a pressure sensor according to any one of claims 1 to 19, the method comprising: Forming a substrate; Forming a sacrificial layer on the substrate; Forming the second electrode of at least one capacitor on the sacrificial layer, removing the sacrificial layer, and forming a hole-sealing layer.

22. The method according to claim 21, wherein, Forming a sacrificial layer on the substrate includes: Depositing a sacrificial thin film on the substrate, processing the sacrificial thin film through a patterning process to form an initial sacrificial layer, and the material for making the sacrificial layer includes at least one of low-temperature glass, phosphosilicate glass, silicon oxide, and silicon nitride; Annealing the initial sacrificial layer to form a sacrificial layer.

23. The method according to claim 21, wherein, Forming the second electrode of at least one capacitor on the sacrificial layer, removing the sacrificial layer, and forming a hole-sealing layer includes: Form a second electrode of at least one capacitor on the sacrificial layer, and the second electrode is provided with release holes; Place the substrate with the second electrode formed thereon into an etching agent, and the etching agent removes the sacrificial layer through the release holes to form a cavity; Form a hole-sealing layer on the substrate with the cavity formed thereon.

24. The method according to claim 23, wherein, The forming of the hole-sealing layer on the substrate with the cavity formed thereon includes: Deposit silicon nitride or silicon oxide on the substrate with the cavity formed thereon by plasma-enhanced chemical vapor deposition process to form a hole-sealing layer; Or, deposit silicon nitride or tetraethoxysilane on the substrate with the cavity formed thereon by low-pressure chemical vapor deposition process to form a hole-sealing layer.

25. The method according to claim 21, wherein, After forming the hole-sealing layer, the method further includes: Etch the hole-sealing layer and form a sealing layer on the hole-sealing layer.

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