Data storage device with memory service for storing access queues

Abstract

A computing device has a compute fast link (CXL) connection between a memory subsystem and a host system and has a memory access queue at least partially configured in the memory subsystem. The memory subsystem may attach a portion of its fast random access memory as a memory device to the host system through the connection. One or more memory access queues may be configured in the memory device. The host system may use a cache coherence memory access protocol to communicate storage access messages over the connection to the random access memory of the memory subsystem. Optionally, the host system may have a memory with a second memory access queue that may be used to access memory services of the memory subsystem over the connection using a memory access protocol.

Description

[0001] Related applications

[0002] This application claims priority to U.S. patent application serial number 18 / 432,518, filed on February 5, 2024, which claims priority to provisional U.S. patent application serial number 63 / 483,824, filed on February 8, 2023, the entire disclosure of which is hereby incorporated by reference into this document. Technical Field

[0003] At least some embodiments disclosed herein relate generally to memory systems, and more particularly, but not limited to, to memory systems configured for use by memory services and storage services. Background Art

[0004] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally speaking, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Embodiments are illustrated by way of example and not limitation in the accompanying figures in which like reference numerals indicate similar elements.

[0006] Figure 1 An example computing system having a memory subsystem according to some embodiments of the present disclosure is described.

[0007] Figure 2 Shown is a memory subsystem configured to provide both memory services and storage services to a host system through a physical connection, according to one embodiment.

[0008] Figure 3 A memory subsystem is shown having a storage access queue configured to enable a host system to access storage services of the memory subsystem according to one embodiment.

[0009] Figure 4 Executing write commands using a memory access queue in a memory subsystem according to one embodiment is described.

[0010] Figure 5 Executing read commands using a memory access queue in a memory subsystem according to one embodiment is described.

[0011] Figure 6 The execution of a write command according to one embodiment is described.

[0012] Figure 7The execution of a read command according to one embodiment is described.

[0013] Figure 8 A method for accessing storage services of a memory subsystem according to one embodiment is presented. DETAILED DESCRIPTION

[0014] At least some aspects of the present disclosure relate to a solid-state drive (SSD) that can provide both memory services and storage services through a physical connection to a host system. The SSD can allocate a portion of its fast memory, such as dynamic random access memory (DRAM), and attach the allocated portion to the host system as a memory device. At least a portion of a storage access queue can be configured in a memory device provided by a portion of the faster memory of the SSD. The host system can use the storage access queue to access storage services, such as storage capacity attached by the SSD as a storage device through a physical connection to the host system.

[0015] For example, a host system and a memory subsystem (e.g., a solid-state drive (SSD)) can be connected via a physical connection based on the Compute Express Link (CXL) computer component interconnect standard. Compute Express Link (CXL) includes protocols for storage access (e.g., cxl.io) and protocols for cache-coherent memory access (e.g., cxl.mem and cxl.cache). Thus, the memory subsystem can be configured to provide both storage services and memory services to the host system via the physical connection using Compute Express Link (CXL).

[0016] A typical solid-state drive (SSD) is configured or designed as a non-volatile storage device that preserves an entire set of data received from a host system during an unexpected power outage. An SSD utilizes volatile memory (e.g., SRAM or DRAM) as a buffer when processing storage access messages (e.g., read commands, write commands) received from the host system. To prevent data loss during a power outage, an SSD is typically configured with an internal backup power supply. This allows the SSD to continue operating for a limited period of time during a power outage to save data buffered in the volatile memory (e.g., SRAM or DRAM) to non-volatile memory (e.g., NAND). When the limited period is sufficient to ensure data preservation in the volatile memory (e.g., SRAM or DRAM) during a power outage, the volatile memory backed by the backup power supply can be considered non-volatile from the host system's perspective. Typical implementations of the backup power supply (e.g., capacitors, batteries) limit the amount of volatile memory (e.g., SRAM or DRAM) configured in the SSD to maintain the SSD's non-volatile nature as a data storage device. When the functionality of this volatile memory is implemented via fast non-volatile memory, the backup power supply can be eliminated from the solid state drive.

[0017] When an SSD is configured with a host interface that supports the Compute Express Link protocol, a portion of the SSD's fast volatile memory can optionally be configured to provide cache-coherent memory services to the host system. Such memory services can be accessed via load / store instructions executed in the host system at the byte level (e.g., 64B or 128B) over the Compute Express Link connection. Another portion of the SSD's volatile memory can be reserved for internal use by the SSD as a buffer memory to facilitate storage services to the host system. Such storage services can be accessed via read / write commands provided by the host system at the logical block level (e.g., 4KB) over the Compute Express Link connection.

[0018] When such a solid-state drive (SSD) is connected to a host system via a computing express link, the SSD can be attached and used as both a memory device and a storage device for the host system. The storage device provides storage capacity addressable by the host system at the block level via read and write commands (e.g., for data records in a database); and the memory device provides physical memory addressable by the host system at the byte level via load and store instructions (e.g., for changes to data records in a database).

[0019] Advantageously, a host system configures at least a portion of a storage access queue for accessing storage capacity of a solid-state drive (SSD) on a memory device attached to the host system.

[0020] For example, when a solid-state drive is connected to a host system via a Compute Express Link (CXL) connection, the host system may configure one or more storage access queues on the memory device that are attached by the solid-state drive to the host system.

[0021] The host system may use a cache coherent memory access protocol to access the storage access queue in the solid-state drive. For example, a storage access command may be stored by the host system in the storage access queue in the solid-state drive to access the storage capacity of the solid-state drive.

[0022] After the host system writes the storage access message to the storage access queue in the SSD through the computing fast link connection using the cache coherent memory access protocol, the SSD can use local access of its fast volatile memory to obtain the message without using the memory bus outside the SSD to access the storage access queue.

[0023] When the fast volatile memory used to host the storage access queue in the solid-state drive is backed by a backup power source, the contents of the storage access queue configured to access the storage capacity of the solid-state drive can be preserved during a power outage in the computer system. Therefore, the host system does not have to handle the preservation of the contents of the storage access queue in response to a power outage.

[0024] Optionally, from the perspective of the host system, the memory space provided by the SSD via the Compute Express Link connection can be configured as non-volatile. The memory allocated by the SSD for providing memory services via the Compute Express Link connection can be implemented via non-volatile memory or via volatile memory backed by a backup power supply. The backup power supply is configured to be sufficient to ensure that, in the event of an interruption in external power to the SSD, the SSD can continue to operate to save data from the volatile memory to the SSD's non-volatile storage capacity. Therefore, in the event of an unexpected power interruption, data in the memory space provided by the SSD is preserved and not lost.

[0025] It is advantageous for the host system to use a communication protocol to query the solid-state drive about the memory attachment capabilities of the solid-state drive, such as whether the solid-state drive can provide cache-coherent memory services, how much memory the solid-state drive can attach to the host system when providing memory services, how much of the memory that can be attached to provide memory services can be considered non-volatile (e.g., implemented via non-volatile memory or supported by a backup power supply), how much access time the memory that can be allocated by the solid-state drive to the memory service, etc.

[0026] The query results can be used to configure memory allocation in the solid-state drive to provide cache-coherent memory services. For example, a portion of the solid-state drive's fast memory can be provided to the host system for cache-coherent memory access; and the remaining portion of the fast memory can be retained internally by the solid-state drive. The partitioning of the solid-state drive's fast memory for different services can be configured to balance the benefits of the memory services provided by the solid-state drive to the host system with the performance of the storage services implemented by the solid-state drive for the host system. Optionally, the host system can explicitly request the solid-state drive to allocate a requested portion of its fast volatile memory as memory that can be accessed by the host system through a connection based on a computing fast link using a cache-coherent memory access protocol.

[0027] For example, when a solid-state drive is connected to a host system via a computing express link to provide storage services, the host system may send a command to the solid-state drive to query the storage attachment capability of the solid-state drive.

[0028] For example, a command to query memory attachment capabilities may be configured with a different command identifier than a read command; and in response, the solid-state drive is configured to provide a response indicating whether the solid-state drive is capable of operating as a memory device to provide memory services accessible via load instructions and store instructions. In addition, the response may be configured to identify the amount of available memory that can be allocated and attached as a memory device accessible via a compute express link connection. Optionally, the response may be further configured to include an identification of the amount of available memory that can be viewed as non-volatile by the host system and that can be used as a memory device by the host system. The non-volatile portion of the memory device attached by the solid-state drive may be implemented via non-volatile memory or volatile memory supported by a backup power source and the non-volatile storage capacity of the solid-state drive.

[0029] Optionally, the solid-state drive may be configured with more volatile memory than its backup power supply supports. After a power outage to the solid-state drive, the backup power supply is sufficient to store data from a portion of the solid-state drive's volatile memory to its storage capacity, but is insufficient to save all of the data in the volatile memory to its storage capacity. Therefore, the response to the memory attachment capability query may include an indication of the ratio of the volatile to non-volatile portions of the memory that can be allocated by the solid-state drive to the memory service. Optionally, the response may further include an identification of the access time of the memory that can be allocated by the solid-state drive to the cache coherent memory service. For example, when a host system requests data from the solid-state drive via a cache coherent protocol over a compute fast link, the solid-state drive may provide the data within a period of time no longer than the access time.

[0030] Optionally, a preconfigured response to this query can be stored at a predetermined location in a storage device attached to the host system by the SSD. For example, the predetermined location can be at a predetermined logical block address in a predetermined namespace. For example, the preconfigured response can be configured as part of the SSD's firmware. The host system can use a read command to retrieve the response from the predetermined location.

[0031] Optionally, when the solid-state drive has the capability to function as a memory device, the solid-state drive may automatically allocate a predetermined amount of its fast volatile memory as a memory device attached to the host system via a computing fast link connection. The predetermined amount may be a minimum or default amount configured in the solid-state drive's manufacturing facility or an amount specified by configuration data stored in the solid-state drive. Subsequently, a memory attachment capability query may optionally be implemented in a command set of a cache coherent memory access protocol (rather than a command set of a storage access protocol); and the host system may use the query to retrieve parameters specifying the memory attachment capability of the solid-state drive. For example, the solid-state drive may place the parameters in a memory device at a predetermined memory address; and the host may retrieve the parameters by executing a load command with the corresponding memory address.

[0032] It would be advantageous for a host system to customize aspects of the memory services of a memory subsystem (eg, a solid state drive) to the host system's memory and storage usage patterns.

[0033] For example, the host system may specify the size of a memory device provided by the SSD for attachment to the host system so that a set of physical memory addresses configured according to the size can be addressed via execution of load / store instructions in a processing device of the host system.

[0034] Optionally, the host system can specify time requirements for accessing a memory device over a Compute Express Link (CXL) connection. For example, when a cache request accesses a memory location over the connection, the SSD is required to provide a response within the access time specified by the host system when configuring the SSD's memory services.

[0035] Optionally, the host system can specify how much of the memory device attached to the solid-state drive is required to be non-volatile, so that when the external power supply to the solid-state drive fails, data in the non-volatile portion of the memory device attached to the host system by the solid-state drive is not lost. The non-volatile portion can be implemented by the solid-state drive via non-volatile memory or volatile memory with a backup power supply to continue copying data from the volatile memory to the non-volatile memory during the interruption of the external power supply to the solid-state drive.

[0036] Optionally, the host system can specify whether the solid state drive will attach the memory device to the host system via a Compute Express Link (CXL) connection.

[0037] For example, a solid-state drive may have an area configured to store configuration parameters for a memory device attached to a host system via a Compute Express Link (CXL) connection. When the solid-state drive is restarted, started, or powered on, the solid-state drive may allocate a portion of its memory resources as a memory device for attachment to the host system according to the configuration parameters stored in the area. After the solid-state drive configures the memory service according to the configuration parameters stored in the area, the host system can access it through the cache by executing load instructions and store instructions that identify the corresponding physical memory addresses. The solid-state drive can configure its remaining memory resources to provide storage services through a Compute Express Link (CXL) connection. For example, a portion of its volatile random access memory may be allocated as a buffer memory reserved for the processing device of the solid-state drive; and the host system cannot access and address the buffer memory via load / store instructions.

[0038] When the solid-state drive is connected to the host system via a compute express link, the host system may send a command to adjust configuration parameters stored in an area of ​​an attachable memory device. The host system may then request the solid-state drive to reattach the memory device with the memory service configured according to the configuration parameters to the host system via the compute express link.

[0039] For example, the host system may be configured to issue a write command (or store command) to save configuration parameters at a predetermined logical block address (or predetermined memory address) in a region to customize the settings of a memory device configured to provide memory services over a compute fast link connection.

[0040] Alternatively, a command having a command identifier different from the write command (or store instruction) may be configured in the read-write protocol (or load-store protocol) to instruct the solid-state drive to adjust the configuration parameters stored in the area.

[0041] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 according to some embodiments of the present disclosure. Memory subsystem 110 may include computer-readable storage media, such as one or more volatile memory devices (e.g., memory device 107), one or more non-volatile memory devices (e.g., memory device 109), or a combination thereof.

[0042] exist Figure 1 In FIG. 1 , the memory subsystem 110 is configured as an article of manufacture (eg, a solid-state drive) that can be used as a component installed in a computing device.

[0043] The memory subsystem 110 further includes a host interface 113 for physical connection 103 with a host system 120 .

[0044] Host system 120 may have an interconnect 121 connecting cache 123 , memory 129 , memory controller 125 , processing device 127 , and change manager 101 configured to use memory services of memory subsystem 110 to accumulate changes for storage in storage capacity of memory subsystem 110 .

[0045] The change manager 101 in the host system 120 may be implemented at least in part via instructions executed by the processing device 127 or via logic circuitry, or both. The change manager 101 in the host system 120 may use a memory device attached to the host system 120 by the memory subsystem 110 to store the changes to the database before the changes are written to a file in the memory device attached to the host system 120 by the memory subsystem 110. Optionally, the change manager 101 in the host system 120 is implemented as part of the operating system 135 of the host system 120, a database manager in the host system 120, or a device driver configured to operate the memory subsystem 110, or a combination of such software components.

[0046] Connections 103 may be in accordance with the Compute Express Link (CXL) standard or other communication protocols that support cache coherent memory access and storage access. Optionally, multiple physical connections 103 are configured to support cache coherent memory access communications and to support storage access communications.

[0047] The processing device 127 may be a microprocessor configured as a central processing unit (CPU) of a computing device. Instructions executed in the processing device 127 (e.g., load instructions, store instructions) may access the memory 129 via the memory controller 125 and the cache 123. In addition, when the memory subsystem 110 attaches the memory device to the host system via the connection 103, the instructions executed in the processing device 127 (e.g., load instructions, store instructions) may access the memory device via the memory controller 125 and the cache 123 in a manner similar to accessing the memory 129.

[0048] For example, in response to executing a load instruction in processing device 127, memory controller 125 may convert the logical memory address specified by the instruction into a physical memory address to request cache 123 to perform a memory access to retrieve data. For example, the physical memory address may be in memory 129 of host system 120 or in a memory device attached to host system 120 by memory subsystem 110 via connection 103. If the data at the physical memory address is not already in cache 123, cache 123 may load the data from the corresponding physical address as cache contents 131. Cache 123 may provide cache contents 131 to service the memory access request at the physical memory address.

[0049] For example, in response to executing a store instruction in the processing device 127, the memory controller 125 may convert the logical memory address specified by the instruction into a physical memory address to request the cache 123 to perform a memory access to store the data. The cache 123 may retain the data of the store instruction as cache content 131 and indicate that the corresponding data at the physical memory address has expired. When the cache 123 needs to free up a cache block (e.g., to load new data from a different memory address or to retain data for a store instruction at a different memory address), the cache 123 may flush the cache content 131 from the cache block to the corresponding physical memory address (e.g., in the host system's memory 129 or in a memory device attached to the host system 120 by the memory subsystem 110 via the connection 103).

[0050] The connection 103 between the host system 120 and the memory subsystem 110 can support a cache coherent memory access protocol. Cache coherence ensures that changes to a copy of data corresponding to a memory address are propagated to other copies of the data corresponding to the memory address, and that a processing device (e.g., 127) sees load / store accesses to the same memory address in the same order.

[0051] Operating system 135 may include routines programmed to process instructions for storage access requests from applications.

[0052] In some embodiments, the host system 120 configures a portion of its memory (e.g., 129) to serve as a storage access queue 133 for storage access messages. Such storage access messages may include read commands, write commands, erase commands, and the like. A storage access command (e.g., read or write) may specify a logical block address of a data block in a storage device (e.g., attached to the host system 120 by the memory subsystem 110 via connection 103). The storage device may retrieve the message from the storage access queue 133, execute the command, and provide the result in the storage access queue 133 for further processing by the host system 120 (e.g., using routines in the operating system 135).

[0053] Typically, the data blocks addressed by storage access commands (e.g., read or write) are much larger than the data units accessible via memory access instructions (e.g., load or store). Therefore, storage access commands can facilitate batch processing of large amounts of data (e.g., data in files managed by a file system) simultaneously and in the same manner with the help of routines in operating system 135. Memory access instructions can be used efficiently for random access to small pieces of data without the overhead of routines in operating system 135.

[0054] The memory subsystem 110 has an interconnect 111 that connects a host interface 113 , a controller 115 , and memory resources (eg, memory devices 107 , . . . , 109 ).

[0055] The controller 115 of the memory subsystem 110 may control the operation of the memory subsystem 110 . For example, the operation of the memory subsystem 110 may be responsive to a memory access message in the memory access queue 133 or in response to a memory access request from the cache 123 .

[0056] In some implementations, each of the memory devices (e.g., 107, ..., 109) includes one or more integrated circuit devices, each enclosed in a separate integrated circuit package. In other implementations, each of the memory devices (e.g., 107, ..., 109) is configured on an integrated circuit die; and the memory devices (e.g., 107, ..., 109) may be configured in the same integrated circuit device enclosed within the same integrated circuit package. In yet another implementation, the memory subsystem 110 is implemented as an integrated circuit device having an integrated circuit package that encloses the memory devices 107, ..., 109, the controller 115, and the host interface 113.

[0057] For example, the memory device 107 of the memory subsystem 110 may have a volatile random access memory 138 that is faster than the non-volatile memory 139 of the memory device 109 of the memory subsystem 110. Thus, the non-volatile memory 139 may be used to provide storage capacity of the memory subsystem 110 for retaining data. At least a portion of the storage capacity may be used to provide storage services to the host system 120. Optionally, a portion of the volatile random access memory 138 may be used to provide cache coherent memory services to the host system 120. The remaining portion of the volatile random access memory 138 may be used to provide buffering services to the controller 115 when processing storage access messages in the storage access queue 133 and when performing other operations (e.g., wear leveling, garbage collection, error detection and correction, encryption).

[0058] When the volatile random access memory 138 is used to buffer data received from the host system 120 before being stored in the non-volatile memory 139, the data in the volatile random access memory 138 may be lost when power to the memory device 107 is interrupted. To prevent data loss, the memory subsystem 110 may have a backup power supply 105 that may be sufficient to operate the memory subsystem 110 for a period of time to allow the controller 115 to commit the buffered data from the volatile random access memory 138 to the non-volatile memory 139 in the event that external power to the memory subsystem 110 is interrupted.

[0059] Optionally, fast memory 138 may be implemented via non-volatile memory (e.g., cross-point memory); and backup power supply 105 may be eliminated. Alternatively, a combination of fast non-volatile memory and fast volatile memory may be configured in memory subsystem 110 for both memory and buffer services.

[0060] The host system 120 may send a memory attachment capability query to the memory subsystem 110 via the connection 103. In response, the memory subsystem 110 may provide a response identifying whether the memory subsystem 110 can provide cache coherent memory services via the connection 103, how much memory can be attached to provide memory services via the connection 103, how much of the memory available for the host system's 120 memory services is considered non-volatile (e.g., implemented via non-volatile memory or backed by the backup power supply 105), how much access time can be allocated to the memory services of the host system 120, etc.

[0061] The host system 120 may send a request to the memory subsystem 110 over the connection 103 to configure the memory services provided by the memory subsystem 110 to the host system 120. In the request, the host system 120 may specify whether the memory subsystem 110 will provide cache coherent memory services over the connection 103, how much memory is to be provided as memory services over the connection 103, how much of the memory provided over the connection 103 is to be considered non-volatile (e.g., implemented via non-volatile memory or backed up by the backup power supply 105), how long the memory is to be accessed as a memory service to the host system 120, etc. In response, the memory subsystem 110 may partition its resources (e.g., memory devices 107, . . . , 109) and provide the requested memory services over the connection 103.

[0062] When a portion of memory 138 is configured to provide memory services over connection 103, host system 120 can access cache portion 132 of memory 138 via load and store instructions and cache 123. Non-volatile memory 139 can be accessed via read and write commands, which are transmitted via memory access queue 133 configured in memory 129 of host system 120.

[0063] Using the memory services of the memory subsystem 110 provided via the connection 103, the host system 120 may accumulate data identifying changes to the database in the subsystem's memory (e.g., in a portion of the volatile random access memory 138). When the size of the accumulated change data exceeds a threshold, the change manager 101 may package the change data into one or more data blocks for one or more write commands addressing one or more logical block addresses. The change manager 101 may be implemented in the host system 120 or the memory subsystem 110, or partially in the host system 120 and partially in the memory subsystem 110. The change manager 101 in the memory subsystem 110 may be implemented at least in part via instructions (e.g., firmware) executed by the processing device 117 of the controller 115 of the memory subsystem 110, or via logic circuitry, or both.

[0064] Figure 2 A memory subsystem is shown that is configured to provide both memory services and storage services to a host system through a physical connection according to one embodiment. Figure 2 The memory subsystem 110 and the host system 120 can be implemented in a manner as Figure 1 computing system 100.

[0065] exist Figure 2 , the memory resources of the memory subsystem 110 (e.g., memory devices 107, ..., 109) are partitioned into a loadable portion 141 and a readable portion 143 (and in some cases, an optional portion of a buffer memory 149, as in Figure 5 The physical connection 103 between the host system 120 and the memory subsystem 110 may support a protocol 145 for load and store instructions to access memory services provided in the loadable portion 141. For example, the load and store instructions may be executed via the cache 123. The connection 103 may further support a protocol 147 for read and write commands to access storage services provided in the readable portion 143. For example, the read and write commands may be provided via a storage access queue 133 configured in the memory 129 of the host system 120. For example, a physical connection 103 supporting a compute express link may be used to connect the host system 120 and the memory subsystem 110.

[0066] Figure 2 An example is illustrated of the same physical connection 103 (e.g., a Compute Express Link connection) configured to facilitate both memory access communications according to a protocol 145 and memory access communications according to another protocol 147. In general, a single physical connection can be used to provide memory access according to the memory access protocol 145 and memory access according to another memory access protocol 147 to the host system 120.

[0067] Figure 3 A memory subsystem is shown having a storage access queue configured to enable a host system to access storage services of the memory subsystem according to one embodiment.

[0068] For example, Figure 3 The memory subsystem 110 can be as follows Figure 1 The method of implementing the loadable part 141 and the readable part 143. Figure 2 , the loadable portion 141 is accessible by the host system 120 over the connection 103 via one protocol 145 for cache coherent memory access; and the readable portion 143 is accessible by the host system 120 over the connection 103 via another protocol 147 for storage access.

[0069] exist Figure 3 In the embodiment, the storage access queue 134 is configured in the loadable portion 141 of the memory subsystem 110 , so that the host system 120 can use the storage access queue 134 and the cache coherent memory access protocol 145 to access the storage service implemented in the readable portion 143 .

[0070] For example, the host system 120 may use the cache coherent memory access protocol 145 to input a read command into the storage access queue 134 to request the memory subsystem 110 to retrieve data 181 from the readable portion 143. Similarly, the host system 120 may use the cache coherent memory access protocol 145 to input a write command into the storage access queue 134 to request the memory subsystem 110 to write data 181 to the readable portion 143. Thus, the host system 120 does not have to allocate a portion of its memory 129 to host a storage access queue for accessing the readable portion 143; and the host system 120 does not have to use the storage access protocol 147 to access the readable portion 143 over a connection.

[0071] For example, the host system 120 may execute a store instruction to store a memory access message in the memory access queue 134 using the cache coherent memory access protocol 145. Since the loadable portion 141 is within the memory subsystem 110, the processing device 117 may retrieve the memory access message from the memory access queue 134 without using an external connection (e.g., 103) and / or without using the memory access protocol 147.

[0072] The processing device 117 may be configured via the firmware 153 to retrieve read commands and write commands from the storage access queue 134 in the loadable portion 141 without using the storage access protocol 147. The processing device 117 may execute the read commands and write commands retrieved from the loadable portion 141 in the memory subsystem 110 in the same manner as the execution of similar commands retrieved from the storage access queue 133 in the memory 129 configured in the host system 120 over the connection 103 using the storage access protocol 147 to retrieve data 181 from the readable portion 143 and write data 181 to the readable portion 143.

[0073] After executing the read command retrieved from the storage access queue 134 in the loadable portion 141, the processing device 117 of the memory subsystem 110 may place the data 181 retrieved from the readable portion 143 into the loadable portion 141 (e.g., in the storage access queue 134 or other location). The host system 120 may retrieve the data 181 from the loadable portion 141 (e.g., the storage access queue 134 or other location) over the connection 103 by executing the load instruction and using the cache coherent memory access protocol 145.

[0074] After executing a read command from the host system 120, the memory subsystem 110 may store or buffer data 181 retrieved from the readable portion 143 in the buffer memory 149. The processing device 117 of the memory subsystem 110 may be configured via firmware 153 to optionally provide the retrieved data 181 from the buffer memory 149 to the host system 120 without passing through the loadable portion 141. For example, the retrieved data 181 may be provided by the memory subsystem 110 from the buffer memory 149 over a connection to a memory access queue 133 configured in the memory 129 of the host system 120 using the storage access protocol 147. Alternatively, the retrieved data 181 may be provided to the host system 120 via the loadable portion 141 over the connection 103 using the cache coherent memory access protocol 145.

[0075] In some implementations, the processing device 117 of the memory subsystem 110 may retrieve the read command from a storage access queue 133 configured in the memory 129 of the host system 120 using the storage access protocol 147. After executing the read command, the processing device 117 of the memory subsystem 110 may place the retrieved data 181 into the loadable portion 141 (e.g., in the storage access queue 134 or other location) for access by the host system 120 via a load instruction and the cache coherent memory access protocol 145. Alternatively, the retrieved data 181 may be provided to the host system 120 over the connection 103 using the storage access protocol 147.

[0076] The memory subsystem 110 can execute a write command received from the host system 120 (e.g., retrieved from a memory access queue 134 configured in the loadable portion 141 or a memory access queue 133 configured in the host system's memory 129). To execute the write command, the processing device 117 of the memory subsystem 110 can retrieve data 181 for the write command from the loadable portion 141 (e.g., the memory access queue 134 or other location). For example, the host system 120 can provide the data 181 for the write command over the connection 103 using a cache coherent memory access protocol 145. Alternatively, the memory subsystem 110 can receive the data for the write command from the host system 120 over the connection using the memory access protocol 145.

[0077] After executing a write command to write data 181 into readable portion 143 , processing device 117 may optionally use storage access queue 134 to provide an indication of completion of the write command.

[0078] For example, the indication of write command completion may be in the form of a write command previously in the storage access queue 134 configured in the loadable portion 141 (or the storage access queue 133 in the memory 129 of the host system 120) being canceled from the storage access queue 134 (or the storage access queue 133).

[0079] For example, the indication that the write command is complete may be in the form of a response message, eg, provided in storage access queue 134 or 133. The response message is configured to indicate that the write command is complete.

[0080] In some implementations, the processing device 117 of the memory subsystem 110 may retrieve a write command from the loadable portion 141. To execute the write command, the processing device 117 of the memory subsystem 110 may be configured via firmware 153 to retrieve data 181 to be written from a storage access queue 133 configured in the memory 129 of the host system 120 over a connection using the storage access protocol 147. The memory subsystem 110 may place the retrieved data 181 in the buffer memory 149 for and during execution of the write command.

[0081] In some implementations, the processing device 117 of the memory subsystem 110 may retrieve a write command from a storage access queue 133 configured in the memory 129 of the host system 120 using a storage access protocol 147. To execute the write command, the processing device 117 of the memory subsystem 110 may retrieve the data 181 to be written from the loadable portion 141 (e.g., the storage access queue 134 or other location). The processing device 117 may use the data 181 in the loadable portion 141 for and during execution of the write command.

[0082] Optionally, the host system 120 may allocate a storage access queue 134 in the loadable portion 141 of the memory subsystem 110 to store a set of storage access requests addressed to the readable portion 143; and the host system 120 may allocate a storage access queue 133 in the memory 129 of the host system 120 to store another set of storage access requests addressed to the readable portion 143 of the memory subsystem 110.

[0083] For example, a request from an application or routine of the operating system 135 may be configured to use the storage access queue 134 in the loadable portion 141 of the memory subsystem 110; and a request from another application or another routine of the operating system 135 may be configured to use the storage access queue 133 in the memory 129 of the host system 120.

[0084] Figure 4 The following describes how to use a storage access queue in a memory subsystem to execute a write command according to one embodiment. For example, Figure 4 The execution of the write command can be implemented in Figure 3 computing system.

[0085] exist Figure 4 In FIG, the host system 120 configures a memory access queue 134 in a loadable portion 141 of the memory subsystem 110. The host system 120 can access the loadable portion 141 using a cache coherent memory access protocol 145 over a connection 103 between the host system 120 and the memory subsystem 110, such as a Compute Express Link (CXL) connection.

[0086] Using the cache coherent memory access protocol 147 , the host system 120 may input a write command 191 and data 193 written via the write command 191 into the memory access queue 134 .

[0087] Since the loadable portion 141 is internal to the memory subsystem 110 , the processing device 117 of the memory subsystem 110 may be configured (eg, via firmware 153 ) to execute the write command 191 in the storage access queue 134 to write data 193 into the readable portion 143 .

[0088] Data 193 written to readable portion 143 may be accessed by host system 120 via connection 103 using storage access protocol 147, as in Figure 2 middle.

[0089] Figure 5 The following describes how to use a storage access queue in a memory subsystem to execute a read command according to one embodiment. For example, Figure 5 The execution of the read command can be implemented in Figure 3 computing system.

[0090] exist Figure 5 In FIG, the host system 120 configures a memory access queue 134 in a loadable portion 141 of the memory subsystem 110. The host system 120 can access the loadable portion 141 using a cache coherent memory access protocol 145 over a connection 103 between the host system 120 and the memory subsystem 110, such as a Compute Express Link (CXL) connection.

[0091] Using the cache coherent memory access protocol 147 , the host system 120 may input a read command 195 into the memory access queue 134 .

[0092] Because the loadable portion 141 is internal to the memory subsystem 110 , the processing device 117 of the memory subsystem 110 may be configured (eg, via firmware 153 ) to execute the read command 195 in the storage access queue 134 and retrieve data 197 from the readable portion 143 .

[0093] The retrieved data 197 may be placed in the storage access queue 134 in response to the read command 195. The host system 120 may load the data 197 from the storage access queue 134 using the cache coherent memory access protocol 145.

[0094] For example, the data 197 read from the readable portion 143 may be as follows Figure 4 In the way or as Figure 2 The data is generally written to the readable portion 143 via the storage access protocol 147 through the connection 103.

[0095] Figure 6 The execution of a write command according to one embodiment is described. For example, Figure 6 The execution of the write command can be implemented in Figure 3 computing system.

[0096] exist Figure 6 , the host system 120 configures a storage access queue 134 in a loadable portion 141 of the memory subsystem 110. The host system 120 can access the loadable portion 141 using a cache coherent memory access protocol 145 over a connection 103 (e.g., a Compute Express Link (CXL) connection) between the host system 120 and the memory subsystem 110. In addition, the host system 120 configures a storage access queue 133 in its memory (e.g., 129) to access the readable portion 143 using a storage access protocol 147 over the connection 103 between the host system 120 and the memory subsystem 110.

[0097] Using the cache coherent memory access protocol 147 , the host system 120 may input a write command 191 into the memory access queue 134 in the load portion 141 .

[0098] Using the storage access protocol 147 , the host system 120 may provide data 193 to be written via a write command 191 using a storage access queue 133 configured in the memory 129 of the host system 120 .

[0099] Because the loadable portion 141 is internal to the memory subsystem 110, the processing device 117 of the memory subsystem 110 can be configured (e.g., via firmware 153) to retrieve the write command 191 for execution directly from the loadable portion 141. To execute the write command 191, the processing device 117 can retrieve the data 193 written over the connection 103 using the storage access protocol 147.

[0100] For example, data 193 written to readable portion 143 may be read by host system 120 as in Figure 2 Typically using storage access protocol 147 via connection 103 or as in Figure 5 or Figure 7 The data is generally accessed via the loadable portion 141.

[0101] Figure 7 The execution of a read command according to one embodiment is described. For example, Figure 7 The execution of the read command can be implemented in Figure 3 computing system.

[0102] exist Figure 7 , the host system 120 configures a storage access queue 134 in a loadable portion 141 of the memory subsystem 110. The host system 120 can access the loadable portion 141 using a cache coherent memory access protocol 145 over a connection 103 (e.g., a Compute Express Link (CXL) connection) between the host system 120 and the memory subsystem 110. In addition, the host system 120 configures a storage access queue 133 in its memory (e.g., 129) to access the readable portion 143 using a storage access protocol 147 over the connection 103 between the host system 120 and the memory subsystem 110.

[0103] Using the cache coherent memory access protocol 147 , the host system 120 may input a read command 195 into the memory access queue 134 .

[0104] Because the loadable portion 141 is internal to the memory subsystem 110 , the processing device 117 of the memory subsystem 110 may be configured (eg, via firmware 153 ) to execute the read command 195 in the storage access queue 134 and retrieve data 197 from the readable portion 143 .

[0105] Retrieved data 197 may be placed in buffer memory 149 of memory subsystem 110 in response to read command 195. Memory subsystem 110 may provide data 197 from buffer memory 149 to storage access queue 133 in memory of host system 120 using storage access protocol 147.

[0106] For example, the data 197 read from the readable portion 143 may be as follows Figure 4 or Figure 6 In the way or as Figure 2 The data is generally written to the readable portion 143 via the storage access protocol 147 through the connection 103.

[0107] Figure 8 A method for accessing storage services of a memory subsystem according to one embodiment is presented. For example, Figure 8 The method can be Figure 3 technology to implement Figure 1 and Figure 2 The computing system 100 may use the memory services of the memory subsystem 110 to communicate storage access messages.

[0108] At block 201 , a connection 103 is established between a host system 120 and a memory subsystem 110 .

[0109] For example, the memory subsystem 110 (eg, a solid state drive) and the host system 120 may be connected via at least one physical connection 103 .

[0110] For example, connection 103 may be implemented according to the Compute Express Link (CXL) standard to support both cache coherent memory access protocol 145 and storage access protocol 147 .

[0111] At block 203 , a portion 141 of the random access memory 138 of the memory subsystem 110 is attached as a memory device accessible by the host system 120 over the connection 103 using a first cache coherent memory access protocol 145 .

[0112] For example, memory subsystem 110 may optically carve out a portion (e.g., loadable portion 141) of its fast random access memory (e.g., 138) as a memory device attached to host system 120 via connection 103. Memory subsystem 110 may reserve another portion of its fast random access memory (e.g., 138) as buffer memory 149 for internal use by its processing device (e.g., 117).

[0113] Optionally, the memory subsystem 110 may have a backup power supply 105 designed to ensure that data stored in at least a portion of the volatile random access memory 138 is preserved in the non-volatile memory 139 when power to the memory subsystem 110 is interrupted. Thus, this portion of the volatile random access memory 138 can be considered non-volatile in the memory services of the host system 120.

[0114] At block 205 , the memory subsystem 110 uses the non-volatile memory 139 of the memory subsystem 110 to provide storage services accessible over the connection 103 using the second protocol 147 for storage access.

[0115] For example, memory subsystem 110 may configure a portion (eg, readable portion 143 ) of its memory resources (eg, nonvolatile memory 139 ) as a storage device attached to host system 120 via connection 103 .

[0116] At block 207 , one or more memory access queues 134 are configured in a memory device implemented using a portion of the random access memory 138 of the memory subsystem 110 .

[0117] For example, one or more memory access queues 134 are configured in the loadable portion 141 of the memory subsystem 110. Therefore, the host system 120 can access the one or more memory access queues 134 via the connection 103 using the first cache coherent memory access protocol 145; and the processing device 117 of the memory subsystem 110 can locally access the one or more memory access queues 134 within the memory subsystem 110.

[0118] Optionally, the second storage access queue 133 may be configured in the memory 129 of the host system 120. The memory subsystem 110 may access the second storage access queue 133 through the connection 103 using the second storage access protocol 147.

[0119] At block 209 , the memory subsystem 110 receives a memory access message from the host system 120 in one or more memory access queues 134 using the first protocol 145 for cache coherent memory access.

[0120] For example, a storage access message may be transmitted from the host system 120 to the memory subsystem 110 via the connection 103 using the second storage access protocol 147. Therefore, the host system 120 may choose to store the storage access message in one or more storage access queues 134 in the fast random access memory 138 of the memory subsystem 110 via the connection 103 using the first cache coherent memory access protocol 145, or choose to store the storage access message in a second storage access queue 133 configured in the memory 129 of the host system 120 for retrieval by the memory subsystem 110 via the connection 103 using the second storage access protocol 147.

[0121] For example, the host system 120 may optionally assign one or more storage access queues (e.g., 133) to storage services associated with requests from a first routine or application running in the host system 120, and assign a second storage access queue (e.g., 134) to storage services associated with requests from a second routine or application running in the host system 120.

[0122] For example, host system 120 may optionally allocate one or more storage access queues configured in memory subsystem 110 for communicating read and write commands, and allocate a second storage access queue configured in host system 120 for communicating data retrieved via read commands and data written via write commands.

[0123] For example, the host system 120 may optionally allocate a second storage access queue configured in the memory 129 of the host system 120 for communicating read commands and write commands, and allocate one or more storage access queues configured in the faster random access memory 138 of the memory subsystem 110 for communicating data retrieved via read commands and data written via write commands.

[0124] At block 211 , the memory subsystem 110 performs memory access operations in the non-volatile memory 139 of the subsystem 110 using memory access messages in one or more memory access queues.

[0125] For example, the storage access message may include a read command 195 ; and the storage access operation may include executing the read command 195 to retrieve the first data 197 from the non-volatile memory 139 of the memory subsystem 110 .

[0126] After executing the read command 195, the memory subsystem 110 may be configured via the firmware 153 to provide the first data 197 in a memory device attached by the memory subsystem 110 via the connection 103 for retrieval by the host system 120 using the first protocol 145 for cache coherent memory access. For example, the first data 197 may be provided to the host system 120 via one or more storage access queues 134 configured in the loadable portion 141 of the memory subsystem 110, as in Figure 5 middle.

[0127] Alternatively, the memory subsystem 110 may provide the first data 197 from the buffer memory 149 of the memory subsystem 110 to the host system 120 via the connection 103 using the second protocol 147 for storage access, as in Figure 7 middle.

[0128] For example, the storage access message may include a write command 191. To execute the write command 191, the memory subsystem 110 receives second data 193 from the host system 120 via the connection 103 using the first protocol 145 for cache coherent memory access. The storage access operation includes executing the write command 191 to write the second data 193 to the non-volatile memory 139 of the memory subsystem 110. For example, the second data 193 may be received in one or more storage access queues 134 from the host system 120 via the connection 103 using the first protocol 145 for cache coherent memory access, as in Figure 4 middle.

[0129] Alternatively, to execute the write command 191, the memory subsystem 110 may receive the second data 193 written via the write command 191 from the host system 120 via the connection 103 using the second protocol 147 for storage access, as in Figure 6 The storage access operation may include executing a write command 191 to write the second data 193 into the non-volatile memory 139 of the memory subsystem 110 .

[0130] For example, the storage access message may include second data 193 written via a write command 191. The write command 191 may be received via one or more storage access queues 134 configured in the memory subsystem 110 or a second storage access queue 133 configured in the memory 129 of the host system.

[0131] For example, the storage access message may include first data 197 retrieved from the readable portion 143 via a read command 195. The read command 195 may be received via one or more storage access queues 134 configured in the memory subsystem 110 or a second storage access queue 133 configured in the memory 129 of the host system.

[0132] In general, the memory subsystem 110 can be a storage device, a memory module, or a mixture of storage devices and memory modules. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual inline memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual inline memory modules (NVDIMMs).

[0133] The computing system 100 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a portion of a vehicle (such as an airplane, drone, train, car, or other transportation vehicle), an Internet of Things (IoT) enabled device, an embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device.

[0134] Computing system 100 may include a host system 120 coupled to one or more memory subsystems 110 . Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0135] For example, host system 120 may include a processor chipset (e.g., processing device 127) and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches (e.g., 123), a memory controller (e.g., controller 125) (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to and read data from memory subsystem 110.

[0136] The host system 120 can be coupled to the memory subsystem 110 via a physical host interface 113. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel interface, a Serial Attached SCSI (SAS) interface, a Double Data Rate (DDR) memory bus interface, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), an Open NAND Flash Interface (ONFI), a Double Data Rate (DDR) interface, a Low Power Double Data Rate (LPDDR) interface, a Compute Express Link (CXL) interface, or any other interface. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., the memory device 109). The physical host interface may provide an interface for passing control, address, data, and other signals between the memory subsystem 110 and the host system 120 . Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems through the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0137] The processing device 127 of the host system 120 may be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some examples, the controller 125 may be referred to as a memory controller, a memory management unit, and / or an initiator. In one example, the controller 125 controls communications via a bus coupled between the host system 120 and the memory subsystem 110. Generally, the controller 125 may send commands or requests to the memory subsystem 110 to access the memory devices 109, 107. The controller 125 may further include interface circuitry for communicating with the memory subsystem 110. The interface circuitry may convert responses received from the memory subsystem 110 into information for the host system 120.

[0138] The controller 125 of the host system 120 can communicate with the controller 115 of the memory subsystem 110 to perform operations such as reading, writing, or erasing data at the memory devices 109, 107, and other such operations. In some examples, the controller 125 is integrated into the same package as the processing device 127. In other examples, the controller 125 is separate from the package of the processing device 127. The controller 125 and / or the processing device 127 may include hardware, such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, cache memory, or a combination thereof. The controller 125 and / or the processing device 127 may be a microcontroller, dedicated logic circuitry (such as a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0139] Memory devices 109, 107 may include any combination of different types of non-volatile memory components and / or volatile memory components. Volatile memory devices, such as memory device 107, may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0140] Some examples of nonvolatile memory devices include NAND (or NOT AND) flash memory and write-in-place memory, such as three-dimensional cross-point ("3D cross-point") memory. Cross-point nonvolatile memory arrays can perform bit storage based on bulk resistance changes in conjunction with a stacked cross-grid data access array. In addition, compared to many flash-based memories, cross-point nonvolatile memory can perform write-in-place operations, where nonvolatile memory cells can be programmed without first erasing the nonvolatile memory cells. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0141] Each of the memory devices 109 may include one or more memory cell arrays. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cells (MLC), triple-level cells (TLC), quad-level cells (QLC), and quintuple-level cells (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 109 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include an SLC portion, an MLC portion, a TLC portion, a QLC portion, and / or a PLC portion of memory cells. The memory cells of the memory devices 109 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. With some types of memory, such as NAND, pages may be grouped to form blocks.

[0142] Although non-volatile memory devices such as 3D cross-point and NAND-type memories (e.g., 2D NAND, 3D NAND) are described, the memory device 109 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0143] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 109 to perform operations such as reading data, writing data, or erasing data at the memory device 109 and other such operations (e.g., in response to commands dispatched by the controller 125 on a command bus). The controller 115 may include hardware such as one or more integrated circuits (ICs) and / or discrete components, buffer memory, or a combination thereof. The hardware may include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

[0144] The controller 115 may include a processing device 117 (processor) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0145] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG has been described as including a controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0146] In general, the controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 109. The controller 115 may be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBAs), namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 109. The controller 115 may further include host interface circuitry that communicates with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory device 109, and also convert responses associated with the memory device 109 into information for the host system 120.

[0147] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive addresses from the controller 115 and decode the addresses to access the memory device 109.

[0148] In some embodiments, memory device 109 includes a local media controller 137 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 109. An external controller (e.g., memory subsystem controller 115) can externally manage memory device 109 (e.g., perform media management operations on memory device 109). In some embodiments, memory device 109 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local media controller 137) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0149] In one embodiment, a computer system is an example machine in which a set of instructions for causing a machine to perform any one or more of the methodologies discussed herein may be executed. In some embodiments, the computer system may correspond to a host system (e.g., Figure 1 host system 120) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 Memory subsystem 110) or may be used to perform the operations discussed above (e.g., execute instructions to perform operations corresponding to reference Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines. The machine may operate in the capacity of a server or a client user machine in server-client user network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client user machine in a cloud computing infrastructure or environment.

[0150] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or bridge, a network attached storage facility, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. Furthermore, while a single machine is described, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0151] An example computer system includes a processing device, a main memory (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM)), etc.), and a data storage system, which communicate with each other via a bus (which may include multiple buses).

[0152] The term "processing device" refers to one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets or a combination of instruction sets. The processing device may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device is configured to execute instructions for performing the operations and steps discussed herein. The computer system may further include a network interface device for communicating over a network.

[0153] The data storage system may include a machine-readable medium (also referred to as a computer-readable medium) on which is stored one or more sets of instructions or software embodying any one or more of the methodologies or functions described herein. The instructions may also reside completely or at least partially within the main memory and the processing device during their execution by the computer system, the main memory and the processing device also constituting machine-readable storage media. The machine-readable medium, data storage system, and / or main memory may correspond to Figure 1 Memory subsystem 110.

[0154] In one embodiment, the instructions include instructions for implementing the functionality discussed above (e.g., referring to Figure 1 Although the machine-readable medium is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be taken to include any medium that is capable of storing or encoding a set of instructions that is executed by a machine and causes the machine to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" should accordingly be taken to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0155] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. Operations are those requiring physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0156] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may involve actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0157] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of magnetic disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0158] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with the programs according to the teachings herein, or it may prove convenient to construct more specialized apparatus to perform the methods. The structures of various such systems will appear as set forth in the description below. Additionally, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present disclosure as described herein.

[0159] The present disclosure may be provided as a computer program product or software that may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform processes according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, or the like.

[0160] In this description, various functions and operations are described as being performed or caused by computer instructions to simplify the description. However, those skilled in the art will recognize that such expressions mean that the functions are generated by one or more controllers or processors (e.g., microprocessors) executing computer instructions. Alternatively, or in combination, the functions and operations may be implemented using dedicated circuitry with or without software instructions, such as using an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). Embodiments may be implemented using hard-wired circuitry without or in combination with software instructions. Therefore, the technology is not limited to any specific combination of hardware circuitry and software, nor to any specific source of instructions executed by the data processing system.

[0161] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be appreciated that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. The specification and drawings are accordingly to be regarded as illustrative rather than restrictive.

Claims

1. A method comprising: establishing a connection between a host system and a memory subsystem; attaching a portion of the random access memory of the memory subsystem as a memory device accessible by the host system over the connection using a first cache coherent memory access protocol; providing, by the memory subsystem, using the non-volatile memory of the memory subsystem, a storage service accessible over the connection using a second storage access protocol; configuring one or more memory access queues in the memory device implemented using the portion of the random access memory of the memory subsystem; receiving a storage access message from the host system using the first protocol for cache coherent memory access in the one or more storage access queues; and A memory access operation is performed by the memory subsystem in the non-volatile memory of the subsystem using the memory access messages in the one or more memory access queues.

2. The method of claim 1, wherein the connection is in accordance with the Compute Express Link (CXL) standard. 3 . The method of claim 2 , wherein the storage access message is transmittable from the host system to the memory subsystem over the connection using the second protocol for storage access.

4. The method of claim 3, wherein the storage access message comprises a read command; and the storage access operation comprises executing the read command to retrieve first data from the non-volatile memory of the memory subsystem.

5. The method according to claim 4, further comprising: The first data is provided by the memory subsystem in the memory device for retrieval using the first protocol of cache coherent memory access. The method of claim 5 , wherein the first data is provided in the one or more storage access queues.

7. The method according to claim 4, further comprising: The first data is provided by the memory subsystem to the host system over the connection using the second protocol for storage access.

8. The method of claim 3, wherein the storage access message comprises a write command; and the method further comprising: Second data is received by the memory subsystem from the host system over the connection using the first protocol of cache coherent memory access, wherein the storage access operation includes executing the write command to write the second data to the non-volatile memory of the memory subsystem.

9. The method of claim 8, wherein the second data is received in the one or more storage access queues from the host system over the connection using the first protocol for cache coherent memory access.

10. The method of claim 3, wherein the storage access message comprises a write command; and the method further comprising: Second data is received by the memory subsystem from the host system over the connection using the second protocol for storage access, wherein the storage access operation includes executing the write command to write the second data to the non-volatile memory of the memory subsystem.

11. A memory subsystem comprising: a host interface operable in connection with a host system; volatile memory, wherein the memory subsystem is operable to allocate a portion of the volatile memory to provide memory services to the host system over the connection using a first protocol for cache coherent memory access; a non-volatile memory operable to provide storage services to the host system via the connection using a second protocol for storage access; and A controller configured to: establishing one or more memory access queues in the volatile memory; communicating a first storage access message with the host system via the one or more storage access queues over the connection using the first cache coherent memory access protocol; and The storage service is provided using the first storage access message communicated from the host system over the connection utilizing the first protocol for cache coherent memory access.

12. The memory subsystem of claim 11, wherein the connection is a Compute Express Link (CXL) connection.

13. The memory subsystem of claim 11 , wherein the controller is further configured to communicate a second storage access message with the host system via a storage access queue configured in a memory of the host system over the connection using the second storage access protocol; and the storage service is further provided based on the second storage access message.

14. The memory subsystem of claim 13, wherein the second storage access message comprises a read command; and the first storage access message comprises first data retrieved from the non-volatile memory via execution of the read command.

15. The memory subsystem of claim 14, wherein the second storage access message comprises a write command; and the first storage access message comprises second data written into the nonvolatile memory via execution of the write command.

16. The memory subsystem of claim 13, wherein the first storage access message includes read or write command data that is retrieved from or written into the nonvolatile memory via execution of the read or write command.

17. A non-transitory computer storage medium storing instructions that, when executed in a computing system, cause the computing system to perform a method comprising: establishing a connection between a host system of the computing system and a memory subsystem of the computing system; configuring one or more memory access queues in a memory device attached by the memory subsystem to the host system via the connection; and communicating a first storage access message between the host system and the memory subsystem via the one or more storage access queues over the connection using a first protocol for cache coherent memory access; Wherein the memory subsystem is configured to provide storage services using the first storage access message communicated from the host system over the connection utilizing the first protocol for cache coherent memory access.

18. The non-transitory computer storage medium of claim 17, wherein the method further comprises: configuring a second storage access queue in a memory of the host system; and A second storage access message is communicated between the host system and the memory subsystem via the second storage access queue over the connection using a second protocol for storage access.

19. The non-transitory computer storage medium of claim 18, wherein the method further comprises: assigning the one or more storage access queues to storage services associated with requests from a first routine or application; and The second storage access queue is assigned to a storage service associated with a request from a second routine or application.

20. The non-transitory computer storage medium of claim 18, wherein the connection is a Compute Express Link (CXL) connection.

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