Radar echo simulation method and device, electronic equipment and storage medium

Through the ping-pong storage and FIFO queue architecture, the problem of pulse loss in the DRFM architecture in the pulse Doppler radar is solved, and the accuracy of Doppler radar testing and calibration is improved.

CN120652407APending Publication Date: 2025-09-16HUNAN ECONOVEL TECH CO LTD
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Patent Information

Application Number
CN202510891093.X
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-06-30
Publication Date
2025-09-16

AI Technical Summary

Technical Problem

The existing DRFM architecture suffers from pulse loss when dealing with pulse Doppler radar, which affects the detection function and speed measurement accuracy.

Method used

It adopts ping-pong storage and FIFO queue architecture, copies radar signals and solves them according to target speed and distance, and uses cyclic switching to store and read signals in the FIFO queue to ensure data delay consistency and avoid pulse loss.

Benefits of technology

The accuracy of Doppler radar testing and calibration is improved, ensuring that output data is strictly consistent with input data, avoiding pulse loss, and improving the accuracy of detection and speed measurement.

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Abstract

The invention provides a radar echo simulation method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a radar signal, copying the radar signal, and obtaining a first signal and a second signal; according to the target speed and the target distance in the scene, the echo time delays of the current beat and the next beat are solved, and a solving result is obtained; respectively receiving the first signal and the second signal through an FIFO queue according to a resolving result; according to the time takt, the first signal and the second signal in the FIFO queue are stored and read in a circulating switching mode, and a radar echo simulation result is obtained. The method has the beneficial effect that the accuracy of Doppler radar testing and calibration is improved.
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Description

Technical Field

[0001] The present invention relates to the technical field of radar signal simulation, and in particular to a radar echo simulation method, device, electronic equipment and storage medium. Background Art

[0002] Currently, radar echo simulators are used for radar testing and calibration. They receive electromagnetic wave signals transmitted by the radar and perform delay and Doppler modulation to simulate targets at different distances and speeds. The radar receives the modulated electromagnetic wave signals forwarded by the echo simulator and processes them to obtain the target's distance and speed parameters. These values ​​are then compared with the set values ​​to evaluate the radar's functionality and performance.

[0003] The echo simulator of DRFM architecture is as follows Figure 1 As shown in the figure, the radar echo simulator receives radar signals through the antenna and converts the RF signal to an intermediate frequency (IF) through a downconversion module. The AD device digitizes the analog signal, stores it, and performs time delay and Doppler frequency modulation before forwarding it to the DA device. The DA device performs digital-to-analog conversion to generate an IF analog signal. Finally, the signal is converted to RF through an upconversion module and radiated through the antenna.

[0004] The storage and reading timing diagram of the DRFM architecture is as follows Figure 2 As shown, when a radar signal is detected, the pulse signal is stored and, after a corresponding time delay τ, the modulated signal, i.e., the echo pulse signal, is forwarded.

[0005] This store-and-forward architecture will have the problem of pulse loss when dealing with pulse Doppler radar. Because pulse Doppler radar generally operates in range ambiguity mode, it does not need to wait until the echo signal is received before transmitting the next radar signal. The relevant timing is as follows Figure 3 As shown in the figure, the radar receives a severely missing pulse sequence, which affects the detection function and ambiguities the speed measurement. In other words, this architecture is not suitable for pulse Doppler radar. Summary of the Invention

[0006] The main purpose of the embodiments of the present invention is to provide a radar echo simulation method, device, electronic device and storage medium, which improve the accuracy of Doppler radar testing and calibration.

[0007] One aspect of the present invention provides a radar echo simulation method, comprising:

[0008] Acquire a radar signal, and copy the radar signal to obtain a first signal and a second signal;

[0009] According to the target speed and target distance in the scene, the echo delay between the current beat and the next beat is solved to obtain the solution result;

[0010] According to the solution result, the first signal and the second signal are received through the FIFO queue respectively;

[0011] According to the time beat, the first signal and the second signal in the FIFO queue are stored and read respectively in a cyclic switching manner to obtain the radar echo simulation result.

[0012] According to the radar echo simulation method, the radar signal is a Doppler radar signal.

[0013] According to the radar echo simulation method, the echo delay between the current beat and the next beat is calculated based on the target speed and target distance in the scene, and the calculation result is obtained, including:

[0014] The solution for this beat is:

[0015]

[0016] Among them, C is the propagation speed of electromagnetic waves, R is the target distance, and the solution result τ is the delay of this beat;

[0017] The solution for the next beat is:

[0018]

[0019] Where Δt is the beat interval, v is the target speed, and the calculated result τ′ is the delay to the next beat.

[0020] According to the radar echo simulation method, the first signal and the second signal are received through FIFO queues respectively according to the solution result, including:

[0021] A FIFO queue with a depth of τ is used to receive the first signal, and a FIFO queue with a depth of τ′ is used to receive the second signal.

[0022] According to the radar echo simulation method, according to the time beat, the first signal and the second signal in the FIFO queue are stored and read respectively in a cyclic switching manner, including:

[0023] Using a FIFO queue with a depth of τ to send the first signal to the analog-to-digital converter, and using a FIFO queue with a depth of τ′ to store the second signal;

[0024] After the current time beat ends, it switches to the FIFO queue with a depth of τ′, and sends the second signal to the analog-to-digital converter through the FIFO queue with a depth of τ′.

[0025] According to the radar echo simulation method, the method further includes:

[0026] Each time a switch occurs, the FIFO queue with a depth of τ is reset, and the depth of the FIFO queue with a depth of τ is adjusted to τ′ through calculation.

[0027] According to the radar echo simulation method, the method further includes:

[0028] The radar signals are repeatedly written into and read out of the two FIFO queues in a cyclic switching manner until the radar echo simulation result is obtained.

[0029] Another aspect of an embodiment of the present invention provides a radar echo simulation device, comprising:

[0030] The first module is configured to acquire a radar signal and replicate the radar signal to obtain a first signal and a second signal;

[0031] The second module is used to calculate the echo delay between the current beat and the next beat according to the target speed and target distance in the scene to obtain the solution result;

[0032] The third module is configured to receive the first signal and the second signal through a FIFO queue respectively according to the solution result;

[0033] The fourth module is used to store and read the first signal and the second signal in the FIFO queue respectively in a cyclic switching manner according to the time beat to obtain the radar echo simulation result.

[0034] Another aspect of an embodiment of the present invention provides an electronic device, including a processor and a memory;

[0035] The memory is used to store programs;

[0036] The processor executes the program to implement the method described above.

[0037] Embodiments of the present invention further disclose a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device can read the computer instructions from the computer-readable storage medium and execute the computer instructions, causing the computer device to perform the method described above.

[0038] The beneficial effects of the present invention are as follows: a storage architecture of ping-pong storage and FIFO is adopted to simultaneously write and read data; by making the depth of the FIFO the same as the required delay, data is synchronously and continuously read at the tail of the FIFO and forwarded to the DA device for output; this architecture adopts a pipeline operation mode, which can ensure that the output data is strictly the same as the input data, and no pulses are left behind except for the required delay, thereby improving the accuracy of Doppler radar testing and calibration. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0040] Figure 1 This is a schematic diagram of the DRFM architecture of the radar echo simulator.

[0041] Figure 2 This is the storage and reading timing diagram of the DRFM architecture.

[0042] Figure 3 is the forwarding timing of the pulse Doppler radar signal.

[0043] Figure 4 4 is a schematic diagram of a radar echo simulation process according to an embodiment of the present invention.

[0044] Figure 5 2 is a schematic diagram of a cyclic switching process according to an embodiment of the present invention.

[0045] Figure 6 This is a synchronous store-and-forward timing diagram of an embodiment of the present invention.

[0046] Figure 7 2 is a diagram of a ping-pong storage architecture according to an embodiment of the present invention.

[0047] Figure 8 Schematic diagram of a radar echo simulation device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. In the subsequent description, suffixes such as "module," "component," or "unit" used to represent elements are used solely to facilitate the description of the present invention and have no specific meaning in themselves. Therefore, "module," "component," or "unit" may be used interchangeably. "First," "second," and the like are used solely to distinguish technical features and should not be construed as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features. In this subsequent description, the consecutive numbering of method steps is for ease of review and understanding. In conjunction with the overall technical solution of the present invention and the logical relationship between the various steps, adjusting the order of implementation of the steps does not affect the technical effects achieved by the technical solution of the present invention. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and should not be construed as limiting the present invention.

[0049] refer to Figure 4 , Figure 4 1 is a schematic diagram of a radar echo simulation process according to an embodiment of the present invention, which includes but is not limited to steps S100 to S400:

[0050] S100: Acquire a radar signal, and copy the radar signal to obtain a first signal and a second signal.

[0051] In some embodiments, the radar signal is a pulse Doppler radar signal.

[0052] S200 , calculating the echo delay between the current beat and the next beat according to the target speed and target distance in the scene to obtain a calculation result.

[0053] In some embodiments, it includes calculating the time delay between the current beat and the next beat. In order to simulate the dynamic target of the scene, it is necessary to solve the target distance and target speed to obtain the time delay between the current beat and the next beat.

[0054] In some embodiments, the solution for this beat is:

[0055]

[0056] Among them, C is the propagation speed of electromagnetic waves, R is the target distance, and the solution result τ is the delay of this beat;

[0057] The solution for the next beat is:

[0058]

[0059] Where Δt is the beat interval, v is the target speed, and the calculated result τ′ is the delay to the next beat.

[0060] S300: According to the calculation result, the first signal and the second signal are received through the FIFO queue respectively.

[0061] In some embodiments, a FIFO queue with a depth of τ is used to receive the first signal, and a FIFO queue with a depth of τ′ is used to receive the second signal simultaneously.

[0062] S400 , storing and reading the first signal and the second signal in the FIFO queue in a cyclic switching manner according to a time rhythm, to obtain a radar echo simulation result.

[0063] In some embodiments, reference Figure 5 The schematic diagram of the cyclic switching process shown includes but is not limited to steps S410 to S420:

[0064] S410, using a FIFO queue with a depth of τ to send the first signal to the analog-to-digital converter, and using a FIFO queue with a depth of τ′ to store the second signal;

[0065] S420 , after the current time beat ends, switch to the FIFO queue with a depth of τ′, and send the second signal to the analog-to-digital converter through the FIFO queue with a depth of τ′.

[0066] In some embodiments, reference Figure 6 As shown in the synchronous store-and-forward timing diagram, when setting a dynamic target scenario, the echo delay needs to be adjusted based on the target's speed. In this case, the FIFO needs to be reset on a tick basis and its depth adjusted to correspond to the new delay requirement. When the FIFO is reset, all stored data is lost, and the echo simulator briefly stops outputting pulses. This lasts approximately the same amount of time as the target's set delay.

[0067] It is understandable that in order to minimize the time of pulse loss as much as possible, the ping-pong storage architecture proposed in this application can seamlessly connect the FIFO parameter switching. Under this architecture, two FIFOs are maintained at the same time. The digital signal input by AD is copied and written to the two FIFOs at the same time. The depth of FIFO1 corresponds to the delay of the current beat, and the depth of FIFO2 corresponds to the delay of the next beat. In the current beat, the data of FIFO1 is output to DA. When this beat ends, it switches to FIFO2, which can achieve instantaneous switching to ensure the continuous output of the echo pulse signal.

[0068] In some embodiments, reference Figure 7 The ping-pong storage architecture diagram shows some of the steps as follows:

[0069] AD inputs data and writes it into FIFO1 and FIFO2 at the same time, and reads data from FIFO1 and sends it to DA.

[0070] Timing, when the time beat is met, switch the storage space, read data from FIFO2 and send it to DA.

[0071] Synchronously reset FIFO1 and set its depth to

[0072]

[0073] Repeat AD input data until the simulation ends.

[0074] Figure 8 FIG. 8 is a schematic diagram of a radar echo simulation device according to an embodiment of the present invention. The device includes a first module 810 , a second module 820 , a third module 830 and a fourth module 840 .

[0075] Among them, the first module is used to obtain the radar signal, copy the radar signal to obtain the first signal and the second signal; the second module is used to solve the echo delay of the current beat and the next beat according to the target speed and target distance in the scene to obtain the solution result; the third module is used to receive the first signal and the second signal respectively through the FIFO queue according to the solution result; the fourth module is used to store and read the first signal and the second signal in the FIFO queue respectively in a cyclic switching manner according to the time beat to obtain the radar echo simulation result.

[0076] For example, with the cooperation of the first to fourth modules in the device, the embodiment device can implement any of the aforementioned radar echo simulation methods, namely, acquiring a radar signal, replicating the radar signal to obtain a first signal and a second signal; solving the echo delay of the current beat and the next beat according to the target speed and target distance in the scene to obtain a solution result; receiving the first signal and the second signal through a FIFO queue according to the solution result; and storing and reading the first signal and the second signal in the FIFO queue in a cyclic switching manner according to the time beat to obtain a radar echo simulation result. The beneficial effects of the present invention are: using a ping-pong storage and FIFO storage architecture to write and read data simultaneously; with the FIFO depth being the same as the required delay, synchronously and continuously reading data at the end of the FIFO and forwarding it to the DA device for output; this architecture adopts a pipeline operation mode, which can ensure that the output data is strictly identical to the input data, and no pulses are left behind except for the required delay, thereby improving the accuracy of Doppler radar testing and calibration.

[0077] An embodiment of the present invention further provides an electronic device, the electronic device including a processor and a memory;

[0078] The memory stores a program;

[0079] The processor executes the program to perform the aforementioned radar echo simulation method; the electronic device has the function of carrying and running the radar echo simulation software system provided by the embodiment of the present invention, for example, a personal computer, a minicomputer, a main frame, a workstation, a network or distributed computing environment, a separate or integrated computer platform, or communicates with a charged particle tool or other imaging device, etc.

[0080] An embodiment of the present invention further provides a computer-readable storage medium, wherein the storage medium stores a program, and the program is executed by a processor to implement the radar echo simulation method as described above.

[0081] In some optional embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the present invention is provided in an exemplary manner for the purpose of providing a more comprehensive understanding of the technology. The disclosed method is not limited to the operation and logic flow presented herein. Optional embodiments are contemplated in which the order of the various operations is changed and the sub-operations described as a part of a larger operation are performed independently.

[0082] Embodiments of the present invention further disclose a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. A processor of a computer device can read the computer instructions from the computer-readable storage medium and execute the computer instructions, causing the computer device to perform the aforementioned radar echo simulation method.

[0083] Furthermore, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise indicated, one or more of the functions and / or features described may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in separate physical devices or software modules. It will also be understood that a detailed discussion of the actual implementation of each module is not necessary for understanding the present invention. More specifically, given the properties, functions, and internal relationships of the various functional modules in the devices disclosed herein, the actual implementation of the module will be understood within the ordinary skill of an engineer. Therefore, a person skilled in the art using ordinary skill will be able to implement the present invention set forth in the claims without undue experimentation. It will also be understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0084] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0085] The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (e.g., a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device). For purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by, or in conjunction with, an instruction execution system, apparatus, or device.

[0086] More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection with one or more wires (electronic devices), a portable computer disk cartridge (magnetic devices), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), a fiber optic device, and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering, or processing in another suitable manner as necessary, and then stored in a computer memory.

[0087] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0088] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0089] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to the embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the claims and their equivalents.

[0090] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A radar echo simulation method, characterized in that: include: Acquire a radar signal, and copy the radar signal to obtain a first signal and a second signal; According to the target speed and target distance in the scene, the echo delay between the current beat and the next beat is solved to obtain the solution result; According to the solution result, the first signal and the second signal are received through the FIFO queue respectively; According to the time beat, the first signal and the second signal in the FIFO queue are stored and read respectively in a cyclic switching manner to obtain the radar echo simulation result.

2. The radar echo simulation method according to claim 1, characterized in that: The radar signal is a Doppler radar signal.

3. The radar echo simulation method according to claim 1, characterized in that: The echo delay between the current beat and the next beat is calculated based on the target speed and target distance in the scene to obtain the calculation result, including: The solution for this beat is: Among them, C is the propagation speed of electromagnetic waves, R is the target distance, and the solution result τ is the delay of this beat; The solution for the next beat is: Where Δt is the beat interval, v is the target speed, and the calculated result τ′ is the delay to the next beat.

4. The radar echo simulation method according to claim 3, characterized in that: The receiving the first signal and the second signal respectively through the FIFO queue according to the solution result includes: A FIFO queue with a depth of τ is used to receive the first signal, and a FIFO queue with a depth of τ′ is used to receive the second signal.

5. The radar echo simulation method according to claim 4, characterized in that: The method of storing and reading the first signal and the second signal in the FIFO queue in a cyclic switching manner according to the time beat includes: Using a FIFO queue with a depth of τ to send the first signal to the analog-to-digital converter, and using a FIFO queue with a depth of τ′ to store the second signal; After the current time beat ends, it switches to the FIFO queue with a depth of τ′, and sends the second signal to the analog-to-digital converter through the FIFO queue with a depth of τ′.

6. The radar echo simulation method according to claim 5, characterized in that: The method further comprises: Each time a switch occurs, the FIFO queue with a depth of τ is reset, and the depth of the FIFO queue with a depth of τ is adjusted to τ′ through calculation.

7. The radar echo simulation method according to claim 1, characterized in that: The method further comprises: The radar signals are repeatedly written into and read out of the two FIFO queues in a cyclic switching manner until the radar echo simulation result is obtained.

8. A radar echo simulation device, characterized in that: include: The first module is configured to acquire a radar signal and replicate the radar signal to obtain a first signal and a second signal; The second module is used to calculate the echo delay between the current beat and the next beat according to the target speed and target distance in the scene to obtain the solution result; The third module is configured to receive the first signal and the second signal through a FIFO queue respectively according to the solution result; The fourth module is used to store and read the first signal and the second signal in the FIFO queue respectively in a cyclic switching manner according to the time beat to obtain the radar echo simulation result.

9. An electronic device, characterized in that: including a processor and a memory; The memory is used to store programs; The processor executes the program to implement the radar echo simulation method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The storage medium stores a program, and the program is executed by a processor to implement the radar echo simulation method according to any one of claims 1 to 7.

Citation Information

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