Packing method and system for improving cross-die transmission efficiency and storage medium

Abstract

The application relates to a package grouping method and system for improving cross-DIE transmission efficiency and a storage medium. The method comprises the following steps: selecting a pipeline according to a preset pipeline arbitration level through an arbitrator; reading FIFO queue depths of entries contained in three transmission channels of a request, a response and data, wherein the number of available entries is recorded through a first counter, and the number of sent entries is recorded through a second counter; determining an optimal format for entry package grouping according to the values of the first and second counters; reading entries from different FIFO queues according to the optimal format and writing the entries into corresponding slot positions of frame segments; and transmitting the frame segments completing package grouping to a package transmitter and further to a physical layer of the pipeline to complete package transmission. The application realizes pipeline bidirectional fairness, multi-channel queuing fairness, channel flow control, and the trade-off between package utilization and delay from the package grouping logic, and meets the high-frequency timing requirements of the DIE pipeline.

Description

Technical Field

[0001] This invention relates to the field of data transmission technology, and in particular to a packet assembly method, system, and storage medium for improving cross-DIE transmission efficiency. Background Technology

[0002] CXL (Compute Express Link) is an open standard high-speed interconnect protocol that inherits the physical layer of PCIe (Peripheral Component Interconnect Express) to provide cache-consistent, low-latency, high-bandwidth communication between the host processor and additional devices (such as memory expansion cards and accelerators). The CXL.cache protocol stack provides cache-consistent load and storage semantics between the host and devices for accessing remote caches or device memory.

[0003] In CXL.cache operations, the transaction layer needs to generate various variable-sized data packets (such as cache line requests, responses with data, etc.) and then segment or aggregate them into fixed-length frame fragments for transmission at the link layer. In CXL 1.x and CXL 2.0, each frame fragment is 528 bits (66 bytes) long, containing several 16-byte slots and a 2-byte CRC checksum. Generally, each 528-bit frame fragment can hold a maximum of four 16-byte slots. Waiting until exactly four frame fragments or data are collected before sending a complete frame fragment maximizes bandwidth utilization but increases latency; sending partially filled frame fragments immediately wastes bandwidth and reduces effective throughput. Furthermore, CXL.cache's frame fragment assembly also needs to balance the traffic of the request (REQ), response (RESP), and data (DATA) channels in one link direction and achieve transmission fairness in both the host-to-device and device-to-host directions.

[0004] Various packet reassembly schemes exist, but these methods often rely on static priority enumeration or simple timeout degradation strategies, and fail to quantify the differences in sent counts for different message types into a unified dynamic ranking metric. In general, existing packet reassembly implementations do not fully integrate bidirectional fairness and multi-channel balance within a single system, and still have many areas for improvement in their details. Summary of the Invention

[0005] This invention provides a packet assembly method, system, and storage medium to improve cross-DIE transmission efficiency, aiming to solve the technical problem that existing packet assembly schemes are difficult to achieve pipelined bidirectional fair transmission and multi-data channel traffic balance.

[0006] To address the aforementioned technical problems, in a first aspect, the present invention provides a packet reassembly method for improving cross-DIE transmission efficiency, comprising the following steps:

[0007] S101. The arbitrator selects the pipeline that needs to be packetized and transmitted according to the preset pipeline arbitration level to start packet assembly. The preset pipeline arbitration level is used to determine the priority of different pipelines and the method of packet assembly. The pipeline includes a first-direction pipeline from host to device and a second-direction pipeline from device to host.

[0008] S102. Read the FIFO queue depth of each of the three transmission channels that need to be packetized: request, response, and data. For each FIFO queue, the number of available entries is recorded by a first counter, and for each transmission channel, the number of sent entries is recorded by a second counter.

[0009] S103. Determine the optimal format for packetizing entries from different transmission channels based on the values ​​of the first counter and the second counter corresponding to the three transmission channels: request, response, and data.

[0010] S104. Read entries from the FIFO queues corresponding to different transmission channels according to the optimal format and write them into the slots corresponding to the frame segments, and determine whether to complete the packet assembly of the frame segments according to the preset pipeline arbitration level.

[0011] S105. The completed frame segment is transmitted to the packet transmitter, and the completed frame segment is further transmitted to the physical layer of the pipeline through the packet transmitter to complete the packet transmission.

[0012] Furthermore, the preset pipeline arbitration level in step S101 specifically refers to:

[0013] Prioritize packet transmission in the first direction pipeline; or,

[0014] Prioritize packet transmission in the second direction pipeline; or,

[0015] Based on transmission requirements, either the first-direction pipeline or the second-direction pipeline is selected for packet assembly and transmission in a round-robin manner; or...

[0016] idle.

[0017] Furthermore, step S103 includes the following sub-steps:

[0018] S1031. Determine multiple preset formats for packaging the items contained in the three transmission channels of different quantities of requests, responses and data;

[0019] S1032. Based on the values ​​of the first counters corresponding to the three transmission channels of request, response and data, distinguish from the preset formats a first type of preset format that fully meets the item number requirement and a second type of preset format that partially meets the item number requirement.

[0020] S1033. Based on the values ​​of the second counters corresponding to the three transmission channels (request, response, and data), calculate the first weight value after packet assembly according to the preset format. Select the preset format corresponding to the maximum value of the first weight value as the optimal format. Define the first weight value as M1, which satisfies the following relationship:

[0021] M1 = (C_lowest - C_mid) + (C_lowest - C_highest);

[0022] C_lowest is the smallest value of the second counter corresponding to each of the three transmission channels (request, response, and data) after the packets are assembled according to the preset format; C_mid is the middle value of the second counter corresponding to each of the three transmission channels (request, response, and data) after the packets are assembled according to the preset format; and C_highest is the largest value of the second counter corresponding to each of the three transmission channels (request, response, and data) after the packets are assembled according to the preset format.

[0023] If the first type of preset format is not empty, the optimal format is selected from the first type of preset format; otherwise, the optimal format is selected from the second type of preset format.

[0024] Furthermore, if the first weight value M1 corresponding to multiple preset formats is the maximum, then based on the values ​​of the second counters corresponding to the three transmission channels of request, response, and data, the second weight value after packet assembly according to the preset format is calculated. The preset format corresponding to the maximum value of the second weight value is selected as the optimal format, and the second weight value is defined as M2, which satisfies the following relationship:

[0025] M2 = C_mid - C_highest.

[0026] Furthermore, if the current preset pipeline arbitration level is non-idle, then step S104 includes the following sub-steps:

[0027] S1041. For the pipeline that prioritizes packet assembly and transmission, determine whether the first type of preset format is not empty. If yes, proceed to step S1042; if no, proceed to step S1043.

[0028] S1042. Update the packet counter by incrementing its value by 1. Read entries from the FIFO queues corresponding to different transmission channels according to the optimal format. Write the read entries into the empty slots corresponding to the frame segments in sequence. At the same time, decrement the value of the preset timeout loop control threshold by 1. If all 4 slots of the frame segment have been filled with entries, proceed to step S1046. Otherwise, return to step S1041.

[0029] S1043. Determine whether the second type of preset format is not empty. If yes, proceed to step S1044; if no, proceed to step S1045.

[0030] S1044. Update the packet counter by incrementing its value by 1. Read entries from the FIFO queues corresponding to different transmission channels according to the optimal format. Write the read entries into the empty slots corresponding to the frame segments in sequence. At the same time, decrement the value of the preset timeout loop control threshold by 1. If all four slots of the frame segment have been filled with entries, proceed to step S1046. Otherwise, proceed to step S1045.

[0031] S1045. Determine whether the value of the package counter is less than the preset timeout loop control threshold. If yes, return to step S1041; if no, proceed to step S1046.

[0032] S1046. If the slot of the frame fragment for which the entry has been written is the first one, then modify the preset pipeline arbitration level to select the first direction pipeline or the second direction pipeline in a round-robin manner according to the transmission requirements for packet assembly and transmission.

[0033] If the slot of the frame segment for which the entry has been written is the 2nd or 3rd, then skip the slot of the frame segment that needs to be packaged and complete the packaging of the frame segment.

[0034] If the slot of the frame fragment for which the current entry has been written is the 4th slot, then the assembly of the frame fragment is completed.

[0035] Furthermore, the packet reassembly method for improving cross-DIE transmission efficiency also includes the following steps:

[0036] S106. An arbitration signal is issued through the arbitrator to modify the preset pipeline arbitration level.

[0037] Furthermore, for the pipeline that currently does not perform packet reassembly transmission, the packet reassembly method for improving cross-DIE transmission efficiency further includes the following steps:

[0038] S201. Determine whether the first type of preset format is not empty. If yes, proceed to step S202; if no, proceed to step S203.

[0039] S202. Update the packet counter by incrementing its value by 1. Read entries from the FIFO queues corresponding to different transmission channels according to the optimal format. Write the read entries into the empty slots corresponding to the frame segments in sequence. At the same time, update the packet counter by incrementing its value by 1. Unless all four slots of the frame segment have been filled with entries, return to step S201.

[0040] S203. If the slot of the frame segment to which the current entry has been written is the 4th, then the frame segment is packaged; otherwise, return to step S201.

[0041] Secondly, the present invention also provides a packet assembly system for improving cross-DIE transmission efficiency, comprising:

[0042] The arbitration module is used to select the pipeline that needs to be packetized and transmitted according to the preset pipeline arbitration level through the arbitrator to start packet assembly. The preset pipeline arbitration level is used to determine the priority of different pipelines and the method of packet assembly. The pipeline includes a first direction pipeline from host to device and a second direction pipeline from device to host.

[0043] The reading module is used to read the FIFO queue depth of each of the three transmission channels that need to be packetized: request, response, and data. For each FIFO queue, the number of available entries is recorded by a first counter, and for each transmission channel, the number of sent entries is recorded by a second counter.

[0044] The format module is used to determine the optimal format for assembling entries from different transmission channels based on the values ​​of the first counter and the second counter corresponding to the three transmission channels: request, response, and data.

[0045] The packet assembly module is used to read entries from the FIFO queues corresponding to different transmission channels according to the optimal format and write them into the slots corresponding to the frame segments, and determine whether to complete the packet assembly of the frame segments according to the preset pipeline arbitration level.

[0046] The transmission module is used to transmit the completed frame fragment to the packet transmitter, and further transmit the completed frame fragment to the physical layer of the pipeline through the packet transmitter to complete the packet transmission.

[0047] Thirdly, the present invention also provides a computer device, comprising: a memory, a processor, and a packet assembly program for improving cross-DIE transmission efficiency stored in the memory and executable on the processor, wherein the processor, when executing the packet assembly program for improving cross-DIE transmission efficiency, implements the steps of the packet assembly method for improving cross-DIE transmission efficiency as described in any of the above embodiments.

[0048] Fourthly, the present invention also provides a storage medium storing a packet assembly program for improving cross-DIE transmission efficiency, wherein the packet assembly program for improving cross-DIE transmission efficiency is executed by a processor to implement the steps of the packet assembly method for improving cross-DIE transmission efficiency as described in any of the above embodiments.

[0049] The beneficial effect achieved by this invention is that it proposes a packet assembly method based on the CXL.cache protocol stack to improve the efficiency of cross-DIE transmission. This packet assembly method realizes pipeline bidirectional fairness, multi-channel queuing fairness, channel flow control, and the trade-off between packet utilization and latency from the packet assembly logic, and meets the high-frequency timing requirements of the DIE pipeline. Attached Figure Description

[0050] Figure 1 This is a flowchart illustrating the steps of the packet assembly method for improving cross-DIE transmission efficiency provided in an embodiment of the present invention.

[0051] Figure 2 This is a schematic diagram of the complete package assembly logic of the priority pipeline provided in an embodiment of the present invention;

[0052] Figure 3 This is a schematic diagram of the priority pipeline packaging logic provided in an embodiment of the present invention;

[0053] Figure 4 This is a schematic diagram of the priority pipeline empty packet grouping logic provided in an embodiment of the present invention;

[0054] Figure 5 This is a schematic diagram of the complete non-priority pipeline assembly logic provided in an embodiment of the present invention;

[0055] Figure 6 This is a schematic diagram of the packet reassembly system for improving cross-DIE transmission efficiency provided in an embodiment of the present invention;

[0056] Figure 7 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0058] Please refer to Figure 1 , Figure 1 This is a flowchart illustrating the steps of a packet reassembly method for improving cross-DIE transmission efficiency provided in an embodiment of the present invention. The packet reassembly method for improving cross-DIE transmission efficiency includes the following steps:

[0059] S101. The arbitrator selects the pipeline that needs to be packetized and transmitted according to the preset pipeline arbitration level to start packet assembly. The preset pipeline arbitration level is used to determine the priority of different pipelines and the method of packet assembly. The pipeline includes a first-direction pipeline from host to device and a second-direction pipeline from device to host.

[0060] As described in the background section, the CXL.cache protocol stack provides cache consistency load and storage semantics between the host and device at both ends of the DIE (Silicon-based Core), enabling access to remote caches or device memory. The CXL protocol is full-duplex, and its pipeline includes both host-to-device (H2D) direction, allowing simultaneous sending of cache requests, and device-to-host (D2H) direction, allowing simultaneous return of cache responses and data.

[0061] The preset pipeline arbitration level in step S101 includes:

[0062] Prioritize packet delivery (H2D) in the first direction pipeline; or,

[0063] Prioritize packet transmission in the second direction pipeline (D2H); or,

[0064] Based on transmission requirements, either the first-direction pipeline or the second-direction pipeline is selected for packet assembly and transmission in a round-robin manner (BOTH); or...

[0065] Free (NONE).

[0066] It is understood that the preset pipeline arbitration level involved in this embodiment of the invention, "prioritizing packet transmission of the first direction pipeline," means that when both pipelines in both directions have packet transmission needs, packet transmission of one of them is prioritized. If the prioritized pipeline does not have a packet transmission need, the pipeline link data is available, and packet transmission of the non-priority pipeline can proceed. A simple idle state refers to the absence of a specific arbitration level; when any pipeline has a packet transmission need, the right to use the link is acquired through preemption. In this embodiment of the invention, the arbitrator adjusts the preset pipeline arbitration level once every packet transmission cycle. However, the preset pipeline arbitration level is only a macro-level strategy; the specific packet transmission and assembly scheme needs to be implemented according to the methods described later in this embodiment of the invention.

[0067] S102. Read the FIFO queue depth of each of the three transmission channels that need to be packetized: request, response, and data. For each FIFO queue, the number of available entries is recorded by a first counter, and for each transmission channel, the number of sent entries is recorded by a second counter.

[0068] This invention defines three key transmission channels in the CXL.cache protocol stack: Request (Req), Response (Rsp), and Data (Data). Without a fair queuing strategy for these transmission channels, a continuous influx of "data" would fill up the frame segments used for packet assembly, delaying "responses" significantly and disrupting cache consistency and timing. Conversely, prioritizing only "responses" or "requests" would waste substantial available bandwidth. Therefore, it is essential to measure which transmission channel is currently lagging behind and prioritize its service (packet assembly) to dynamically balance the traffic across the three channels.

[0069] This invention proposes a credit mechanism based on FIFO (First-In, First-Out) queues. Specifically, for the three transmission channels—request, response, and data—each maintains an independent, credit-based FIFO queue, defined in this embodiment as Req FIFO, Rsp FIFO, and Data-Header FIFO, respectively. During implementation, each entry in Req FIFO stores a 79-bit buffered request, each entry in Rsp FIFO stores a 20-bit buffered response, and each entry in Data-Header FIFO stores a 17-bit data.

[0070] Each FIFO queue records the number of its available entries using a first counter. In this embodiment of the invention, the first counters for the FIFO queues corresponding to the three transmission channels of request, response, and data are defined as ReqCnt, RspCnt, and DataCnt, respectively, and the second counters for the three transmission channels of request, response, and data are defined as ReqPrio, RspPrio, and DataPrio, respectively.

[0071] In particular, the credit-based FIFO queue in this embodiment of the invention has a credit return mechanism. After the host or device at one end of the DIE finishes processing the request for the corresponding transmission channel, it will add credit points to the FIFO queue of the corresponding transmission channel of the host or device at the other end through packet assembly, so as to increase the number of available entries in the FIFO queue.

[0072] S103. Determine the optimal format for assembling entries from different transmission channels based on the values ​​of the first counter and the second counter corresponding to the three transmission channels: request, response, and data.

[0073] Step S103 includes the following sub-steps:

[0074] S1031. Determine multiple preset formats for packaging the entries contained in the three transmission channels of different quantities of requests, responses and data.

[0075] Specifically, the packet size of CXL.cache is fixed (528 bits, including 4 16B slots). In this embodiment of the invention, based on the size of the entries contained in the three transmission channels of request, response and data, 6 preset formats are designed as shown in Table 1 below. Each format packs a specific number of request, response and data entries.

[0076] Table 1 Example of Preset Format

[0077]

[0078] For example, the default format of H0 refers to bundling one entry from the data with two entries from the response.

[0079] S1032. Based on the values ​​of the first counters corresponding to the three transmission channels of request, response and data, distinguish from the preset formats a first type of preset format that fully meets the item number requirement and a second type of preset format that partially meets the item number requirement.

[0080] As shown in Table 1 above, each preset format has certain requirements for the number of entries in the three transmission channels of request, response and data. For example, the preset format of H2 requires 4 entries from data and 1 entry from response. If the data transmission channel only has 3 entries, then the preset format of H2 is not satisfied.

[0081] S1033. Based on the values ​​of the second counters corresponding to the three transmission channels (request, response, and data), calculate the first weight value after packet assembly according to the preset format. Select the preset format corresponding to the maximum value of the first weight value as the optimal format. Define the first weight value as M1, which satisfies the following relationship:

[0082] M1 = (C_lowest - C_mid) + (C_lowest - C_highest);

[0083] C_lowest is the smallest value of the second counter corresponding to each of the three transmission channels (request, response, and data) after the packets are assembled according to the preset format; C_mid is the middle value of the second counter corresponding to each of the three transmission channels (request, response, and data) after the packets are assembled according to the preset format; and C_highest is the largest value of the second counter corresponding to each of the three transmission channels (request, response, and data) after the packets are assembled according to the preset format.

[0084] If the first type of preset format is not empty, the optimal format is selected from the first type of preset format; otherwise, the optimal format is selected from the second type of preset format.

[0085] If the first weight value M1 corresponding to multiple preset formats is the maximum, then based on the values ​​of the second counters corresponding to the three transmission channels of request, response, and data, the second weight value after packet assembly according to the preset format is calculated, and the preset format corresponding to the maximum value of the second weight value is selected as the optimal format. The second weight value is defined as M2, which satisfies the following relationship:

[0086] M2 = C_mid - C_highest.

[0087] Based on the ranking strategy described in the above embodiments, this invention ensures that the format selected for each packet always minimizes the largest gap between different channels, and then minimizes the gap in the next packet assembly. During implementation, after comparing the total number of packets sent from the three different channels, the impact of different packet formats on the current ranking of the total number of channels is calculated, resulting in thirteen different ranking orders for the total number of channels, as shown in Table 2.

[0088] Table 2 Example of Preset Format Priority Ranking

[0089]

[0090] As shown in the third case in Table 2, if the second counter value of the response channel is equal to the second counter value of the request channel and greater than the second counter value of the data channel, then according to the optimal format selection method of this embodiment, the preset format of G3 will be selected as the optimal format.

[0091] S104. Read entries from the FIFO queues corresponding to different transmission channels according to the optimal format and write them into the slots corresponding to the frame segments, and determine whether to complete the packet assembly of the frame segments according to the preset pipeline arbitration level.

[0092] Since the embodiments of the present invention design two pipelines with different directions and it is necessary to ensure the flow balance between the two pipelines, the packaging process on the pipeline will have different timeout and degradation logic according to the preset pipeline arbitration level.

[0093] Specifically, if the current preset pipeline arbitration level is non-idle, then step S104 includes the following sub-steps:

[0094] S1041. For the pipeline that prioritizes packet assembly and transmission, determine whether the first type of preset format is not empty. If yes, proceed to step S1042; if no, proceed to step S1043.

[0095] S1042. Update the packet counter by incrementing its value by 1. Read entries from the FIFO queues corresponding to different transmission channels according to the optimal format. Write the read entries into the empty slots corresponding to the frame segments in sequence. At the same time, decrement the value of the preset timeout loop control threshold by 1. If all 4 slots of the frame segment have been filled with entries, proceed to step S1046. Otherwise, return to step S1041.

[0096] S1043. Determine whether the second type of preset format is not empty. If yes, proceed to step S1044; if no, proceed to step S1045.

[0097] S1044. Update the packet counter by incrementing its value by 1. Read entries from the FIFO queues corresponding to different transmission channels according to the optimal format. Write the read entries into the empty slots corresponding to the frame segments in sequence. At the same time, decrement the value of the preset timeout loop control threshold by 1. If all four slots of the frame segment have been filled with entries, proceed to step S1046. Otherwise, proceed to step S1045.

[0098] S1045. Determine whether the value of the package counter is less than the preset timeout loop control threshold. If yes, return to step S1041; if no, proceed to step S1046.

[0099] S1046. If the slot of the frame fragment for which the entry has been written is the first one, then modify the preset pipeline arbitration level to select the first direction pipeline or the second direction pipeline in a round-robin manner according to the transmission requirements for packet assembly and transmission.

[0100] If the slot of the frame segment for which the entry has been written is the 2nd or 3rd, then skip the slot of the frame segment that needs to be packaged and complete the packaging of the frame segment.

[0101] If the slot of the frame fragment for which the current entry has been written is the 4th slot, then the assembly of the frame fragment is completed.

[0102] In this embodiment of the invention, the case of packet assembly and transmission using the first direction pipeline is described. In this case, the preset pipeline arbitration level is to prioritize packet assembly and transmission of the first direction pipeline (D2H), or to select either the first direction pipeline or the second direction pipeline for packet assembly and transmission in a round-robin manner according to transmission requirements (BOTH), with the first direction pipeline being polled. Since the arbitration level is not idle at this time, the first direction pipeline needs to complete packet assembly as soon as possible, so complete format packet assembly is not required. It can be understood that complete format packet assembly means that all four slots of the frame segment have data written. In step S1041, before packet assembly, it is determined whether slot data can be written in the first type of preset format. The purpose is to prioritize complete format packet assembly so that as much data as possible can be written to the slots. Correspondingly, step S1042 writes slot data according to the first type of preset format, thereby achieving full slot data writing.

[0103] Figure 2 The text specifically illustrates the case where packets are assembled using the G2 preset format as the optimal format. The C1 stage represents the preset format selection process, where Available=1 indicates that the first type of preset format is used as the optimal format, and NonEmpty=1 indicates that the second type of preset format is used as the optimal format. The C2 stage represents the packet assembly and transmission process.

[0104] Furthermore, such as Figure 3As shown, in step S1043, the determination of whether slot data can be written in the second type of preset format before packaging is because there is no available complete format packaging scheme in step S1041 (or during the loop). Compared with the first type of preset format, the items required by the second type of preset format are not fully satisfied. However, under the priority of the first pipeline, the goal is still to maximize the amount of data that can be written to the slots and to complete the packaging quickly. Figure 2 The difference in the process shown is that in step S1044, slot data is written according to the second type of preset format. Although data is written to the slot at this time, the data is not complete.

[0105] like Figure 4 As shown, in step S1045, determining whether the packet assembly counter value is less than the preset timeout loop control threshold is used to determine the timeout status of the current packet assembly process. The purpose of this design is that since step S104 uses a specific pipeline for packet transmission, even so, the method designed in this embodiment of the invention does not want to continue waiting for the current pipeline to complete packet assembly when there is no data to assemble. Therefore, if the preset timeout loop control threshold has been exceeded, for some slots where no data entries have been written, as described in step S1046, the preset pipeline arbitration level can be modified in a certain way to poll another pipeline, or the slots without written entries can be directly empty to complete the packet assembly, thus ending the current pipeline's packet assembly process early. Of course, as described in the above embodiment, if all four slots of the frame segment have completed entry writing, the complete frame segment can be assembled without triggering the timeout loop control, achieving the highest packet assembly bandwidth utilization.

[0106] Preferably, in this embodiment of the invention, in order to minimize the waiting time of the production line, after determining in step S1045 that the value of the package counter exceeds the preset timeout loop control threshold, the value of the preset timeout loop control threshold can be reduced (e.g., Figure 3 In the middle, the value of the preset timeout loop control threshold will be halved.

[0107] On the other hand, as described in the above embodiment, when the preset pipeline arbitration level is not idle, only one pipeline performs packet assembly transmission. For pipelines that are not currently performing packet assembly transmission, they can perform packet assembly without timeout restrictions and quickly assemble and send their completed frame fragments after obtaining permission to perform packet assembly transmission. Specifically, for the pipelines that are not currently performing packet assembly transmission, the packet assembly method for improving cross-DIE transmission efficiency further includes the following steps:

[0108] S201. Determine whether the first type of preset format is not empty. If yes, proceed to step S202; if no, proceed to step S203.

[0109] S202. Update the packet counter by incrementing its value by 1. Read entries from the FIFO queues corresponding to different transmission channels according to the optimal format. Write the read entries into the empty slots corresponding to the frame segments in sequence. At the same time, update the packet counter by incrementing its value by 1. Unless all four slots of the frame segment have been filled with entries, return to step S201.

[0110] S203. If the slot of the frame segment to which the current entry has been written is the 4th, then the frame segment is packaged; otherwise, return to step S201.

[0111] Please refer to Figure 5 The embodiments of the present invention are still described using the packaging process of the first direction assembly line, which is different from... Figures 2 to 4 The current pipeline arbitration level is Second Direction Pipeline Priority (H2D) or idle time is preempted by the second pipeline. Unlike step S104, when a pipeline that is not prioritizing packet transmission performs packet assembly, since it is not subject to timeout limits, in order to maximize packet assembly bandwidth utilization, it no longer writes entries based on the second type of preset format, but only writes relevant entries based on the first type of preset format. This allows it to assemble frame fragments with complete entry data in all four slots as much as possible within the unrestricted time. It should be noted that this packet assembly process still uses a packet counter. The purpose is that if the pipeline obtains the arbitration level for priority packet transmission or obtains the arbitration level through polling during its packet assembly process, it can quickly execute the packet assembly mechanism of step S104 using the existing packet counter.

[0112] S105. The completed frame segment is transmitted to the packet transmitter, and the completed frame segment is further transmitted to the physical layer of the pipeline through the packet transmitter to complete the packet transmission.

[0113] It is understood that the packet assembly method described in the embodiments of the present invention conforms to the DIE design and the CXL.cache protocol stack. The arbitrator, packet assembler, and unit for reading and updating the FIFO queue can all be set in the DIE, and the corresponding method logic can be executed through the packet assembly method described in the embodiments of the present invention.

[0114] The packet reassembly method for improving cross-DIE transmission efficiency also includes the following steps:

[0115] S106. An arbitration signal is issued through the arbitrator to modify the preset pipeline arbitration level.

[0116] In this embodiment of the invention, the issuance of the arbitration signal is mainly used to modify the preset pipeline arbitration level, such as changing the pipeline that prioritizes packet assembly transmission to another, or modifying it to a polling state, which can be set according to actual needs. The arbitration signal is issued by the arbitrator, meaning that both the host and device on both sides of the DIE can receive the arbitration signal. Figures 2 to 5 As shown, the arbitration signal is also used to update the values ​​of the first and second counters corresponding to the three transmission channels of the host and device: request, response, and data, thereby realizing the credit mechanism update of the FIFO queue.

[0117] It is understood that the preset formats and their priority rankings shown in Tables 1 and 2 are a usable numerical rule adopted in the implementation of the embodiments of the present invention. Based on this numerical rule, the degree of matching between the embodiments of the present invention and the existing CXL.cache protocol stack at a specific data size can be clearly reflected, and the efficiency of CXL.cache packet assembly can be maximized based on the method of the embodiments of the present invention. However, this is not intended to limit the scope of protection of the present invention.

[0118] The beneficial effect achieved by this invention is that it proposes a packet assembly method based on the CXL.cache protocol stack to improve the efficiency of cross-DIE transmission. This packet assembly method realizes pipeline bidirectional fairness, multi-channel queuing fairness, channel flow control, and the trade-off between packet utilization and latency from the packet assembly logic, and meets the high-frequency timing requirements of the DIE pipeline.

[0119] This invention also provides a packet reassembly system 300 to improve cross-DIE transmission efficiency. Please refer to [link / reference]. Figure 6 , Figure 6 This is a schematic diagram of the packet reassembly system for improving cross-DIE transmission efficiency provided in an embodiment of the present invention, which includes:

[0120] Arbitration module 301 is used to select the pipeline that needs to be packetized and transmitted according to the preset pipeline arbitration level through the arbitrator to start packet assembly. The preset pipeline arbitration level is used to determine the priority of different pipelines and the method of packet assembly. The pipeline includes a first direction pipeline from host to device and a second direction pipeline from device to host.

[0121] The reading module 302 is used to read the FIFO queue depth of each of the three transmission channels that need to be packetized: request, response, and data. For each FIFO queue, the number of available entries is recorded by a first counter, and for each transmission channel, the number of sent entries is recorded by a second counter.

[0122] The format module 303 is used to determine the optimal format for assembling entries from different transmission channels based on the values ​​of the first counter and the second counter corresponding to the three transmission channels of request, response and data respectively.

[0123] The packet assembly module 304 is used to read entries from the FIFO queues corresponding to different transmission channels according to the optimal format and write them into the slots corresponding to the frame segments, and determine whether to complete the packet assembly of the frame segments according to the preset pipeline arbitration level.

[0124] The transmission module 305 is used to transmit the completed frame fragment to the packet transmitter, and further transmit the completed frame fragment to the physical layer of the pipeline through the packet transmitter to complete the packet transmission.

[0125] The packet assembly system 300 for improving cross-DIE transmission efficiency can implement the steps in the packet assembly method for improving cross-DIE transmission efficiency as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0126] This invention also provides a computer device, please refer to... Figure 7 , Figure 7 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 400 includes: a memory 402, a processor 401, and a packet assembly program stored in the memory 402 and capable of running on the processor 401 to improve the efficiency of cross-DIE transmission.

[0127] The processor 401 calls the packet assembly program for improving cross-DIE transmission efficiency stored in the memory 402, and executes the steps in the packet assembly method for improving cross-DIE transmission efficiency provided in this embodiment of the invention. Please refer to... Figure 1 Specifically, it includes the following steps:

[0128] S101. The arbitrator selects the pipeline that needs to be packetized and transmitted according to the preset pipeline arbitration level to start packet assembly. The preset pipeline arbitration level is used to determine the priority of different pipelines and the method of packet assembly. The pipeline includes a first-direction pipeline from host to device and a second-direction pipeline from device to host.

[0129] The preset pipeline arbitration level in step S101 is specifically as follows:

[0130] Prioritize packet transmission in the first direction pipeline; or,

[0131] Prioritize packet transmission in the second direction pipeline; or,

[0132] Based on transmission requirements, either the first-direction pipeline or the second-direction pipeline is selected for packet assembly and transmission in a round-robin manner; or...

[0133] idle.

[0134] S102. Read the FIFO queue depth of each of the three transmission channels that need to be packetized: request, response, and data. For each FIFO queue, the number of available entries is recorded by a first counter, and for each transmission channel, the number of sent entries is recorded by a second counter.

[0135] S103. Determine the optimal format for assembling entries from different transmission channels based on the values ​​of the first counter and the second counter corresponding to the three transmission channels: request, response, and data.

[0136] Step S103 includes the following sub-steps:

[0137] S1031. Determine multiple preset formats for packaging the items contained in the three transmission channels of different quantities of requests, responses and data;

[0138] S1032. Based on the values ​​of the first counters corresponding to the three transmission channels of request, response and data, distinguish from the preset formats a first type of preset format that fully meets the item number requirement and a second type of preset format that partially meets the item number requirement.

[0139] S1033. Based on the values ​​of the second counters corresponding to the three transmission channels (request, response, and data), calculate the first weight value after packet assembly according to the preset format. Select the preset format corresponding to the maximum value of the first weight value as the optimal format. Define the first weight value as M1, which satisfies the following relationship:

[0140] M1 = (C_lowest - C_mid) + (C_lowest - C_highest);

[0141] C_lowest is the smallest value of the second counter corresponding to each of the three transmission channels (request, response, and data) after the packets are assembled according to the preset format; C_mid is the middle value of the second counter corresponding to each of the three transmission channels (request, response, and data) after the packets are assembled according to the preset format; and C_highest is the largest value of the second counter corresponding to each of the three transmission channels (request, response, and data) after the packets are assembled according to the preset format.

[0142] If the first type of preset format is not empty, the optimal format is selected from the first type of preset format; otherwise, the optimal format is selected from the second type of preset format.

[0143] If the first weight value M1 corresponding to multiple preset formats is the maximum, then based on the values ​​of the second counters corresponding to the three transmission channels of request, response, and data, the second weight value after packet assembly according to the preset format is calculated, and the preset format corresponding to the maximum second weight value is selected as the optimal format definition. The second weight value is M2, which satisfies the following relationship:

[0144] M2 = C_mid - C_highest.

[0145] S104. Read entries from the FIFO queues corresponding to different transmission channels according to the optimal format and write them into the slots corresponding to the frame segments, and determine whether to complete the packet assembly of the frame segments according to the preset pipeline arbitration level.

[0146] If the current preset pipeline arbitration level is non-idle, then step S104 includes the following sub-steps:

[0147] S1041. For the pipeline that prioritizes packet assembly and transmission, determine whether the first type of preset format is not empty. If yes, proceed to step S1042; if no, proceed to step S1043.

[0148] S1042. Update the packet counter by incrementing its value by 1. Read entries from the FIFO queues corresponding to different transmission channels according to the optimal format. Write the read entries into the empty slots corresponding to the frame segments in sequence. At the same time, decrement the value of the preset timeout loop control threshold by 1. If all 4 slots of the frame segment have been filled with entries, proceed to step S1046. Otherwise, return to step S1041.

[0149] S1043. Determine whether the second type of preset format is not empty. If yes, proceed to step S1044; if no, proceed to step S1045.

[0150] S1044. Update the packet counter by incrementing its value by 1. Read entries from the FIFO queues corresponding to different transmission channels according to the optimal format. Write the read entries into the empty slots corresponding to the frame segments in sequence. At the same time, decrement the value of the preset timeout loop control threshold by 1. If all four slots of the frame segment have been filled with entries, proceed to step S1046. Otherwise, proceed to step S1045.

[0151] S1045. Determine whether the value of the package counter is less than the preset timeout loop control threshold. If yes, return to step S1041; if no, proceed to step S1046.

[0152] S1046. If the slot of the frame fragment for which the entry has been written is the first one, then modify the preset pipeline arbitration level to select the first direction pipeline or the second direction pipeline in a round-robin manner according to the transmission requirements for packet assembly and transmission.

[0153] If the slot of the frame segment for which the entry has been written is the 2nd or 3rd, then skip the slot of the frame segment that needs to be packaged and complete the packaging of the frame segment.

[0154] If the slot of the frame fragment for which the current entry has been written is the 4th slot, then the assembly of the frame fragment is completed.

[0155] For the pipeline that does not currently perform packet reassembly transmission, the packet reassembly method for improving cross-DIE transmission efficiency further includes the following steps:

[0156] S201. Determine whether the first type of preset format is not empty. If yes, proceed to step S202; if no, proceed to step S203.

[0157] S202. Update the packet counter by incrementing its value by 1. Read entries from the FIFO queues corresponding to different transmission channels according to the optimal format. Write the read entries into the empty slots corresponding to the frame segments in sequence. At the same time, update the packet counter by incrementing its value by 1. Unless all four slots of the frame segment have been filled with entries, return to step S201.

[0158] S203. If the slot of the frame segment to which the current entry has been written is the 4th, then the frame segment is packaged; otherwise, return to step S201.

[0159] S105. The completed frame segment is transmitted to the packet transmitter, and the completed frame segment is further transmitted to the physical layer of the pipeline through the packet transmitter to complete the packet transmission.

[0160] The packet reassembly method for improving cross-DIE transmission efficiency also includes the following steps:

[0161] S106. An arbitration signal is issued through the arbitrator to modify the preset pipeline arbitration level.

[0162] The computer device 400 provided in this embodiment of the invention can implement the steps in the packet assembly method for improving cross-DIE transmission efficiency as described in the above embodiments, and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0163] This invention also provides a storage medium storing a packet assembly program for improving cross-DIE transmission efficiency. When executed by a processor, this packet assembly program implements the various processes and steps of the packet assembly method for improving cross-DIE transmission efficiency provided in this invention, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0164] Those skilled in the art will understand that implementing all or part of the processes in the above embodiments can be accomplished by instructing related hardware (such as mobile phones, computers, servers, air conditioners, or network devices, etc.) through a packet-assembly program that improves cross-DIE transmission efficiency. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0165] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0166] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form under the guidance of the present invention without departing from the spirit and scope of the claims. All such changes are within the protection scope of the present invention.

Claims

1. A packet reassembly method for improving cross-DIE transmission efficiency, characterized in that, Includes the following steps: S101. The arbitrator selects the pipeline that needs to be packetized and transmitted according to the preset pipeline arbitration level to start packet assembly. The preset pipeline arbitration level is used to determine the priority of different pipelines and the method of packet assembly. The pipeline includes a first-direction pipeline from host to device and a second-direction pipeline from device to host. S102. Read the FIFO queue depth of each of the three transmission channels that need to be packetized: request, response, and data. For each FIFO queue, the number of available entries is recorded by a first counter, and for each transmission channel, the number of sent entries is recorded by a second counter. S103. Determine the optimal format for packetizing entries from different transmission channels based on the values ​​of the first counter and the second counter corresponding to the three transmission channels: request, response, and data. S104. Read entries from the FIFO queues corresponding to different transmission channels according to the optimal format and write them into the slots corresponding to the frame segments, and determine whether to complete the packet assembly of the frame segments according to the preset pipeline arbitration level. S105. The completed frame segment is transmitted to the packet transmitter, and the completed frame segment is further transmitted to the physical layer of the pipeline through the packet transmitter to complete the packet transmission.

2. The packet reassembly method for improving cross-DIE transmission efficiency according to claim 1, characterized in that, The preset pipeline arbitration level in step S101 is specifically as follows: Prioritize packet transmission in the first direction pipeline; or, Prioritize packet transmission in the second direction pipeline; or, Based on transmission requirements, either the first-direction pipeline or the second-direction pipeline is selected for packet assembly and transmission in a round-robin manner; or... idle.

3. The packet reassembly method for improving cross-DIE transmission efficiency according to claim 2, characterized in that, Step S103 includes the following sub-steps: S1031. Determine multiple preset formats for packaging the items contained in the three transmission channels of different quantities of requests, responses and data; S1032. Based on the values ​​of the first counters corresponding to the three transmission channels of request, response and data, distinguish from the preset formats a first type of preset format that fully meets the item number requirement and a second type of preset format that partially meets the item number requirement. S1033. Based on the values ​​of the second counters corresponding to the three transmission channels (request, response, and data), calculate the first weight value after packet assembly according to the preset format. Select the preset format corresponding to the maximum value of the first weight value as the optimal format. Define the first weight value as M1, which satisfies the following relationship: M1 = (C_lowest - C_mid) + (C_lowest - C_highest); C_lowest is the smallest value of the second counter corresponding to each of the three transmission channels (request, response, and data) after the packets are assembled according to the preset format; C_mid is the middle value of the second counter corresponding to each of the three transmission channels (request, response, and data) after the packets are assembled according to the preset format; and C_highest is the largest value of the second counter corresponding to each of the three transmission channels (request, response, and data) after the packets are assembled according to the preset format. If the first type of preset format is not empty, the optimal format is selected from the first type of preset format; otherwise, the optimal format is selected from the second type of preset format.

4. The packet reassembly method for improving cross-DIE transmission efficiency according to claim 3, characterized in that, If the first weight value M1 corresponding to multiple preset formats is the maximum, then based on the values ​​of the second counters corresponding to the three transmission channels of request, response, and data, the second weight value after packet assembly according to the preset format is calculated, and the preset format corresponding to the maximum value of the second weight value is selected as the optimal format. The second weight value is defined as M2, which satisfies the following relationship: M2 = C_mid - C_highest.

5. The packet reassembly method for improving cross-DIE transmission efficiency according to claim 4, characterized in that, If the current preset pipeline arbitration level is non-idle, then step S104 includes the following sub-steps: S1041. For the pipeline that prioritizes packet assembly and transmission, determine whether the first type of preset format is not empty. If yes, proceed to step S1042; if no, proceed to step S1043. S1042. Update the packet counter by incrementing its value by 1. Read entries from the FIFO queues corresponding to different transmission channels according to the optimal format. Write the read entries into the empty slots corresponding to the frame segments in sequence. At the same time, decrement the value of the preset timeout loop control threshold by 1. If all 4 slots of the frame segment have been filled with entries, proceed to step S1046. Otherwise, return to step S1041. S1043. Determine whether the second type of preset format is not empty. If yes, proceed to step S1044; if no, proceed to step S1045. S1044. Update the packet counter by incrementing its value by 1. Read entries from the FIFO queues corresponding to different transmission channels according to the optimal format. Write the read entries into the empty slots corresponding to the frame segments in sequence. At the same time, decrement the value of the preset timeout loop control threshold by 1. If all four slots of the frame segment have been filled with entries, proceed to step S1046. Otherwise, proceed to step S1045. S1045. Determine whether the value of the package counter is less than the preset timeout loop control threshold. If yes, return to step S1041; if no, proceed to step S1046. S1046. If the slot of the frame fragment for which the entry has been written is the first one, then modify the preset pipeline arbitration level to select the first direction pipeline or the second direction pipeline in a round-robin manner according to the transmission requirements for packet assembly and transmission. If the slot of the frame segment for which the entry has been written is the 2nd or 3rd, then skip the slot of the frame segment that needs to be packaged and complete the packaging of the frame segment. If the slot of the frame fragment for which the current entry has been written is the 4th slot, then the assembly of the frame fragment is completed.

6. The packet reassembly method for improving cross-DIE transmission efficiency according to claim 1, characterized in that, The packet reassembly method for improving cross-DIE transmission efficiency also includes the following steps: S106. An arbitration signal is issued through the arbitrator to modify the preset pipeline arbitration level.

7. The packet reassembly method for improving cross-DIE transmission efficiency according to claim 5, characterized in that, For the pipeline that does not currently perform packet reassembly transmission, the packet reassembly method for improving cross-DIE transmission efficiency further includes the following steps: S201. Determine whether the first type of preset format is not empty. If yes, proceed to step S202; if no, proceed to step S203. S202. Update the packet counter by incrementing its value by 1. Read entries from the FIFO queues corresponding to different transmission channels according to the optimal format. Write the read entries into the empty slots corresponding to the frame segments in sequence. At the same time, update the packet counter by incrementing its value by 1. Unless all four slots of the frame segment have been filled with entries, return to step S201. S203. If the slot of the frame segment to which the current entry has been written is the 4th, then the frame segment is packaged; otherwise, return to step S201.

8. A packet reassembly system for improving cross-DIE transmission efficiency, characterized in that, include: The arbitration module is used to select the pipeline that needs to be packetized and transmitted according to the preset pipeline arbitration level through the arbitrator to start packet assembly. The preset pipeline arbitration level is used to determine the priority of different pipelines and the method of packet assembly. The pipeline includes a first direction pipeline from host to device and a second direction pipeline from device to host. The reading module is used to read the FIFO queue depth of each of the three transmission channels that need to be packetized: request, response, and data. For each FIFO queue, the number of available entries is recorded by a first counter, and for each transmission channel, the number of sent entries is recorded by a second counter. The format module is used to determine the optimal format for assembling entries from different transmission channels based on the values ​​of the first counter and the second counter corresponding to the three transmission channels: request, response, and data. The packet assembly module is used to read entries from the FIFO queues corresponding to different transmission channels according to the optimal format and write them into the slots corresponding to the frame segments, and determine whether to complete the packet assembly of the frame segments according to the preset pipeline arbitration level. The transmission module is used to transmit the completed frame fragment to the packet transmitter, and further transmit the completed frame fragment to the physical layer of the pipeline through the packet transmitter to complete the packet transmission.

9. A computer device, characterized in that, include: The package assembly method for improving cross-DIE transmission efficiency, which is stored in the memory and can run on the processor, includes a memory, a processor, and a packet assembly program for improving cross-DIE transmission efficiency, wherein the processor, when executing the packet assembly program for improving cross-DIE transmission efficiency, implements the steps of the packet assembly method for improving cross-DIE transmission efficiency as described in any one of claims 1-7.

10. A storage medium, characterized in that, The storage medium stores a packet assembly program for improving cross-DIE transmission efficiency. When the packet assembly program for improving cross-DIE transmission efficiency is executed by the processor, it implements the steps in the packet assembly method for improving cross-DIE transmission efficiency as described in any one of claims 1-7.

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