Low-delay display method and device of display equipment, equipment and storage medium

Abstract

The invention relates to a low-delay display method and device for display equipment, equipment and a storage medium, and the method comprises the following steps: carrying out the hierarchical rendering priority distribution of continuous image frames based on a dynamic region mask image, and obtaining an intra-frame priority rendering mapping table; performing multi-step prediction calculation on the intra-frame priority rendering mapping table to obtain an inter-frame display delay compensation parameter set; performing hardware acceleration cache pre-distribution on the continuous image frames based on the inter-frame display delay compensation parameter set to obtain a multi-stage rendering cache structure; performing parallel computing processing on the multi-stage rendering cache structure to obtain a low-delay scanning line rendering data stream; regional self-adaptive refresh control is performed on a display panel of the display equipment based on the low-delay scanning line rendering data stream to obtain display output of dynamic response optimization, and the problems that rendering resources are unreasonable in distribution and poor in reliability due to the fact that a traditional inter-frame prediction algorithm is lack of accurate recognition capacity for a picture dynamic region are solved. And the display delay of the key area cannot be effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of display devices, and in particular to a low-latency display method, apparatus, device, and storage medium for a display device. Background Art

[0002] In the current display technology landscape, as users' demands for a higher visual experience continue to rise, particularly for highly dynamic content like games and HD video, the latency issues experienced by traditional display devices when processing complex image changes have become particularly prominent. This latency not only impacts the user experience but can also become a bottleneck restricting the further development of certain application scenarios. For example, in virtual reality (VR) and augmented reality (AR) applications, even the slightest delay can significantly reduce user immersion and even cause discomfort. Therefore, reducing display device latency and improving response speed and image quality have become key research areas in the industry.

[0003] However, existing technologies face many challenges in reducing display latency. On the one hand, traditional inter-frame prediction algorithms lack the ability to accurately identify dynamic areas of the picture, resulting in irrational allocation of rendering resources and an inability to effectively reduce display latency in key areas. On the other hand, improvements at the hardware level are often accompanied by increased costs and increased technical difficulty, which forces manufacturers to consider commercial feasibility while pursuing performance optimization. In addition, existing display technologies are prone to screen tearing and blurring when processing rapidly changing pictures. The existence of these problems has prompted researchers to find new ways to solve the above problems.

[0004] In response to these challenges, an innovative low-latency display method has emerged. It aims to optimize display output by intelligently analyzing dynamic areas in consecutive image frames and performing efficient rendering priority allocation and delay compensation calculations based on this. This method uses advanced visual frame differential detection technology and an asynchronous scan line rendering scheduler to achieve fine control of the display panel and significantly reduce display latency. At the same time, through a hardware-accelerated cache pre-allocation strategy, this method can further improve display effects and response speeds without significantly increasing hardware costs, providing users with a smoother and more natural viewing experience. The introduction of this method not only provides new ideas for solving problems in existing technologies, but also points out the direction for the development of future display technologies. Summary of the Invention

[0005] The main purpose of the present invention is to provide a low-latency display method, device, equipment and storage medium for a display device, which solves the technical problem that the traditional lack of accurate recognition of dynamic areas of the picture leads to unreasonable allocation of rendering resources and cannot effectively reduce the display delay of key areas.

[0006] To achieve the above object, the present invention provides a low-latency display method for a display device, comprising the following steps: Perform dynamic area recognition and analysis on continuous image frames received by a preset display device through visual frame difference detection technology to obtain a dynamic area mask map; Performing layered rendering priority assignment on the consecutive image frames based on the dynamic area mask map to obtain an intra-frame priority rendering mapping table; Performing multi-step prediction calculations on the intra-frame priority rendering mapping table by a temporal interpolation predictor to obtain an inter-frame display delay compensation parameter set; Performing hardware acceleration cache pre-allocation on the continuous image frames based on the inter-frame display delay compensation parameter set to obtain a multi-level rendering cache structure; Performing parallel computing processing on the multi-level rendering cache structure through an asynchronous scanline rendering scheduler to obtain a low-latency scanline rendering data stream; Based on the low-latency scan line rendering data stream, regional adaptive refresh control is performed on the display panel of the display device to obtain a display output with optimized dynamic response.

[0007] Furthermore, the method of performing dynamic region recognition analysis on the continuous image frames received by the preset display device by using the visual frame difference detection technology to obtain the dynamic region mask map includes: Performing multi-scale optical flow analysis on the continuous image frames to obtain a pixel-level motion vector map, and performing adaptive threshold segmentation on the pixel-level motion vector map to obtain a candidate dynamic region mask; performing spatiotemporal correlation calculation on the continuous image frames based on the candidate dynamic region mask to obtain a region boundary feature descriptor, and performing morphological optimization processing on the region boundary feature descriptor to obtain a region contour accurate mapping; The region contour is accurately mapped and connected domains are marked using a region growing algorithm to obtain a dynamic region classification label, and the continuous image frames are subjected to region merging and splitting processing based on the dynamic region classification label to obtain the dynamic region mask map; wherein the dynamic region mask map includes the dynamic region position coordinates, the region boundary contour point set and the region motion feature vector.

[0008] Furthermore, the layered rendering priority allocation is performed on the continuous image frames based on the dynamic area mask map to obtain an intra-frame priority rendering mapping table, including: Performing regional feature complexity calculation on the dynamic region mask image to obtain a regional calculation density vector, and performing hierarchical clustering on the regional calculation density vector to obtain a regional rendering hierarchy tree; Performing layered rendering processing on the continuous image frames based on the regional rendering hierarchy tree to obtain a multi-level rendering task graph, and performing rendering dependency propagation analysis on the multi-level rendering task graph to obtain an inter-layer data flow dependency chain; wherein the inter-layer data flow dependency chain includes a layer transmission order, a data interaction type, and a cross-layer dependency strength; Performing temporal decomposition of the inter-layer data flow dependency chain through a distributed task scheduler to obtain a parallel rendering task sequence, and allocating computing resources based on the parallel rendering task sequence to obtain a hardware execution schedule; wherein the hardware execution schedule includes a processor core allocation scheme, memory bandwidth allocation, and computing unit timing; The rendering priority of the hardware execution scheduling table is reordered to obtain an optimized rendering execution plan, and the optimized rendering execution plan is time-sliced ​​and synchronously controlled to obtain the intra-frame priority rendering mapping table; wherein the intra-frame priority rendering mapping table includes a regional rendering priority identifier, a rendering task execution timing, and a computing resource allocation plan.

[0009] Furthermore, the intra-frame priority rendering mapping table is subjected to multi-step prediction calculation by the time domain interpolation predictor to obtain an inter-frame display delay compensation parameter set, including: Performing temporal convolution analysis on the intra-frame priority rendering mapping table to obtain a rendering task time series feature vector, and performing nonlinear transformation processing on the rendering task time series feature vector to obtain a multi-scale temporal feature pyramid; wherein the multi-scale temporal feature pyramid includes rendering task feature descriptions at different time granularities, temporal correlation between layers, and feature importance weights; Using a preset time-domain interpolation predictor, autoregressive prediction processing is performed on the parallel rendering task sequence based on the multi-scale temporal feature pyramid to obtain an inter-frame rendering delay prediction map, and adaptive weighted fusion is performed on the inter-frame rendering delay prediction map to obtain a rendering delay distribution heat map; Performing a spatial transfer function calculation on the rendering delay distribution heat map using a preset wavefront propagation model to obtain a display refresh wavefront prediction model, and performing display delay quantization modeling on different regions in the continuous image frames based on the display refresh wavefront prediction model to obtain a regional display response characteristic curve; Performing differential analysis on the regional display response characteristic curve to obtain a display delay gradient field, and performing optimal path planning on the display delay gradient field to obtain a delay compensation strategy matrix; Based on the delay compensation strategy matrix, the parallel rendering task sequence is hierarchically scheduled and allocated to obtain a multi-level delay compensation execution plan, and the multi-level delay compensation execution plan is evaluated for hardware resource constraints to obtain the inter-frame display delay compensation parameter set; wherein, the inter-frame display delay compensation parameter set includes a regional display priority index, a scan line rendering timing adjustment parameter, and a regional cache prefetch configuration strategy.

[0010] Furthermore, the hardware acceleration cache pre-allocation is performed on the continuous image frames based on the inter-frame display delay compensation parameter set to obtain a multi-level rendering cache structure, including: Performing hierarchical storage granularity division on the inter-frame display delay compensation parameter set to obtain a multi-level cache block allocation scheme, and performing bandwidth resource constraint calculation on the multi-level cache block allocation scheme to obtain a cache access scheduling table; Performing a topology optimization configuration on the hardware storage system in the display device based on the cache access scheduling table to obtain a hierarchical storage access network, and performing data flow conflict detection and analysis on the hierarchical storage access network to obtain a conflict avoidance routing table; Performing instruction-level parallel processing on the conflict avoidance routing table to obtain a parallel prefetch instruction set, performing regional correlation analysis and compact layout reorganization on the parallel prefetch instruction set to obtain a partitioned cache organization structure; Based on the partitioned cache organizational structure, the hardware rendering pipeline in the display device is configured with parallel processing units to obtain a heterogeneous computing resource allocation strategy, and the heterogeneous computing resource allocation strategy is dynamically controlled for power consumption balance to obtain the multi-level rendering cache structure; wherein, the multi-level rendering cache structure includes a regional rendering cache hierarchy, a hardware computing unit mapping relationship, and a cache synchronization control protocol.

[0011] Furthermore, the asynchronous scanline rendering scheduler performs parallel computing processing on the multi-level rendering cache structure to obtain a low-latency scanline rendering data stream, including: Performing scan line segment mapping processing on the multi-level rendering cache structure to obtain a scan line rendering task segmentation table, and performing priority reordering processing on the scan line rendering task segmentation table to obtain a dynamic scan line execution sequence; Using a preset asynchronous scanline rendering scheduler, a preset hardware rendering unit is subjected to uneven load distribution based on the dynamic scanline execution sequence to obtain a multi-channel rendering instruction stream, and the multi-channel rendering instruction stream is subjected to pipeline interleaving scheduling to obtain a fine-grained parallel execution solution; wherein the hardware rendering unit is disposed in the display device; Performing inter-scanline parallel processing on the fine-grained parallel execution scheme by using a preset partition rendering technology to obtain a parallel rendering result set, and performing inter-scanline boundary fusion processing on the parallel rendering result set to obtain a seamlessly spliced ​​rendered image; The seamless splicing rendering image is processed by parallel transmission through an asynchronous data transmission controller to obtain the low-latency scan line rendering data stream.

[0012] Furthermore, the performing of regional adaptive refresh control on the display panel of the display device based on the low-latency scanline rendering data stream to obtain a display output with optimized dynamic response includes: Performing scan line timing analysis on the low-latency scan line rendering data stream to obtain a regional refresh time distribution diagram, and performing phase compensation calculation on a preset display drive signal based on the regional refresh time distribution diagram to obtain a drive timing adjustment parameter set; performing multi-region drive frequency modulation on a gate drive circuit of a display panel in the display device based on the drive timing adjustment parameter set to obtain a non-uniform scan drive scheme, and performing voltage compensation optimization processing on the non-uniform scan drive scheme to obtain a pixel response balance control strategy; Performing transition frame synthesis processing on the pixel response equalization control strategy through a preset regional overdrive controller to obtain a multi-level response transition frame sequence, and performing time domain interpolation calculation on the multi-level response transition frame sequence to obtain a sub-frame drive control signal; Performing inter-region boundary synchronization and coordination processing on the sub-frame drive control signal to obtain a seamless regional boundary control scheme, and performing parallel loading control on the data line drive circuit of the display panel based on the seamless regional boundary control scheme to obtain a regional parallel drive execution sequence; Based on the regional parallel drive execution sequence, electro-optical conversion characteristics of the display area of ​​the display panel are compensated to obtain a perceptually uniform display output, and visual persistence effect optimization processing is performed on the perceptually uniform display output to obtain the dynamic response optimized display output.

[0013] The present invention also provides a low-latency display device for a display device, comprising: The recognition module is used to perform dynamic area recognition and analysis on the continuous image frames received by the preset display device through visual frame difference detection technology to obtain a dynamic area mask map; an allocation module, configured to allocate hierarchical rendering priorities to the consecutive image frames based on the dynamic area mask map to obtain an intra-frame priority rendering mapping table; a calculation module, configured to perform multi-step prediction calculation on the intra-frame priority rendering mapping table through a time domain interpolation predictor to obtain an inter-frame display delay compensation parameter set; an allocation module, configured to pre-allocate hardware acceleration cache for the consecutive image frames based on the inter-frame display delay compensation parameter set to obtain a multi-level rendering cache structure; A parallel computing module, configured to perform parallel computing processing on the multi-level rendering cache structure through an asynchronous scanline rendering scheduler to obtain a low-latency scanline rendering data stream; Refresh control is used to perform regional adaptive refresh control on the display panel of the display device based on the low-latency scan line rendering data stream to obtain a display output with optimized dynamic response.

[0014] The present invention also provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any one of the above methods when executing the computer program.

[0015] The present invention also provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of any of the above methods are implemented.

[0016] The present invention provides a low-latency display method for a display device, comprising the following steps: performing dynamic region identification and analysis on continuous image frames received by a preset display device using visual frame difference detection technology to obtain a dynamic region mask map; performing layered rendering priority allocation on the continuous image frames based on the dynamic region mask map to obtain an intra-frame priority rendering mapping table; performing multi-step prediction calculation on the intra-frame priority rendering mapping table using a temporal interpolation predictor to obtain an inter-frame display delay compensation parameter set; performing hardware acceleration cache pre-allocation on the continuous image frames based on the inter-frame display delay compensation parameter set to obtain a multi-level rendering cache structure; performing parallel computing processing on the multi-level rendering cache structure using an asynchronous scanline rendering scheduler to obtain a low-latency scanline rendering data stream; and performing regional adaptive refresh control on the display panel of the display device based on the low-latency scanline rendering data stream to obtain a display output with optimized dynamic response. The method solves the technical problem of irrational rendering resource allocation and inability to effectively reduce display delays in key areas due to a lack of accurate recognition capability for dynamic regions of the image, and implements parallel computing processing of the multi-level rendering cache structure using an asynchronous scanline rendering scheduler to generate a low-latency scanline rendering data stream. This approach greatly improves rendering efficiency, reduces rendering time, and further reduces overall display latency. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 1 is a schematic diagram of the steps of a low-latency display method for a display device according to an embodiment of the present invention; Figure 2 is a structural block diagram of a low-latency display device of a display device according to an embodiment of the present invention; Figure 3 It is a schematic block diagram of the structure of a computer device according to an embodiment of the present invention.

[0018] The purpose, features and advantages of the present invention will be further described with reference to the accompanying drawings and in conjunction with the embodiments. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0020] like Figure 1 As shown, Figure 1 This is a schematic diagram of the steps of a low-latency display method for a display device according to an embodiment of the present invention; In one embodiment of the present invention, a low-latency display method for a display device is provided, comprising the following steps: Step S1 : performing dynamic region recognition analysis on continuous image frames received by a preset display device through visual frame difference detection technology to obtain a dynamic region mask image.

[0021] Specifically, the system uses visual frame differencing technology to identify and analyze dynamic regions in consecutive image frames received by a preset display device, generating a dynamic region mask. This process aims to accurately capture changes in the image sequence so that subsequent processing steps can optimize these areas, reducing unnecessary computing resources and improving the overall display quality. Specifically, the system first acquires a series of consecutive image frames received by the display device. These frames represent different moments in the video content on the timeline. Next, using frame differencing technology—comparing the pixel differences between adjacent frames—it identifies which areas have changed. For example, in a high-speed action game scene, the player character's rapid movement can cause significant changes in the background and the character itself. These changes are precisely the areas that require focused processing. During this process, the system performs pixel-level comparisons on each pair of consecutive frames, marking all locations where pixel values ​​have changed. This creates a binary mask, where changed areas are marked as 1 and unchanged areas as 0. This dynamic region mask clearly defines the areas of the image that require priority processing. Then, based on this mask map, the system can allocate rendering resources more efficiently. For example, in a racing game, when a vehicle is traveling at high speed, the scenery on both sides of the road quickly recedes. At this time, the dynamic area mask map will help the system focus on the changes in the vehicle and the surrounding dynamic environment, rather than the static sky or unchanging buildings in the distance, ensuring that the player sees the smoothest and clearest picture. Therefore, through this precise dynamic area recognition method, not only is the processing efficiency improved, but the user's immersion and gaming experience are also greatly enhanced. The application of this method is not limited to games, but is also applicable to any scenario that requires high response speed and high-quality display output, such as virtual reality experience or high-definition video playback, effectively solving the delay and image quality problems existing in traditional display technology.

[0022] Step S2: performing layered rendering priority allocation on the continuous image frames based on the dynamic area mask image to obtain an intra-frame priority rendering mapping table.

[0023] Specifically, a hierarchical rendering priority is assigned to consecutive image frames based on a dynamic region mask, generating an intra-frame priority rendering map. This process aims to optimize the allocation of rendering resources based on the dynamic characteristics of different regions within the image. Specifically, the system first utilizes the dynamic region mask generated in the previous step, which clearly marks the parts that change and those that do not change within each frame. The system then analyzes this information to identify key dynamic regions that the user is most interested in and require high priority processing. For example, in a racing game, the changes in the vehicle and its surroundings are the most critical, while the distant background or sky is relatively static and does not require frequent updates. After determining these key regions, the system divides each component within each frame into layers based on its importance and dynamics, and assigns a corresponding rendering priority to each layer. For example, in the racing game example above, the vehicle and the nearby track would be given the highest priority, as these are directly related to the player's gaming experience. Next would be minor dynamic elements, such as the spectator seats or billboards, which change less frequently but still require attention. Finally, background elements that rarely change, such as the blue sky and white clouds, would be given the lowest priority. In this way, the system can generate a detailed intra-frame priority rendering map, which not only records the priority of each part in each frame, but also guides the subsequent steps on how to perform rendering calculations efficiently. The benefits of doing so are obvious. For example, in games, even if the scenes are complex and changing, the most important visual information can be presented to players at the fastest speed, thereby providing a smoother and more realistic driving experience. At the same time, this strategy can also effectively reduce unnecessary computing loads and improve the performance of the overall system, so that players can enjoy delay-free, high-quality picture display effects whether they are driving at high speed or racing fiercely.

[0024] Step S3: performing multi-step prediction calculation on the intra-frame priority rendering mapping table by a time domain interpolation predictor to obtain an inter-frame display delay compensation parameter set.

[0025] Specifically, a temporal interpolation predictor performs multi-step predictions on the intra-frame priority rendering map to obtain a set of inter-frame display delay compensation parameters. This process aims to reduce display delay and optimize the smoothness of dynamic content by predicting future frames. Specifically, after obtaining the intra-frame priority rendering map, the system uses the temporal interpolation predictor to analyze this priority information to predict the change trends of each region in the next few frames. By analyzing the change patterns between consecutive frames, the temporal interpolation predictor can infer which regions will continue to change in the following frames and to what extent. For example, in a racing game, the movement path of a vehicle and changes in the surrounding environment can be reasonably predicted based on data from previous frames. In practice, the system first performs a time series analysis on the data in the intra-frame priority rendering map to identify the temporal change patterns of dynamic regions at different levels. Then, based on these patterns, the temporal interpolation predictor performs multi-step predictions to generate a series of predictions for future frames. These predictions include not only the movement direction and speed of each region in the image, but also details such as potential deformation or color changes. Ultimately, the system generates a set of inter-frame display delay compensation parameters based on these predictions. This set includes optimized adjustments for each frame to compensate for delays caused by data transmission, processing, or other factors. For example, in a racing game, when the player is driving at high speed, distant scenery may quickly shift backwards, while the nearby track requires more detailed presentation. Using the multi-step prediction calculations of the temporal interpolation predictor, the system can prepare for these dynamically changing data in advance, ensuring smooth, lag-free visual output even under poor network conditions or high hardware load. This technology not only enhances the gaming experience but is also widely applicable to other highly dynamic content, such as virtual reality (VR) applications and HD video playback, enabling users to enjoy smooth and responsive visuals in a variety of complex scenarios. This ensures that both rapidly changing game scenes and complex video content are presented to the user in optimal condition, greatly enhancing user immersion and satisfaction.

[0026] Step S4: pre-allocating hardware acceleration cache for the continuous image frames based on the inter-frame display delay compensation parameter set to obtain a multi-level rendering cache structure.

[0027] Specifically, hardware-accelerated cache pre-allocation is performed for consecutive image frames based on the inter-frame display delay compensation parameter set, resulting in a multi-level rendering cache structure. This process aims to reduce display latency and improve rendering efficiency by optimizing cache management. Specifically, after obtaining the inter-frame display delay compensation parameter set, the system uses these parameters to comprehensively analyze the changing trends and delay compensation requirements for the next few frames. This analysis enables the system to identify which areas require priority processing and which data should be pre-loaded into the cache to ensure smooth display. For example, in a racing game, the changes in the vehicle and its surroundings are the most critical, so the data for these areas must be efficiently managed and scheduled. In practice, the system first uses the information in the inter-frame display delay compensation parameter set to determine the rendering resources and time required for different areas in each frame and formulates a cache pre-allocation strategy accordingly. The system then intelligently allocates the hardware-accelerated cache to ensure sufficient cache space for high-priority dynamic areas. This includes not only the data for the current frame, but also the data predicted for the next few frames, allowing for pre-loading and processing. For example, in a racing game scene, when the player drives at high speed, the system predicts changes to the track, vehicle, and other dynamic elements in the next few frames and pre-loads the relevant data into the cache. This ensures smooth and responsive graphics even in complex scenes. Furthermore, the system further improves rendering efficiency by building a multi-level render cache structure. This multi-level cache structure allows the system to store and manage data in a tiered manner based on its importance and access frequency, achieving more efficient resource utilization. For example, the system can store data for frequently changing and important areas, such as the vehicle and the surrounding track, in the high-speed cache, while using lower-level cache for relatively static or less important background elements. This significantly improves overall performance without increasing hardware costs. Ultimately, through this hardware-accelerated cache pre-allocation strategy based on the inter-frame display delay compensation parameter set, the system generates an optimized multi-level render cache structure. This ensures that both fast-moving scenes in racing games and other highly dynamic content, such as complex interactions in virtual reality applications, are presented to users in optimal condition, greatly enhancing user immersion and quality of experience. The application of this technology not only improves the user experience, but also provides developers with more flexibility and possibilities, and promotes the development of display technology.

[0028] Step S5: performing parallel computing processing on the multi-level rendering cache structure through an asynchronous scanline rendering scheduler to obtain a low-latency scanline rendering data stream.

[0029] Specifically, an asynchronous scanline rendering scheduler performs parallel computation on a multi-level render buffer structure, generating a low-latency scanline rendering data stream. This process aims to significantly reduce display latency and improve rendering efficiency by leveraging efficient scheduling and parallel computing techniques. Specifically, after constructing an optimized multi-level render buffer structure, the system utilizes an asynchronous scanline rendering scheduler to efficiently manage and schedule the data within these buffers. The asynchronous scanline rendering scheduler identifies the priorities of different regions within each frame and dynamically allocates computing resources based on these priorities, enabling parallel processing. In practice, when the system receives a frame, the asynchronous scanline rendering scheduler first analyzes the data distribution within the multi-level render buffer structure to determine which regions require priority processing and how to allocate computing tasks. For example, in a racing game scene, the vehicle and the surrounding track are key areas of user attention, so data for these areas is given higher priority. The scheduler then distributes data from these high-priority regions to multiple parallel processing units, while simultaneously making corresponding arrangements for processing lower-priority background elements. This allows the system to process data from multiple regions simultaneously, significantly improving overall rendering speed. To further illustrate this point, consider a racing game where the player's vehicle is traveling at high speed and the surrounding environment is rapidly changing. In this scenario, the asynchronous scanline rendering scheduler, based on a previously generated multi-level render buffer structure, identifies changes in the vehicle, track, and other dynamic elements and distributes their data to different processors for parallel computation. Meanwhile, the system prioritizes processing of relatively static background elements, such as distant sky or buildings, with lower priority. This strategy not only ensures fast response times in critical areas but also effectively avoids overall latency issues caused by concentrating processing on a single area. Ultimately, through this efficient parallel processing mechanism, the system generates a low-latency scanline rendering data stream. This data stream contains optimized image information, enabling each frame to be transmitted to the display device at the fastest speed, resulting in a smooth and lag-free display. Whether in the intense racing of a racing game or the complex interactive scenes of a virtual reality application, this approach significantly enhances the user experience, delivering a more realistic and immersive visual experience. This approach not only improves rendering efficiency but also provides users with higher-quality display output, pushing display technology to a higher level.

[0030] Step S6: performing regional adaptive refresh control on the display panel of the display device based on the low-latency scan line rendering data stream to obtain a display output with optimized dynamic response.

[0031] Specifically, the display device's display panel performs regional adaptive refresh control based on a low-latency scanline rendering data stream, resulting in a dynamically responsive and optimized display output. This process aims to ensure that every frame is presented to the user in optimal condition by intelligently managing the display panel's refresh strategy. Specifically, after generating the low-latency scanline rendering data stream, the system uses the information in this data stream to identify which areas require priority updating and dynamically adjusts the display panel's refresh strategy based on this information. For example, in a racing game, the vehicle and the surrounding track are key areas of user attention, requiring a higher refresh rate and faster response. In practice, the system first analyzes the content of the low-latency scanline rendering data stream to determine the changes and importance of each area. For frequently changing and critical areas, such as a high-speed vehicle and its surroundings, the system allocates a higher refresh rate to ensure real-time updates and a smooth visual experience. Meanwhile, for relatively static or less important background elements, such as the distant sky or buildings, a lower refresh rate can be used, saving resources and improving overall efficiency. This flexible refresh strategy not only improves the user experience but also effectively reduces energy consumption and hardware burden. To better understand this process, consider a racing game scenario where the player's vehicle is moving rapidly and the surrounding environment is changing rapidly. In this scenario, the system uses information from the low-latency scanline rendering data stream to identify the vehicle and the surrounding track as critical areas and assign them a higher refresh rate. Simultaneously, for the static background in the distance, the system can reduce the refresh rate or even temporarily freeze updates in these areas to reduce unnecessary computational load. In this way, the system optimizes overall resource utilization while ensuring smooth display in critical areas. Ultimately, this region-adaptive refresh control method generates a display output that is dynamically responsive and optimized. This means that users can enjoy lag-free, high-definition visuals, whether in the intense racing scenes of a racing game or the complex interactive environments of a virtual reality application. This technology not only significantly enhances user immersion and quality of experience, but also provides developers with greater flexibility and possibilities, advancing the development of display technology. Through this intelligent region-adaptive refresh control strategy, the system not only improves the overall performance of the display device but also ensures that every frame is presented to the user in optimal condition, delivering a more realistic and smooth visual experience.

[0032] In a specific embodiment, the method of performing dynamic region recognition analysis on continuous image frames received by a preset display device using a visual frame difference detection technology to obtain a dynamic region mask image includes: Performing multi-scale optical flow analysis on the continuous image frames to obtain a pixel-level motion vector map, and performing adaptive threshold segmentation on the pixel-level motion vector map to obtain a candidate dynamic region mask; performing spatiotemporal correlation calculation on the continuous image frames based on the candidate dynamic region mask to obtain a region boundary feature descriptor, and performing morphological optimization processing on the region boundary feature descriptor to obtain a region contour accurate mapping; The region contour is accurately mapped and connected domains are marked using a region growing algorithm to obtain a dynamic region classification label, and the continuous image frames are subjected to region merging and splitting processing based on the dynamic region classification label to obtain the dynamic region mask map; wherein the dynamic region mask map includes the dynamic region position coordinates, the region boundary contour point set and the region motion feature vector.

[0033] Specifically, visual frame difference detection technology performs multi-scale optical flow analysis on consecutive image frames to generate pixel-level motion vector maps. This pixel-level motion vector map is then adaptively segmented using thresholding to create candidate dynamic region masks. This process aims to accurately identify dynamically changing portions of the image. Specifically, after acquiring consecutive image frames from the display device, the visual frame difference detection technology first performs multi-scale optical flow analysis on these frames. Multi-scale optical flow analysis calculates pixel motion vectors between adjacent frames at different resolutions, capturing motion information at various scales. For example, in a racing game, the vehicle and the surrounding track are key areas of user attention, making the motion vectors of these areas particularly important. The system calculates the motion direction and speed of each pixel in each frame to generate a detailed pixel-level motion vector map. Next, the system applies adaptive thresholding to classify each pixel as either a dynamic or static region based on its motion intensity, generating candidate dynamic region masks. This approach effectively identifies key dynamic regions that require prioritization. Based on the candidate dynamic region masks, the system performs spatiotemporal correlation calculations on consecutive image frames to obtain region boundary feature descriptors. These descriptors are then morphologically optimized to produce a refined region outline map, further refining dynamic region identification. The system first uses the candidate dynamic region masks to identify preliminary dynamic regions and then performs spatiotemporal correlation calculations on them. This spatiotemporal correlation calculation not only considers the spatial relationship between adjacent pixels but also incorporates temporal trends between frames, resulting in more accurate region boundary feature descriptors. For example, in a racing game scene, when a vehicle moves rapidly, the changes in its surroundings can be more accurately captured through this spatiotemporal correlation calculation. The system then performs morphological optimization on the generated region boundary feature descriptors, using operations such as dilation and erosion, to remove noise and smooth the region boundaries, ultimately producing a refined region outline map. This step ensures the accuracy and smoothness of dynamic region boundaries, providing high-quality foundational data for subsequent processing. The system uses a region growing algorithm to mark the connected domains of the refined region contour map to obtain dynamic region classification labels. Based on the dynamic region classification labels, the system then merges and splits the regions of the consecutive image frames to obtain the dynamic region mask map. This is the last step of the entire process and the most critical part. The system first uses the region growing algorithm to mark each connected region in the refined region contour map to generate a dynamic region classification label. The region growing algorithm starts from the seed point and gradually expands to all pixels belonging to the same dynamic region to form a complete connected domain. For example, in a racing game scene, the vehicle and the surrounding track can be marked as a connected domain. The system then performs further region merging and splitting on the consecutive image frames based on these dynamic region classification labels.The system merges overly scattered or disjointed small regions into larger ones. Large regions containing multiple types of dynamic elements are appropriately split to improve recognition accuracy. Ultimately, the system generates a dynamic region mask containing the coordinates of the dynamic region's location, a set of region boundary contour points, and the region's motion feature vector. To better understand this process, imagine a racing game where the player's vehicle is driving at high speed and the surrounding environment is rapidly changing. The system first uses multi-scale optical flow analysis to calculate the motion vector for each pixel in each frame and generates a pixel-level motion vector map. Next, the system applies adaptive threshold segmentation to mark pixels with high motion intensity as dynamic regions, generating candidate dynamic region masks. Based on this mask, the system then calculates spatiotemporal correlations to generate region boundary feature descriptors. Morphological optimization is then performed to refine the region contour map. This step allows the system to accurately capture changes in the vehicle and the surrounding track. Finally, the system uses a region growing algorithm to label these refined regions as connected components. Regions are then merged and split based on the dynamic region classification labels to generate the dynamic region mask. This mask image not only contains the position coordinates and boundary contour points of the vehicle and its surrounding track, but also records their motion feature vectors, enabling the system to efficiently allocate rendering resources and provide a smooth and lag-free display. The application of this technology not only significantly improves the user experience, but also provides developers with more flexibility and possibilities, promoting the development of display technology. Through this intelligent dynamic area recognition method, the system not only improves the overall performance of the display device, but also ensures that every frame of the image is presented to the user in its optimal state, bringing a more realistic and smooth visual experience.

[0034] In a specific embodiment, the layered rendering priority allocation for the consecutive image frames based on the dynamic area mask map to obtain an intra-frame priority rendering mapping table includes: Performing regional feature complexity calculation on the dynamic region mask image to obtain a regional calculation density vector, and performing hierarchical clustering on the regional calculation density vector to obtain a regional rendering hierarchy tree; Performing layered rendering processing on the continuous image frames based on the regional rendering hierarchy tree to obtain a multi-level rendering task graph, and performing rendering dependency propagation analysis on the multi-level rendering task graph to obtain an inter-layer data flow dependency chain; wherein the inter-layer data flow dependency chain includes a layer transmission order, a data interaction type, and a cross-layer dependency strength; Performing temporal decomposition of the inter-layer data flow dependency chain through a distributed task scheduler to obtain a parallel rendering task sequence, and allocating computing resources based on the parallel rendering task sequence to obtain a hardware execution schedule; wherein the hardware execution schedule includes a processor core allocation scheme, memory bandwidth allocation, and computing unit timing; The rendering priority of the hardware execution scheduling table is reordered to obtain an optimized rendering execution plan, and the optimized rendering execution plan is time-sliced ​​and synchronously controlled to obtain the intra-frame priority rendering mapping table; wherein the intra-frame priority rendering mapping table includes a regional rendering priority identifier, a rendering task execution timing, and a computing resource allocation plan.

[0035] Specifically, the process of assigning hierarchical rendering priorities for consecutive image frames based on a dynamic region mask to generate an intra-frame priority rendering map is a complex, multi-step process. First, the system calculates the regional feature complexity of the dynamic region mask to obtain regional computational density vectors. These vectors are then hierarchically clustered to form a region rendering hierarchy tree. The region rendering hierarchy tree includes region depth indexes, inter-node connections, and hierarchical computational costs. The regional feature complexity calculation is a key step in this process, determining its computational density vector by analyzing the detail and degree of change of each dynamic region. For example, in a racing game scene, the speed and complexity of changes in the vehicle and its surroundings vary, resulting in higher computational density in certain regions (such as the vehicle itself). The system then uses these computational density vectors to perform hierarchical clustering to construct a region rendering hierarchy tree. This tree structure includes not only each region's depth index, but also inter-node connections and hierarchical computational costs, enabling more efficient organization and management of different rendering tasks. Next, based on the region rendering hierarchy tree, the system hierarchically processes the rendering content of consecutive image frames to generate a multi-level rendering task graph. During this phase, the system carefully considers how to distribute rendering tasks across different layers to optimize the overall rendering process. For example, in a racing game, the vehicle can be treated as a single high-level task, while the track background is treated as a lower-level task. The system then performs rendering dependency propagation analysis on the multi-level rendering task graph to identify inter-layer data flow dependency chains. This inter-layer data flow dependency chain details the relationships between rendering tasks, including the order of layer propagation, the type of data interaction, and the strength of cross-layer dependencies. For example, in the racing game example, the vehicle's motion directly affects its relative position to the track background. This requires the system to account for these data dependencies during rendering to ensure the fidelity and coherence of the final image. Subsequently, the distributed task scheduler performs temporal decomposition of the inter-layer data flow dependency chain, generating parallel rendering task sequences. Computing resources are allocated based on these sequences, resulting in a hardware execution schedule. The distributed task scheduler plays a crucial role here, identifying which tasks can be executed in parallel and which must be executed sequentially to maximize the system's computing power. For example, in a racing game scene, if the car and background can be rendered independently, they can be assigned to different processor cores for parallel processing. However, for tasks that require a strict sequence, such as rendering the car before the background, they must be executed in the correct order. The hardware execution schedule details information such as processor core allocation, memory bandwidth allocation, and compute unit timing, providing specific guidance for actual rendering work.Finally, the hardware execution schedule is reordered to prioritize rendering, resulting in an optimized rendering execution plan. This plan is then time-sliced ​​and synchronized, ultimately generating an intra-frame priority rendering map. During this step, the system not only reassesses the importance of each rendering task but also considers how to most effectively utilize limited computing resources. For example, in a high-load racing game, to ensure smooth visuals, it may be necessary to prioritize rendering elements that have the greatest impact on the user experience, such as the vehicle's speed and direction indicators. This approach ensures a high-quality visual experience even under tight computing resources. The intra-frame priority rendering map contains information such as region rendering priority identification, rendering task execution timing, and computing resource allocation—all crucial for efficient rendering. For example, in a typical 1080p racing game, assuming 60 frames per second, each frame has a window of approximately 16.7 milliseconds to perform all necessary computation and rendering operations. Through meticulous priority management and resource allocation, the system is able to complete high-quality rendering tasks within such tight time constraints, ensuring a smooth gaming experience for players. In short, through this series of complex steps and technical means, the system can effectively improve rendering efficiency and quality, and meet the needs of modern multimedia applications for high-performance graphics processing.

[0036] In a specific embodiment, the multi-step prediction calculation of the intra-frame priority rendering mapping table by the temporal interpolation predictor to obtain the inter-frame display delay compensation parameter set includes: Performing temporal convolution analysis on the intra-frame priority rendering mapping table to obtain a rendering task time series feature vector, and performing nonlinear transformation processing on the rendering task time series feature vector to obtain a multi-scale temporal feature pyramid; wherein the multi-scale temporal feature pyramid includes rendering task feature descriptions at different time granularities, temporal correlation between layers, and feature importance weights; Using a preset time-domain interpolation predictor, autoregressive prediction processing is performed on the parallel rendering task sequence based on the multi-scale temporal feature pyramid to obtain an inter-frame rendering delay prediction map, and adaptive weighted fusion is performed on the inter-frame rendering delay prediction map to obtain a rendering delay distribution heat map; Performing a spatial transfer function calculation on the rendering delay distribution heat map using a preset wavefront propagation model to obtain a display refresh wavefront prediction model, and performing display delay quantization modeling on different regions in the continuous image frames based on the display refresh wavefront prediction model to obtain a regional display response characteristic curve; Performing differential analysis on the regional display response characteristic curve to obtain a display delay gradient field, and performing optimal path planning on the display delay gradient field to obtain a delay compensation strategy matrix; Based on the delay compensation strategy matrix, the parallel rendering task sequence is hierarchically scheduled and allocated to obtain a multi-level delay compensation execution plan, and the multi-level delay compensation execution plan is evaluated for hardware resource constraints to obtain the inter-frame display delay compensation parameter set; wherein, the inter-frame display delay compensation parameter set includes a regional display priority index, a scan line rendering timing adjustment parameter, and a regional cache prefetch configuration strategy.

[0037] Specifically, the process of performing multi-step predictions on the intra-frame priority rendering map using a temporal interpolation predictor to derive the inter-frame display delay compensation parameter set is a complex and multi-layered process. First, the system performs temporal convolution analysis on the intra-frame priority rendering map to extract rendering task time series feature vectors. These feature vectors are then subjected to nonlinear transformations to generate a multi-scale temporal feature pyramid. The key to this process lies in accurately capturing the rendering task feature descriptions at different temporal granularities, the temporal correlations between layers, and the feature importance weights. For example, in a racing game scene, the relative position change rates between the vehicle and the background vary significantly. This requires the system to identify and quantify these temporal inconsistencies, providing a solid foundation for subsequent predictions. The multi-scale temporal feature pyramid not only incorporates information at different temporal granularities but also considers the interrelationships between layers and their importance within the overall rendering task. Specifically, assuming a racing game requires processing 60 frames per second, the system needs to accurately evaluate the temporal characteristics of each rendering task within each 16.7 millisecond time window. For example, the vehicle itself changes frequently and with greater complexity, while the distant background changes less frequently. Therefore, the system assigns different temporal granularities to each region based on these characteristics. Through temporal convolution analysis, the system can identify these subtle changes and generate a detailed temporal feature vector for the rendering task. Next, by applying nonlinear transformations to these feature vectors, the system constructs a multi-scale temporal feature pyramid. This pyramid contains descriptions of rendering task features at different temporal granularities, the temporal correlations between layers, and feature importance weights. This step ensures that the system fully understands the dynamic changes of each region in each frame. Next, the system uses a pre-defined temporal interpolation predictor to perform autoregressive prediction on the parallel rendering task sequence based on the multi-scale temporal feature pyramid, thereby obtaining a predicted inter-frame rendering latency map. Autoregressive prediction technology plays a key role in this step, allowing the system to make reasonable estimates of potential future rendering latency based on historical data. For example, in a racing game scenario, if the rendering latency of the vehicle portion of a particular frame is greater than that of the background portion, the system can use the autoregressive prediction model to predict this latency trend in advance and take appropriate compensatory measures. By adaptively weighting and fusing inter-frame rendering latency prediction maps, the system generates a rendering latency distribution heat map. This heat map comprehensively considers the importance of each rendering task and its interdependence to ensure the accuracy of the final result. For example, in a racing game, for each 16.7 millisecond time window, the system needs to accurately evaluate and adjust the execution order and resource allocation of each rendering task to achieve optimal performance. The system then uses a preset wavefront propagation model to calculate the spatial transfer function of the rendering latency distribution heat map, deriving the display refresh wavefront prediction pattern.This step is crucial in the entire process, as it directly impacts how to effectively manage display latency in different regions. Specifically, using a wavefront propagation model, the system simulates the display refresh wavefronts of each region in successive image frames, thereby developing a specific latency quantification modeling scheme for each region. For example, in a racing game, if the road ahead changes significantly faster than the distant mountains, the system needs to adjust the display response curves of these regions accordingly to ensure smooth and coherent visuals. Assuming a typical racing game with a vehicle speed of 50 meters per second, the system needs to adjust the rendering priority and scanline rendering timing of the road ahead based on this speed to ensure real-time and stable display. Furthermore, the regional display response curves are differentially analyzed to obtain a display latency gradient field, which is then used for optimal path planning, ultimately forming a latency compensation strategy matrix. In this step, the system not only determines which regions require priority processing but also designs the most effective scheduling scheme to minimize overall display latency. For example, in a typical scene from a racing game, if the system detects that the vehicle portion of a frame has a greater delay than the background portion, it will dynamically adjust the rendering order to ensure the vehicle's display is not affected. Typically, to maintain a 60-frame-per-second refresh rate, any delay exceeding 5 milliseconds can cause screen tearing or stuttering, making timely and effective delay compensation crucial. Through differential analysis, the system accurately identifies areas of high latency and determines the most appropriate delay compensation strategy through optimal path planning. Finally, based on the delay compensation strategy matrix, the system hierarchically schedules and allocates the parallel rendering task sequence, generating a multi-level delay compensation execution plan. This plan is then evaluated for hardware resource constraints, ultimately generating a set of inter-frame display delay compensation parameters. At this stage, the system must carefully balance the demands of each rendering task with available hardware resources. For example, in the high-performance environment of racing games, CPU and GPU load directly impacts final rendering quality and efficiency. Through appropriate hierarchical scheduling and allocation, the system minimizes hardware resource waste while ensuring high-quality graphical output. The inter-frame display delay compensation parameter set includes information such as regional display priority indicators, scan line rendering timing adjustment parameters, and regional cache prefetch configuration strategies, which are key factors in ensuring a smooth user experience. For example, in a typical racing game, assuming that the vehicle rendering task requires more computing resources, the system can dynamically adjust the resource allocation of other lower priority tasks according to the delay compensation strategy matrix to ensure that the rendering quality of the vehicle part is not affected. At the same time, by adjusting the scan line rendering timing, the system can optimize the rendering order of each frame image and further reduce the delay. In short, through the above series of complex and precise operations, the system can effectively reduce the inter-frame display delay and enhance the user's visual experience.These optimization measures are particularly important in high-load application scenarios, such as racing games or virtual reality applications, as they directly determine whether users can enjoy a seamless and smooth visual feast. For example, in racing games, through precise delay compensation strategies, the system can maintain the clarity and smoothness of the vehicle and its surroundings during high-speed driving, providing realistic visual effects even in complex track environments. The application of this technology not only significantly improves the user experience, but also provides developers with more flexibility and possibilities, promoting the development of display technology. Through this intelligent delay compensation mechanism, the system not only improves the overall performance of the display device, but also ensures that every frame of the image is presented to the user in the best condition, bringing a more realistic and smooth visual experience.

[0038] In a specific embodiment, the pre-allocation of hardware acceleration cache for the consecutive image frames based on the inter-frame display delay compensation parameter set to obtain a multi-level rendering cache structure includes: Performing hierarchical storage granularity division on the inter-frame display delay compensation parameter set to obtain a multi-level cache block allocation scheme, and performing bandwidth resource constraint calculation on the multi-level cache block allocation scheme to obtain a cache access scheduling table; Performing a topology optimization configuration on the hardware storage system in the display device based on the cache access scheduling table to obtain a hierarchical storage access network, and performing data flow conflict detection and analysis on the hierarchical storage access network to obtain a conflict avoidance routing table; Performing instruction-level parallel processing on the conflict avoidance routing table to obtain a parallel prefetch instruction set, performing regional correlation analysis and compact layout reorganization on the parallel prefetch instruction set to obtain a partitioned cache organization structure; Based on the partitioned cache organizational structure, the hardware rendering pipeline in the display device is configured with parallel processing units to obtain a heterogeneous computing resource allocation strategy, and the heterogeneous computing resource allocation strategy is dynamically controlled for power consumption balance to obtain the multi-level rendering cache structure; wherein, the multi-level rendering cache structure includes a regional rendering cache hierarchy, a hardware computing unit mapping relationship, and a cache synchronization control protocol.

[0039] Specifically, the process of hardware-accelerated cache pre-allocation for consecutive image frames based on the inter-frame display delay compensation parameter set to create a multi-level rendering cache structure is a complex and multi-layered process. First, the system partitions the inter-frame display delay compensation parameter set into a hierarchical storage granularity, generates a multi-level cache block allocation scheme, and calculates bandwidth resource constraints for this scheme, ultimately generating a cache access schedule. The key to this process lies in how to rationally allocate storage resources based on varying delay compensation requirements to ensure sufficient cache support for rendering tasks in each area. For example, in a racing game scene, the vehicle and its surroundings change at a high rate, requiring more cache resources to ensure smooth rendering. This hierarchical storage granularity allows the system to allocate appropriate cache blocks to tasks of different priorities, thereby improving overall rendering efficiency. For example, in a typical racing game, 60 frames per second are processed. Within each 16.7 millisecond window, the system needs to accurately assess the cache requirements of each rendering task and generate a multi-level cache block allocation scheme based on these requirements. Next, the hardware storage system in the display device is topologically optimized based on the cache access schedule. This generates a hierarchical storage access network, which is then subjected to data flow conflict detection and analysis to obtain a conflict avoidance routing table. The key to this step lies in optimizing the hardware storage system's topology to reduce data flow conflicts and improve access efficiency. For example, in a racing game scenario, data access frequencies and sequences vary across different areas, such as the vehicle, track, and background. Therefore, the system needs to design an efficient hierarchical storage access network to ensure fast and accurate data access in each area. By performing data flow conflict detection and analysis on this network, the system can identify potential conflict points and generate a conflict avoidance routing table, thereby avoiding data access bottlenecks. For example, in a given image frame, the vehicle's motion causes its relative position to change frequently relative to the track. The system needs to implement an optimized routing strategy to ensure that these changes are promptly reflected in the rendering results. The conflict avoidance routing table is then parallelized at the instruction level to generate a parallel prefetch instruction set. This instruction set is then subjected to regional correlation analysis and compact layout reorganization, ultimately forming a partitioned cache organization. This step aims to improve data prefetching efficiency through parallel processing technology, while optimizing cache layout through regional correlation analysis to reduce unnecessary memory access. For example, in a racing game, changes in the vehicle and its surroundings are key areas of user attention, so data prefetching in these areas has a higher priority. Through instruction-level parallel processing, the system can prefetch data from multiple areas simultaneously, improving rendering efficiency. Furthermore, by performing regional correlation analysis and compact layout reorganization on the parallel prefetch instruction set, the system can optimize the organizational structure of the cache, allowing related data to be stored more closely together, reducing access latency.For example, if the road ahead of a vehicle changes frequently in a given frame, the system can preload this data using a parallel prefetch instruction set, ensuring no delays or lags during rendering. Next, based on the partitioned cache organization, the hardware rendering pipeline in the display device is configured with parallel processing units, generating a heterogeneous computing resource allocation strategy. Dynamic power balancing is then applied to this strategy, ultimately resulting in a multi-level rendering cache structure. During this step, the system not only considers how to efficiently utilize hardware resources but also ensures that the overall system power consumption remains within a manageable range. For example, in the high-performance environment of a racing game, the CPU and GPU load directly impacts the final rendering quality and efficiency. By implementing a rational heterogeneous computing resource allocation strategy, the system can minimize hardware resource waste while ensuring high-quality graphics output. For example, in a typical racing game, vehicle rendering requires a significant amount of computing resources. Based on the partitioned cache organization, the system can dynamically adjust resource allocation for other lower-priority tasks to ensure that vehicle rendering quality is not affected. Furthermore, through dynamic power balancing, the system can optimize power consumption across various computing units, avoiding overheating or performance degradation caused by overuse of certain units. Finally, the multi-level render cache structure includes key information such as the regional render cache hierarchy, hardware compute unit mappings, and a cache synchronization control protocol. This information is crucial for efficient rendering. For example, in a typical scene from a racing game, assuming a vehicle speed of 50 meters per second, the system needs to adjust the rendering priority of the road ahead and the scanline rendering timing based on this speed to ensure real-time and stable rendering. The regional render cache hierarchy allows the system to allocate cache resources to tasks of different priorities, ensuring faster response times for high-priority tasks. Furthermore, the hardware compute unit mapping ensures that each rendering task is assigned to the most appropriate compute unit, thereby improving overall rendering efficiency. Furthermore, the cache synchronization control protocol ensures data consistency across cache blocks, preventing screen tearing or stuttering caused by untimely cache updates. In summary, through this complex and sophisticated series of operations, the system effectively reduces inter-frame display latency and enhances the user's visual experience. These optimization measures are particularly important in high-load applications such as racing games or virtual reality applications, as they directly determine whether users can enjoy a seamless and smooth visual experience. For example, in racing games, precise delay compensation strategies and efficient cache management mechanisms allow the system to maintain clarity and smoothness of the vehicle and its surroundings during high-speed driving, providing realistic visuals even in complex racing environments. This technology not only significantly enhances the user experience but also provides developers with greater flexibility and possibilities, driving the development of display technology.Through this intelligent cache management and hardware resource optimization mechanism, the system not only improves the overall performance of the display device, but also ensures that each frame of the image can be presented to the user in the best state, bringing a more realistic and smooth visual enjoyment.

[0040] In a specific embodiment, the asynchronous scanline rendering scheduler performs parallel computing processing on the multi-level rendering cache structure to obtain a low-latency scanline rendering data stream, including: Performing scan line segment mapping processing on the multi-level rendering cache structure to obtain a scan line rendering task segmentation table, and performing priority reordering processing on the scan line rendering task segmentation table to obtain a dynamic scan line execution sequence; Using a preset asynchronous scanline rendering scheduler, a preset hardware rendering unit is subjected to uneven load distribution based on the dynamic scanline execution sequence to obtain a multi-channel rendering instruction stream, and the multi-channel rendering instruction stream is subjected to pipeline interleaving scheduling to obtain a fine-grained parallel execution solution; wherein the hardware rendering unit is disposed in the display device; Performing inter-scanline parallel processing on the fine-grained parallel execution scheme by using a preset partition rendering technology to obtain a parallel rendering result set, and performing inter-scanline boundary fusion processing on the parallel rendering result set to obtain a seamlessly spliced ​​rendered image; The seamless splicing rendering image is processed by parallel transmission through an asynchronous data transmission controller to obtain the low-latency scan line rendering data stream.

[0041] Specifically, the process of parallelizing computations on a multi-level render buffer structure through an asynchronous scanline rendering scheduler to achieve a low-latency scanline rendering data stream is a complex, multi-layered process. First, the system performs scanline segment mapping on the multi-level render buffer structure to generate a scanline rendering task partitioning table. This table is then prioritized to produce a dynamic scanline execution sequence. The core of this process lies in decomposing complex rendering tasks into multiple independent scanline tasks and prioritizing them based on their importance and priority. For example, in a racing game scene, the vehicle and its surroundings change at a high rate, so these components require higher priority to ensure smooth rendering. Through scanline segment mapping, the system can partition each frame into multiple scanline tasks and generate a dynamic scanline execution sequence based on their priorities. Assuming that a typical racing game processes 60 frames per second, the system must accurately assess the priorities of each scanline task within each 16.7 millisecond window and generate an execution sequence based on these priorities. Next, a pre-defined asynchronous scanline rendering scheduler distributes uneven loads across the pre-defined hardware rendering units based on the dynamic scanline execution sequence, generating a multi-pass rendering instruction stream. This instruction stream is then pipelined and interleaved, resulting in a fine-grained parallel execution solution. The key to this step lies in efficiently utilizing hardware resources while avoiding performance bottlenecks caused by uneven loads. For example, in a racing game scenario, data access frequencies and orders vary across different areas, such as the vehicle, track, and background. Therefore, the system requires an efficient load distribution strategy to ensure that data from each area is processed quickly and accurately. By implementing uneven load distribution across the dynamic scanline execution sequence, the system dynamically adjusts the load distribution across the hardware rendering units based on the complexity and priority of each scanline task. Furthermore, by pipeline-interleaving the multi-pass rendering instruction stream, the system achieves a fine-grained parallel execution solution, improving overall rendering efficiency. For example, if the road ahead of the vehicle changes frequently in a given frame, the system can pre-load and process this data through pipeline interleaving, ensuring no delays or lags during rendering. Then, the fine-grained parallel execution scheme is processed in parallel across scan lines using a preset partitioned rendering technique to generate a parallel rendering result set. This result set is then subjected to inter-scanline boundary fusion processing to produce a seamlessly stitched rendered image. This step aims to improve parallel processing efficiency through partitioned rendering technology, while ensuring the seamlessness and consistency of the final rendered image through boundary fusion processing. For example, in a racing game scene, changes in the vehicle and its surroundings are key areas of user attention, so data processing for these areas is prioritized. Through partitioned rendering technology, the system can divide the entire rendering task into multiple subtasks, processing these subtasks in parallel and increasing rendering speed.Furthermore, by performing inter-scanline boundary blending on the parallel rendering result sets, the system can eliminate gaps and discontinuities between different scanlines, ensuring the integrity of the final rendered image. For example, if the relative position of the vehicle and the track changes frequently within a given frame, the system can use boundary blending to ensure that these changes are promptly reflected in the rendered result, providing realistic visuals. Finally, an asynchronous data transfer controller (DTC) performs parallel transmission of the seamlessly stitched rendered image, generating a low-latency scanline rendering data stream. The key to this step is how to efficiently transmit the rendering results to the display device, ensuring real-time and smooth rendering of the final image. For example, in the high-performance environment of racing games, the CPU and GPU load directly impacts the final rendering quality and efficiency. Using an asynchronous data transfer controller (DTC), the system can minimize data transmission latency while ensuring high-quality graphics output. For example, in a typical racing game, the vehicle's speed is 50 meters per second. The system needs to adjust the rendering priority of the road ahead and the scanline rendering timing based on this speed to ensure real-time and stable rendering. Using an asynchronous data transfer controller (DTC), the system can transmit multiple scanline rendering results in parallel, reducing transmission time and overall latency. The multi-level render cache structure plays a crucial role in this entire process. Through the regional render cache hierarchy, the system allocates corresponding cache resources to tasks of different priorities, ensuring faster response times for high-priority tasks. Hardware compute unit mapping ensures that each rendering task is assigned to the most appropriate compute unit for execution, thereby improving overall rendering efficiency. Furthermore, the cache synchronization control protocol ensures data consistency across cache blocks, preventing screen tearing or lag caused by untimely cache updates. For example, in a typical scene in a racing game, assuming a vehicle speed of 50 meters per second, the system needs to adjust the rendering priority of the road ahead and the scanline rendering timing based on this speed to ensure real-time and stable rendering. Through scanline segment mapping, the system divides each frame into multiple scanline tasks and generates a dynamic scanline execution sequence based on their priorities. The asynchronous scanline rendering scheduler then uses this dynamic scanline execution sequence to unevenly distribute the load across hardware rendering units, generating a multi-pass rendering instruction stream and implementing fine-grained parallel execution through pipeline interleaving. Then, through partitioned rendering technology and boundary fusion processing, the system can generate a seamless rendered image. Finally, through an asynchronous data transfer controller, the rendering results of multiple scan lines are transmitted in parallel, reducing transmission time and thus reducing overall latency. In short, through this series of complex and sophisticated operations, the system can effectively reduce inter-frame display latency and enhance the user's visual experience.These optimizations are particularly crucial in high-load scenarios, such as racing games or virtual reality applications, as they directly determine whether users can enjoy a seamless and smooth visual experience. The application of this technology not only significantly enhances the user experience but also provides developers with greater flexibility and possibilities, advancing the development of display technology. Through this intelligent cache management and hardware resource optimization mechanism, the system not only improves the overall performance of the display device, but also ensures that every frame of the image is presented to the user in optimal condition, bringing a more realistic and smooth visual experience.

[0042] In a specific embodiment, performing regional adaptive refresh control on a display panel of the display device based on the low-latency scanline rendering data stream to obtain a display output with optimized dynamic response includes: Performing scan line timing analysis on the low-latency scan line rendering data stream to obtain a regional refresh time distribution diagram, and performing phase compensation calculation on a preset display drive signal based on the regional refresh time distribution diagram to obtain a drive timing adjustment parameter set; performing multi-region drive frequency modulation on a gate drive circuit of a display panel in the display device based on the drive timing adjustment parameter set to obtain a non-uniform scan drive scheme, and performing voltage compensation optimization processing on the non-uniform scan drive scheme to obtain a pixel response balance control strategy; Performing transition frame synthesis processing on the pixel response equalization control strategy through a preset regional overdrive controller to obtain a multi-level response transition frame sequence, and performing time domain interpolation calculation on the multi-level response transition frame sequence to obtain a sub-frame drive control signal; Performing inter-region boundary synchronization and coordination processing on the sub-frame drive control signal to obtain a seamless regional boundary control scheme, and performing parallel loading control on the data line drive circuit of the display panel based on the seamless regional boundary control scheme to obtain a regional parallel drive execution sequence; Based on the regional parallel drive execution sequence, electro-optical conversion characteristics of the display area of ​​the display panel are compensated to obtain a perceptually uniform display output, and visual persistence effect optimization processing is performed on the perceptually uniform display output to obtain the dynamic response optimized display output.

[0043] Specifically, implementing regional adaptive refresh control on a display device's display panel based on a low-latency scanline rendering data stream to achieve a dynamically responsive and optimized display output is a complex and multi-layered process. First, the system performs scanline timing analysis on the low-latency scanline rendering data stream to generate a regional refresh time distribution map. Based on this map, the system calculates phase compensation for the preset display drive signals to obtain a set of drive timing adjustment parameters. The core of this process lies in accurately analyzing the refresh requirements of each region within each frame, ensuring that appropriate refresh strategies are applied to each region based on its frequency of change and importance. For example, in a racing game scene, the vehicle and its surroundings change at a high rate, requiring a higher refresh rate to ensure a smooth visual experience. Through scanline timing analysis, the system identifies the temporal distribution characteristics of each scanline and generates a detailed regional refresh time distribution map. Assuming that a typical racing game processes 60 frames per second, within each 16.7 millisecond window, the system needs to accurately assess the refresh requirements of each region and generate corresponding drive timing adjustment parameters based on these requirements. Next, based on the drive timing adjustment parameter set, the gate drive circuit of the display panel in the display device performs multi-region drive frequency modulation to generate a non-uniform scan drive scheme. This scheme is then optimized for voltage compensation to achieve a balanced pixel response control strategy. The key to this step lies in dynamically adjusting the drive frequency and voltage based on the needs of different regions to ensure the response speed and stability of each pixel. For example, in a racing game scenario, the data access frequency and order of different regions, such as the vehicle, track, and background, vary. Therefore, the system requires an efficient multi-region drive frequency modulation strategy to ensure that data in each region is refreshed quickly and accurately. By optimizing the voltage compensation of the non-uniform scan drive scheme, the system can adjust the voltage level according to the specific needs of each region, thereby achieving balanced pixel response control. For example, if the road ahead of the vehicle changes frequently in a given image frame, the system can use voltage compensation optimization to ensure that these changes are promptly reflected in the final display result. The pixel response balanced control strategy is then synthesized using a preset regional overdrive controller to generate a multi-level response transition frame sequence. This sequence is then subjected to time-domain interpolation to obtain the sub-frame drive control signal. This step aims to improve the display panel's response speed through transition frame synthesis processing, while further refining the drive control signal through time domain interpolation calculations to ensure the smoothness and consistency of the final display effect. For example, in a racing game scene, the changes in the vehicle and its surroundings are the key areas of user attention, so the data processing of these areas has a higher priority. Through the regional overdrive controller, the system can insert transition frames between adjacent frames to reduce screen tearing and stuttering.Furthermore, by performing temporal interpolation on the multi-level response transition frame sequence, the system can generate more refined sub-frame drive control signals, improving overall display quality. For example, if the relative position of the vehicle and the track changes frequently within a given frame, the system can use temporal interpolation to ensure these changes are smoothly displayed on the final image. Next, the sub-frame drive control signals undergo inter-region boundary synchronization and coordination to generate a seamless region boundary control scheme. Based on this scheme, parallel loading is performed on the display panel's data line driver circuits to generate a region parallel drive execution sequence. The key to this step is ensuring that the boundaries between different regions remain seamless during display, avoiding noticeable splicing artifacts or discontinuities. For example, in a racing game scene, changes in the vehicle and its surroundings are key areas of user attention, so data processing for these areas is prioritized. By performing inter-region boundary synchronization and coordination on the sub-frame drive control signals, the system ensures smooth transitions between regions, avoiding screen tearing caused by varying refresh rates. Furthermore, by performing parallel loading on the display panel's data line driver circuits, the system can generate an efficient region parallel drive execution sequence, improving overall display efficiency. Finally, based on the regional parallel drive execution sequence, the display panel's display areas are electro-optical conversion characteristics compensated to generate a perceptually uniform display output. This output is then optimized for persistence of vision, resulting in a display output with optimized dynamic response. The key to this step lies in ensuring consistent brightness and color performance for each pixel through electro-optical conversion characteristic compensation, while also enhancing the user's viewing experience through persistence of vision optimization. For example, in a racing game scenario, the vehicle's speed is 50 meters per second. The system needs to adjust the rendering priority of the road ahead and the scanline rendering timing based on this speed to ensure real-time and stable display. Through electro-optical conversion characteristic compensation, the system can correct the actual brightness and color output of each pixel, ensuring the consistency and uniformity of the final display. Furthermore, by optimizing the persistence of vision effect for the perceptually uniform display output, the system can reduce image blur caused by rapid motion, providing a clearer and more realistic visual experience. Low-latency scanline rendering data streams play a crucial role in this entire process. Through scanline timing analysis and processing, the system can accurately identify the refresh requirements of each area and generate a corresponding set of drive timing adjustment parameters. By optimizing multi-zone drive frequency modulation and voltage compensation, the system ensures the responsiveness and stability of each pixel. Furthermore, through regional overdrive controllers and time-domain interpolation, the system generates more refined drive control signals, improving overall display quality. Finally, by synchronizing and coordinating subframe drive control signals across regional boundaries, the system ensures seamless transitions between different regions, avoiding noticeable splicing artifacts or discontinuities.For example, in a typical racing game scene, assuming a vehicle speed of 50 meters per second, the system needs to adjust the rendering priority of the road ahead and the scanline rendering timing based on this speed to ensure real-time and stable rendering. Through scanline timing analysis, the system divides each frame into multiple scanline tasks and generates a dynamic scanline execution sequence based on their priorities. Next, through multi-region drive frequency modulation and voltage compensation optimization, the system adjusts the drive frequency and voltage levels according to the specific needs of each region, ensuring balanced pixel response. Furthermore, through regional overdrive controllers and temporal interpolation, the system inserts transition frames between adjacent frames to reduce screen tearing and stuttering. Finally, by synchronizing and coordinating sub-frame drive control signals at inter-region boundaries, the system ensures smooth transitions between regions, avoiding screen tearing caused by refresh rate differences. In summary, through this complex and sophisticated series of operations, the system effectively reduces inter-frame display latency and enhances the user's visual experience. These optimization measures are particularly important in high-load applications such as racing games or virtual reality, as they directly determine whether users can enjoy a seamless and smooth visual experience. The application of this technology not only significantly enhances the user experience, but also provides developers with greater flexibility and possibilities, driving the development of display technology. Through this intelligent cache management and hardware resource optimization mechanism, the system not only improves the overall performance of the display device, but also ensures that every frame of the image is presented to the user in optimal condition, bringing a more realistic and smooth visual experience.

[0044] The above describes the low-latency display method of the display device in the embodiment of the present invention. The following describes the low-latency display device of the display device in the embodiment of the present invention. Figure 2 An embodiment of a low-latency display device of a display device according to an embodiment of the present invention includes: The recognition module 21 is used to perform dynamic region recognition and analysis on the continuous image frames received by the preset display device through the visual frame difference detection technology to obtain a dynamic region mask image; an allocation module 22 for allocating layered rendering priorities to the consecutive image frames based on the dynamic region mask map to obtain an intra-frame priority rendering mapping table; A calculation module 23 is configured to perform multi-step prediction calculation on the intra-frame priority rendering mapping table through a temporal interpolation predictor to obtain an inter-frame display delay compensation parameter set; an allocation module 24 for pre-allocating hardware acceleration cache for the consecutive image frames based on the inter-frame display delay compensation parameter set to obtain a multi-level rendering cache structure; A parallel computing module 25 is configured to perform parallel computing processing on the multi-level rendering cache structure through an asynchronous scanline rendering scheduler to obtain a low-latency scanline rendering data stream; The refresh control module 26 is used to perform regional adaptive refresh control on the display panel of the display device based on the low-latency scan line rendering data stream to obtain a display output with optimized dynamic response.

[0045] In this embodiment, for the specific implementation of each unit in the above device embodiment, please refer to the above method embodiment, which will not be repeated here.

[0046] Reference Figure 3 In an embodiment of the present invention, a computer device is also provided, wherein the internal structure of the computer device can be as follows: Figure 3 As shown. The computer device includes a processor, memory, display screen, input device, network interface and database connected via a system bus. The processor of the computer design is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, the above method is implemented.

[0047] Those skilled in the art will understand that Figure 3 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention and does not constitute a limitation on the computer device to which the solution of the present invention is applied.

[0048] An embodiment of the present invention further provides a computer-readable storage medium having a computer program stored thereon, which implements the above-described method when executed by a processor. It is understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0049] Those skilled in the art will appreciate that all or part of the processes in the above-described method embodiments can be implemented by instructing the relevant hardware using a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the above-described method embodiments. Any reference to memory, storage, database, or other media provided herein and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double-speed SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct RAMbus dynamic RAM (DRDRAM), and RAMbus dynamic RAM.

[0050] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, apparatus, article, or method comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, apparatus, article, or method. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, apparatus, article, or method comprising the element.

[0051] The above description is only a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A low-latency display method for a display device, characterized in that: The following steps are involved: Perform dynamic area recognition and analysis on continuous image frames received by a preset display device through visual frame difference detection technology to obtain a dynamic area mask map; Performing layered rendering priority assignment on the consecutive image frames based on the dynamic area mask map to obtain an intra-frame priority rendering mapping table; Performing multi-step prediction calculations on the intra-frame priority rendering mapping table by a temporal interpolation predictor to obtain an inter-frame display delay compensation parameter set; Performing hardware acceleration cache pre-allocation on the continuous image frames based on the inter-frame display delay compensation parameter set to obtain a multi-level rendering cache structure; Performing parallel computing processing on the multi-level rendering cache structure through an asynchronous scanline rendering scheduler to obtain a low-latency scanline rendering data stream; Based on the low-latency scan line rendering data stream, regional adaptive refresh control is performed on the display panel of the display device to obtain a display output with optimized dynamic response.

2. The low-latency display method of a display device according to claim 1, characterized in that: The method of performing dynamic region recognition and analysis on continuous image frames received by a preset display device using a visual frame difference detection technology to obtain a dynamic region mask image includes: Performing multi-scale optical flow field analysis on the continuous image frames by using visual frame difference detection technology to obtain a pixel-level motion vector map, and performing adaptive threshold segmentation on the pixel-level motion vector map to obtain a candidate dynamic region mask; performing spatiotemporal correlation calculation on the continuous image frames based on the candidate dynamic region mask to obtain a region boundary feature descriptor, and performing morphological optimization processing on the region boundary feature descriptor to obtain a region contour accurate mapping; The region contour is accurately mapped and connected domains are marked using a region growing algorithm to obtain a dynamic region classification label, and the continuous image frames are subjected to region merging and splitting processing based on the dynamic region classification label to obtain the dynamic region mask map; wherein the dynamic region mask map includes the dynamic region position coordinates, the region boundary contour point set and the region motion feature vector.

3. The low-latency display method of a display device according to claim 1, wherein: The step of performing layered rendering priority allocation on the continuous image frames based on the dynamic area mask map to obtain an intra-frame priority rendering mapping table includes: Performing regional feature complexity calculation on the dynamic region mask image to obtain a regional calculation density vector, and performing hierarchical clustering on the regional calculation density vector to obtain a regional rendering hierarchy tree; Performing layered rendering processing on the continuous image frames based on the regional rendering hierarchy tree to obtain a multi-level rendering task graph, and performing rendering dependency propagation analysis on the multi-level rendering task graph to obtain an inter-layer data flow dependency chain; wherein the inter-layer data flow dependency chain includes a layer transmission order, a data interaction type, and a cross-layer dependency strength; Performing temporal decomposition of the inter-layer data flow dependency chain through a distributed task scheduler to obtain a parallel rendering task sequence, and allocating computing resources based on the parallel rendering task sequence to obtain a hardware execution schedule; wherein the hardware execution schedule includes a processor core allocation scheme, memory bandwidth allocation, and computing unit timing; The rendering priority of the hardware execution scheduling table is reordered to obtain an optimized rendering execution plan, and the optimized rendering execution plan is time-sliced ​​and synchronously controlled to obtain the intra-frame priority rendering mapping table; wherein the intra-frame priority rendering mapping table includes a regional rendering priority identifier, a rendering task execution timing, and a computing resource allocation plan.

4. The low-latency display method of a display device according to claim 3, wherein: The multi-step prediction calculation of the intra-frame priority rendering mapping table is performed by the time domain interpolation predictor to obtain the inter-frame display delay compensation parameter set, including: Performing temporal convolution analysis on the intra-frame priority rendering mapping table to obtain a rendering task time series feature vector, and performing nonlinear transformation processing on the rendering task time series feature vector to obtain a multi-scale temporal feature pyramid; wherein the multi-scale temporal feature pyramid includes rendering task feature descriptions at different time granularities, temporal correlation between layers, and feature importance weights; Using a preset time-domain interpolation predictor, autoregressive prediction processing is performed on the parallel rendering task sequence based on the multi-scale temporal feature pyramid to obtain an inter-frame rendering delay prediction map, and adaptive weighted fusion is performed on the inter-frame rendering delay prediction map to obtain a rendering delay distribution heat map; Performing a spatial transfer function calculation on the rendering delay distribution heat map using a preset wavefront propagation model to obtain a display refresh wavefront prediction model, and performing display delay quantization modeling on different regions in the continuous image frames based on the display refresh wavefront prediction model to obtain a regional display response characteristic curve; Performing differential analysis on the regional display response characteristic curve to obtain a display delay gradient field, and performing optimal path planning on the display delay gradient field to obtain a delay compensation strategy matrix; Based on the delay compensation strategy matrix, the parallel rendering task sequence is hierarchically scheduled and allocated to obtain a multi-level delay compensation execution plan, and the multi-level delay compensation execution plan is evaluated for hardware resource constraints to obtain the inter-frame display delay compensation parameter set; wherein, the inter-frame display delay compensation parameter set includes a regional display priority index, a scan line rendering timing adjustment parameter, and a regional cache prefetch configuration strategy.

5. The low-latency display method of a display device according to claim 1, characterized in that: The performing hardware acceleration cache pre-allocation on the continuous image frames based on the inter-frame display delay compensation parameter set to obtain a multi-level rendering cache structure includes: Performing hierarchical storage granularity division on the inter-frame display delay compensation parameter set to obtain a multi-level cache block allocation scheme, and performing bandwidth resource constraint calculation on the multi-level cache block allocation scheme to obtain a cache access scheduling table; Performing a topology optimization configuration on the hardware storage system in the display device based on the cache access scheduling table to obtain a hierarchical storage access network, and performing data flow conflict detection and analysis on the hierarchical storage access network to obtain a conflict avoidance routing table; Performing instruction-level parallel processing on the conflict avoidance routing table to obtain a parallel prefetch instruction set, performing regional correlation analysis and compact layout reorganization on the parallel prefetch instruction set to obtain a partitioned cache organization structure; Based on the partitioned cache organizational structure, the hardware rendering pipeline in the display device is configured with parallel processing units to obtain a heterogeneous computing resource allocation strategy, and the heterogeneous computing resource allocation strategy is dynamically controlled for power consumption balance to obtain the multi-level rendering cache structure; wherein, the multi-level rendering cache structure includes a regional rendering cache hierarchy, a hardware computing unit mapping relationship, and a cache synchronization control protocol.

6. The low-latency display method of a display device according to claim 1, characterized in that: The asynchronous scanline rendering scheduler performs parallel computing processing on the multi-level rendering cache structure to obtain a low-latency scanline rendering data stream, including: Performing scan line segment mapping processing on the multi-level rendering cache structure to obtain a scan line rendering task segmentation table, and performing priority reordering processing on the scan line rendering task segmentation table to obtain a dynamic scan line execution sequence; Using a preset asynchronous scanline rendering scheduler, a preset hardware rendering unit is subjected to uneven load distribution based on the dynamic scanline execution sequence to obtain a multi-channel rendering instruction stream, and the multi-channel rendering instruction stream is subjected to pipeline interleaving scheduling to obtain a fine-grained parallel execution solution; wherein the hardware rendering unit is disposed in the display device; Performing inter-scanline parallel processing on the fine-grained parallel execution scheme by using a preset partition rendering technology to obtain a parallel rendering result set, and performing inter-scanline boundary fusion processing on the parallel rendering result set to obtain a seamlessly spliced ​​rendered image; The seamless splicing rendering image is processed by parallel transmission through an asynchronous data transmission controller to obtain the low-latency scan line rendering data stream.

7. The low-latency display method of a display device according to claim 1, characterized in that: The performing regional adaptive refresh control on the display panel of the display device based on the low-latency scanline rendering data stream to obtain a display output with optimized dynamic response includes: Performing scan line timing analysis on the low-latency scan line rendering data stream to obtain a regional refresh time distribution diagram, and performing phase compensation calculation on a preset display drive signal based on the regional refresh time distribution diagram to obtain a drive timing adjustment parameter set; performing multi-region drive frequency modulation on a gate drive circuit of a display panel in the display device based on the drive timing adjustment parameter set to obtain a non-uniform scan drive scheme, and performing voltage compensation optimization processing on the non-uniform scan drive scheme to obtain a pixel response balance control strategy; Performing transition frame synthesis processing on the pixel response equalization control strategy through a preset regional overdrive controller to obtain a multi-level response transition frame sequence, and performing time domain interpolation calculation on the multi-level response transition frame sequence to obtain a sub-frame drive control signal; Performing inter-region boundary synchronization and coordination processing on the sub-frame drive control signal to obtain a seamless regional boundary control scheme, and performing parallel loading control on the data line drive circuit of the display panel based on the seamless regional boundary control scheme to obtain a regional parallel drive execution sequence; Based on the regional parallel drive execution sequence, electro-optical conversion characteristics of the display area of ​​the display panel are compensated to obtain a perceptually uniform display output, and visual persistence effect optimization processing is performed on the perceptually uniform display output to obtain the dynamic response optimized display output.

8. A low-latency display device for a display device, characterized in that: include: The recognition module is used to perform dynamic area recognition and analysis on the continuous image frames received by the preset display device through visual frame difference detection technology to obtain a dynamic area mask map; an allocation module, configured to allocate hierarchical rendering priorities to the consecutive image frames based on the dynamic area mask map to obtain an intra-frame priority rendering mapping table; a calculation module, configured to perform multi-step prediction calculation on the intra-frame priority rendering mapping table through a time domain interpolation predictor to obtain an inter-frame display delay compensation parameter set; an allocation module, configured to pre-allocate hardware acceleration cache for the consecutive image frames based on the inter-frame display delay compensation parameter set to obtain a multi-level rendering cache structure; A parallel computing module, configured to perform parallel computing processing on the multi-level rendering cache structure through an asynchronous scanline rendering scheduler to obtain a low-latency scanline rendering data stream; Refresh control is used to perform regional adaptive refresh control on the display panel of the display device based on the low-latency scan line rendering data stream to obtain a display output with optimized dynamic response.

9. A computer device comprising a memory and a processor, wherein a computer program is stored in the memory, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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